drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static __rte_always_inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci);
  75
  76 static __rte_always_inline void
  77 txq_complete(struct txq *txq);
  78
  79 static __rte_always_inline uint32_t
  80 txq_mp2mr(struct txq *txq, struct rte_mempool *mp);
  81
  82 static __rte_always_inline void
  83 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe);
  84
  85 static __rte_always_inline uint32_t
  86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  87
  88 static __rte_always_inline int
  89 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  90                  uint16_t cqe_cnt, uint32_t *rss_hash);
  91
  92 static __rte_always_inline uint32_t
  93 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  94
  95 #ifndef NDEBUG
  96
  97 /**
  98  * Verify or set magic value in CQE.
  99  *
 100  * @param cqe
 101  *   Pointer to CQE.
 102  *
 103  * @return
 104  *   0 the first time.
 105  */
 106 static inline int
 107 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 108 {
 109         static const uint8_t magic[] = "seen";
 110         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 111         int ret = 1;
 112         unsigned int i;
 113
 114         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 115                 if (!ret || (*buf)[i] != magic[i]) {
 116                         ret = 0;
 117                         (*buf)[i] = magic[i];
 118                 }
 119         return ret;
 120 }
 121
 122 #endif /* NDEBUG */
 123
 124 /**
 125  * Check whether CQE is valid.
 126  *
 127  * @param cqe
 128  *   Pointer to CQE.
 129  * @param cqes_n
 130  *   Size of completion queue.
 131  * @param ci
 132  *   Consumer index.
 133  *
 134  * @return
 135  *   0 on success, 1 on failure.
 136  */
 137 static inline int
 138 check_cqe(volatile struct mlx5_cqe *cqe,
 139           unsigned int cqes_n, const uint16_t ci)
 140 {
 141         uint16_t idx = ci & cqes_n;
 142         uint8_t op_own = cqe->op_own;
 143         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 144         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 145
 146         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 147                 return 1; /* No CQE. */
 148 #ifndef NDEBUG
 149         if ((op_code == MLX5_CQE_RESP_ERR) ||
 150             (op_code == MLX5_CQE_REQ_ERR)) {
 151                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 152                 uint8_t syndrome = err_cqe->syndrome;
 153
 154                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 155                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 156                         return 0;
 157                 if (!check_cqe_seen(cqe))
 158                         ERROR("unexpected CQE error %u (0x%02x)"
 159                               " syndrome 0x%02x",
 160                               op_code, op_code, syndrome);
 161                 return 1;
 162         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 163                    (op_code != MLX5_CQE_REQ)) {
 164                 if (!check_cqe_seen(cqe))
 165                         ERROR("unexpected CQE opcode %u (0x%02x)",
 166                               op_code, op_code);
 167                 return 1;
 168         }
 169 #endif /* NDEBUG */
 170         return 0;
 171 }
 172
 173 /**
 174  * Return the address of the WQE.
 175  *
 176  * @param txq
 177  *   Pointer to TX queue structure.
 178  * @param  wqe_ci
 179  *   WQE consumer index.
 180  *
 181  * @return
 182  *   WQE address.
 183  */
 184 static inline uintptr_t *
 185 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 186 {
 187         ci &= ((1 << txq->wqe_n) - 1);
 188         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 189 }
 190
 191 /**
 192  * Return the size of tailroom of WQ.
 193  *
 194  * @param txq
 195  *   Pointer to TX queue structure.
 196  * @param addr
 197  *   Pointer to tail of WQ.
 198  *
 199  * @return
 200  *   Size of tailroom.
 201  */
 202 static inline size_t
 203 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 204 {
 205         size_t tailroom;
 206         tailroom = (uintptr_t)(txq->wqes) +
 207                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 208                    (uintptr_t)addr;
 209         return tailroom;
 210 }
 211
 212 /**
 213  * Copy data to tailroom of circular queue.
 214  *
 215  * @param dst
 216  *   Pointer to destination.
 217  * @param src
 218  *   Pointer to source.
 219  * @param n
 220  *   Number of bytes to copy.
 221  * @param base
 222  *   Pointer to head of queue.
 223  * @param tailroom
 224  *   Size of tailroom from dst.
 225  *
 226  * @return
 227  *   Pointer after copied data.
 228  */
 229 static inline void *
 230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 231                 void *base, size_t tailroom)
 232 {
 233         void *ret;
 234
 235         if (n > tailroom) {
 236                 rte_memcpy(dst, src, tailroom);
 237                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 238                            n - tailroom);
 239                 ret = (uint8_t *)base + n - tailroom;
 240         } else {
 241                 rte_memcpy(dst, src, n);
 242                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 243         }
 244         return ret;
 245 }
 246
 247 /**
 248  * Manage TX completions.
 249  *
 250  * When sending a burst, mlx5_tx_burst() posts several WRs.
 251  *
 252  * @param txq
 253  *   Pointer to TX queue structure.
 254  */
 255 static inline void
 256 txq_complete(struct txq *txq)
 257 {
 258         const uint16_t elts_n = 1 << txq->elts_n;
 259         const uint16_t elts_m = elts_n - 1;
 260         const unsigned int cqe_n = 1 << txq->cqe_n;
 261         const unsigned int cqe_cnt = cqe_n - 1;
 262         uint16_t elts_free = txq->elts_tail;
 263         uint16_t elts_tail;
 264         uint16_t cq_ci = txq->cq_ci;
 265         volatile struct mlx5_cqe *cqe = NULL;
 266         volatile struct mlx5_wqe_ctrl *ctrl;
 267
 268         do {
 269                 volatile struct mlx5_cqe *tmp;
 270
 271                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 272                 if (check_cqe(tmp, cqe_n, cq_ci))
 273                         break;
 274                 cqe = tmp;
 275 #ifndef NDEBUG
 276                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 277                         if (!check_cqe_seen(cqe))
 278                                 ERROR("unexpected compressed CQE, TX stopped");
 279                         return;
 280                 }
 281                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 282                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 283                         if (!check_cqe_seen(cqe))
 284                                 ERROR("unexpected error CQE, TX stopped");
 285                         return;
 286                 }
 287 #endif /* NDEBUG */
 288                 ++cq_ci;
 289         } while (1);
 290         if (unlikely(cqe == NULL))
 291                 return;
 292         txq->wqe_pi = ntohs(cqe->wqe_counter);
 293         ctrl = (volatile struct mlx5_wqe_ctrl *)
 294                 tx_mlx5_wqe(txq, txq->wqe_pi);
 295         elts_tail = ctrl->ctrl3;
 296         assert((elts_tail & elts_m) < (1 << txq->wqe_n));
 297         /* Free buffers. */
 298         while (elts_free != elts_tail) {
 299                 struct rte_mbuf *elt = (*txq->elts)[elts_free & elts_m];
 300                 struct rte_mbuf *elt_next =
 301                         (*txq->elts)[(elts_free + 1) & elts_m];
 302
 303 #ifndef NDEBUG
 304                 /* Poisoning. */
 305                 memset(&(*txq->elts)[elts_free & elts_m],
 306                        0x66,
 307                        sizeof((*txq->elts)[elts_free & elts_m]));
 308 #endif
 309                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 310                 /* Only one segment needs to be freed. */
 311                 rte_pktmbuf_free_seg(elt);
 312                 ++elts_free;
 313         }
 314         txq->cq_ci = cq_ci;
 315         txq->elts_tail = elts_tail;
 316         /* Update the consumer index. */
 317         rte_wmb();
 318         *txq->cq_db = htonl(cq_ci);
 319 }
 320
 321 /**
 322  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 323  * the cloned mbuf is allocated is returned instead.
 324  *
 325  * @param buf
 326  *   Pointer to mbuf.
 327  *
 328  * @return
 329  *   Memory pool where data is located for given mbuf.
 330  */
 331 static struct rte_mempool *
 332 txq_mb2mp(struct rte_mbuf *buf)
 333 {
 334         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 335                 return rte_mbuf_from_indirect(buf)->pool;
 336         return buf->pool;
 337 }
 338
 339 /**
 340  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 341  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 342  * remove an entry first.
 343  *
 344  * @param txq
 345  *   Pointer to TX queue structure.
 346  * @param[in] mp
 347  *   Memory Pool for which a Memory Region lkey must be returned.
 348  *
 349  * @return
 350  *   mr->lkey on success, (uint32_t)-1 on failure.
 351  */
 352 static inline uint32_t
 353 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 354 {
 355         unsigned int i;
 356         uint32_t lkey = (uint32_t)-1;
 357
 358         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 359                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 360                         /* Unknown MP, add a new MR for it. */
 361                         break;
 362                 }
 363                 if (txq->mp2mr[i].mp == mp) {
 364                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 365                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 366                                txq->mp2mr[i].lkey);
 367                         lkey = txq->mp2mr[i].lkey;
 368                         break;
 369                 }
 370         }
 371         if (unlikely(lkey == (uint32_t)-1))
 372                 lkey = txq_mp2mr_reg(txq, mp, i);
 373         return lkey;
 374 }
 375
 376 /**
 377  * Ring TX queue doorbell.
 378  *
 379  * @param txq
 380  *   Pointer to TX queue structure.
 381  * @param wqe
 382  *   Pointer to the last WQE posted in the NIC.
 383  */
 384 static inline void
 385 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 386 {
 387         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 388         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 389
 390         rte_wmb();
 391         *txq->qp_db = htonl(txq->wqe_ci);
 392         /* Ensure ordering between DB record and BF copy. */
 393         rte_wmb();
 394         *dst = *src;
 395 }
 396
 397 /**
 398  * DPDK callback to check the status of a tx descriptor.
 399  *
 400  * @param tx_queue
 401  *   The tx queue.
 402  * @param[in] offset
 403  *   The index of the descriptor in the ring.
 404  *
 405  * @return
 406  *   The status of the tx descriptor.
 407  */
 408 int
 409 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 410 {
 411         struct txq *txq = tx_queue;
 412         uint16_t used;
 413
 414         txq_complete(txq);
 415         used = txq->elts_head - txq->elts_tail;
 416         if (offset < used)
 417                 return RTE_ETH_TX_DESC_FULL;
 418         return RTE_ETH_TX_DESC_DONE;
 419 }
 420
 421 /**
 422  * DPDK callback to check the status of a rx descriptor.
 423  *
 424  * @param rx_queue
 425  *   The rx queue.
 426  * @param[in] offset
 427  *   The index of the descriptor in the ring.
 428  *
 429  * @return
 430  *   The status of the tx descriptor.
 431  */
 432 int
 433 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 434 {
 435         struct rxq *rxq = rx_queue;
 436         struct rxq_zip *zip = &rxq->zip;
 437         volatile struct mlx5_cqe *cqe;
 438         const unsigned int cqe_n = (1 << rxq->cqe_n);
 439         const unsigned int cqe_cnt = cqe_n - 1;
 440         unsigned int cq_ci;
 441         unsigned int used;
 442
 443         /* if we are processing a compressed cqe */
 444         if (zip->ai) {
 445                 used = zip->cqe_cnt - zip->ca;
 446                 cq_ci = zip->cq_ci;
 447         } else {
 448                 used = 0;
 449                 cq_ci = rxq->cq_ci;
 450         }
 451         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 452         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 453                 int8_t op_own;
 454                 unsigned int n;
 455
 456                 op_own = cqe->op_own;
 457                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 458                         n = ntohl(cqe->byte_cnt);
 459                 else
 460                         n = 1;
 461                 cq_ci += n;
 462                 used += n;
 463                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 464         }
 465         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 466         if (offset < used)
 467                 return RTE_ETH_RX_DESC_DONE;
 468         return RTE_ETH_RX_DESC_AVAIL;
 469 }
 470
 471 /**
 472  * DPDK callback for TX.
 473  *
 474  * @param dpdk_txq
 475  *   Generic pointer to TX queue structure.
 476  * @param[in] pkts
 477  *   Packets to transmit.
 478  * @param pkts_n
 479  *   Number of packets in array.
 480  *
 481  * @return
 482  *   Number of packets successfully transmitted (<= pkts_n).
 483  */
 484 uint16_t
 485 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 486 {
 487         struct txq *txq = (struct txq *)dpdk_txq;
 488         uint16_t elts_head = txq->elts_head;
 489         const uint16_t elts_n = 1 << txq->elts_n;
 490         const uint16_t elts_m = elts_n - 1;
 491         unsigned int i = 0;
 492         unsigned int j = 0;
 493         unsigned int k = 0;
 494         uint16_t max_elts;
 495         unsigned int max_inline = txq->max_inline;
 496         const unsigned int inline_en = !!max_inline && txq->inline_en;
 497         uint16_t max_wqe;
 498         unsigned int comp;
 499         volatile struct mlx5_wqe_v *wqe = NULL;
 500         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 501         unsigned int segs_n = 0;
 502         struct rte_mbuf *buf = NULL;
 503         uint8_t *raw;
 504
 505         if (unlikely(!pkts_n))
 506                 return 0;
 507         /* Prefetch first packet cacheline. */
 508         rte_prefetch0(*pkts);
 509         /* Start processing. */
 510         txq_complete(txq);
 511         max_elts = (elts_n - (elts_head - txq->elts_tail));
 512         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 513         if (unlikely(!max_wqe))
 514                 return 0;
 515         do {
 516                 volatile rte_v128u32_t *dseg = NULL;
 517                 uint32_t length;
 518                 unsigned int ds = 0;
 519                 unsigned int sg = 0; /* counter of additional segs attached. */
 520                 uintptr_t addr;
 521                 uint64_t naddr;
 522                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 523                 uint16_t tso_header_sz = 0;
 524                 uint16_t ehdr;
 525                 uint8_t cs_flags = 0;
 526                 uint64_t tso = 0;
 527                 uint16_t tso_segsz = 0;
 528 #ifdef MLX5_PMD_SOFT_COUNTERS
 529                 uint32_t total_length = 0;
 530 #endif
 531
 532                 /* first_seg */
 533                 buf = *pkts;
 534                 segs_n = buf->nb_segs;
 535                 /*
 536                  * Make sure there is enough room to store this packet and
 537                  * that one ring entry remains unused.
 538                  */
 539                 assert(segs_n);
 540                 if (max_elts < segs_n)
 541                         break;
 542                 max_elts -= segs_n;
 543                 --segs_n;
 544                 if (unlikely(--max_wqe == 0))
 545                         break;
 546                 wqe = (volatile struct mlx5_wqe_v *)
 547                         tx_mlx5_wqe(txq, txq->wqe_ci);
 548                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 549                 if (pkts_n - i > 1)
 550                         rte_prefetch0(*(pkts + 1));
 551                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 552                 length = DATA_LEN(buf);
 553                 ehdr = (((uint8_t *)addr)[1] << 8) |
 554                        ((uint8_t *)addr)[0];
 555 #ifdef MLX5_PMD_SOFT_COUNTERS
 556                 total_length = length;
 557 #endif
 558                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 559                         break;
 560                 /* Update element. */
 561                 (*txq->elts)[elts_head & elts_m] = buf;
 562                 /* Prefetch next buffer data. */
 563                 if (pkts_n - i > 1)
 564                         rte_prefetch0(
 565                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 566                 /* Should we enable HW CKSUM offload */
 567                 if (buf->ol_flags &
 568                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 569                         const uint64_t is_tunneled = buf->ol_flags &
 570                                                      (PKT_TX_TUNNEL_GRE |
 571                                                       PKT_TX_TUNNEL_VXLAN);
 572
 573                         if (is_tunneled && txq->tunnel_en) {
 574                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 575                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 576                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 577                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 578                         } else {
 579                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 580                                            MLX5_ETH_WQE_L4_CSUM;
 581                         }
 582                 }
 583                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 584                 /* Replace the Ethernet type by the VLAN if necessary. */
 585                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 586                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 587                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 588
 589                         addr += 2;
 590                         length -= 2;
 591                         /* Copy Destination and source mac address. */
 592                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 593                         /* Copy VLAN. */
 594                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 595                         /* Copy missing two bytes to end the DSeg. */
 596                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 597                                ((uint8_t *)addr) + len, 2);
 598                         addr += len + 2;
 599                         length -= (len + 2);
 600                 } else {
 601                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 602                                MLX5_WQE_DWORD_SIZE);
 603                         length -= pkt_inline_sz;
 604                         addr += pkt_inline_sz;
 605                 }
 606                 if (txq->tso_en) {
 607                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 608                         if (tso) {
 609                                 uintptr_t end = (uintptr_t)
 610                                                 (((uintptr_t)txq->wqes) +
 611                                                 (1 << txq->wqe_n) *
 612                                                 MLX5_WQE_SIZE);
 613                                 unsigned int copy_b;
 614                                 uint8_t vlan_sz = (buf->ol_flags &
 615                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 616                                 const uint64_t is_tunneled =
 617                                                         buf->ol_flags &
 618                                                         (PKT_TX_TUNNEL_GRE |
 619                                                          PKT_TX_TUNNEL_VXLAN);
 620
 621                                 tso_header_sz = buf->l2_len + vlan_sz +
 622                                                 buf->l3_len + buf->l4_len;
 623                                 tso_segsz = buf->tso_segsz;
 624
 625                                 if (is_tunneled && txq->tunnel_en) {
 626                                         tso_header_sz += buf->outer_l2_len +
 627                                                          buf->outer_l3_len;
 628                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 629                                 } else {
 630                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 631                                 }
 632                                 if (unlikely(tso_header_sz >
 633                                              MLX5_MAX_TSO_HEADER))
 634                                         break;
 635                                 copy_b = tso_header_sz - pkt_inline_sz;
 636                                 /* First seg must contain all headers. */
 637                                 assert(copy_b <= length);
 638                                 raw += MLX5_WQE_DWORD_SIZE;
 639                                 if (copy_b &&
 640                                    ((end - (uintptr_t)raw) > copy_b)) {
 641                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 642                                                       1 + 3) / 4;
 643
 644                                         if (unlikely(max_wqe < n))
 645                                                 break;
 646                                         max_wqe -= n;
 647                                         rte_memcpy((void *)raw,
 648                                                    (void *)addr, copy_b);
 649                                         addr += copy_b;
 650                                         length -= copy_b;
 651                                         pkt_inline_sz += copy_b;
 652                                         /*
 653                                          * Another DWORD will be added
 654                                          * in the inline part.
 655                                          */
 656                                         raw += MLX5_WQE_DS(copy_b) *
 657                                                MLX5_WQE_DWORD_SIZE -
 658                                                MLX5_WQE_DWORD_SIZE;
 659                                 } else {
 660                                         /* NOP WQE. */
 661                                         wqe->ctrl = (rte_v128u32_t){
 662                                                      htonl(txq->wqe_ci << 8),
 663                                                      htonl(txq->qp_num_8s | 1),
 664                                                      0,
 665                                                      0,
 666                                         };
 667                                         ds = 1;
 668                                         total_length = 0;
 669                                         k++;
 670                                         goto next_wqe;
 671                                 }
 672                         }
 673                 }
 674                 /* Inline if enough room. */
 675                 if (inline_en || tso) {
 676                         uintptr_t end = (uintptr_t)
 677                                 (((uintptr_t)txq->wqes) +
 678                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 679                         unsigned int inline_room = max_inline *
 680                                                    RTE_CACHE_LINE_SIZE -
 681                                                    (pkt_inline_sz - 2);
 682                         uintptr_t addr_end = (addr + inline_room) &
 683                                              ~(RTE_CACHE_LINE_SIZE - 1);
 684                         unsigned int copy_b = (addr_end > addr) ?
 685                                 RTE_MIN((addr_end - addr), length) :
 686                                 0;
 687
 688                         raw += MLX5_WQE_DWORD_SIZE;
 689                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 690                                 /*
 691                                  * One Dseg remains in the current WQE.  To
 692                                  * keep the computation positive, it is
 693                                  * removed after the bytes to Dseg conversion.
 694                                  */
 695                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 696
 697                                 if (unlikely(max_wqe < n))
 698                                         break;
 699                                 max_wqe -= n;
 700                                 if (tso) {
 701                                         uint32_t inl =
 702                                                 htonl(copy_b | MLX5_INLINE_SEG);
 703
 704                                         pkt_inline_sz =
 705                                                 MLX5_WQE_DS(tso_header_sz) *
 706                                                 MLX5_WQE_DWORD_SIZE;
 707                                         rte_memcpy((void *)raw,
 708                                                    (void *)&inl, sizeof(inl));
 709                                         raw += sizeof(inl);
 710                                         pkt_inline_sz += sizeof(inl);
 711                                 }
 712                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 713                                 addr += copy_b;
 714                                 length -= copy_b;
 715                                 pkt_inline_sz += copy_b;
 716                         }
 717                         /*
 718                          * 2 DWORDs consumed by the WQE header + ETH segment +
 719                          * the size of the inline part of the packet.
 720                          */
 721                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 722                         if (length > 0) {
 723                                 if (ds % (MLX5_WQE_SIZE /
 724                                           MLX5_WQE_DWORD_SIZE) == 0) {
 725                                         if (unlikely(--max_wqe == 0))
 726                                                 break;
 727                                         dseg = (volatile rte_v128u32_t *)
 728                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 729                                                            ds / 4);
 730                                 } else {
 731                                         dseg = (volatile rte_v128u32_t *)
 732                                                 ((uintptr_t)wqe +
 733                                                  (ds * MLX5_WQE_DWORD_SIZE));
 734                                 }
 735                                 goto use_dseg;
 736                         } else if (!segs_n) {
 737                                 goto next_pkt;
 738                         } else {
 739                                 /* dseg will be advance as part of next_seg */
 740                                 dseg = (volatile rte_v128u32_t *)
 741                                         ((uintptr_t)wqe +
 742                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 743                                 goto next_seg;
 744                         }
 745                 } else {
 746                         /*
 747                          * No inline has been done in the packet, only the
 748                          * Ethernet Header as been stored.
 749                          */
 750                         dseg = (volatile rte_v128u32_t *)
 751                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 752                         ds = 3;
 753 use_dseg:
 754                         /* Add the remaining packet as a simple ds. */
 755                         naddr = htonll(addr);
 756                         *dseg = (rte_v128u32_t){
 757                                 htonl(length),
 758                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 759                                 naddr,
 760                                 naddr >> 32,
 761                         };
 762                         ++ds;
 763                         if (!segs_n)
 764                                 goto next_pkt;
 765                 }
 766 next_seg:
 767                 assert(buf);
 768                 assert(ds);
 769                 assert(wqe);
 770                 /*
 771                  * Spill on next WQE when the current one does not have
 772                  * enough room left. Size of WQE must a be a multiple
 773                  * of data segment size.
 774                  */
 775                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 776                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 777                         if (unlikely(--max_wqe == 0))
 778                                 break;
 779                         dseg = (volatile rte_v128u32_t *)
 780                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 781                         rte_prefetch0(tx_mlx5_wqe(txq,
 782                                                   txq->wqe_ci + ds / 4 + 1));
 783                 } else {
 784                         ++dseg;
 785                 }
 786                 ++ds;
 787                 buf = buf->next;
 788                 assert(buf);
 789                 length = DATA_LEN(buf);
 790 #ifdef MLX5_PMD_SOFT_COUNTERS
 791                 total_length += length;
 792 #endif
 793                 /* Store segment information. */
 794                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 795                 *dseg = (rte_v128u32_t){
 796                         htonl(length),
 797                         txq_mp2mr(txq, txq_mb2mp(buf)),
 798                         naddr,
 799                         naddr >> 32,
 800                 };
 801                 (*txq->elts)[++elts_head & elts_m] = buf;
 802                 ++sg;
 803                 /* Advance counter only if all segs are successfully posted. */
 804                 if (sg < segs_n)
 805                         goto next_seg;
 806                 else
 807                         j += sg;
 808 next_pkt:
 809                 ++elts_head;
 810                 ++pkts;
 811                 ++i;
 812                 /* Initialize known and common part of the WQE structure. */
 813                 if (tso) {
 814                         wqe->ctrl = (rte_v128u32_t){
 815                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 816                                 htonl(txq->qp_num_8s | ds),
 817                                 0,
 818                                 0,
 819                         };
 820                         wqe->eseg = (rte_v128u32_t){
 821                                 0,
 822                                 cs_flags | (htons(tso_segsz) << 16),
 823                                 0,
 824                                 (ehdr << 16) | htons(tso_header_sz),
 825                         };
 826                 } else {
 827                         wqe->ctrl = (rte_v128u32_t){
 828                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 829                                 htonl(txq->qp_num_8s | ds),
 830                                 0,
 831                                 0,
 832                         };
 833                         wqe->eseg = (rte_v128u32_t){
 834                                 0,
 835                                 cs_flags,
 836                                 0,
 837                                 (ehdr << 16) | htons(pkt_inline_sz),
 838                         };
 839                 }
 840 next_wqe:
 841                 txq->wqe_ci += (ds + 3) / 4;
 842                 /* Save the last successful WQE for completion request */
 843                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 844 #ifdef MLX5_PMD_SOFT_COUNTERS
 845                 /* Increment sent bytes counter. */
 846                 txq->stats.obytes += total_length;
 847 #endif
 848         } while (i < pkts_n);
 849         /* Take a shortcut if nothing must be sent. */
 850         if (unlikely((i + k) == 0))
 851                 return 0;
 852         txq->elts_head += (i + j);
 853         /* Check whether completion threshold has been reached. */
 854         comp = txq->elts_comp + i + j + k;
 855         if (comp >= MLX5_TX_COMP_THRESH) {
 856                 /* Request completion on last WQE. */
 857                 last_wqe->ctrl2 = htonl(8);
 858                 /* Save elts_head in unused "immediate" field of WQE. */
 859                 last_wqe->ctrl3 = txq->elts_head;
 860                 txq->elts_comp = 0;
 861         } else {
 862                 txq->elts_comp = comp;
 863         }
 864 #ifdef MLX5_PMD_SOFT_COUNTERS
 865         /* Increment sent packets counter. */
 866         txq->stats.opackets += i;
 867 #endif
 868         /* Ring QP doorbell. */
 869         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 870         return i;
 871 }
 872
 873 /**
 874  * Open a MPW session.
 875  *
 876  * @param txq
 877  *   Pointer to TX queue structure.
 878  * @param mpw
 879  *   Pointer to MPW session structure.
 880  * @param length
 881  *   Packet length.
 882  */
 883 static inline void
 884 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 885 {
 886         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 887         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 888                 (volatile struct mlx5_wqe_data_seg (*)[])
 889                 tx_mlx5_wqe(txq, idx + 1);
 890
 891         mpw->state = MLX5_MPW_STATE_OPENED;
 892         mpw->pkts_n = 0;
 893         mpw->len = length;
 894         mpw->total_len = 0;
 895         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 896         mpw->wqe->eseg.mss = htons(length);
 897         mpw->wqe->eseg.inline_hdr_sz = 0;
 898         mpw->wqe->eseg.rsvd0 = 0;
 899         mpw->wqe->eseg.rsvd1 = 0;
 900         mpw->wqe->eseg.rsvd2 = 0;
 901         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 902                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 903         mpw->wqe->ctrl[2] = 0;
 904         mpw->wqe->ctrl[3] = 0;
 905         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 906                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 907         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 908                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 909         mpw->data.dseg[2] = &(*dseg)[0];
 910         mpw->data.dseg[3] = &(*dseg)[1];
 911         mpw->data.dseg[4] = &(*dseg)[2];
 912 }
 913
 914 /**
 915  * Close a MPW session.
 916  *
 917  * @param txq
 918  *   Pointer to TX queue structure.
 919  * @param mpw
 920  *   Pointer to MPW session structure.
 921  */
 922 static inline void
 923 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 924 {
 925         unsigned int num = mpw->pkts_n;
 926
 927         /*
 928          * Store size in multiple of 16 bytes. Control and Ethernet segments
 929          * count as 2.
 930          */
 931         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 932         mpw->state = MLX5_MPW_STATE_CLOSED;
 933         if (num < 3)
 934                 ++txq->wqe_ci;
 935         else
 936                 txq->wqe_ci += 2;
 937         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 938         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 939 }
 940
 941 /**
 942  * DPDK callback for TX with MPW support.
 943  *
 944  * @param dpdk_txq
 945  *   Generic pointer to TX queue structure.
 946  * @param[in] pkts
 947  *   Packets to transmit.
 948  * @param pkts_n
 949  *   Number of packets in array.
 950  *
 951  * @return
 952  *   Number of packets successfully transmitted (<= pkts_n).
 953  */
 954 uint16_t
 955 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 956 {
 957         struct txq *txq = (struct txq *)dpdk_txq;
 958         uint16_t elts_head = txq->elts_head;
 959         const uint16_t elts_n = 1 << txq->elts_n;
 960         const uint16_t elts_m = elts_n - 1;
 961         unsigned int i = 0;
 962         unsigned int j = 0;
 963         uint16_t max_elts;
 964         uint16_t max_wqe;
 965         unsigned int comp;
 966         struct mlx5_mpw mpw = {
 967                 .state = MLX5_MPW_STATE_CLOSED,
 968         };
 969
 970         if (unlikely(!pkts_n))
 971                 return 0;
 972         /* Prefetch first packet cacheline. */
 973         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 974         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 975         /* Start processing. */
 976         txq_complete(txq);
 977         max_elts = (elts_n - (elts_head - txq->elts_tail));
 978         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 979         if (unlikely(!max_wqe))
 980                 return 0;
 981         do {
 982                 struct rte_mbuf *buf = *(pkts++);
 983                 uint32_t length;
 984                 unsigned int segs_n = buf->nb_segs;
 985                 uint32_t cs_flags = 0;
 986
 987                 /*
 988                  * Make sure there is enough room to store this packet and
 989                  * that one ring entry remains unused.
 990                  */
 991                 assert(segs_n);
 992                 if (max_elts < segs_n)
 993                         break;
 994                 /* Do not bother with large packets MPW cannot handle. */
 995                 if (segs_n > MLX5_MPW_DSEG_MAX)
 996                         break;
 997                 max_elts -= segs_n;
 998                 --pkts_n;
 999                 /* Should we enable HW CKSUM offload */
1000                 if (buf->ol_flags &
1001                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1002                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1003                 /* Retrieve packet information. */
1004                 length = PKT_LEN(buf);
1005                 assert(length);
1006                 /* Start new session if packet differs. */
1007                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1008                     ((mpw.len != length) ||
1009                      (segs_n != 1) ||
1010                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1011                         mlx5_mpw_close(txq, &mpw);
1012                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1013                         /*
1014                          * Multi-Packet WQE consumes at most two WQE.
1015                          * mlx5_mpw_new() expects to be able to use such
1016                          * resources.
1017                          */
1018                         if (unlikely(max_wqe < 2))
1019                                 break;
1020                         max_wqe -= 2;
1021                         mlx5_mpw_new(txq, &mpw, length);
1022                         mpw.wqe->eseg.cs_flags = cs_flags;
1023                 }
1024                 /* Multi-segment packets must be alone in their MPW. */
1025                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1026 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1027                 length = 0;
1028 #endif
1029                 do {
1030                         volatile struct mlx5_wqe_data_seg *dseg;
1031                         uintptr_t addr;
1032
1033                         assert(buf);
1034                         (*txq->elts)[elts_head++ & elts_m] = buf;
1035                         dseg = mpw.data.dseg[mpw.pkts_n];
1036                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1037                         *dseg = (struct mlx5_wqe_data_seg){
1038                                 .byte_count = htonl(DATA_LEN(buf)),
1039                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1040                                 .addr = htonll(addr),
1041                         };
1042 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1043                         length += DATA_LEN(buf);
1044 #endif
1045                         buf = buf->next;
1046                         ++mpw.pkts_n;
1047                         ++j;
1048                 } while (--segs_n);
1049                 assert(length == mpw.len);
1050                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1051                         mlx5_mpw_close(txq, &mpw);
1052 #ifdef MLX5_PMD_SOFT_COUNTERS
1053                 /* Increment sent bytes counter. */
1054                 txq->stats.obytes += length;
1055 #endif
1056                 ++i;
1057         } while (pkts_n);
1058         /* Take a shortcut if nothing must be sent. */
1059         if (unlikely(i == 0))
1060                 return 0;
1061         /* Check whether completion threshold has been reached. */
1062         /* "j" includes both packets and segments. */
1063         comp = txq->elts_comp + j;
1064         if (comp >= MLX5_TX_COMP_THRESH) {
1065                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1066
1067                 /* Request completion on last WQE. */
1068                 wqe->ctrl[2] = htonl(8);
1069                 /* Save elts_head in unused "immediate" field of WQE. */
1070                 wqe->ctrl[3] = elts_head;
1071                 txq->elts_comp = 0;
1072         } else {
1073                 txq->elts_comp = comp;
1074         }
1075 #ifdef MLX5_PMD_SOFT_COUNTERS
1076         /* Increment sent packets counter. */
1077         txq->stats.opackets += i;
1078 #endif
1079         /* Ring QP doorbell. */
1080         if (mpw.state == MLX5_MPW_STATE_OPENED)
1081                 mlx5_mpw_close(txq, &mpw);
1082         mlx5_tx_dbrec(txq, mpw.wqe);
1083         txq->elts_head = elts_head;
1084         return i;
1085 }
1086
1087 /**
1088  * Open a MPW inline session.
1089  *
1090  * @param txq
1091  *   Pointer to TX queue structure.
1092  * @param mpw
1093  *   Pointer to MPW session structure.
1094  * @param length
1095  *   Packet length.
1096  */
1097 static inline void
1098 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1099 {
1100         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1101         struct mlx5_wqe_inl_small *inl;
1102
1103         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1104         mpw->pkts_n = 0;
1105         mpw->len = length;
1106         mpw->total_len = 0;
1107         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1108         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1109                                   (txq->wqe_ci << 8) |
1110                                   MLX5_OPCODE_TSO);
1111         mpw->wqe->ctrl[2] = 0;
1112         mpw->wqe->ctrl[3] = 0;
1113         mpw->wqe->eseg.mss = htons(length);
1114         mpw->wqe->eseg.inline_hdr_sz = 0;
1115         mpw->wqe->eseg.cs_flags = 0;
1116         mpw->wqe->eseg.rsvd0 = 0;
1117         mpw->wqe->eseg.rsvd1 = 0;
1118         mpw->wqe->eseg.rsvd2 = 0;
1119         inl = (struct mlx5_wqe_inl_small *)
1120                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1121         mpw->data.raw = (uint8_t *)&inl->raw;
1122 }
1123
1124 /**
1125  * Close a MPW inline session.
1126  *
1127  * @param txq
1128  *   Pointer to TX queue structure.
1129  * @param mpw
1130  *   Pointer to MPW session structure.
1131  */
1132 static inline void
1133 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1134 {
1135         unsigned int size;
1136         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1137                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1138
1139         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1140         /*
1141          * Store size in multiple of 16 bytes. Control and Ethernet segments
1142          * count as 2.
1143          */
1144         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1145         mpw->state = MLX5_MPW_STATE_CLOSED;
1146         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1147         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1148 }
1149
1150 /**
1151  * DPDK callback for TX with MPW inline support.
1152  *
1153  * @param dpdk_txq
1154  *   Generic pointer to TX queue structure.
1155  * @param[in] pkts
1156  *   Packets to transmit.
1157  * @param pkts_n
1158  *   Number of packets in array.
1159  *
1160  * @return
1161  *   Number of packets successfully transmitted (<= pkts_n).
1162  */
1163 uint16_t
1164 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1165                          uint16_t pkts_n)
1166 {
1167         struct txq *txq = (struct txq *)dpdk_txq;
1168         uint16_t elts_head = txq->elts_head;
1169         const uint16_t elts_n = 1 << txq->elts_n;
1170         const uint16_t elts_m = elts_n - 1;
1171         unsigned int i = 0;
1172         unsigned int j = 0;
1173         uint16_t max_elts;
1174         uint16_t max_wqe;
1175         unsigned int comp;
1176         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1177         struct mlx5_mpw mpw = {
1178                 .state = MLX5_MPW_STATE_CLOSED,
1179         };
1180         /*
1181          * Compute the maximum number of WQE which can be consumed by inline
1182          * code.
1183          * - 2 DSEG for:
1184          *   - 1 control segment,
1185          *   - 1 Ethernet segment,
1186          * - N Dseg from the inline request.
1187          */
1188         const unsigned int wqe_inl_n =
1189                 ((2 * MLX5_WQE_DWORD_SIZE +
1190                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1191                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1192
1193         if (unlikely(!pkts_n))
1194                 return 0;
1195         /* Prefetch first packet cacheline. */
1196         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1197         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1198         /* Start processing. */
1199         txq_complete(txq);
1200         max_elts = (elts_n - (elts_head - txq->elts_tail));
1201         do {
1202                 struct rte_mbuf *buf = *(pkts++);
1203                 uintptr_t addr;
1204                 uint32_t length;
1205                 unsigned int segs_n = buf->nb_segs;
1206                 uint32_t cs_flags = 0;
1207
1208                 /*
1209                  * Make sure there is enough room to store this packet and
1210                  * that one ring entry remains unused.
1211                  */
1212                 assert(segs_n);
1213                 if (max_elts < segs_n)
1214                         break;
1215                 /* Do not bother with large packets MPW cannot handle. */
1216                 if (segs_n > MLX5_MPW_DSEG_MAX)
1217                         break;
1218                 max_elts -= segs_n;
1219                 --pkts_n;
1220                 /*
1221                  * Compute max_wqe in case less WQE were consumed in previous
1222                  * iteration.
1223                  */
1224                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1225                 /* Should we enable HW CKSUM offload */
1226                 if (buf->ol_flags &
1227                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1228                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1229                 /* Retrieve packet information. */
1230                 length = PKT_LEN(buf);
1231                 /* Start new session if packet differs. */
1232                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1233                         if ((mpw.len != length) ||
1234                             (segs_n != 1) ||
1235                             (mpw.wqe->eseg.cs_flags != cs_flags))
1236                                 mlx5_mpw_close(txq, &mpw);
1237                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1238                         if ((mpw.len != length) ||
1239                             (segs_n != 1) ||
1240                             (length > inline_room) ||
1241                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1242                                 mlx5_mpw_inline_close(txq, &mpw);
1243                                 inline_room =
1244                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1245                         }
1246                 }
1247                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1248                         if ((segs_n != 1) ||
1249                             (length > inline_room)) {
1250                                 /*
1251                                  * Multi-Packet WQE consumes at most two WQE.
1252                                  * mlx5_mpw_new() expects to be able to use
1253                                  * such resources.
1254                                  */
1255                                 if (unlikely(max_wqe < 2))
1256                                         break;
1257                                 max_wqe -= 2;
1258                                 mlx5_mpw_new(txq, &mpw, length);
1259                                 mpw.wqe->eseg.cs_flags = cs_flags;
1260                         } else {
1261                                 if (unlikely(max_wqe < wqe_inl_n))
1262                                         break;
1263                                 max_wqe -= wqe_inl_n;
1264                                 mlx5_mpw_inline_new(txq, &mpw, length);
1265                                 mpw.wqe->eseg.cs_flags = cs_flags;
1266                         }
1267                 }
1268                 /* Multi-segment packets must be alone in their MPW. */
1269                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1270                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1271                         assert(inline_room ==
1272                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1273 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1274                         length = 0;
1275 #endif
1276                         do {
1277                                 volatile struct mlx5_wqe_data_seg *dseg;
1278
1279                                 assert(buf);
1280                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1281                                 dseg = mpw.data.dseg[mpw.pkts_n];
1282                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1283                                 *dseg = (struct mlx5_wqe_data_seg){
1284                                         .byte_count = htonl(DATA_LEN(buf)),
1285                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1286                                         .addr = htonll(addr),
1287                                 };
1288 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1289                                 length += DATA_LEN(buf);
1290 #endif
1291                                 buf = buf->next;
1292                                 ++mpw.pkts_n;
1293                                 ++j;
1294                         } while (--segs_n);
1295                         assert(length == mpw.len);
1296                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1297                                 mlx5_mpw_close(txq, &mpw);
1298                 } else {
1299                         unsigned int max;
1300
1301                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1302                         assert(length <= inline_room);
1303                         assert(length == DATA_LEN(buf));
1304                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1305                         (*txq->elts)[elts_head++ & elts_m] = buf;
1306                         /* Maximum number of bytes before wrapping. */
1307                         max = ((((uintptr_t)(txq->wqes)) +
1308                                 (1 << txq->wqe_n) *
1309                                 MLX5_WQE_SIZE) -
1310                                (uintptr_t)mpw.data.raw);
1311                         if (length > max) {
1312                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1313                                            (void *)addr,
1314                                            max);
1315                                 mpw.data.raw = (volatile void *)txq->wqes;
1316                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1317                                            (void *)(addr + max),
1318                                            length - max);
1319                                 mpw.data.raw += length - max;
1320                         } else {
1321                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1322                                            (void *)addr,
1323                                            length);
1324
1325                                 if (length == max)
1326                                         mpw.data.raw =
1327                                                 (volatile void *)txq->wqes;
1328                                 else
1329                                         mpw.data.raw += length;
1330                         }
1331                         ++mpw.pkts_n;
1332                         mpw.total_len += length;
1333                         ++j;
1334                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1335                                 mlx5_mpw_inline_close(txq, &mpw);
1336                                 inline_room =
1337                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1338                         } else {
1339                                 inline_room -= length;
1340                         }
1341                 }
1342 #ifdef MLX5_PMD_SOFT_COUNTERS
1343                 /* Increment sent bytes counter. */
1344                 txq->stats.obytes += length;
1345 #endif
1346                 ++i;
1347         } while (pkts_n);
1348         /* Take a shortcut if nothing must be sent. */
1349         if (unlikely(i == 0))
1350                 return 0;
1351         /* Check whether completion threshold has been reached. */
1352         /* "j" includes both packets and segments. */
1353         comp = txq->elts_comp + j;
1354         if (comp >= MLX5_TX_COMP_THRESH) {
1355                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1356
1357                 /* Request completion on last WQE. */
1358                 wqe->ctrl[2] = htonl(8);
1359                 /* Save elts_head in unused "immediate" field of WQE. */
1360                 wqe->ctrl[3] = elts_head;
1361                 txq->elts_comp = 0;
1362         } else {
1363                 txq->elts_comp = comp;
1364         }
1365 #ifdef MLX5_PMD_SOFT_COUNTERS
1366         /* Increment sent packets counter. */
1367         txq->stats.opackets += i;
1368 #endif
1369         /* Ring QP doorbell. */
1370         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1371                 mlx5_mpw_inline_close(txq, &mpw);
1372         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1373                 mlx5_mpw_close(txq, &mpw);
1374         mlx5_tx_dbrec(txq, mpw.wqe);
1375         txq->elts_head = elts_head;
1376         return i;
1377 }
1378
1379 /**
1380  * Open an Enhanced MPW session.
1381  *
1382  * @param txq
1383  *   Pointer to TX queue structure.
1384  * @param mpw
1385  *   Pointer to MPW session structure.
1386  * @param length
1387  *   Packet length.
1388  */
1389 static inline void
1390 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1391 {
1392         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1393
1394         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1395         mpw->pkts_n = 0;
1396         mpw->total_len = sizeof(struct mlx5_wqe);
1397         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1398         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1399                                   (txq->wqe_ci << 8) |
1400                                   MLX5_OPCODE_ENHANCED_MPSW);
1401         mpw->wqe->ctrl[2] = 0;
1402         mpw->wqe->ctrl[3] = 0;
1403         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1404         if (unlikely(padding)) {
1405                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1406
1407                 /* Pad the first 2 DWORDs with zero-length inline header. */
1408                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1409                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1410                         htonl(MLX5_INLINE_SEG);
1411                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1412                 /* Start from the next WQEBB. */
1413                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1414         } else {
1415                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1416         }
1417 }
1418
1419 /**
1420  * Close an Enhanced MPW session.
1421  *
1422  * @param txq
1423  *   Pointer to TX queue structure.
1424  * @param mpw
1425  *   Pointer to MPW session structure.
1426  *
1427  * @return
1428  *   Number of consumed WQEs.
1429  */
1430 static inline uint16_t
1431 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1432 {
1433         uint16_t ret;
1434
1435         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1436          * count as 2.
1437          */
1438         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1439         mpw->state = MLX5_MPW_STATE_CLOSED;
1440         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1441         txq->wqe_ci += ret;
1442         return ret;
1443 }
1444
1445 /**
1446  * DPDK callback for TX with Enhanced MPW support.
1447  *
1448  * @param dpdk_txq
1449  *   Generic pointer to TX queue structure.
1450  * @param[in] pkts
1451  *   Packets to transmit.
1452  * @param pkts_n
1453  *   Number of packets in array.
1454  *
1455  * @return
1456  *   Number of packets successfully transmitted (<= pkts_n).
1457  */
1458 uint16_t
1459 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1460 {
1461         struct txq *txq = (struct txq *)dpdk_txq;
1462         uint16_t elts_head = txq->elts_head;
1463         const uint16_t elts_n = 1 << txq->elts_n;
1464         const uint16_t elts_m = elts_n - 1;
1465         unsigned int i = 0;
1466         unsigned int j = 0;
1467         uint16_t max_elts;
1468         uint16_t max_wqe;
1469         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1470         unsigned int mpw_room = 0;
1471         unsigned int inl_pad = 0;
1472         uint32_t inl_hdr;
1473         struct mlx5_mpw mpw = {
1474                 .state = MLX5_MPW_STATE_CLOSED,
1475         };
1476
1477         if (unlikely(!pkts_n))
1478                 return 0;
1479         /* Start processing. */
1480         txq_complete(txq);
1481         max_elts = (elts_n - (elts_head - txq->elts_tail));
1482         /* A CQE slot must always be available. */
1483         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1484         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1485         if (unlikely(!max_wqe))
1486                 return 0;
1487         do {
1488                 struct rte_mbuf *buf = *(pkts++);
1489                 uintptr_t addr;
1490                 uint64_t naddr;
1491                 unsigned int n;
1492                 unsigned int do_inline = 0; /* Whether inline is possible. */
1493                 uint32_t length;
1494                 unsigned int segs_n = buf->nb_segs;
1495                 uint32_t cs_flags = 0;
1496
1497                 /*
1498                  * Make sure there is enough room to store this packet and
1499                  * that one ring entry remains unused.
1500                  */
1501                 assert(segs_n);
1502                 if (max_elts - j < segs_n)
1503                         break;
1504                 /* Do not bother with large packets MPW cannot handle. */
1505                 if (segs_n > MLX5_MPW_DSEG_MAX)
1506                         break;
1507                 /* Should we enable HW CKSUM offload. */
1508                 if (buf->ol_flags &
1509                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1510                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1511                 /* Retrieve packet information. */
1512                 length = PKT_LEN(buf);
1513                 /* Start new session if:
1514                  * - multi-segment packet
1515                  * - no space left even for a dseg
1516                  * - next packet can be inlined with a new WQE
1517                  * - cs_flag differs
1518                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1519                  * segmented packet.
1520                  */
1521                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1522                         if ((segs_n != 1) ||
1523                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1524                               mpw_room) ||
1525                             (length <= txq->inline_max_packet_sz &&
1526                              inl_pad + sizeof(inl_hdr) + length >
1527                               mpw_room) ||
1528                             (mpw.wqe->eseg.cs_flags != cs_flags))
1529                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1530                 }
1531                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1532                         if (unlikely(segs_n != 1)) {
1533                                 /* Fall back to legacy MPW.
1534                                  * A MPW session consumes 2 WQEs at most to
1535                                  * include MLX5_MPW_DSEG_MAX pointers.
1536                                  */
1537                                 if (unlikely(max_wqe < 2))
1538                                         break;
1539                                 mlx5_mpw_new(txq, &mpw, length);
1540                         } else {
1541                                 /* In Enhanced MPW, inline as much as the budget
1542                                  * is allowed. The remaining space is to be
1543                                  * filled with dsegs. If the title WQEBB isn't
1544                                  * padded, it will have 2 dsegs there.
1545                                  */
1546                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1547                                             (max_inline ? max_inline :
1548                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1549                                             MLX5_WQE_SIZE);
1550                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1551                                               mpw_room))
1552                                         break;
1553                                 /* Don't pad the title WQEBB to not waste WQ. */
1554                                 mlx5_empw_new(txq, &mpw, 0);
1555                                 mpw_room -= mpw.total_len;
1556                                 inl_pad = 0;
1557                                 do_inline =
1558                                         length <= txq->inline_max_packet_sz &&
1559                                         sizeof(inl_hdr) + length <= mpw_room &&
1560                                         !txq->mpw_hdr_dseg;
1561                         }
1562                         mpw.wqe->eseg.cs_flags = cs_flags;
1563                 } else {
1564                         /* Evaluate whether the next packet can be inlined.
1565                          * Inlininig is possible when:
1566                          * - length is less than configured value
1567                          * - length fits for remaining space
1568                          * - not required to fill the title WQEBB with dsegs
1569                          */
1570                         do_inline =
1571                                 length <= txq->inline_max_packet_sz &&
1572                                 inl_pad + sizeof(inl_hdr) + length <=
1573                                  mpw_room &&
1574                                 (!txq->mpw_hdr_dseg ||
1575                                  mpw.total_len >= MLX5_WQE_SIZE);
1576                 }
1577                 /* Multi-segment packets must be alone in their MPW. */
1578                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1579                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1580 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1581                         length = 0;
1582 #endif
1583                         do {
1584                                 volatile struct mlx5_wqe_data_seg *dseg;
1585
1586                                 assert(buf);
1587                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1588                                 dseg = mpw.data.dseg[mpw.pkts_n];
1589                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1590                                 *dseg = (struct mlx5_wqe_data_seg){
1591                                         .byte_count = htonl(DATA_LEN(buf)),
1592                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1593                                         .addr = htonll(addr),
1594                                 };
1595 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1596                                 length += DATA_LEN(buf);
1597 #endif
1598                                 buf = buf->next;
1599                                 ++j;
1600                                 ++mpw.pkts_n;
1601                         } while (--segs_n);
1602                         /* A multi-segmented packet takes one MPW session.
1603                          * TODO: Pack more multi-segmented packets if possible.
1604                          */
1605                         mlx5_mpw_close(txq, &mpw);
1606                         if (mpw.pkts_n < 3)
1607                                 max_wqe--;
1608                         else
1609                                 max_wqe -= 2;
1610                 } else if (do_inline) {
1611                         /* Inline packet into WQE. */
1612                         unsigned int max;
1613
1614                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1615                         assert(length == DATA_LEN(buf));
1616                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1617                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1618                         mpw.data.raw = (volatile void *)
1619                                 ((uintptr_t)mpw.data.raw + inl_pad);
1620                         max = tx_mlx5_wq_tailroom(txq,
1621                                         (void *)(uintptr_t)mpw.data.raw);
1622                         /* Copy inline header. */
1623                         mpw.data.raw = (volatile void *)
1624                                 mlx5_copy_to_wq(
1625                                           (void *)(uintptr_t)mpw.data.raw,
1626                                           &inl_hdr,
1627                                           sizeof(inl_hdr),
1628                                           (void *)(uintptr_t)txq->wqes,
1629                                           max);
1630                         max = tx_mlx5_wq_tailroom(txq,
1631                                         (void *)(uintptr_t)mpw.data.raw);
1632                         /* Copy packet data. */
1633                         mpw.data.raw = (volatile void *)
1634                                 mlx5_copy_to_wq(
1635                                           (void *)(uintptr_t)mpw.data.raw,
1636                                           (void *)addr,
1637                                           length,
1638                                           (void *)(uintptr_t)txq->wqes,
1639                                           max);
1640                         ++mpw.pkts_n;
1641                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1642                         /* No need to get completion as the entire packet is
1643                          * copied to WQ. Free the buf right away.
1644                          */
1645                         rte_pktmbuf_free_seg(buf);
1646                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1647                         /* Add pad in the next packet if any. */
1648                         inl_pad = (((uintptr_t)mpw.data.raw +
1649                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1650                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1651                                   (uintptr_t)mpw.data.raw;
1652                 } else {
1653                         /* No inline. Load a dseg of packet pointer. */
1654                         volatile rte_v128u32_t *dseg;
1655
1656                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1657                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1658                         assert(length == DATA_LEN(buf));
1659                         if (!tx_mlx5_wq_tailroom(txq,
1660                                         (void *)((uintptr_t)mpw.data.raw
1661                                                 + inl_pad)))
1662                                 dseg = (volatile void *)txq->wqes;
1663                         else
1664                                 dseg = (volatile void *)
1665                                         ((uintptr_t)mpw.data.raw +
1666                                          inl_pad);
1667                         (*txq->elts)[elts_head++ & elts_m] = buf;
1668                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1669                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1670                                 rte_prefetch2((void *)(addr +
1671                                                 n * RTE_CACHE_LINE_SIZE));
1672                         naddr = htonll(addr);
1673                         *dseg = (rte_v128u32_t) {
1674                                 htonl(length),
1675                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1676                                 naddr,
1677                                 naddr >> 32,
1678                         };
1679                         mpw.data.raw = (volatile void *)(dseg + 1);
1680                         mpw.total_len += (inl_pad + sizeof(*dseg));
1681                         ++j;
1682                         ++mpw.pkts_n;
1683                         mpw_room -= (inl_pad + sizeof(*dseg));
1684                         inl_pad = 0;
1685                 }
1686 #ifdef MLX5_PMD_SOFT_COUNTERS
1687                 /* Increment sent bytes counter. */
1688                 txq->stats.obytes += length;
1689 #endif
1690                 ++i;
1691         } while (i < pkts_n);
1692         /* Take a shortcut if nothing must be sent. */
1693         if (unlikely(i == 0))
1694                 return 0;
1695         /* Check whether completion threshold has been reached. */
1696         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1697                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1698                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1699                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1700
1701                 /* Request completion on last WQE. */
1702                 wqe->ctrl[2] = htonl(8);
1703                 /* Save elts_head in unused "immediate" field of WQE. */
1704                 wqe->ctrl[3] = elts_head;
1705                 txq->elts_comp = 0;
1706                 txq->mpw_comp = txq->wqe_ci;
1707                 txq->cq_pi++;
1708         } else {
1709                 txq->elts_comp += j;
1710         }
1711 #ifdef MLX5_PMD_SOFT_COUNTERS
1712         /* Increment sent packets counter. */
1713         txq->stats.opackets += i;
1714 #endif
1715         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1716                 mlx5_empw_close(txq, &mpw);
1717         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1718                 mlx5_mpw_close(txq, &mpw);
1719         /* Ring QP doorbell. */
1720         mlx5_tx_dbrec(txq, mpw.wqe);
1721         txq->elts_head = elts_head;
1722         return i;
1723 }
1724
1725 /**
1726  * Translate RX completion flags to packet type.
1727  *
1728  * @param[in] cqe
1729  *   Pointer to CQE.
1730  *
1731  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1732  *
1733  * @return
1734  *   Packet type for struct rte_mbuf.
1735  */
1736 static inline uint32_t
1737 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1738 {
1739         uint32_t pkt_type;
1740         uint16_t flags = ntohs(cqe->hdr_type_etc);
1741
1742         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1743                 pkt_type =
1744                         TRANSPOSE(flags,
1745                                   MLX5_CQE_RX_IPV4_PACKET,
1746                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1747                         TRANSPOSE(flags,
1748                                   MLX5_CQE_RX_IPV6_PACKET,
1749                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1750                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1751                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1752                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1753         } else {
1754                 pkt_type =
1755                         TRANSPOSE(flags,
1756                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1757                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1758                         TRANSPOSE(flags,
1759                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1760                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1761         }
1762         return pkt_type;
1763 }
1764
1765 /**
1766  * Get size of the next packet for a given CQE. For compressed CQEs, the
1767  * consumer index is updated only once all packets of the current one have
1768  * been processed.
1769  *
1770  * @param rxq
1771  *   Pointer to RX queue.
1772  * @param cqe
1773  *   CQE to process.
1774  * @param[out] rss_hash
1775  *   Packet RSS Hash result.
1776  *
1777  * @return
1778  *   Packet size in bytes (0 if there is none), -1 in case of completion
1779  *   with error.
1780  */
1781 static inline int
1782 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1783                  uint16_t cqe_cnt, uint32_t *rss_hash)
1784 {
1785         struct rxq_zip *zip = &rxq->zip;
1786         uint16_t cqe_n = cqe_cnt + 1;
1787         int len = 0;
1788         uint16_t idx, end;
1789
1790         /* Process compressed data in the CQE and mini arrays. */
1791         if (zip->ai) {
1792                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1793                         (volatile struct mlx5_mini_cqe8 (*)[8])
1794                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1795
1796                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1797                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1798                 if ((++zip->ai & 7) == 0) {
1799                         /* Invalidate consumed CQEs */
1800                         idx = zip->ca;
1801                         end = zip->na;
1802                         while (idx != end) {
1803                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1804                                         MLX5_CQE_INVALIDATE;
1805                                 ++idx;
1806                         }
1807                         /*
1808                          * Increment consumer index to skip the number of
1809                          * CQEs consumed. Hardware leaves holes in the CQ
1810                          * ring for software use.
1811                          */
1812                         zip->ca = zip->na;
1813                         zip->na += 8;
1814                 }
1815                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1816                         /* Invalidate the rest */
1817                         idx = zip->ca;
1818                         end = zip->cq_ci;
1819
1820                         while (idx != end) {
1821                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1822                                         MLX5_CQE_INVALIDATE;
1823                                 ++idx;
1824                         }
1825                         rxq->cq_ci = zip->cq_ci;
1826                         zip->ai = 0;
1827                 }
1828         /* No compressed data, get next CQE and verify if it is compressed. */
1829         } else {
1830                 int ret;
1831                 int8_t op_own;
1832
1833                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1834                 if (unlikely(ret == 1))
1835                         return 0;
1836                 ++rxq->cq_ci;
1837                 op_own = cqe->op_own;
1838                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1839                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1840                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1841                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1842                                                           cqe_cnt]);
1843
1844                         /* Fix endianness. */
1845                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1846                         /*
1847                          * Current mini array position is the one returned by
1848                          * check_cqe64().
1849                          *
1850                          * If completion comprises several mini arrays, as a
1851                          * special case the second one is located 7 CQEs after
1852                          * the initial CQE instead of 8 for subsequent ones.
1853                          */
1854                         zip->ca = rxq->cq_ci;
1855                         zip->na = zip->ca + 7;
1856                         /* Compute the next non compressed CQE. */
1857                         --rxq->cq_ci;
1858                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1859                         /* Get packet size to return. */
1860                         len = ntohl((*mc)[0].byte_cnt);
1861                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1862                         zip->ai = 1;
1863                         /* Prefetch all the entries to be invalidated */
1864                         idx = zip->ca;
1865                         end = zip->cq_ci;
1866                         while (idx != end) {
1867                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1868                                 ++idx;
1869                         }
1870                 } else {
1871                         len = ntohl(cqe->byte_cnt);
1872                         *rss_hash = ntohl(cqe->rx_hash_res);
1873                 }
1874                 /* Error while receiving packet. */
1875                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1876                         return -1;
1877         }
1878         return len;
1879 }
1880
1881 /**
1882  * Translate RX completion flags to offload flags.
1883  *
1884  * @param[in] rxq
1885  *   Pointer to RX queue structure.
1886  * @param[in] cqe
1887  *   Pointer to CQE.
1888  *
1889  * @return
1890  *   Offload flags (ol_flags) for struct rte_mbuf.
1891  */
1892 static inline uint32_t
1893 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1894 {
1895         uint32_t ol_flags = 0;
1896         uint16_t flags = ntohs(cqe->hdr_type_etc);
1897
1898         ol_flags =
1899                 TRANSPOSE(flags,
1900                           MLX5_CQE_RX_L3_HDR_VALID,
1901                           PKT_RX_IP_CKSUM_GOOD) |
1902                 TRANSPOSE(flags,
1903                           MLX5_CQE_RX_L4_HDR_VALID,
1904                           PKT_RX_L4_CKSUM_GOOD);
1905         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1906                 ol_flags |=
1907                         TRANSPOSE(flags,
1908                                   MLX5_CQE_RX_L3_HDR_VALID,
1909                                   PKT_RX_IP_CKSUM_GOOD) |
1910                         TRANSPOSE(flags,
1911                                   MLX5_CQE_RX_L4_HDR_VALID,
1912                                   PKT_RX_L4_CKSUM_GOOD);
1913         return ol_flags;
1914 }
1915
1916 /**
1917  * DPDK callback for RX.
1918  *
1919  * @param dpdk_rxq
1920  *   Generic pointer to RX queue structure.
1921  * @param[out] pkts
1922  *   Array to store received packets.
1923  * @param pkts_n
1924  *   Maximum number of packets in array.
1925  *
1926  * @return
1927  *   Number of packets successfully received (<= pkts_n).
1928  */
1929 uint16_t
1930 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1931 {
1932         struct rxq *rxq = dpdk_rxq;
1933         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1934         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1935         const unsigned int sges_n = rxq->sges_n;
1936         struct rte_mbuf *pkt = NULL;
1937         struct rte_mbuf *seg = NULL;
1938         volatile struct mlx5_cqe *cqe =
1939                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1940         unsigned int i = 0;
1941         unsigned int rq_ci = rxq->rq_ci << sges_n;
1942         int len = 0; /* keep its value across iterations. */
1943
1944         while (pkts_n) {
1945                 unsigned int idx = rq_ci & wqe_cnt;
1946                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1947                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1948                 uint32_t rss_hash_res = 0;
1949
1950                 if (pkt)
1951                         NEXT(seg) = rep;
1952                 seg = rep;
1953                 rte_prefetch0(seg);
1954                 rte_prefetch0(cqe);
1955                 rte_prefetch0(wqe);
1956                 rep = rte_mbuf_raw_alloc(rxq->mp);
1957                 if (unlikely(rep == NULL)) {
1958                         ++rxq->stats.rx_nombuf;
1959                         if (!pkt) {
1960                                 /*
1961                                  * no buffers before we even started,
1962                                  * bail out silently.
1963                                  */
1964                                 break;
1965                         }
1966                         while (pkt != seg) {
1967                                 assert(pkt != (*rxq->elts)[idx]);
1968                                 rep = NEXT(pkt);
1969                                 NEXT(pkt) = NULL;
1970                                 NB_SEGS(pkt) = 1;
1971                                 rte_mbuf_raw_free(pkt);
1972                                 pkt = rep;
1973                         }
1974                         break;
1975                 }
1976                 if (!pkt) {
1977                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1978                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1979                                                &rss_hash_res);
1980                         if (!len) {
1981                                 rte_mbuf_raw_free(rep);
1982                                 break;
1983                         }
1984                         if (unlikely(len == -1)) {
1985                                 /* RX error, packet is likely too large. */
1986                                 rte_mbuf_raw_free(rep);
1987                                 ++rxq->stats.idropped;
1988                                 goto skip;
1989                         }
1990                         pkt = seg;
1991                         assert(len >= (rxq->crc_present << 2));
1992                         /* Update packet information. */
1993                         pkt->packet_type = 0;
1994                         pkt->ol_flags = 0;
1995                         if (rss_hash_res && rxq->rss_hash) {
1996                                 pkt->hash.rss = rss_hash_res;
1997                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1998                         }
1999                         if (rxq->mark &&
2000                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2001                                 pkt->ol_flags |= PKT_RX_FDIR;
2002                                 if (cqe->sop_drop_qpn !=
2003                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2004                                         uint32_t mark = cqe->sop_drop_qpn;
2005
2006                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2007                                         pkt->hash.fdir.hi =
2008                                                 mlx5_flow_mark_get(mark);
2009                                 }
2010                         }
2011                         if (rxq->csum | rxq->csum_l2tun) {
2012                                 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2013                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2014                         }
2015                         if (rxq->vlan_strip &&
2016                             (cqe->hdr_type_etc &
2017                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2018                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2019                                         PKT_RX_VLAN_STRIPPED;
2020                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2021                         }
2022                         if (rxq->crc_present)
2023                                 len -= ETHER_CRC_LEN;
2024                         PKT_LEN(pkt) = len;
2025                 }
2026                 DATA_LEN(rep) = DATA_LEN(seg);
2027                 PKT_LEN(rep) = PKT_LEN(seg);
2028                 SET_DATA_OFF(rep, DATA_OFF(seg));
2029                 PORT(rep) = PORT(seg);
2030                 (*rxq->elts)[idx] = rep;
2031                 /*
2032                  * Fill NIC descriptor with the new buffer.  The lkey and size
2033                  * of the buffers are already known, only the buffer address
2034                  * changes.
2035                  */
2036                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2037                 if (len > DATA_LEN(seg)) {
2038                         len -= DATA_LEN(seg);
2039                         ++NB_SEGS(pkt);
2040                         ++rq_ci;
2041                         continue;
2042                 }
2043                 DATA_LEN(seg) = len;
2044 #ifdef MLX5_PMD_SOFT_COUNTERS
2045                 /* Increment bytes counter. */
2046                 rxq->stats.ibytes += PKT_LEN(pkt);
2047 #endif
2048                 /* Return packet. */
2049                 *(pkts++) = pkt;
2050                 pkt = NULL;
2051                 --pkts_n;
2052                 ++i;
2053 skip:
2054                 /* Align consumer index to the next stride. */
2055                 rq_ci >>= sges_n;
2056                 ++rq_ci;
2057                 rq_ci <<= sges_n;
2058         }
2059         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2060                 return 0;
2061         /* Update the consumer index. */
2062         rxq->rq_ci = rq_ci >> sges_n;
2063         rte_wmb();
2064         *rxq->cq_db = htonl(rxq->cq_ci);
2065         rte_wmb();
2066         *rxq->rq_db = htonl(rxq->rq_ci);
2067 #ifdef MLX5_PMD_SOFT_COUNTERS
2068         /* Increment packets counter. */
2069         rxq->stats.ipackets += i;
2070 #endif
2071         return i;
2072 }
2073
2074 /**
2075  * Dummy DPDK callback for TX.
2076  *
2077  * This function is used to temporarily replace the real callback during
2078  * unsafe control operations on the queue, or in case of error.
2079  *
2080  * @param dpdk_txq
2081  *   Generic pointer to TX queue structure.
2082  * @param[in] pkts
2083  *   Packets to transmit.
2084  * @param pkts_n
2085  *   Number of packets in array.
2086  *
2087  * @return
2088  *   Number of packets successfully transmitted (<= pkts_n).
2089  */
2090 uint16_t
2091 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2092 {
2093         (void)dpdk_txq;
2094         (void)pkts;
2095         (void)pkts_n;
2096         return 0;
2097 }
2098
2099 /**
2100  * Dummy DPDK callback for RX.
2101  *
2102  * This function is used to temporarily replace the real callback during
2103  * unsafe control operations on the queue, or in case of error.
2104  *
2105  * @param dpdk_rxq
2106  *   Generic pointer to RX queue structure.
2107  * @param[out] pkts
2108  *   Array to store received packets.
2109  * @param pkts_n
2110  *   Maximum number of packets in array.
2111  *
2112  * @return
2113  *   Number of packets successfully received (<= pkts_n).
2114  */
2115 uint16_t
2116 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2117 {
2118         (void)dpdk_rxq;
2119         (void)pkts;
2120         (void)pkts_n;
2121         return 0;
2122 }