1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include <mlx5_devx_cmds.h>
33 #include <mlx5_common.h>
35 #include "mlx5_defs.h"
37 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
41 /* TX burst subroutines return codes. */
42 enum mlx5_txcmp_code {
43 MLX5_TXCMP_CODE_EXIT = 0,
44 MLX5_TXCMP_CODE_ERROR,
45 MLX5_TXCMP_CODE_SINGLE,
46 MLX5_TXCMP_CODE_MULTI,
52 * These defines are used to configure Tx burst routine option set
53 * supported at compile time. The not specified options are optimized out
54 * out due to if conditions can be explicitly calculated at compile time.
55 * The offloads with bigger runtime check (require more CPU cycles to
56 * skip) overhead should have the bigger index - this is needed to
57 * select the better matching routine function if no exact match and
58 * some offloads are not actually requested.
60 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
61 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
62 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
63 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
64 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
65 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
66 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
67 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
68 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
70 /* The most common offloads groups. */
71 #define MLX5_TXOFF_CONFIG_NONE 0
72 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
73 MLX5_TXOFF_CONFIG_TSO | \
74 MLX5_TXOFF_CONFIG_SWP | \
75 MLX5_TXOFF_CONFIG_CSUM | \
76 MLX5_TXOFF_CONFIG_INLINE | \
77 MLX5_TXOFF_CONFIG_VLAN | \
78 MLX5_TXOFF_CONFIG_METADATA)
80 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
82 #define MLX5_TXOFF_DECL(func, olx) \
83 static uint16_t mlx5_tx_burst_##func(void *txq, \
84 struct rte_mbuf **pkts, \
87 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
88 pkts, pkts_n, (olx)); \
91 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
93 static __rte_always_inline uint32_t
94 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
96 static __rte_always_inline int
97 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
98 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
100 static __rte_always_inline uint32_t
101 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
103 static __rte_always_inline void
104 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
105 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
107 static __rte_always_inline void
108 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
109 const unsigned int strd_n);
112 mlx5_queue_state_modify(struct rte_eth_dev *dev,
113 struct mlx5_mp_arg_queue_state_modify *sm);
116 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
117 volatile struct mlx5_cqe *restrict cqe,
121 mlx5_lro_update_hdr(uint8_t *restrict padd,
122 volatile struct mlx5_cqe *restrict cqe,
125 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
126 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
129 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
130 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
133 * Build a table to translate Rx completion flags to packet type.
135 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
138 mlx5_set_ptype_table(void)
141 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
143 /* Last entry must not be overwritten, reserved for errored packet. */
144 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
145 (*p)[i] = RTE_PTYPE_UNKNOWN;
147 * The index to the array should have:
148 * bit[1:0] = l3_hdr_type
149 * bit[4:2] = l4_hdr_type
152 * bit[7] = outer_l3_type
155 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
157 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 RTE_PTYPE_L4_NONFRAG;
159 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
160 RTE_PTYPE_L4_NONFRAG;
162 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
169 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
184 /* Repeat with outer_l3_type being set. Just in case. */
185 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_L4_NONFRAG;
187 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 RTE_PTYPE_L4_NONFRAG;
189 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
193 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
195 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
197 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
199 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
203 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
210 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
211 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L4_NONFRAG;
214 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
216 RTE_PTYPE_INNER_L4_NONFRAG;
217 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
218 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
219 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L4_NONFRAG;
221 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L4_NONFRAG;
224 /* Tunneled - Fragmented */
225 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_FRAG;
228 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
229 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L4_FRAG;
231 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
232 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L4_FRAG;
234 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L4_FRAG;
238 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
262 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_TCP;
265 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
266 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L4_TCP;
268 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
269 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L4_TCP;
271 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L4_TCP;
275 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_UDP;
278 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
279 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L4_UDP;
281 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
282 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
283 RTE_PTYPE_INNER_L4_UDP;
284 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
285 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
286 RTE_PTYPE_INNER_L4_UDP;
290 * Build a table to translate packet to checksum type of Verbs.
293 mlx5_set_cksum_table(void)
299 * The index should have:
300 * bit[0] = PKT_TX_TCP_SEG
301 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
302 * bit[4] = PKT_TX_IP_CKSUM
303 * bit[8] = PKT_TX_OUTER_IP_CKSUM
306 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
309 /* Tunneled packet. */
310 if (i & (1 << 8)) /* Outer IP. */
311 v |= MLX5_ETH_WQE_L3_CSUM;
312 if (i & (1 << 4)) /* Inner IP. */
313 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
314 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
315 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
318 if (i & (1 << 4)) /* IP. */
319 v |= MLX5_ETH_WQE_L3_CSUM;
320 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
321 v |= MLX5_ETH_WQE_L4_CSUM;
323 mlx5_cksum_table[i] = v;
328 * Build a table to translate packet type of mbuf to SWP type of Verbs.
331 mlx5_set_swp_types_table(void)
337 * The index should have:
338 * bit[0:1] = PKT_TX_L4_MASK
339 * bit[4] = PKT_TX_IPV6
340 * bit[8] = PKT_TX_OUTER_IPV6
341 * bit[9] = PKT_TX_OUTER_UDP
343 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
346 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
348 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
350 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
351 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
352 v |= MLX5_ETH_WQE_L4_INNER_UDP;
353 mlx5_swp_types_table[i] = v;
358 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
359 * Flags must be preliminary initialized to zero.
362 * Pointer to burst routine local context.
364 * Pointer to store Software Parser flags
366 * Configured Tx offloads mask. It is fully defined at
367 * compile time and may be used for optimization.
370 * Software Parser offsets packed in dword.
371 * Software Parser flags are set by pointer.
373 static __rte_always_inline uint32_t
374 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
379 unsigned int idx, off;
382 if (!MLX5_TXOFF_CONFIG(SWP))
384 ol = loc->mbuf->ol_flags;
385 tunnel = ol & PKT_TX_TUNNEL_MASK;
387 * Check whether Software Parser is required.
388 * Only customized tunnels may ask for.
390 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
393 * The index should have:
394 * bit[0:1] = PKT_TX_L4_MASK
395 * bit[4] = PKT_TX_IPV6
396 * bit[8] = PKT_TX_OUTER_IPV6
397 * bit[9] = PKT_TX_OUTER_UDP
399 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
400 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
401 *swp_flags = mlx5_swp_types_table[idx];
403 * Set offsets for SW parser. Since ConnectX-5, SW parser just
404 * complements HW parser. SW parser starts to engage only if HW parser
405 * can't reach a header. For the older devices, HW parser will not kick
406 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
407 * should be set regardless of HW offload.
409 off = loc->mbuf->outer_l2_len;
410 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
411 off += sizeof(struct rte_vlan_hdr);
412 set = (off >> 1) << 8; /* Outer L3 offset. */
413 off += loc->mbuf->outer_l3_len;
414 if (tunnel == PKT_TX_TUNNEL_UDP)
415 set |= off >> 1; /* Outer L4 offset. */
416 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
417 const uint64_t csum = ol & PKT_TX_L4_MASK;
418 off += loc->mbuf->l2_len;
419 set |= (off >> 1) << 24; /* Inner L3 offset. */
420 if (csum == PKT_TX_TCP_CKSUM ||
421 csum == PKT_TX_UDP_CKSUM ||
422 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
423 off += loc->mbuf->l3_len;
424 set |= (off >> 1) << 16; /* Inner L4 offset. */
427 set = rte_cpu_to_le_32(set);
432 * Convert the Checksum offloads to Verbs.
435 * Pointer to the mbuf.
438 * Converted checksum flags.
440 static __rte_always_inline uint8_t
441 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
444 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
445 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
446 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
449 * The index should have:
450 * bit[0] = PKT_TX_TCP_SEG
451 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
452 * bit[4] = PKT_TX_IP_CKSUM
453 * bit[8] = PKT_TX_OUTER_IP_CKSUM
456 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
457 return mlx5_cksum_table[idx];
461 * Internal function to compute the number of used descriptors in an RX queue
467 * The number of used rx descriptor.
470 rx_queue_count(struct mlx5_rxq_data *rxq)
472 struct rxq_zip *zip = &rxq->zip;
473 volatile struct mlx5_cqe *cqe;
474 const unsigned int cqe_n = (1 << rxq->cqe_n);
475 const unsigned int cqe_cnt = cqe_n - 1;
479 /* if we are processing a compressed cqe */
481 used = zip->cqe_cnt - zip->ca;
487 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
488 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
492 op_own = cqe->op_own;
493 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
494 n = rte_be_to_cpu_32(cqe->byte_cnt);
499 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
501 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
506 * DPDK callback to check the status of a rx descriptor.
511 * The index of the descriptor in the ring.
514 * The status of the tx descriptor.
517 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
519 struct mlx5_rxq_data *rxq = rx_queue;
520 struct mlx5_rxq_ctrl *rxq_ctrl =
521 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
522 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
524 if (dev->rx_pkt_burst != mlx5_rx_burst) {
528 if (offset >= (1 << rxq->elts_n)) {
532 if (offset < rx_queue_count(rxq))
533 return RTE_ETH_RX_DESC_DONE;
534 return RTE_ETH_RX_DESC_AVAIL;
538 * DPDK callback to get the number of used descriptors in a RX queue
541 * Pointer to the device structure.
547 * The number of used rx descriptor.
548 * -EINVAL if the queue is invalid
551 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
553 struct mlx5_priv *priv = dev->data->dev_private;
554 struct mlx5_rxq_data *rxq;
556 if (dev->rx_pkt_burst != mlx5_rx_burst) {
560 rxq = (*priv->rxqs)[rx_queue_id];
565 return rx_queue_count(rxq);
568 #define MLX5_SYSTEM_LOG_DIR "/var/log"
570 * Dump debug information to log file.
575 * If not NULL this string is printed as a header to the output
576 * and the output will be in hexadecimal view.
578 * This is the buffer address to print out.
580 * The number of bytes to dump out.
583 mlx5_dump_debug_information(const char *fname, const char *hex_title,
584 const void *buf, unsigned int hex_len)
588 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
589 fd = fopen(path, "a+");
591 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
592 MKSTR(path2, "./%s", fname);
593 fd = fopen(path2, "a+");
595 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
598 DRV_LOG(INFO, "New debug dump in file %s", path2);
600 DRV_LOG(INFO, "New debug dump in file %s", path);
603 rte_hexdump(fd, hex_title, buf, hex_len);
605 fprintf(fd, "%s", (const char *)buf);
606 fprintf(fd, "\n\n\n");
611 * Move QP from error state to running state and initialize indexes.
614 * Pointer to TX queue control structure.
617 * 0 on success, else -1.
620 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
622 struct mlx5_mp_arg_queue_state_modify sm = {
624 .queue_id = txq_ctrl->txq.idx,
627 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
629 txq_ctrl->txq.wqe_ci = 0;
630 txq_ctrl->txq.wqe_pi = 0;
631 txq_ctrl->txq.elts_comp = 0;
635 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
637 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
639 static const uint8_t magic[] = "seen";
643 for (i = 0; i < sizeof(magic); ++i)
644 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
646 err_cqe->rsvd1[i] = magic[i];
655 * Pointer to TX queue structure.
657 * Pointer to the error CQE.
660 * Negative value if queue recovery failed, otherwise
661 * the error completion entry is handled successfully.
664 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
665 volatile struct mlx5_err_cqe *err_cqe)
667 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
668 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
669 struct mlx5_txq_ctrl *txq_ctrl =
670 container_of(txq, struct mlx5_txq_ctrl, txq);
671 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
672 int seen = check_err_cqe_seen(err_cqe);
674 if (!seen && txq_ctrl->dump_file_n <
675 txq_ctrl->priv->config.max_dump_files_num) {
676 MKSTR(err_str, "Unexpected CQE error syndrome "
677 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
678 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
679 txq->cqe_s, txq->qp_num_8s >> 8,
680 rte_be_to_cpu_16(err_cqe->wqe_counter),
681 txq->wqe_ci, txq->cq_ci);
682 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
683 PORT_ID(txq_ctrl->priv), txq->idx,
684 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
685 mlx5_dump_debug_information(name, NULL, err_str, 0);
686 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
687 (const void *)((uintptr_t)
691 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
692 (const void *)((uintptr_t)
696 txq_ctrl->dump_file_n++;
700 * Count errors in WQEs units.
701 * Later it can be improved to count error packets,
702 * for example, by SQ parsing to find how much packets
703 * should be counted for each WQE.
705 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
707 if (tx_recover_qp(txq_ctrl)) {
708 /* Recovering failed - retry later on the same WQE. */
711 /* Release all the remaining buffers. */
712 txq_free_elts(txq_ctrl);
718 * Translate RX completion flags to packet type.
721 * Pointer to RX queue structure.
725 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
728 * Packet type for struct rte_mbuf.
730 static inline uint32_t
731 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
734 uint8_t pinfo = cqe->pkt_info;
735 uint16_t ptype = cqe->hdr_type_etc;
738 * The index to the array should have:
739 * bit[1:0] = l3_hdr_type
740 * bit[4:2] = l4_hdr_type
743 * bit[7] = outer_l3_type
745 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
746 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
750 * Initialize Rx WQ and indexes.
753 * Pointer to RX queue structure.
756 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
758 const unsigned int wqe_n = 1 << rxq->elts_n;
761 for (i = 0; (i != wqe_n); ++i) {
762 volatile struct mlx5_wqe_data_seg *scat;
766 if (mlx5_rxq_mprq_enabled(rxq)) {
767 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
769 scat = &((volatile struct mlx5_wqe_mprq *)
771 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
772 1 << rxq->strd_num_n);
773 byte_count = (1 << rxq->strd_sz_n) *
774 (1 << rxq->strd_num_n);
776 struct rte_mbuf *buf = (*rxq->elts)[i];
778 scat = &((volatile struct mlx5_wqe_data_seg *)
780 addr = rte_pktmbuf_mtod(buf, uintptr_t);
781 byte_count = DATA_LEN(buf);
783 /* scat->addr must be able to store a pointer. */
784 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
785 *scat = (struct mlx5_wqe_data_seg){
786 .addr = rte_cpu_to_be_64(addr),
787 .byte_count = rte_cpu_to_be_32(byte_count),
788 .lkey = mlx5_rx_addr2mr(rxq, addr),
791 rxq->consumed_strd = 0;
792 rxq->decompressed = 0;
794 rxq->zip = (struct rxq_zip){
797 /* Update doorbell counter. */
798 rxq->rq_ci = wqe_n >> rxq->sges_n;
800 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
804 * Modify a Verbs/DevX queue state.
805 * This must be called from the primary process.
808 * Pointer to Ethernet device.
810 * State modify request parameters.
813 * 0 in case of success else non-zero value and rte_errno is set.
816 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
817 const struct mlx5_mp_arg_queue_state_modify *sm)
820 struct mlx5_priv *priv = dev->data->dev_private;
823 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
824 struct mlx5_rxq_ctrl *rxq_ctrl =
825 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
827 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
828 struct ibv_wq_attr mod = {
829 .attr_mask = IBV_WQ_ATTR_STATE,
830 .wq_state = sm->state,
833 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
834 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
835 struct mlx5_devx_modify_rq_attr rq_attr;
837 memset(&rq_attr, 0, sizeof(rq_attr));
838 if (sm->state == IBV_WQS_RESET) {
839 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
840 rq_attr.state = MLX5_RQC_STATE_RST;
841 } else if (sm->state == IBV_WQS_RDY) {
842 rq_attr.rq_state = MLX5_RQC_STATE_RST;
843 rq_attr.state = MLX5_RQC_STATE_RDY;
844 } else if (sm->state == IBV_WQS_ERR) {
845 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
846 rq_attr.state = MLX5_RQC_STATE_ERR;
848 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
852 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
853 sm->state, strerror(errno));
858 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
859 struct mlx5_txq_ctrl *txq_ctrl =
860 container_of(txq, struct mlx5_txq_ctrl, txq);
861 struct ibv_qp_attr mod = {
862 .qp_state = IBV_QPS_RESET,
863 .port_num = (uint8_t)priv->ibv_port,
865 struct ibv_qp *qp = txq_ctrl->obj->qp;
867 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
869 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
870 "%s", strerror(errno));
874 mod.qp_state = IBV_QPS_INIT;
875 ret = mlx5_glue->modify_qp(qp, &mod,
876 (IBV_QP_STATE | IBV_QP_PORT));
878 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
883 mod.qp_state = IBV_QPS_RTR;
884 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
886 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
891 mod.qp_state = IBV_QPS_RTS;
892 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
894 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
904 * Modify a Verbs queue state.
907 * Pointer to Ethernet device.
909 * State modify request parameters.
912 * 0 in case of success else non-zero value.
915 mlx5_queue_state_modify(struct rte_eth_dev *dev,
916 struct mlx5_mp_arg_queue_state_modify *sm)
920 switch (rte_eal_process_type()) {
921 case RTE_PROC_PRIMARY:
922 ret = mlx5_queue_state_modify_primary(dev, sm);
924 case RTE_PROC_SECONDARY:
925 ret = mlx5_mp_req_queue_state_modify(dev, sm);
935 * The function inserts the RQ state to reset when the first error CQE is
936 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
937 * it moves the RQ state to ready and initializes the RQ.
938 * Next CQE identification and error counting are in the caller responsibility.
941 * Pointer to RX queue structure.
943 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
944 * 0 when called from non-vectorized Rx burst.
947 * -1 in case of recovery error, otherwise the CQE status.
950 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
952 const uint16_t cqe_n = 1 << rxq->cqe_n;
953 const uint16_t cqe_mask = cqe_n - 1;
954 const unsigned int wqe_n = 1 << rxq->elts_n;
955 struct mlx5_rxq_ctrl *rxq_ctrl =
956 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
958 volatile struct mlx5_cqe *cqe;
959 volatile struct mlx5_err_cqe *err_cqe;
961 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
963 struct mlx5_mp_arg_queue_state_modify sm;
966 switch (rxq->err_state) {
967 case MLX5_RXQ_ERR_STATE_NO_ERROR:
968 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
970 case MLX5_RXQ_ERR_STATE_NEED_RESET:
972 sm.queue_id = rxq->idx;
973 sm.state = IBV_WQS_RESET;
974 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
976 if (rxq_ctrl->dump_file_n <
977 rxq_ctrl->priv->config.max_dump_files_num) {
978 MKSTR(err_str, "Unexpected CQE error syndrome "
979 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
980 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
981 rxq->cqn, rxq_ctrl->wqn,
982 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
983 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
984 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
985 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
986 mlx5_dump_debug_information(name, NULL, err_str, 0);
987 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
988 (const void *)((uintptr_t)
990 sizeof(*u.cqe) * cqe_n);
991 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
992 (const void *)((uintptr_t)
995 rxq_ctrl->dump_file_n++;
997 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
999 case MLX5_RXQ_ERR_STATE_NEED_READY:
1000 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1001 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1003 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1006 * The RQ consumer index must be zeroed while moving
1007 * from RESET state to RDY state.
1009 *rxq->rq_db = rte_cpu_to_be_32(0);
1012 sm.queue_id = rxq->idx;
1013 sm.state = IBV_WQS_RDY;
1014 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1018 const uint16_t q_mask = wqe_n - 1;
1020 struct rte_mbuf **elt;
1022 unsigned int n = wqe_n - (rxq->rq_ci -
1025 for (i = 0; i < (int)n; ++i) {
1026 elt_idx = (rxq->rq_ci + i) & q_mask;
1027 elt = &(*rxq->elts)[elt_idx];
1028 *elt = rte_mbuf_raw_alloc(rxq->mp);
1030 for (i--; i >= 0; --i) {
1031 elt_idx = (rxq->rq_ci +
1035 rte_pktmbuf_free_seg
1041 for (i = 0; i < (int)wqe_n; ++i) {
1042 elt = &(*rxq->elts)[i];
1044 (uint16_t)((*elt)->buf_len -
1045 rte_pktmbuf_headroom(*elt));
1047 /* Padding with a fake mbuf for vec Rx. */
1048 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1049 (*rxq->elts)[wqe_n + i] =
1052 mlx5_rxq_initialize(rxq);
1053 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1062 * Get size of the next packet for a given CQE. For compressed CQEs, the
1063 * consumer index is updated only once all packets of the current one have
1067 * Pointer to RX queue.
1071 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1075 * 0 in case of empty CQE, otherwise the packet size in bytes.
1078 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1079 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1081 struct rxq_zip *zip = &rxq->zip;
1082 uint16_t cqe_n = cqe_cnt + 1;
1088 /* Process compressed data in the CQE and mini arrays. */
1090 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1091 (volatile struct mlx5_mini_cqe8 (*)[8])
1092 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1095 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1096 *mcqe = &(*mc)[zip->ai & 7];
1097 if ((++zip->ai & 7) == 0) {
1098 /* Invalidate consumed CQEs */
1101 while (idx != end) {
1102 (*rxq->cqes)[idx & cqe_cnt].op_own =
1103 MLX5_CQE_INVALIDATE;
1107 * Increment consumer index to skip the number
1108 * of CQEs consumed. Hardware leaves holes in
1109 * the CQ ring for software use.
1114 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1115 /* Invalidate the rest */
1119 while (idx != end) {
1120 (*rxq->cqes)[idx & cqe_cnt].op_own =
1121 MLX5_CQE_INVALIDATE;
1124 rxq->cq_ci = zip->cq_ci;
1128 * No compressed data, get next CQE and verify if it is
1135 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1136 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1137 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1139 ret = mlx5_rx_err_handle(rxq, 0);
1140 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1148 op_own = cqe->op_own;
1149 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1150 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1151 (volatile struct mlx5_mini_cqe8 (*)[8])
1152 (uintptr_t)(&(*rxq->cqes)
1156 /* Fix endianness. */
1157 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1159 * Current mini array position is the one
1160 * returned by check_cqe64().
1162 * If completion comprises several mini arrays,
1163 * as a special case the second one is located
1164 * 7 CQEs after the initial CQE instead of 8
1165 * for subsequent ones.
1167 zip->ca = rxq->cq_ci;
1168 zip->na = zip->ca + 7;
1169 /* Compute the next non compressed CQE. */
1171 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1172 /* Get packet size to return. */
1173 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1176 /* Prefetch all to be invalidated */
1179 while (idx != end) {
1180 rte_prefetch0(&(*rxq->cqes)[(idx) &
1185 len = rte_be_to_cpu_32(cqe->byte_cnt);
1188 if (unlikely(rxq->err_state)) {
1189 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1190 ++rxq->stats.idropped;
1198 * Translate RX completion flags to offload flags.
1204 * Offload flags (ol_flags) for struct rte_mbuf.
1206 static inline uint32_t
1207 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1209 uint32_t ol_flags = 0;
1210 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1214 MLX5_CQE_RX_L3_HDR_VALID,
1215 PKT_RX_IP_CKSUM_GOOD) |
1217 MLX5_CQE_RX_L4_HDR_VALID,
1218 PKT_RX_L4_CKSUM_GOOD);
1223 * Fill in mbuf fields from RX completion flags.
1224 * Note that pkt->ol_flags should be initialized outside of this function.
1227 * Pointer to RX queue.
1232 * @param rss_hash_res
1233 * Packet RSS Hash result.
1236 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1237 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1239 /* Update packet information. */
1240 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1241 if (rss_hash_res && rxq->rss_hash) {
1242 pkt->hash.rss = rss_hash_res;
1243 pkt->ol_flags |= PKT_RX_RSS_HASH;
1245 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1246 pkt->ol_flags |= PKT_RX_FDIR;
1247 if (cqe->sop_drop_qpn !=
1248 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1249 uint32_t mark = cqe->sop_drop_qpn;
1251 pkt->ol_flags |= PKT_RX_FDIR_ID;
1252 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1255 if (rte_flow_dynf_metadata_avail() && cqe->flow_table_metadata) {
1256 pkt->ol_flags |= PKT_RX_DYNF_METADATA;
1257 *RTE_FLOW_DYNF_METADATA(pkt) = cqe->flow_table_metadata;
1260 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1261 if (rxq->vlan_strip &&
1262 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1263 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1264 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1266 if (rxq->hw_timestamp) {
1267 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1268 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1273 * DPDK callback for RX.
1276 * Generic pointer to RX queue structure.
1278 * Array to store received packets.
1280 * Maximum number of packets in array.
1283 * Number of packets successfully received (<= pkts_n).
1286 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1288 struct mlx5_rxq_data *rxq = dpdk_rxq;
1289 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1290 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1291 const unsigned int sges_n = rxq->sges_n;
1292 struct rte_mbuf *pkt = NULL;
1293 struct rte_mbuf *seg = NULL;
1294 volatile struct mlx5_cqe *cqe =
1295 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1297 unsigned int rq_ci = rxq->rq_ci << sges_n;
1298 int len = 0; /* keep its value across iterations. */
1301 unsigned int idx = rq_ci & wqe_cnt;
1302 volatile struct mlx5_wqe_data_seg *wqe =
1303 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1304 struct rte_mbuf *rep = (*rxq->elts)[idx];
1305 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1306 uint32_t rss_hash_res;
1314 rep = rte_mbuf_raw_alloc(rxq->mp);
1315 if (unlikely(rep == NULL)) {
1316 ++rxq->stats.rx_nombuf;
1319 * no buffers before we even started,
1320 * bail out silently.
1324 while (pkt != seg) {
1325 assert(pkt != (*rxq->elts)[idx]);
1329 rte_mbuf_raw_free(pkt);
1335 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1336 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1338 rte_mbuf_raw_free(rep);
1342 assert(len >= (rxq->crc_present << 2));
1343 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1344 /* If compressed, take hash result from mini-CQE. */
1345 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1347 mcqe->rx_hash_result);
1348 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1349 if (rxq->crc_present)
1350 len -= RTE_ETHER_CRC_LEN;
1352 if (cqe->lro_num_seg > 1) {
1354 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1356 pkt->ol_flags |= PKT_RX_LRO;
1357 pkt->tso_segsz = len / cqe->lro_num_seg;
1360 DATA_LEN(rep) = DATA_LEN(seg);
1361 PKT_LEN(rep) = PKT_LEN(seg);
1362 SET_DATA_OFF(rep, DATA_OFF(seg));
1363 PORT(rep) = PORT(seg);
1364 (*rxq->elts)[idx] = rep;
1366 * Fill NIC descriptor with the new buffer. The lkey and size
1367 * of the buffers are already known, only the buffer address
1370 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1371 /* If there's only one MR, no need to replace LKey in WQE. */
1372 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1373 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1374 if (len > DATA_LEN(seg)) {
1375 len -= DATA_LEN(seg);
1380 DATA_LEN(seg) = len;
1381 #ifdef MLX5_PMD_SOFT_COUNTERS
1382 /* Increment bytes counter. */
1383 rxq->stats.ibytes += PKT_LEN(pkt);
1385 /* Return packet. */
1390 /* Align consumer index to the next stride. */
1395 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1397 /* Update the consumer index. */
1398 rxq->rq_ci = rq_ci >> sges_n;
1400 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1402 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1403 #ifdef MLX5_PMD_SOFT_COUNTERS
1404 /* Increment packets counter. */
1405 rxq->stats.ipackets += i;
1411 * Update LRO packet TCP header.
1412 * The HW LRO feature doesn't update the TCP header after coalescing the
1413 * TCP segments but supplies information in CQE to fill it by SW.
1416 * Pointer to the TCP header.
1418 * Pointer to the completion entry..
1420 * The L3 pseudo-header checksum.
1423 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1424 volatile struct mlx5_cqe *restrict cqe,
1427 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1428 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1430 * The HW calculates only the TCP payload checksum, need to complete
1431 * the TCP header checksum and the L3 pseudo-header checksum.
1433 uint32_t csum = phcsum + cqe->csum;
1435 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1436 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1437 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1438 tcp->recv_ack = cqe->lro_ack_seq_num;
1439 tcp->rx_win = cqe->lro_tcp_win;
1441 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1442 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1444 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1445 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1446 csum = (~csum) & 0xffff;
1453 * Update LRO packet headers.
1454 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1455 * TCP segments but supply information in CQE to fill it by SW.
1458 * The packet address.
1460 * Pointer to the completion entry..
1462 * The packet length.
1465 mlx5_lro_update_hdr(uint8_t *restrict padd,
1466 volatile struct mlx5_cqe *restrict cqe,
1470 struct rte_ether_hdr *eth;
1471 struct rte_vlan_hdr *vlan;
1472 struct rte_ipv4_hdr *ipv4;
1473 struct rte_ipv6_hdr *ipv6;
1474 struct rte_tcp_hdr *tcp;
1479 uint16_t proto = h.eth->ether_type;
1483 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1484 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1485 proto = h.vlan->eth_proto;
1488 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1489 h.ipv4->time_to_live = cqe->lro_min_ttl;
1490 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1491 h.ipv4->hdr_checksum = 0;
1492 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1493 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1496 h.ipv6->hop_limits = cqe->lro_min_ttl;
1497 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1499 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1502 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1506 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1508 struct mlx5_mprq_buf *buf = opaque;
1510 if (rte_atomic16_read(&buf->refcnt) == 1) {
1511 rte_mempool_put(buf->mp, buf);
1512 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1513 rte_atomic16_set(&buf->refcnt, 1);
1514 rte_mempool_put(buf->mp, buf);
1519 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1521 mlx5_mprq_buf_free_cb(NULL, buf);
1525 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1526 const unsigned int strd_n)
1528 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1529 volatile struct mlx5_wqe_data_seg *wqe =
1530 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1533 assert(rep != NULL);
1534 /* Replace MPRQ buf. */
1535 (*rxq->mprq_bufs)[rq_idx] = rep;
1537 addr = mlx5_mprq_buf_addr(rep, strd_n);
1538 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1539 /* If there's only one MR, no need to replace LKey in WQE. */
1540 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1541 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1542 /* Stash a mbuf for next replacement. */
1543 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1544 rxq->mprq_repl = rep;
1546 rxq->mprq_repl = NULL;
1550 * DPDK callback for RX with Multi-Packet RQ support.
1553 * Generic pointer to RX queue structure.
1555 * Array to store received packets.
1557 * Maximum number of packets in array.
1560 * Number of packets successfully received (<= pkts_n).
1563 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1565 struct mlx5_rxq_data *rxq = dpdk_rxq;
1566 const unsigned int strd_n = 1 << rxq->strd_num_n;
1567 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1568 const unsigned int strd_shift =
1569 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1570 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1571 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1572 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1574 uint32_t rq_ci = rxq->rq_ci;
1575 uint16_t consumed_strd = rxq->consumed_strd;
1576 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1577 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1579 while (i < pkts_n) {
1580 struct rte_mbuf *pkt;
1588 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1589 uint32_t rss_hash_res = 0;
1590 uint8_t lro_num_seg;
1592 if (consumed_strd == strd_n) {
1593 /* Replace WQE only if the buffer is still in use. */
1594 if (rte_atomic16_read(&buf->refcnt) > 1) {
1595 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1596 /* Release the old buffer. */
1597 mlx5_mprq_buf_free(buf);
1598 } else if (unlikely(rxq->mprq_repl == NULL)) {
1599 struct mlx5_mprq_buf *rep;
1602 * Currently, the MPRQ mempool is out of buffer
1603 * and doing memcpy regardless of the size of Rx
1604 * packet. Retry allocation to get back to
1607 if (!rte_mempool_get(rxq->mprq_mp,
1609 rxq->mprq_repl = rep;
1611 /* Advance to the next WQE. */
1614 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1616 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1617 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1621 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1622 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1624 consumed_strd += strd_cnt;
1625 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1628 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1629 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1631 /* mini-CQE for MPRQ doesn't have hash result. */
1632 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1634 assert(strd_idx < strd_n);
1635 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1636 lro_num_seg = cqe->lro_num_seg;
1638 * Currently configured to receive a packet per a stride. But if
1639 * MTU is adjusted through kernel interface, device could
1640 * consume multiple strides without raising an error. In this
1641 * case, the packet should be dropped because it is bigger than
1642 * the max_rx_pkt_len.
1644 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1645 ++rxq->stats.idropped;
1648 pkt = rte_pktmbuf_alloc(rxq->mp);
1649 if (unlikely(pkt == NULL)) {
1650 ++rxq->stats.rx_nombuf;
1653 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1654 assert((int)len >= (rxq->crc_present << 2));
1655 if (rxq->crc_present)
1656 len -= RTE_ETHER_CRC_LEN;
1657 offset = strd_idx * strd_sz + strd_shift;
1658 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1660 * Memcpy packets to the target mbuf if:
1661 * - The size of packet is smaller than mprq_max_memcpy_len.
1662 * - Out of buffer in the Mempool for Multi-Packet RQ.
1664 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1666 * When memcpy'ing packet due to out-of-buffer, the
1667 * packet must be smaller than the target mbuf.
1669 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1670 rte_pktmbuf_free_seg(pkt);
1671 ++rxq->stats.idropped;
1674 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1675 DATA_LEN(pkt) = len;
1677 rte_iova_t buf_iova;
1678 struct rte_mbuf_ext_shared_info *shinfo;
1679 uint16_t buf_len = strd_cnt * strd_sz;
1682 /* Increment the refcnt of the whole chunk. */
1683 rte_atomic16_add_return(&buf->refcnt, 1);
1684 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1686 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1688 * MLX5 device doesn't use iova but it is necessary in a
1689 * case where the Rx packet is transmitted via a
1692 buf_iova = rte_mempool_virt2iova(buf) +
1693 RTE_PTR_DIFF(buf_addr, buf);
1694 shinfo = &buf->shinfos[strd_idx];
1695 rte_mbuf_ext_refcnt_set(shinfo, 1);
1697 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1698 * attaching the stride to mbuf and more offload flags
1699 * will be added below by calling rxq_cq_to_mbuf().
1700 * Other fields will be overwritten.
1702 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1704 /* Set mbuf head-room. */
1705 pkt->data_off = headroom_sz;
1706 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1708 * Prevent potential overflow due to MTU change through
1711 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1712 rte_pktmbuf_free_seg(pkt);
1713 ++rxq->stats.idropped;
1716 DATA_LEN(pkt) = len;
1718 * LRO packet may consume all the stride memory, in this
1719 * case packet head-room space is not guaranteed so must
1720 * to add an empty mbuf for the head-room.
1722 if (!rxq->strd_headroom_en) {
1723 struct rte_mbuf *headroom_mbuf =
1724 rte_pktmbuf_alloc(rxq->mp);
1726 if (unlikely(headroom_mbuf == NULL)) {
1727 rte_pktmbuf_free_seg(pkt);
1728 ++rxq->stats.rx_nombuf;
1731 PORT(pkt) = rxq->port_id;
1732 NEXT(headroom_mbuf) = pkt;
1733 pkt = headroom_mbuf;
1737 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1738 if (lro_num_seg > 1) {
1739 mlx5_lro_update_hdr(addr, cqe, len);
1740 pkt->ol_flags |= PKT_RX_LRO;
1741 pkt->tso_segsz = strd_sz;
1744 PORT(pkt) = rxq->port_id;
1745 #ifdef MLX5_PMD_SOFT_COUNTERS
1746 /* Increment bytes counter. */
1747 rxq->stats.ibytes += PKT_LEN(pkt);
1749 /* Return packet. */
1753 /* Update the consumer indexes. */
1754 rxq->consumed_strd = consumed_strd;
1756 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1757 if (rq_ci != rxq->rq_ci) {
1760 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1762 #ifdef MLX5_PMD_SOFT_COUNTERS
1763 /* Increment packets counter. */
1764 rxq->stats.ipackets += i;
1770 * Dummy DPDK callback for TX.
1772 * This function is used to temporarily replace the real callback during
1773 * unsafe control operations on the queue, or in case of error.
1776 * Generic pointer to TX queue structure.
1778 * Packets to transmit.
1780 * Number of packets in array.
1783 * Number of packets successfully transmitted (<= pkts_n).
1786 removed_tx_burst(void *dpdk_txq __rte_unused,
1787 struct rte_mbuf **pkts __rte_unused,
1788 uint16_t pkts_n __rte_unused)
1795 * Dummy DPDK callback for RX.
1797 * This function is used to temporarily replace the real callback during
1798 * unsafe control operations on the queue, or in case of error.
1801 * Generic pointer to RX queue structure.
1803 * Array to store received packets.
1805 * Maximum number of packets in array.
1808 * Number of packets successfully received (<= pkts_n).
1811 removed_rx_burst(void *dpdk_txq __rte_unused,
1812 struct rte_mbuf **pkts __rte_unused,
1813 uint16_t pkts_n __rte_unused)
1820 * Vectorized Rx/Tx routines are not compiled in when required vector
1821 * instructions are not supported on a target architecture. The following null
1822 * stubs are needed for linkage when those are not included outside of this file
1823 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1827 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1828 struct rte_mbuf **pkts __rte_unused,
1829 uint16_t pkts_n __rte_unused)
1835 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1841 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1847 * Free the mbufs from the linear array of pointers.
1850 * Pointer to array of packets to be free.
1852 * Number of packets to be freed.
1854 * Configured Tx offloads mask. It is fully defined at
1855 * compile time and may be used for optimization.
1857 static __rte_always_inline void
1858 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1859 unsigned int pkts_n,
1860 unsigned int olx __rte_unused)
1862 struct rte_mempool *pool = NULL;
1863 struct rte_mbuf **p_free = NULL;
1864 struct rte_mbuf *mbuf;
1865 unsigned int n_free = 0;
1868 * The implemented algorithm eliminates
1869 * copying pointers to temporary array
1870 * for rte_mempool_put_bulk() calls.
1877 * Decrement mbuf reference counter, detach
1878 * indirect and external buffers if needed.
1880 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1881 if (likely(mbuf != NULL)) {
1882 assert(mbuf == *pkts);
1883 if (likely(n_free != 0)) {
1884 if (unlikely(pool != mbuf->pool))
1885 /* From different pool. */
1888 /* Start new scan array. */
1895 if (unlikely(pkts_n == 0)) {
1901 * This happens if mbuf is still referenced.
1902 * We can't put it back to the pool, skip.
1906 if (unlikely(n_free != 0))
1907 /* There is some array to free.*/
1909 if (unlikely(pkts_n == 0))
1910 /* Last mbuf, nothing to free. */
1916 * This loop is implemented to avoid multiple
1917 * inlining of rte_mempool_put_bulk().
1923 * Free the array of pre-freed mbufs
1924 * belonging to the same memory pool.
1926 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1927 if (unlikely(mbuf != NULL)) {
1928 /* There is the request to start new scan. */
1933 if (likely(pkts_n != 0))
1936 * This is the last mbuf to be freed.
1937 * Do one more loop iteration to complete.
1938 * This is rare case of the last unique mbuf.
1943 if (likely(pkts_n == 0))
1952 * Free the mbuf from the elts ring buffer till new tail.
1955 * Pointer to Tx queue structure.
1957 * Index in elts to free up to, becomes new elts tail.
1959 * Configured Tx offloads mask. It is fully defined at
1960 * compile time and may be used for optimization.
1962 static __rte_always_inline void
1963 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1965 unsigned int olx __rte_unused)
1967 uint16_t n_elts = tail - txq->elts_tail;
1970 assert(n_elts <= txq->elts_s);
1972 * Implement a loop to support ring buffer wraparound
1973 * with single inlining of mlx5_tx_free_mbuf().
1978 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1979 part = RTE_MIN(part, n_elts);
1981 assert(part <= txq->elts_s);
1982 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1984 txq->elts_tail += part;
1990 * Store the mbuf being sent into elts ring buffer.
1991 * On Tx completion these mbufs will be freed.
1994 * Pointer to Tx queue structure.
1996 * Pointer to array of packets to be stored.
1998 * Number of packets to be stored.
2000 * Configured Tx offloads mask. It is fully defined at
2001 * compile time and may be used for optimization.
2003 static __rte_always_inline void
2004 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
2005 struct rte_mbuf **restrict pkts,
2006 unsigned int pkts_n,
2007 unsigned int olx __rte_unused)
2010 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2014 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2016 assert(part <= txq->elts_s);
2017 /* This code is a good candidate for vectorizing with SIMD. */
2018 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2020 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2021 txq->elts_head += pkts_n;
2022 if (unlikely(part < pkts_n))
2023 /* The copy is wrapping around the elts array. */
2024 rte_memcpy((void *)elts, (void *)(pkts + part),
2025 (pkts_n - part) * sizeof(struct rte_mbuf *));
2029 * Update completion queue consuming index via doorbell
2030 * and flush the completed data buffers.
2033 * Pointer to TX queue structure.
2034 * @param valid CQE pointer
2035 * if not NULL update txq->wqe_pi and flush the buffers
2037 * Configured Tx offloads mask. It is fully defined at
2038 * compile time and may be used for optimization.
2040 static __rte_always_inline void
2041 mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
2042 volatile struct mlx5_cqe *last_cqe,
2043 unsigned int olx __rte_unused)
2045 if (likely(last_cqe != NULL)) {
2048 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2049 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2050 if (likely(tail != txq->elts_tail)) {
2051 mlx5_tx_free_elts(txq, tail, olx);
2052 assert(tail == txq->elts_tail);
2058 * Manage TX completions. This routine checks the CQ for
2059 * arrived CQEs, deduces the last accomplished WQE in SQ,
2060 * updates SQ producing index and frees all completed mbufs.
2063 * Pointer to TX queue structure.
2065 * Configured Tx offloads mask. It is fully defined at
2066 * compile time and may be used for optimization.
2068 * NOTE: not inlined intentionally, it makes tx_burst
2069 * routine smaller, simple and faster - from experiments.
2072 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2073 unsigned int olx __rte_unused)
2075 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2076 volatile struct mlx5_cqe *last_cqe = NULL;
2077 uint16_t ci = txq->cq_ci;
2080 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2081 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2083 volatile struct mlx5_cqe *cqe;
2085 cqe = &txq->cqes[ci & txq->cqe_m];
2086 ret = check_cqe(cqe, txq->cqe_s, ci);
2087 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2088 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2089 /* No new CQEs in completion queue. */
2090 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2094 * Some error occurred, try to restart.
2095 * We have no barrier after WQE related Doorbell
2096 * written, make sure all writes are completed
2097 * here, before we might perform SQ reset.
2101 ret = mlx5_tx_error_cqe_handle
2102 (txq, (volatile struct mlx5_err_cqe *)cqe);
2103 if (unlikely(ret < 0)) {
2105 * Some error occurred on queue error
2106 * handling, we do not advance the index
2107 * here, allowing to retry on next call.
2112 * We are going to fetch all entries with
2113 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2114 * The send queue is supposed to be empty.
2121 /* Normal transmit completion. */
2122 assert(ci != txq->cq_pi);
2123 assert((txq->fcqs[ci & txq->cqe_m] >> 16) == cqe->wqe_counter);
2127 * We have to restrict the amount of processed CQEs
2128 * in one tx_burst routine call. The CQ may be large
2129 * and many CQEs may be updated by the NIC in one
2130 * transaction. Buffers freeing is time consuming,
2131 * multiple iterations may introduce significant
2134 if (likely(--count == 0))
2137 if (likely(ci != txq->cq_ci)) {
2139 * Update completion queue consuming index
2140 * and ring doorbell to notify hardware.
2142 rte_compiler_barrier();
2144 *txq->cq_db = rte_cpu_to_be_32(ci);
2145 mlx5_tx_comp_flush(txq, last_cqe, olx);
2150 * Check if the completion request flag should be set in the last WQE.
2151 * Both pushed mbufs and WQEs are monitored and the completion request
2152 * flag is set if any of thresholds is reached.
2155 * Pointer to TX queue structure.
2157 * Pointer to burst routine local context.
2159 * Configured Tx offloads mask. It is fully defined at
2160 * compile time and may be used for optimization.
2162 static __rte_always_inline void
2163 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2164 struct mlx5_txq_local *restrict loc,
2167 uint16_t head = txq->elts_head;
2170 part = MLX5_TXOFF_CONFIG(INLINE) ?
2171 0 : loc->pkts_sent - loc->pkts_copy;
2173 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2174 (MLX5_TXOFF_CONFIG(INLINE) &&
2175 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2176 volatile struct mlx5_wqe *last = loc->wqe_last;
2178 txq->elts_comp = head;
2179 if (MLX5_TXOFF_CONFIG(INLINE))
2180 txq->wqe_comp = txq->wqe_ci;
2181 /* Request unconditional completion on last WQE. */
2182 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2183 MLX5_COMP_MODE_OFFSET);
2184 /* Save elts_head in dedicated free on completion queue. */
2186 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2188 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2189 (last->cseg.opcode >> 8) << 16;
2191 /* A CQE slot must always be available. */
2192 assert((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2197 * DPDK callback to check the status of a tx descriptor.
2202 * The index of the descriptor in the ring.
2205 * The status of the tx descriptor.
2208 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2210 struct mlx5_txq_data *restrict txq = tx_queue;
2213 mlx5_tx_handle_completion(txq, 0);
2214 used = txq->elts_head - txq->elts_tail;
2216 return RTE_ETH_TX_DESC_FULL;
2217 return RTE_ETH_TX_DESC_DONE;
2221 * Build the Control Segment with specified opcode:
2222 * - MLX5_OPCODE_SEND
2223 * - MLX5_OPCODE_ENHANCED_MPSW
2227 * Pointer to TX queue structure.
2229 * Pointer to burst routine local context.
2231 * Pointer to WQE to fill with built Control Segment.
2233 * Supposed length of WQE in segments.
2235 * SQ WQE opcode to put into Control Segment.
2237 * Configured Tx offloads mask. It is fully defined at
2238 * compile time and may be used for optimization.
2240 static __rte_always_inline void
2241 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2242 struct mlx5_txq_local *restrict loc __rte_unused,
2243 struct mlx5_wqe *restrict wqe,
2245 unsigned int opcode,
2246 unsigned int olx __rte_unused)
2248 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2250 /* For legacy MPW replace the EMPW by TSO with modifier. */
2251 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2252 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2253 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2254 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2255 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2256 MLX5_COMP_MODE_OFFSET);
2257 cs->misc = RTE_BE32(0);
2261 * Build the Ethernet Segment without inlined data.
2262 * Supports Software Parser, Checksums and VLAN
2263 * insertion Tx offload features.
2266 * Pointer to TX queue structure.
2268 * Pointer to burst routine local context.
2270 * Pointer to WQE to fill with built Ethernet Segment.
2272 * Configured Tx offloads mask. It is fully defined at
2273 * compile time and may be used for optimization.
2275 static __rte_always_inline void
2276 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2277 struct mlx5_txq_local *restrict loc,
2278 struct mlx5_wqe *restrict wqe,
2281 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2285 * Calculate and set check sum flags first, dword field
2286 * in segment may be shared with Software Parser flags.
2288 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2289 es->flags = rte_cpu_to_le_32(csum);
2291 * Calculate and set Software Parser offsets and flags.
2292 * These flags a set for custom UDP and IP tunnel packets.
2294 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2295 /* Fill metadata field if needed. */
2296 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2297 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2298 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2299 /* Engage VLAN tag insertion feature if requested. */
2300 if (MLX5_TXOFF_CONFIG(VLAN) &&
2301 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2303 * We should get here only if device support
2304 * this feature correctly.
2306 assert(txq->vlan_en);
2307 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2308 loc->mbuf->vlan_tci);
2310 es->inline_hdr = RTE_BE32(0);
2315 * Build the Ethernet Segment with minimal inlined data
2316 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2317 * used to fill the gap in single WQEBB WQEs.
2318 * Supports Software Parser, Checksums and VLAN
2319 * insertion Tx offload features.
2322 * Pointer to TX queue structure.
2324 * Pointer to burst routine local context.
2326 * Pointer to WQE to fill with built Ethernet Segment.
2328 * Length of VLAN tag insertion if any.
2330 * Configured Tx offloads mask. It is fully defined at
2331 * compile time and may be used for optimization.
2333 static __rte_always_inline void
2334 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2335 struct mlx5_txq_local *restrict loc,
2336 struct mlx5_wqe *restrict wqe,
2340 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2342 uint8_t *psrc, *pdst;
2345 * Calculate and set check sum flags first, dword field
2346 * in segment may be shared with Software Parser flags.
2348 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2349 es->flags = rte_cpu_to_le_32(csum);
2351 * Calculate and set Software Parser offsets and flags.
2352 * These flags a set for custom UDP and IP tunnel packets.
2354 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2355 /* Fill metadata field if needed. */
2356 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2357 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2358 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2359 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2361 sizeof(rte_v128u32_t)),
2362 "invalid Ethernet Segment data size");
2363 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2365 sizeof(struct rte_vlan_hdr) +
2366 2 * RTE_ETHER_ADDR_LEN),
2367 "invalid Ethernet Segment data size");
2368 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2369 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2370 es->inline_data = *(unaligned_uint16_t *)psrc;
2371 psrc += sizeof(uint16_t);
2372 pdst = (uint8_t *)(es + 1);
2373 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2374 /* Implement VLAN tag insertion as part inline data. */
2375 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2376 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2377 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2378 /* Insert VLAN ethertype + VLAN tag. */
2379 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2380 ((RTE_ETHER_TYPE_VLAN << 16) |
2381 loc->mbuf->vlan_tci);
2382 pdst += sizeof(struct rte_vlan_hdr);
2383 /* Copy the rest two bytes from packet data. */
2384 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2385 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2387 /* Fill the gap in the title WQEBB with inline data. */
2388 rte_mov16(pdst, psrc);
2393 * Build the Ethernet Segment with entire packet
2394 * data inlining. Checks the boundary of WQEBB and
2395 * ring buffer wrapping, supports Software Parser,
2396 * Checksums and VLAN insertion Tx offload features.
2399 * Pointer to TX queue structure.
2401 * Pointer to burst routine local context.
2403 * Pointer to WQE to fill with built Ethernet Segment.
2405 * Length of VLAN tag insertion if any.
2407 * Length of data to inline (VLAN included, if any).
2409 * TSO flag, set mss field from the packet.
2411 * Configured Tx offloads mask. It is fully defined at
2412 * compile time and may be used for optimization.
2415 * Pointer to the next Data Segment (aligned and wrapped around).
2417 static __rte_always_inline struct mlx5_wqe_dseg *
2418 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2419 struct mlx5_txq_local *restrict loc,
2420 struct mlx5_wqe *restrict wqe,
2426 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2428 uint8_t *psrc, *pdst;
2432 * Calculate and set check sum flags first, dword field
2433 * in segment may be shared with Software Parser flags.
2435 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2438 csum |= loc->mbuf->tso_segsz;
2439 es->flags = rte_cpu_to_be_32(csum);
2441 es->flags = rte_cpu_to_le_32(csum);
2444 * Calculate and set Software Parser offsets and flags.
2445 * These flags a set for custom UDP and IP tunnel packets.
2447 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2448 /* Fill metadata field if needed. */
2449 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2450 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2451 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2452 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2454 sizeof(rte_v128u32_t)),
2455 "invalid Ethernet Segment data size");
2456 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2458 sizeof(struct rte_vlan_hdr) +
2459 2 * RTE_ETHER_ADDR_LEN),
2460 "invalid Ethernet Segment data size");
2461 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2462 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2463 es->inline_data = *(unaligned_uint16_t *)psrc;
2464 psrc += sizeof(uint16_t);
2465 pdst = (uint8_t *)(es + 1);
2466 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2467 /* Implement VLAN tag insertion as part inline data. */
2468 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2469 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2470 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2471 /* Insert VLAN ethertype + VLAN tag. */
2472 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2473 ((RTE_ETHER_TYPE_VLAN << 16) |
2474 loc->mbuf->vlan_tci);
2475 pdst += sizeof(struct rte_vlan_hdr);
2476 /* Copy the rest two bytes from packet data. */
2477 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2478 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2479 psrc += sizeof(uint16_t);
2481 /* Fill the gap in the title WQEBB with inline data. */
2482 rte_mov16(pdst, psrc);
2483 psrc += sizeof(rte_v128u32_t);
2485 pdst = (uint8_t *)(es + 2);
2486 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2487 assert(pdst < (uint8_t *)txq->wqes_end);
2488 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2490 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2491 return (struct mlx5_wqe_dseg *)pdst;
2494 * The WQEBB space availability is checked by caller.
2495 * Here we should be aware of WQE ring buffer wraparound only.
2497 part = (uint8_t *)txq->wqes_end - pdst;
2498 part = RTE_MIN(part, inlen);
2500 rte_memcpy(pdst, psrc, part);
2502 if (likely(!inlen)) {
2504 * If return value is not used by the caller
2505 * the code below will be optimized out.
2508 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2509 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2510 pdst = (uint8_t *)txq->wqes;
2511 return (struct mlx5_wqe_dseg *)pdst;
2513 pdst = (uint8_t *)txq->wqes;
2520 * Copy data from chain of mbuf to the specified linear buffer.
2521 * Checksums and VLAN insertion Tx offload features. If data
2522 * from some mbuf copied completely this mbuf is freed. Local
2523 * structure is used to keep the byte stream state.
2526 * Pointer to the destination linear buffer.
2528 * Pointer to burst routine local context.
2530 * Length of data to be copied.
2532 * Configured Tx offloads mask. It is fully defined at
2533 * compile time and may be used for optimization.
2535 static __rte_always_inline void
2536 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2537 struct mlx5_txq_local *restrict loc,
2539 unsigned int olx __rte_unused)
2541 struct rte_mbuf *mbuf;
2542 unsigned int part, dlen;
2547 /* Allow zero length packets, must check first. */
2548 dlen = rte_pktmbuf_data_len(loc->mbuf);
2549 if (dlen <= loc->mbuf_off) {
2550 /* Exhausted packet, just free. */
2552 loc->mbuf = mbuf->next;
2553 rte_pktmbuf_free_seg(mbuf);
2555 assert(loc->mbuf_nseg > 1);
2560 dlen -= loc->mbuf_off;
2561 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2563 part = RTE_MIN(len, dlen);
2564 rte_memcpy(pdst, psrc, part);
2565 loc->mbuf_off += part;
2568 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2570 /* Exhausted packet, just free. */
2572 loc->mbuf = mbuf->next;
2573 rte_pktmbuf_free_seg(mbuf);
2575 assert(loc->mbuf_nseg >= 1);
2585 * Build the Ethernet Segment with inlined data from
2586 * multi-segment packet. Checks the boundary of WQEBB
2587 * and ring buffer wrapping, supports Software Parser,
2588 * Checksums and VLAN insertion Tx offload features.
2591 * Pointer to TX queue structure.
2593 * Pointer to burst routine local context.
2595 * Pointer to WQE to fill with built Ethernet Segment.
2597 * Length of VLAN tag insertion if any.
2599 * Length of data to inline (VLAN included, if any).
2601 * TSO flag, set mss field from the packet.
2603 * Configured Tx offloads mask. It is fully defined at
2604 * compile time and may be used for optimization.
2607 * Pointer to the next Data Segment (aligned and
2608 * possible NOT wrapped around - caller should do
2609 * wrapping check on its own).
2611 static __rte_always_inline struct mlx5_wqe_dseg *
2612 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2613 struct mlx5_txq_local *restrict loc,
2614 struct mlx5_wqe *restrict wqe,
2620 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2626 * Calculate and set check sum flags first, uint32_t field
2627 * in segment may be shared with Software Parser flags.
2629 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2632 csum |= loc->mbuf->tso_segsz;
2633 es->flags = rte_cpu_to_be_32(csum);
2635 es->flags = rte_cpu_to_le_32(csum);
2638 * Calculate and set Software Parser offsets and flags.
2639 * These flags a set for custom UDP and IP tunnel packets.
2641 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2642 /* Fill metadata field if needed. */
2643 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2644 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2645 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2646 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2648 sizeof(rte_v128u32_t)),
2649 "invalid Ethernet Segment data size");
2650 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2652 sizeof(struct rte_vlan_hdr) +
2653 2 * RTE_ETHER_ADDR_LEN),
2654 "invalid Ethernet Segment data size");
2655 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2656 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2657 pdst = (uint8_t *)&es->inline_data;
2658 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2659 /* Implement VLAN tag insertion as part inline data. */
2660 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2661 pdst += 2 * RTE_ETHER_ADDR_LEN;
2662 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2663 ((RTE_ETHER_TYPE_VLAN << 16) |
2664 loc->mbuf->vlan_tci);
2665 pdst += sizeof(struct rte_vlan_hdr);
2666 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2668 assert(pdst < (uint8_t *)txq->wqes_end);
2670 * The WQEBB space availability is checked by caller.
2671 * Here we should be aware of WQE ring buffer wraparound only.
2673 part = (uint8_t *)txq->wqes_end - pdst;
2674 part = RTE_MIN(part, inlen);
2677 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2679 if (likely(!inlen)) {
2681 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2682 return (struct mlx5_wqe_dseg *)pdst;
2684 pdst = (uint8_t *)txq->wqes;
2690 * Build the Data Segment of pointer type.
2693 * Pointer to TX queue structure.
2695 * Pointer to burst routine local context.
2697 * Pointer to WQE to fill with built Data Segment.
2699 * Data buffer to point.
2701 * Data buffer length.
2703 * Configured Tx offloads mask. It is fully defined at
2704 * compile time and may be used for optimization.
2706 static __rte_always_inline void
2707 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2708 struct mlx5_txq_local *restrict loc,
2709 struct mlx5_wqe_dseg *restrict dseg,
2712 unsigned int olx __rte_unused)
2716 dseg->bcount = rte_cpu_to_be_32(len);
2717 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2718 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2722 * Build the Data Segment of pointer type or inline
2723 * if data length is less than buffer in minimal
2724 * Data Segment size.
2727 * Pointer to TX queue structure.
2729 * Pointer to burst routine local context.
2731 * Pointer to WQE to fill with built Data Segment.
2733 * Data buffer to point.
2735 * Data buffer length.
2737 * Configured Tx offloads mask. It is fully defined at
2738 * compile time and may be used for optimization.
2740 static __rte_always_inline void
2741 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2742 struct mlx5_txq_local *restrict loc,
2743 struct mlx5_wqe_dseg *restrict dseg,
2746 unsigned int olx __rte_unused)
2752 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2753 dseg->bcount = rte_cpu_to_be_32(len);
2754 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2755 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2759 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2760 /* Unrolled implementation of generic rte_memcpy. */
2761 dst = (uintptr_t)&dseg->inline_data[0];
2762 src = (uintptr_t)buf;
2764 #ifdef RTE_ARCH_STRICT_ALIGN
2765 assert(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2766 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2767 dst += sizeof(uint32_t);
2768 src += sizeof(uint32_t);
2769 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2770 dst += sizeof(uint32_t);
2771 src += sizeof(uint32_t);
2773 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2774 dst += sizeof(uint64_t);
2775 src += sizeof(uint64_t);
2779 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2780 dst += sizeof(uint32_t);
2781 src += sizeof(uint32_t);
2784 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2785 dst += sizeof(uint16_t);
2786 src += sizeof(uint16_t);
2789 *(uint8_t *)dst = *(uint8_t *)src;
2793 * Build the Data Segment of inlined data from single
2794 * segment packet, no VLAN insertion.
2797 * Pointer to TX queue structure.
2799 * Pointer to burst routine local context.
2801 * Pointer to WQE to fill with built Data Segment.
2803 * Data buffer to point.
2805 * Data buffer length.
2807 * Configured Tx offloads mask. It is fully defined at
2808 * compile time and may be used for optimization.
2811 * Pointer to the next Data Segment after inlined data.
2812 * Ring buffer wraparound check is needed. We do not
2813 * do it here because it may not be needed for the
2814 * last packet in the eMPW session.
2816 static __rte_always_inline struct mlx5_wqe_dseg *
2817 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2818 struct mlx5_txq_local *restrict loc __rte_unused,
2819 struct mlx5_wqe_dseg *restrict dseg,
2822 unsigned int olx __rte_unused)
2827 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2828 pdst = &dseg->inline_data[0];
2830 * The WQEBB space availability is checked by caller.
2831 * Here we should be aware of WQE ring buffer wraparound only.
2833 part = (uint8_t *)txq->wqes_end - pdst;
2834 part = RTE_MIN(part, len);
2836 rte_memcpy(pdst, buf, part);
2840 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2841 /* Note: no final wraparound check here. */
2842 return (struct mlx5_wqe_dseg *)pdst;
2844 pdst = (uint8_t *)txq->wqes;
2851 * Build the Data Segment of inlined data from single
2852 * segment packet with VLAN insertion.
2855 * Pointer to TX queue structure.
2857 * Pointer to burst routine local context.
2859 * Pointer to the dseg fill with built Data Segment.
2861 * Data buffer to point.
2863 * Data buffer length.
2865 * Configured Tx offloads mask. It is fully defined at
2866 * compile time and may be used for optimization.
2869 * Pointer to the next Data Segment after inlined data.
2870 * Ring buffer wraparound check is needed.
2872 static __rte_always_inline struct mlx5_wqe_dseg *
2873 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2874 struct mlx5_txq_local *restrict loc __rte_unused,
2875 struct mlx5_wqe_dseg *restrict dseg,
2878 unsigned int olx __rte_unused)
2884 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2885 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2886 (2 * RTE_ETHER_ADDR_LEN),
2887 "invalid Data Segment data size");
2888 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2889 MLX5_ETH_WQE_DATA_INLINE);
2890 pdst = &dseg->inline_data[0];
2891 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2892 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2893 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2894 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2895 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2896 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2897 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2898 pdst = (uint8_t *)txq->wqes;
2899 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2900 loc->mbuf->vlan_tci);
2901 pdst += sizeof(struct rte_vlan_hdr);
2903 * The WQEBB space availability is checked by caller.
2904 * Here we should be aware of WQE ring buffer wraparound only.
2906 part = (uint8_t *)txq->wqes_end - pdst;
2907 part = RTE_MIN(part, len);
2909 rte_memcpy(pdst, buf, part);
2913 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2914 /* Note: no final wraparound check here. */
2915 return (struct mlx5_wqe_dseg *)pdst;
2917 pdst = (uint8_t *)txq->wqes;
2924 * Build the Ethernet Segment with optionally inlined data with
2925 * VLAN insertion and following Data Segments (if any) from
2926 * multi-segment packet. Used by ordinary send and TSO.
2929 * Pointer to TX queue structure.
2931 * Pointer to burst routine local context.
2933 * Pointer to WQE to fill with built Ethernet/Data Segments.
2935 * Length of VLAN header to insert, 0 means no VLAN insertion.
2937 * Data length to inline. For TSO this parameter specifies
2938 * exact value, for ordinary send routine can be aligned by
2939 * caller to provide better WQE space saving and data buffer
2940 * start address alignment. This length includes VLAN header
2943 * Zero means ordinary send, inlined data can be extended,
2944 * otherwise this is TSO, inlined data length is fixed.
2946 * Configured Tx offloads mask. It is fully defined at
2947 * compile time and may be used for optimization.
2950 * Actual size of built WQE in segments.
2952 static __rte_always_inline unsigned int
2953 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2954 struct mlx5_txq_local *restrict loc,
2955 struct mlx5_wqe *restrict wqe,
2959 unsigned int olx __rte_unused)
2961 struct mlx5_wqe_dseg *restrict dseg;
2964 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2965 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2968 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2969 if (!loc->mbuf_nseg)
2972 * There are still some mbuf remaining, not inlined.
2973 * The first mbuf may be partially inlined and we
2974 * must process the possible non-zero data offset.
2976 if (loc->mbuf_off) {
2981 * Exhausted packets must be dropped before.
2982 * Non-zero offset means there are some data
2983 * remained in the packet.
2985 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2986 assert(rte_pktmbuf_data_len(loc->mbuf));
2987 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2989 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2991 * Build the pointer/minimal data Data Segment.
2992 * Do ring buffer wrapping check in advance.
2994 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2995 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2996 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2997 /* Store the mbuf to be freed on completion. */
2998 assert(loc->elts_free);
2999 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3002 if (--loc->mbuf_nseg == 0)
3004 loc->mbuf = loc->mbuf->next;
3008 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3009 struct rte_mbuf *mbuf;
3011 /* Zero length segment found, just skip. */
3013 loc->mbuf = loc->mbuf->next;
3014 rte_pktmbuf_free_seg(mbuf);
3015 if (--loc->mbuf_nseg == 0)
3018 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3019 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3022 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3023 rte_pktmbuf_data_len(loc->mbuf), olx);
3024 assert(loc->elts_free);
3025 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3028 if (--loc->mbuf_nseg == 0)
3030 loc->mbuf = loc->mbuf->next;
3035 /* Calculate actual segments used from the dseg pointer. */
3036 if ((uintptr_t)wqe < (uintptr_t)dseg)
3037 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3039 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3040 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3045 * Tx one packet function for multi-segment TSO. Supports all
3046 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3047 * sends one packet per WQE.
3049 * This routine is responsible for storing processed mbuf
3050 * into elts ring buffer and update elts_head.
3053 * Pointer to TX queue structure.
3055 * Pointer to burst routine local context.
3057 * Configured Tx offloads mask. It is fully defined at
3058 * compile time and may be used for optimization.
3061 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3062 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3063 * Local context variables partially updated.
3065 static __rte_always_inline enum mlx5_txcmp_code
3066 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3067 struct mlx5_txq_local *restrict loc,
3070 struct mlx5_wqe *restrict wqe;
3071 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3074 * Calculate data length to be inlined to estimate
3075 * the required space in WQE ring buffer.
3077 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3078 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3079 vlan = sizeof(struct rte_vlan_hdr);
3080 inlen = loc->mbuf->l2_len + vlan +
3081 loc->mbuf->l3_len + loc->mbuf->l4_len;
3082 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3083 return MLX5_TXCMP_CODE_ERROR;
3084 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3085 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3086 /* Packet must contain all TSO headers. */
3087 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3088 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3089 inlen > (dlen + vlan)))
3090 return MLX5_TXCMP_CODE_ERROR;
3091 assert(inlen >= txq->inlen_mode);
3093 * Check whether there are enough free WQEBBs:
3095 * - Ethernet Segment
3096 * - First Segment of inlined Ethernet data
3097 * - ... data continued ...
3098 * - Data Segments of pointer/min inline type
3100 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3101 MLX5_ESEG_MIN_INLINE_SIZE +
3103 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3104 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3105 return MLX5_TXCMP_CODE_EXIT;
3106 /* Check for maximal WQE size. */
3107 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3108 return MLX5_TXCMP_CODE_ERROR;
3109 #ifdef MLX5_PMD_SOFT_COUNTERS
3110 /* Update sent data bytes/packets counters. */
3111 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3112 loc->mbuf->tso_segsz;
3114 * One will be added for mbuf itself
3115 * at the end of the mlx5_tx_burst from
3116 * loc->pkts_sent field.
3119 txq->stats.opackets += ntcp;
3120 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3122 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3123 loc->wqe_last = wqe;
3124 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3125 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3126 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3127 txq->wqe_ci += (ds + 3) / 4;
3128 loc->wqe_free -= (ds + 3) / 4;
3129 return MLX5_TXCMP_CODE_MULTI;
3133 * Tx one packet function for multi-segment SEND. Supports all
3134 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3135 * sends one packet per WQE, without any data inlining in
3138 * This routine is responsible for storing processed mbuf
3139 * into elts ring buffer and update elts_head.
3142 * Pointer to TX queue structure.
3144 * Pointer to burst routine local context.
3146 * Configured Tx offloads mask. It is fully defined at
3147 * compile time and may be used for optimization.
3150 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3151 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3152 * Local context variables partially updated.
3154 static __rte_always_inline enum mlx5_txcmp_code
3155 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3156 struct mlx5_txq_local *restrict loc,
3159 struct mlx5_wqe_dseg *restrict dseg;
3160 struct mlx5_wqe *restrict wqe;
3161 unsigned int ds, nseg;
3163 assert(NB_SEGS(loc->mbuf) > 1);
3165 * No inline at all, it means the CPU cycles saving
3166 * is prioritized at configuration, we should not
3167 * copy any packet data to WQE.
3169 nseg = NB_SEGS(loc->mbuf);
3171 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3172 return MLX5_TXCMP_CODE_EXIT;
3173 /* Check for maximal WQE size. */
3174 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3175 return MLX5_TXCMP_CODE_ERROR;
3177 * Some Tx offloads may cause an error if
3178 * packet is not long enough, check against
3179 * assumed minimal length.
3181 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3182 return MLX5_TXCMP_CODE_ERROR;
3183 #ifdef MLX5_PMD_SOFT_COUNTERS
3184 /* Update sent data bytes counter. */
3185 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3186 if (MLX5_TXOFF_CONFIG(VLAN) &&
3187 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3188 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3191 * SEND WQE, one WQEBB:
3192 * - Control Segment, SEND opcode
3193 * - Ethernet Segment, optional VLAN, no inline
3194 * - Data Segments, pointer only type
3196 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3197 loc->wqe_last = wqe;
3198 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3199 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3200 dseg = &wqe->dseg[0];
3202 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3203 struct rte_mbuf *mbuf;
3206 * Zero length segment found, have to
3207 * correct total size of WQE in segments.
3208 * It is supposed to be rare occasion, so
3209 * in normal case (no zero length segments)
3210 * we avoid extra writing to the Control
3214 wqe->cseg.sq_ds -= RTE_BE32(1);
3216 loc->mbuf = mbuf->next;
3217 rte_pktmbuf_free_seg(mbuf);
3223 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3224 rte_pktmbuf_data_len(loc->mbuf), olx);
3225 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3230 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3231 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3232 loc->mbuf = loc->mbuf->next;
3235 txq->wqe_ci += (ds + 3) / 4;
3236 loc->wqe_free -= (ds + 3) / 4;
3237 return MLX5_TXCMP_CODE_MULTI;
3241 * Tx one packet function for multi-segment SEND. Supports all
3242 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3243 * sends one packet per WQE, with data inlining in
3244 * Ethernet Segment and minimal Data Segments.
3246 * This routine is responsible for storing processed mbuf
3247 * into elts ring buffer and update elts_head.
3250 * Pointer to TX queue structure.
3252 * Pointer to burst routine local context.
3254 * Configured Tx offloads mask. It is fully defined at
3255 * compile time and may be used for optimization.
3258 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3259 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3260 * Local context variables partially updated.
3262 static __rte_always_inline enum mlx5_txcmp_code
3263 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3264 struct mlx5_txq_local *restrict loc,
3267 struct mlx5_wqe *restrict wqe;
3268 unsigned int ds, inlen, dlen, vlan = 0;
3270 assert(MLX5_TXOFF_CONFIG(INLINE));
3271 assert(NB_SEGS(loc->mbuf) > 1);
3273 * First calculate data length to be inlined
3274 * to estimate the required space for WQE.
3276 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3277 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3278 vlan = sizeof(struct rte_vlan_hdr);
3279 inlen = dlen + vlan;
3280 /* Check against minimal length. */
3281 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3282 return MLX5_TXCMP_CODE_ERROR;
3283 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3284 if (inlen > txq->inlen_send) {
3285 struct rte_mbuf *mbuf;
3290 * Packet length exceeds the allowed inline
3291 * data length, check whether the minimal
3292 * inlining is required.
3294 if (txq->inlen_mode) {
3295 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3296 assert(txq->inlen_mode <= txq->inlen_send);
3297 inlen = txq->inlen_mode;
3299 if (!vlan || txq->vlan_en) {
3301 * VLAN insertion will be done inside by HW.
3302 * It is not utmost effective - VLAN flag is
3303 * checked twice, but we should proceed the
3304 * inlining length correctly and take into
3305 * account the VLAN header being inserted.
3307 return mlx5_tx_packet_multi_send
3310 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3313 * Now we know the minimal amount of data is requested
3314 * to inline. Check whether we should inline the buffers
3315 * from the chain beginning to eliminate some mbufs.
3318 nxlen = rte_pktmbuf_data_len(mbuf);
3319 if (unlikely(nxlen <= txq->inlen_send)) {
3320 /* We can inline first mbuf at least. */
3321 if (nxlen < inlen) {
3324 /* Scan mbufs till inlen filled. */
3329 nxlen = rte_pktmbuf_data_len(mbuf);
3331 } while (unlikely(nxlen < inlen));
3332 if (unlikely(nxlen > txq->inlen_send)) {
3333 /* We cannot inline entire mbuf. */
3334 smlen = inlen - smlen;
3335 start = rte_pktmbuf_mtod_offset
3336 (mbuf, uintptr_t, smlen);
3343 /* There should be not end of packet. */
3345 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3346 } while (unlikely(nxlen < txq->inlen_send));
3348 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3350 * Check whether we can do inline to align start
3351 * address of data buffer to cacheline.
3354 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3355 if (unlikely(start)) {
3357 if (start <= txq->inlen_send)
3362 * Check whether there are enough free WQEBBs:
3364 * - Ethernet Segment
3365 * - First Segment of inlined Ethernet data
3366 * - ... data continued ...
3367 * - Data Segments of pointer/min inline type
3369 * Estimate the number of Data Segments conservatively,
3370 * supposing no any mbufs is being freed during inlining.
3372 assert(inlen <= txq->inlen_send);
3373 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3374 MLX5_ESEG_MIN_INLINE_SIZE +
3376 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3377 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3378 return MLX5_TXCMP_CODE_EXIT;
3379 /* Check for maximal WQE size. */
3380 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3381 return MLX5_TXCMP_CODE_ERROR;
3382 #ifdef MLX5_PMD_SOFT_COUNTERS
3383 /* Update sent data bytes/packets counters. */
3384 txq->stats.obytes += dlen + vlan;
3386 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3387 loc->wqe_last = wqe;
3388 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3389 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3390 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3391 txq->wqe_ci += (ds + 3) / 4;
3392 loc->wqe_free -= (ds + 3) / 4;
3393 return MLX5_TXCMP_CODE_MULTI;
3397 * Tx burst function for multi-segment packets. Supports all
3398 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3399 * sends one packet per WQE. Function stops sending if it
3400 * encounters the single-segment packet.
3402 * This routine is responsible for storing processed mbuf
3403 * into elts ring buffer and update elts_head.
3406 * Pointer to TX queue structure.
3408 * Packets to transmit.
3410 * Number of packets in array.
3412 * Pointer to burst routine local context.
3414 * Configured Tx offloads mask. It is fully defined at
3415 * compile time and may be used for optimization.
3418 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3419 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3420 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3421 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3422 * Local context variables updated.
3424 static __rte_always_inline enum mlx5_txcmp_code
3425 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3426 struct rte_mbuf **restrict pkts,
3427 unsigned int pkts_n,
3428 struct mlx5_txq_local *restrict loc,
3431 assert(loc->elts_free && loc->wqe_free);
3432 assert(pkts_n > loc->pkts_sent);
3433 pkts += loc->pkts_sent + 1;
3434 pkts_n -= loc->pkts_sent;
3436 enum mlx5_txcmp_code ret;
3438 assert(NB_SEGS(loc->mbuf) > 1);
3440 * Estimate the number of free elts quickly but
3441 * conservatively. Some segment may be fully inlined
3442 * and freed, ignore this here - precise estimation
3445 if (loc->elts_free < NB_SEGS(loc->mbuf))
3446 return MLX5_TXCMP_CODE_EXIT;
3447 if (MLX5_TXOFF_CONFIG(TSO) &&
3448 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3449 /* Proceed with multi-segment TSO. */
3450 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3451 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3452 /* Proceed with multi-segment SEND with inlining. */
3453 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3455 /* Proceed with multi-segment SEND w/o inlining. */
3456 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3458 if (ret == MLX5_TXCMP_CODE_EXIT)
3459 return MLX5_TXCMP_CODE_EXIT;
3460 if (ret == MLX5_TXCMP_CODE_ERROR)
3461 return MLX5_TXCMP_CODE_ERROR;
3462 /* WQE is built, go to the next packet. */
3465 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3466 return MLX5_TXCMP_CODE_EXIT;
3467 loc->mbuf = *pkts++;
3469 rte_prefetch0(*pkts);
3470 if (likely(NB_SEGS(loc->mbuf) > 1))
3472 /* Here ends the series of multi-segment packets. */
3473 if (MLX5_TXOFF_CONFIG(TSO) &&
3474 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3475 return MLX5_TXCMP_CODE_TSO;
3476 return MLX5_TXCMP_CODE_SINGLE;
3482 * Tx burst function for single-segment packets with TSO.
3483 * Supports all types of Tx offloads, except multi-packets.
3484 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3485 * Function stops sending if it encounters the multi-segment
3486 * packet or packet without TSO requested.
3488 * The routine is responsible for storing processed mbuf
3489 * into elts ring buffer and update elts_head if inline
3490 * offloads is requested due to possible early freeing
3491 * of the inlined mbufs (can not store pkts array in elts
3495 * Pointer to TX queue structure.
3497 * Packets to transmit.
3499 * Number of packets in array.
3501 * Pointer to burst routine local context.
3503 * Configured Tx offloads mask. It is fully defined at
3504 * compile time and may be used for optimization.
3507 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3508 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3509 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3510 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3511 * Local context variables updated.
3513 static __rte_always_inline enum mlx5_txcmp_code
3514 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3515 struct rte_mbuf **restrict pkts,
3516 unsigned int pkts_n,
3517 struct mlx5_txq_local *restrict loc,
3520 assert(loc->elts_free && loc->wqe_free);
3521 assert(pkts_n > loc->pkts_sent);
3522 pkts += loc->pkts_sent + 1;
3523 pkts_n -= loc->pkts_sent;
3525 struct mlx5_wqe_dseg *restrict dseg;
3526 struct mlx5_wqe *restrict wqe;
3527 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3530 assert(NB_SEGS(loc->mbuf) == 1);
3531 dlen = rte_pktmbuf_data_len(loc->mbuf);
3532 if (MLX5_TXOFF_CONFIG(VLAN) &&
3533 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3534 vlan = sizeof(struct rte_vlan_hdr);
3537 * First calculate the WQE size to check
3538 * whether we have enough space in ring buffer.
3540 hlen = loc->mbuf->l2_len + vlan +
3541 loc->mbuf->l3_len + loc->mbuf->l4_len;
3542 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3543 return MLX5_TXCMP_CODE_ERROR;
3544 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3545 hlen += loc->mbuf->outer_l2_len +
3546 loc->mbuf->outer_l3_len;
3547 /* Segment must contain all TSO headers. */
3548 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3549 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3550 hlen > (dlen + vlan)))
3551 return MLX5_TXCMP_CODE_ERROR;
3553 * Check whether there are enough free WQEBBs:
3555 * - Ethernet Segment
3556 * - First Segment of inlined Ethernet data
3557 * - ... data continued ...
3558 * - Finishing Data Segment of pointer type
3560 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3561 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3562 if (loc->wqe_free < ((ds + 3) / 4))
3563 return MLX5_TXCMP_CODE_EXIT;
3564 #ifdef MLX5_PMD_SOFT_COUNTERS
3565 /* Update sent data bytes/packets counters. */
3566 ntcp = (dlen + vlan - hlen +
3567 loc->mbuf->tso_segsz - 1) /
3568 loc->mbuf->tso_segsz;
3570 * One will be added for mbuf itself at the end
3571 * of the mlx5_tx_burst from loc->pkts_sent field.
3574 txq->stats.opackets += ntcp;
3575 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3578 * Build the TSO WQE:
3580 * - Ethernet Segment with hlen bytes inlined
3581 * - Data Segment of pointer type
3583 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3584 loc->wqe_last = wqe;
3585 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3586 MLX5_OPCODE_TSO, olx);
3587 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3588 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3589 dlen -= hlen - vlan;
3590 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3592 * WQE is built, update the loop parameters
3593 * and go to the next packet.
3595 txq->wqe_ci += (ds + 3) / 4;
3596 loc->wqe_free -= (ds + 3) / 4;
3597 if (MLX5_TXOFF_CONFIG(INLINE))
3598 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3602 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3603 return MLX5_TXCMP_CODE_EXIT;
3604 loc->mbuf = *pkts++;
3606 rte_prefetch0(*pkts);
3607 if (MLX5_TXOFF_CONFIG(MULTI) &&
3608 unlikely(NB_SEGS(loc->mbuf) > 1))
3609 return MLX5_TXCMP_CODE_MULTI;
3610 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3611 return MLX5_TXCMP_CODE_SINGLE;
3612 /* Continue with the next TSO packet. */
3618 * Analyze the packet and select the best method to send.
3621 * Pointer to TX queue structure.
3623 * Pointer to burst routine local context.
3625 * Configured Tx offloads mask. It is fully defined at
3626 * compile time and may be used for optimization.
3628 * The predefined flag whether do complete check for
3629 * multi-segment packets and TSO.
3632 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3633 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3634 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3635 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3637 static __rte_always_inline enum mlx5_txcmp_code
3638 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3639 struct mlx5_txq_local *restrict loc,
3643 /* Check for multi-segment packet. */
3645 MLX5_TXOFF_CONFIG(MULTI) &&
3646 unlikely(NB_SEGS(loc->mbuf) > 1))
3647 return MLX5_TXCMP_CODE_MULTI;
3648 /* Check for TSO packet. */
3650 MLX5_TXOFF_CONFIG(TSO) &&
3651 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3652 return MLX5_TXCMP_CODE_TSO;
3653 /* Check if eMPW is enabled at all. */
3654 if (!MLX5_TXOFF_CONFIG(EMPW))
3655 return MLX5_TXCMP_CODE_SINGLE;
3656 /* Check if eMPW can be engaged. */
3657 if (MLX5_TXOFF_CONFIG(VLAN) &&
3658 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3659 (!MLX5_TXOFF_CONFIG(INLINE) ||
3660 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3661 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3663 * eMPW does not support VLAN insertion offload,
3664 * we have to inline the entire packet but
3665 * packet is too long for inlining.
3667 return MLX5_TXCMP_CODE_SINGLE;
3669 return MLX5_TXCMP_CODE_EMPW;
3673 * Check the next packet attributes to match with the eMPW batch ones.
3674 * In addition, for legacy MPW the packet length is checked either.
3677 * Pointer to TX queue structure.
3679 * Pointer to Ethernet Segment of eMPW batch.
3681 * Pointer to burst routine local context.
3683 * Length of previous packet in MPW descriptor.
3685 * Configured Tx offloads mask. It is fully defined at
3686 * compile time and may be used for optimization.
3689 * true - packet match with eMPW batch attributes.
3690 * false - no match, eMPW should be restarted.
3692 static __rte_always_inline bool
3693 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3694 struct mlx5_wqe_eseg *restrict es,
3695 struct mlx5_txq_local *restrict loc,
3699 uint8_t swp_flags = 0;
3701 /* Compare the checksum flags, if any. */
3702 if (MLX5_TXOFF_CONFIG(CSUM) &&
3703 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3705 /* Compare the Software Parser offsets and flags. */
3706 if (MLX5_TXOFF_CONFIG(SWP) &&
3707 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3708 es->swp_flags != swp_flags))
3710 /* Fill metadata field if needed. */
3711 if (MLX5_TXOFF_CONFIG(METADATA) &&
3712 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3713 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3715 /* Legacy MPW can send packets with the same lengt only. */
3716 if (MLX5_TXOFF_CONFIG(MPW) &&
3717 dlen != rte_pktmbuf_data_len(loc->mbuf))
3719 /* There must be no VLAN packets in eMPW loop. */
3720 if (MLX5_TXOFF_CONFIG(VLAN))
3721 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3726 * Update send loop variables and WQE for eMPW loop
3727 * without data inlining. Number of Data Segments is
3728 * equal to the number of sent packets.
3731 * Pointer to TX queue structure.
3733 * Pointer to burst routine local context.
3735 * Number of packets/Data Segments/Packets.
3737 * Accumulated statistics, bytes sent
3739 * Configured Tx offloads mask. It is fully defined at
3740 * compile time and may be used for optimization.
3743 * true - packet match with eMPW batch attributes.
3744 * false - no match, eMPW should be restarted.
3746 static __rte_always_inline void
3747 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3748 struct mlx5_txq_local *restrict loc,
3751 unsigned int olx __rte_unused)
3753 assert(!MLX5_TXOFF_CONFIG(INLINE));
3754 #ifdef MLX5_PMD_SOFT_COUNTERS
3755 /* Update sent data bytes counter. */
3756 txq->stats.obytes += slen;
3760 loc->elts_free -= ds;
3761 loc->pkts_sent += ds;
3763 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3764 txq->wqe_ci += (ds + 3) / 4;
3765 loc->wqe_free -= (ds + 3) / 4;
3769 * Update send loop variables and WQE for eMPW loop
3770 * with data inlining. Gets the size of pushed descriptors
3771 * and data to the WQE.
3774 * Pointer to TX queue structure.
3776 * Pointer to burst routine local context.
3778 * Total size of descriptor/data in bytes.
3780 * Accumulated statistics, data bytes sent.
3782 * Configured Tx offloads mask. It is fully defined at
3783 * compile time and may be used for optimization.
3786 * true - packet match with eMPW batch attributes.
3787 * false - no match, eMPW should be restarted.
3789 static __rte_always_inline void
3790 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3791 struct mlx5_txq_local *restrict loc,
3794 unsigned int olx __rte_unused)
3796 assert(MLX5_TXOFF_CONFIG(INLINE));
3797 assert((len % MLX5_WSEG_SIZE) == 0);
3798 #ifdef MLX5_PMD_SOFT_COUNTERS
3799 /* Update sent data bytes counter. */
3800 txq->stats.obytes += slen;
3804 len = len / MLX5_WSEG_SIZE + 2;
3805 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3806 txq->wqe_ci += (len + 3) / 4;
3807 loc->wqe_free -= (len + 3) / 4;
3811 * The set of Tx burst functions for single-segment packets
3812 * without TSO and with Multi-Packet Writing feature support.
3813 * Supports all types of Tx offloads, except multi-packets
3816 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3817 * as many packet per WQE as it can. If eMPW is not configured
3818 * or packet can not be sent with eMPW (VLAN insertion) the
3819 * ordinary SEND opcode is used and only one packet placed
3822 * Functions stop sending if it encounters the multi-segment
3823 * packet or packet with TSO requested.
3825 * The routines are responsible for storing processed mbuf
3826 * into elts ring buffer and update elts_head if inlining
3827 * offload is requested. Otherwise the copying mbufs to elts
3828 * can be postponed and completed at the end of burst routine.
3831 * Pointer to TX queue structure.
3833 * Packets to transmit.
3835 * Number of packets in array.
3837 * Pointer to burst routine local context.
3839 * Configured Tx offloads mask. It is fully defined at
3840 * compile time and may be used for optimization.
3843 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3844 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3845 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3846 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3847 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3848 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3850 * Local context variables updated.
3853 * The routine sends packets with MLX5_OPCODE_EMPW
3854 * without inlining, this is dedicated optimized branch.
3855 * No VLAN insertion is supported.
3857 static __rte_always_inline enum mlx5_txcmp_code
3858 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3859 struct rte_mbuf **restrict pkts,
3860 unsigned int pkts_n,
3861 struct mlx5_txq_local *restrict loc,
3865 * Subroutine is the part of mlx5_tx_burst_single()
3866 * and sends single-segment packet with eMPW opcode
3867 * without data inlining.
3869 assert(!MLX5_TXOFF_CONFIG(INLINE));
3870 assert(MLX5_TXOFF_CONFIG(EMPW));
3871 assert(loc->elts_free && loc->wqe_free);
3872 assert(pkts_n > loc->pkts_sent);
3873 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3874 pkts += loc->pkts_sent + 1;
3875 pkts_n -= loc->pkts_sent;
3877 struct mlx5_wqe_dseg *restrict dseg;
3878 struct mlx5_wqe_eseg *restrict eseg;
3879 enum mlx5_txcmp_code ret;
3880 unsigned int part, loop;
3881 unsigned int slen = 0;
3884 assert(NB_SEGS(loc->mbuf) == 1);
3885 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
3886 MLX5_MPW_MAX_PACKETS :
3887 MLX5_EMPW_MAX_PACKETS);
3888 if (unlikely(loc->elts_free < part)) {
3889 /* We have no enough elts to save all mbufs. */
3890 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3891 return MLX5_TXCMP_CODE_EXIT;
3892 /* But we still able to send at least minimal eMPW. */
3893 part = loc->elts_free;
3895 /* Check whether we have enough WQEs */
3896 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3897 if (unlikely(loc->wqe_free <
3898 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3899 return MLX5_TXCMP_CODE_EXIT;
3900 part = (loc->wqe_free * 4) - 2;
3902 if (likely(part > 1))
3903 rte_prefetch0(*pkts);
3904 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3906 * Build eMPW title WQEBB:
3907 * - Control Segment, eMPW opcode
3908 * - Ethernet Segment, no inline
3910 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3911 MLX5_OPCODE_ENHANCED_MPSW, olx);
3912 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3913 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3914 eseg = &loc->wqe_last->eseg;
3915 dseg = &loc->wqe_last->dseg[0];
3917 /* Store the packet length for legacy MPW. */
3918 if (MLX5_TXOFF_CONFIG(MPW))
3919 eseg->mss = rte_cpu_to_be_16
3920 (rte_pktmbuf_data_len(loc->mbuf));
3922 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3923 #ifdef MLX5_PMD_SOFT_COUNTERS
3924 /* Update sent data bytes counter. */
3929 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3931 if (unlikely(--loop == 0))
3933 loc->mbuf = *pkts++;
3934 if (likely(loop > 1))
3935 rte_prefetch0(*pkts);
3936 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3938 * Unroll the completion code to avoid
3939 * returning variable value - it results in
3940 * unoptimized sequent checking in caller.
3942 if (ret == MLX5_TXCMP_CODE_MULTI) {
3944 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3945 if (unlikely(!loc->elts_free ||
3947 return MLX5_TXCMP_CODE_EXIT;
3948 return MLX5_TXCMP_CODE_MULTI;
3950 assert(NB_SEGS(loc->mbuf) == 1);
3951 if (ret == MLX5_TXCMP_CODE_TSO) {
3953 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3954 if (unlikely(!loc->elts_free ||
3956 return MLX5_TXCMP_CODE_EXIT;
3957 return MLX5_TXCMP_CODE_TSO;
3959 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3961 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3962 if (unlikely(!loc->elts_free ||
3964 return MLX5_TXCMP_CODE_EXIT;
3965 return MLX5_TXCMP_CODE_SINGLE;
3967 if (ret != MLX5_TXCMP_CODE_EMPW) {
3970 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3971 return MLX5_TXCMP_CODE_ERROR;
3974 * Check whether packet parameters coincide
3975 * within assumed eMPW batch:
3976 * - check sum settings
3978 * - software parser settings
3979 * - packets length (legacy MPW only)
3981 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
3984 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3985 if (unlikely(!loc->elts_free ||
3987 return MLX5_TXCMP_CODE_EXIT;
3991 /* Packet attributes match, continue the same eMPW. */
3993 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3994 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3996 /* eMPW is built successfully, update loop parameters. */
3998 assert(pkts_n >= part);
3999 #ifdef MLX5_PMD_SOFT_COUNTERS
4000 /* Update sent data bytes counter. */
4001 txq->stats.obytes += slen;
4003 loc->elts_free -= part;
4004 loc->pkts_sent += part;
4005 txq->wqe_ci += (2 + part + 3) / 4;
4006 loc->wqe_free -= (2 + part + 3) / 4;
4008 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4009 return MLX5_TXCMP_CODE_EXIT;
4010 loc->mbuf = *pkts++;
4011 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4012 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4014 /* Continue sending eMPW batches. */
4020 * The routine sends packets with MLX5_OPCODE_EMPW
4021 * with inlining, optionally supports VLAN insertion.
4023 static __rte_always_inline enum mlx5_txcmp_code
4024 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
4025 struct rte_mbuf **restrict pkts,
4026 unsigned int pkts_n,
4027 struct mlx5_txq_local *restrict loc,
4031 * Subroutine is the part of mlx5_tx_burst_single()
4032 * and sends single-segment packet with eMPW opcode
4033 * with data inlining.
4035 assert(MLX5_TXOFF_CONFIG(INLINE));
4036 assert(MLX5_TXOFF_CONFIG(EMPW));
4037 assert(loc->elts_free && loc->wqe_free);
4038 assert(pkts_n > loc->pkts_sent);
4039 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4040 pkts += loc->pkts_sent + 1;
4041 pkts_n -= loc->pkts_sent;
4043 struct mlx5_wqe_dseg *restrict dseg;
4044 struct mlx5_wqe_eseg *restrict eseg;
4045 enum mlx5_txcmp_code ret;
4046 unsigned int room, part, nlim;
4047 unsigned int slen = 0;
4049 assert(NB_SEGS(loc->mbuf) == 1);
4051 * Limits the amount of packets in one WQE
4052 * to improve CQE latency generation.
4054 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4055 MLX5_MPW_INLINE_MAX_PACKETS :
4056 MLX5_EMPW_MAX_PACKETS);
4057 /* Check whether we have minimal amount WQEs */
4058 if (unlikely(loc->wqe_free <
4059 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4060 return MLX5_TXCMP_CODE_EXIT;
4061 if (likely(pkts_n > 1))
4062 rte_prefetch0(*pkts);
4063 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4065 * Build eMPW title WQEBB:
4066 * - Control Segment, eMPW opcode, zero DS
4067 * - Ethernet Segment, no inline
4069 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
4070 MLX5_OPCODE_ENHANCED_MPSW, olx);
4071 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4072 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4073 eseg = &loc->wqe_last->eseg;
4074 dseg = &loc->wqe_last->dseg[0];
4075 /* Store the packet length for legacy MPW. */
4076 if (MLX5_TXOFF_CONFIG(MPW))
4077 eseg->mss = rte_cpu_to_be_16
4078 (rte_pktmbuf_data_len(loc->mbuf));
4079 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4080 loc->wqe_free) * MLX5_WQE_SIZE -
4081 MLX5_WQE_CSEG_SIZE -
4083 /* Build WQE till we have space, packets and resources. */
4086 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4087 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4090 assert(room >= MLX5_WQE_DSEG_SIZE);
4091 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
4092 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4094 * Some Tx offloads may cause an error if
4095 * packet is not long enough, check against
4096 * assumed minimal length.
4098 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4100 if (unlikely(!part))
4101 return MLX5_TXCMP_CODE_ERROR;
4103 * We have some successfully built
4104 * packet Data Segments to send.
4106 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4107 return MLX5_TXCMP_CODE_ERROR;
4109 /* Inline or not inline - that's the Question. */
4110 if (dlen > txq->inlen_empw)
4112 /* Inline entire packet, optional VLAN insertion. */
4113 tlen = sizeof(dseg->bcount) + dlen;
4114 if (MLX5_TXOFF_CONFIG(VLAN) &&
4115 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4117 * The packet length must be checked in
4118 * mlx5_tx_able_to_empw() and packet
4119 * fits into inline length guaranteed.
4121 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
4123 tlen += sizeof(struct rte_vlan_hdr);
4126 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4128 #ifdef MLX5_PMD_SOFT_COUNTERS
4129 /* Update sent data bytes counter. */
4130 slen += sizeof(struct rte_vlan_hdr);
4135 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4138 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4139 assert(room >= tlen);
4142 * Packet data are completely inlined,
4143 * free the packet immediately.
4145 rte_pktmbuf_free_seg(loc->mbuf);
4149 * Not inlinable VLAN packets are
4150 * proceeded outside of this routine.
4152 assert(room >= MLX5_WQE_DSEG_SIZE);
4153 if (MLX5_TXOFF_CONFIG(VLAN))
4154 assert(!(loc->mbuf->ol_flags &
4156 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4157 /* We have to store mbuf in elts.*/
4158 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4159 room -= MLX5_WQE_DSEG_SIZE;
4160 /* Ring buffer wraparound is checked at the loop end.*/
4163 #ifdef MLX5_PMD_SOFT_COUNTERS
4164 /* Update sent data bytes counter. */
4170 if (unlikely(!pkts_n || !loc->elts_free)) {
4172 * We have no resources/packets to
4173 * continue build descriptors.
4176 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4177 return MLX5_TXCMP_CODE_EXIT;
4179 loc->mbuf = *pkts++;
4180 if (likely(pkts_n > 1))
4181 rte_prefetch0(*pkts);
4182 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4184 * Unroll the completion code to avoid
4185 * returning variable value - it results in
4186 * unoptimized sequent checking in caller.
4188 if (ret == MLX5_TXCMP_CODE_MULTI) {
4190 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4191 if (unlikely(!loc->elts_free ||
4193 return MLX5_TXCMP_CODE_EXIT;
4194 return MLX5_TXCMP_CODE_MULTI;
4196 assert(NB_SEGS(loc->mbuf) == 1);
4197 if (ret == MLX5_TXCMP_CODE_TSO) {
4199 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4200 if (unlikely(!loc->elts_free ||
4202 return MLX5_TXCMP_CODE_EXIT;
4203 return MLX5_TXCMP_CODE_TSO;
4205 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4207 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4208 if (unlikely(!loc->elts_free ||
4210 return MLX5_TXCMP_CODE_EXIT;
4211 return MLX5_TXCMP_CODE_SINGLE;
4213 if (ret != MLX5_TXCMP_CODE_EMPW) {
4216 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4217 return MLX5_TXCMP_CODE_ERROR;
4219 /* Check if we have minimal room left. */
4221 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4224 * Check whether packet parameters coincide
4225 * within assumed eMPW batch:
4226 * - check sum settings
4228 * - software parser settings
4229 * - packets length (legacy MPW only)
4231 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx))
4233 /* Packet attributes match, continue the same eMPW. */
4234 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4235 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4238 * We get here to close an existing eMPW
4239 * session and start the new one.
4243 if (unlikely(!part))
4244 return MLX5_TXCMP_CODE_EXIT;
4245 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4246 if (unlikely(!loc->elts_free ||
4248 return MLX5_TXCMP_CODE_EXIT;
4249 /* Continue the loop with new eMPW session. */
4255 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4256 * Data inlining and VLAN insertion are supported.
4258 static __rte_always_inline enum mlx5_txcmp_code
4259 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4260 struct rte_mbuf **restrict pkts,
4261 unsigned int pkts_n,
4262 struct mlx5_txq_local *restrict loc,
4266 * Subroutine is the part of mlx5_tx_burst_single()
4267 * and sends single-segment packet with SEND opcode.
4269 assert(loc->elts_free && loc->wqe_free);
4270 assert(pkts_n > loc->pkts_sent);
4271 pkts += loc->pkts_sent + 1;
4272 pkts_n -= loc->pkts_sent;
4274 struct mlx5_wqe *restrict wqe;
4275 enum mlx5_txcmp_code ret;
4277 assert(NB_SEGS(loc->mbuf) == 1);
4278 if (MLX5_TXOFF_CONFIG(INLINE)) {
4279 unsigned int inlen, vlan = 0;
4281 inlen = rte_pktmbuf_data_len(loc->mbuf);
4282 if (MLX5_TXOFF_CONFIG(VLAN) &&
4283 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4284 vlan = sizeof(struct rte_vlan_hdr);
4286 static_assert((sizeof(struct rte_vlan_hdr) +
4287 sizeof(struct rte_ether_hdr)) ==
4288 MLX5_ESEG_MIN_INLINE_SIZE,
4289 "invalid min inline data size");
4292 * If inlining is enabled at configuration time
4293 * the limit must be not less than minimal size.
4294 * Otherwise we would do extra check for data
4295 * size to avoid crashes due to length overflow.
4297 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4298 if (inlen <= txq->inlen_send) {
4299 unsigned int seg_n, wqe_n;
4301 rte_prefetch0(rte_pktmbuf_mtod
4302 (loc->mbuf, uint8_t *));
4303 /* Check against minimal length. */
4304 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4305 return MLX5_TXCMP_CODE_ERROR;
4307 * Completely inlined packet data WQE:
4308 * - Control Segment, SEND opcode
4309 * - Ethernet Segment, no VLAN insertion
4310 * - Data inlined, VLAN optionally inserted
4311 * - Alignment to MLX5_WSEG_SIZE
4312 * Have to estimate amount of WQEBBs
4314 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4315 MLX5_ESEG_MIN_INLINE_SIZE +
4316 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4317 /* Check if there are enough WQEBBs. */
4318 wqe_n = (seg_n + 3) / 4;
4319 if (wqe_n > loc->wqe_free)
4320 return MLX5_TXCMP_CODE_EXIT;
4321 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4322 loc->wqe_last = wqe;
4323 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4324 MLX5_OPCODE_SEND, olx);
4325 mlx5_tx_eseg_data(txq, loc, wqe,
4326 vlan, inlen, 0, olx);
4327 txq->wqe_ci += wqe_n;
4328 loc->wqe_free -= wqe_n;
4330 * Packet data are completely inlined,
4331 * free the packet immediately.
4333 rte_pktmbuf_free_seg(loc->mbuf);
4334 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4335 MLX5_TXOFF_CONFIG(MPW)) &&
4338 * If minimal inlining is requested the eMPW
4339 * feature should be disabled due to data is
4340 * inlined into Ethernet Segment, which can
4341 * not contain inlined data for eMPW due to
4342 * segment shared for all packets.
4344 struct mlx5_wqe_dseg *restrict dseg;
4349 * The inline-mode settings require
4350 * to inline the specified amount of
4351 * data bytes to the Ethernet Segment.
4352 * We should check the free space in
4353 * WQE ring buffer to inline partially.
4355 assert(txq->inlen_send >= txq->inlen_mode);
4356 assert(inlen > txq->inlen_mode);
4357 assert(txq->inlen_mode >=
4358 MLX5_ESEG_MIN_INLINE_SIZE);
4360 * Check whether there are enough free WQEBBs:
4362 * - Ethernet Segment
4363 * - First Segment of inlined Ethernet data
4364 * - ... data continued ...
4365 * - Finishing Data Segment of pointer type
4367 ds = (MLX5_WQE_CSEG_SIZE +
4368 MLX5_WQE_ESEG_SIZE +
4369 MLX5_WQE_DSEG_SIZE +
4371 MLX5_ESEG_MIN_INLINE_SIZE +
4372 MLX5_WQE_DSEG_SIZE +
4373 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4374 if (loc->wqe_free < ((ds + 3) / 4))
4375 return MLX5_TXCMP_CODE_EXIT;
4377 * Build the ordinary SEND WQE:
4379 * - Ethernet Segment, inline inlen_mode bytes
4380 * - Data Segment of pointer type
4382 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4383 loc->wqe_last = wqe;
4384 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4385 MLX5_OPCODE_SEND, olx);
4386 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4389 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4390 txq->inlen_mode - vlan;
4391 inlen -= txq->inlen_mode;
4392 mlx5_tx_dseg_ptr(txq, loc, dseg,
4395 * WQE is built, update the loop parameters
4396 * and got to the next packet.
4398 txq->wqe_ci += (ds + 3) / 4;
4399 loc->wqe_free -= (ds + 3) / 4;
4400 /* We have to store mbuf in elts.*/
4401 assert(MLX5_TXOFF_CONFIG(INLINE));
4402 txq->elts[txq->elts_head++ & txq->elts_m] =
4410 * Partially inlined packet data WQE, we have
4411 * some space in title WQEBB, we can fill it
4412 * with some packet data. It takes one WQEBB,
4413 * it is available, no extra space check:
4414 * - Control Segment, SEND opcode
4415 * - Ethernet Segment, no VLAN insertion
4416 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4417 * - Data Segment, pointer type
4419 * We also get here if VLAN insertion is not
4420 * supported by HW, the inline is enabled.
4422 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4423 loc->wqe_last = wqe;
4424 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4425 MLX5_OPCODE_SEND, olx);
4426 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4427 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4428 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4430 * The length check is performed above, by
4431 * comparing with txq->inlen_send. We should
4432 * not get overflow here.
4434 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4435 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4436 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4440 /* We have to store mbuf in elts.*/
4441 assert(MLX5_TXOFF_CONFIG(INLINE));
4442 txq->elts[txq->elts_head++ & txq->elts_m] =
4446 #ifdef MLX5_PMD_SOFT_COUNTERS
4447 /* Update sent data bytes counter. */
4448 txq->stats.obytes += vlan +
4449 rte_pktmbuf_data_len(loc->mbuf);
4453 * No inline at all, it means the CPU cycles saving
4454 * is prioritized at configuration, we should not
4455 * copy any packet data to WQE.
4457 * SEND WQE, one WQEBB:
4458 * - Control Segment, SEND opcode
4459 * - Ethernet Segment, optional VLAN, no inline
4460 * - Data Segment, pointer type
4462 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4463 loc->wqe_last = wqe;
4464 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4465 MLX5_OPCODE_SEND, olx);
4466 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4468 (txq, loc, &wqe->dseg[0],
4469 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4470 rte_pktmbuf_data_len(loc->mbuf), olx);
4474 * We should not store mbuf pointer in elts
4475 * if no inlining is configured, this is done
4476 * by calling routine in a batch copy.
4478 assert(!MLX5_TXOFF_CONFIG(INLINE));
4480 #ifdef MLX5_PMD_SOFT_COUNTERS
4481 /* Update sent data bytes counter. */
4482 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4483 if (MLX5_TXOFF_CONFIG(VLAN) &&
4484 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4485 txq->stats.obytes +=
4486 sizeof(struct rte_vlan_hdr);
4491 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4492 return MLX5_TXCMP_CODE_EXIT;
4493 loc->mbuf = *pkts++;
4495 rte_prefetch0(*pkts);
4496 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4497 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4503 static __rte_always_inline enum mlx5_txcmp_code
4504 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4505 struct rte_mbuf **restrict pkts,
4506 unsigned int pkts_n,
4507 struct mlx5_txq_local *restrict loc,
4510 enum mlx5_txcmp_code ret;
4512 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4513 if (ret == MLX5_TXCMP_CODE_SINGLE)
4515 assert(ret == MLX5_TXCMP_CODE_EMPW);
4517 /* Optimize for inline/no inline eMPW send. */
4518 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4519 mlx5_tx_burst_empw_inline
4520 (txq, pkts, pkts_n, loc, olx) :
4521 mlx5_tx_burst_empw_simple
4522 (txq, pkts, pkts_n, loc, olx);
4523 if (ret != MLX5_TXCMP_CODE_SINGLE)
4525 /* The resources to send one packet should remain. */
4526 assert(loc->elts_free && loc->wqe_free);
4528 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4529 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4530 if (ret != MLX5_TXCMP_CODE_EMPW)
4532 /* The resources to send one packet should remain. */
4533 assert(loc->elts_free && loc->wqe_free);
4538 * DPDK Tx callback template. This is configured template
4539 * used to generate routines optimized for specified offload setup.
4540 * One of this generated functions is chosen at SQ configuration
4544 * Generic pointer to TX queue structure.
4546 * Packets to transmit.
4548 * Number of packets in array.
4550 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4551 * values. Should be static to take compile time static configuration
4555 * Number of packets successfully transmitted (<= pkts_n).
4557 static __rte_always_inline uint16_t
4558 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4559 struct rte_mbuf **restrict pkts,
4563 struct mlx5_txq_local loc;
4564 enum mlx5_txcmp_code ret;
4567 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4568 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4569 if (unlikely(!pkts_n))
4573 loc.wqe_last = NULL;
4576 loc.pkts_loop = loc.pkts_sent;
4578 * Check if there are some CQEs, if any:
4579 * - process an encountered errors
4580 * - process the completed WQEs
4581 * - free related mbufs
4582 * - doorbell the NIC about processed CQEs
4584 rte_prefetch0(*(pkts + loc.pkts_sent));
4585 mlx5_tx_handle_completion(txq, olx);
4587 * Calculate the number of available resources - elts and WQEs.
4588 * There are two possible different scenarios:
4589 * - no data inlining into WQEs, one WQEBB may contains upto
4590 * four packets, in this case elts become scarce resource
4591 * - data inlining into WQEs, one packet may require multiple
4592 * WQEBBs, the WQEs become the limiting factor.
4594 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4595 loc.elts_free = txq->elts_s -
4596 (uint16_t)(txq->elts_head - txq->elts_tail);
4597 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4598 loc.wqe_free = txq->wqe_s -
4599 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4600 if (unlikely(!loc.elts_free || !loc.wqe_free))
4604 * Fetch the packet from array. Usually this is
4605 * the first packet in series of multi/single
4608 loc.mbuf = *(pkts + loc.pkts_sent);
4609 /* Dedicated branch for multi-segment packets. */
4610 if (MLX5_TXOFF_CONFIG(MULTI) &&
4611 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4613 * Multi-segment packet encountered.
4614 * Hardware is able to process it only
4615 * with SEND/TSO opcodes, one packet
4616 * per WQE, do it in dedicated routine.
4619 assert(loc.pkts_sent >= loc.pkts_copy);
4620 part = loc.pkts_sent - loc.pkts_copy;
4621 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4623 * There are some single-segment mbufs not
4624 * stored in elts. The mbufs must be in the
4625 * same order as WQEs, so we must copy the
4626 * mbufs to elts here, before the coming
4627 * multi-segment packet mbufs is appended.
4629 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4631 loc.pkts_copy = loc.pkts_sent;
4633 assert(pkts_n > loc.pkts_sent);
4634 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4635 if (!MLX5_TXOFF_CONFIG(INLINE))
4636 loc.pkts_copy = loc.pkts_sent;
4638 * These returned code checks are supposed
4639 * to be optimized out due to routine inlining.
4641 if (ret == MLX5_TXCMP_CODE_EXIT) {
4643 * The routine returns this code when
4644 * all packets are sent or there is no
4645 * enough resources to complete request.
4649 if (ret == MLX5_TXCMP_CODE_ERROR) {
4651 * The routine returns this code when
4652 * some error in the incoming packets
4655 txq->stats.oerrors++;
4658 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4660 * The single-segment packet was encountered
4661 * in the array, try to send it with the
4662 * best optimized way, possible engaging eMPW.
4664 goto enter_send_single;
4666 if (MLX5_TXOFF_CONFIG(TSO) &&
4667 ret == MLX5_TXCMP_CODE_TSO) {
4669 * The single-segment TSO packet was
4670 * encountered in the array.
4672 goto enter_send_tso;
4674 /* We must not get here. Something is going wrong. */
4676 txq->stats.oerrors++;
4679 /* Dedicated branch for single-segment TSO packets. */
4680 if (MLX5_TXOFF_CONFIG(TSO) &&
4681 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4683 * TSO might require special way for inlining
4684 * (dedicated parameters) and is sent with
4685 * MLX5_OPCODE_TSO opcode only, provide this
4686 * in dedicated branch.
4689 assert(NB_SEGS(loc.mbuf) == 1);
4690 assert(pkts_n > loc.pkts_sent);
4691 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4693 * These returned code checks are supposed
4694 * to be optimized out due to routine inlining.
4696 if (ret == MLX5_TXCMP_CODE_EXIT)
4698 if (ret == MLX5_TXCMP_CODE_ERROR) {
4699 txq->stats.oerrors++;
4702 if (ret == MLX5_TXCMP_CODE_SINGLE)
4703 goto enter_send_single;
4704 if (MLX5_TXOFF_CONFIG(MULTI) &&
4705 ret == MLX5_TXCMP_CODE_MULTI) {
4707 * The multi-segment packet was
4708 * encountered in the array.
4710 goto enter_send_multi;
4712 /* We must not get here. Something is going wrong. */
4714 txq->stats.oerrors++;
4718 * The dedicated branch for the single-segment packets
4719 * without TSO. Often these ones can be sent using
4720 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4721 * The routine builds the WQEs till it encounters
4722 * the TSO or multi-segment packet (in case if these
4723 * offloads are requested at SQ configuration time).
4726 assert(pkts_n > loc.pkts_sent);
4727 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4729 * These returned code checks are supposed
4730 * to be optimized out due to routine inlining.
4732 if (ret == MLX5_TXCMP_CODE_EXIT)
4734 if (ret == MLX5_TXCMP_CODE_ERROR) {
4735 txq->stats.oerrors++;
4738 if (MLX5_TXOFF_CONFIG(MULTI) &&
4739 ret == MLX5_TXCMP_CODE_MULTI) {
4741 * The multi-segment packet was
4742 * encountered in the array.
4744 goto enter_send_multi;
4746 if (MLX5_TXOFF_CONFIG(TSO) &&
4747 ret == MLX5_TXCMP_CODE_TSO) {
4749 * The single-segment TSO packet was
4750 * encountered in the array.
4752 goto enter_send_tso;
4754 /* We must not get here. Something is going wrong. */
4756 txq->stats.oerrors++;
4760 * Main Tx loop is completed, do the rest:
4761 * - set completion request if thresholds are reached
4762 * - doorbell the hardware
4763 * - copy the rest of mbufs to elts (if any)
4765 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4766 /* Take a shortcut if nothing is sent. */
4767 if (unlikely(loc.pkts_sent == loc.pkts_loop))
4769 /* Request CQE generation if limits are reached. */
4770 mlx5_tx_request_completion(txq, &loc, olx);
4772 * Ring QP doorbell immediately after WQE building completion
4773 * to improve latencies. The pure software related data treatment
4774 * can be completed after doorbell. Tx CQEs for this SQ are
4775 * processed in this thread only by the polling.
4777 * The rdma core library can map doorbell register in two ways,
4778 * depending on the environment variable "MLX5_SHUT_UP_BF":
4780 * - as regular cached memory, the variable is either missing or
4781 * set to zero. This type of mapping may cause the significant
4782 * doorbell register writing latency and requires explicit
4783 * memory write barrier to mitigate this issue and prevent
4786 * - as non-cached memory, the variable is present and set to
4787 * not "0" value. This type of mapping may cause performance
4788 * impact under heavy loading conditions but the explicit write
4789 * memory barrier is not required and it may improve core
4792 * - the legacy behaviour (prior 19.08 release) was to use some
4793 * heuristics to decide whether write memory barrier should
4794 * be performed. This behavior is supported with specifying
4795 * tx_db_nc=2, write barrier is skipped if application
4796 * provides the full recommended burst of packets, it
4797 * supposes the next packets are coming and the write barrier
4798 * will be issued on the next burst (after descriptor writing,
4801 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
4802 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
4803 /* Not all of the mbufs may be stored into elts yet. */
4804 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4805 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4807 * There are some single-segment mbufs not stored in elts.
4808 * It can be only if the last packet was single-segment.
4809 * The copying is gathered into one place due to it is
4810 * a good opportunity to optimize that with SIMD.
4811 * Unfortunately if inlining is enabled the gaps in
4812 * pointer array may happen due to early freeing of the
4815 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4816 loc.pkts_copy = loc.pkts_sent;
4818 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4819 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4820 if (pkts_n > loc.pkts_sent) {
4822 * If burst size is large there might be no enough CQE
4823 * fetched from completion queue and no enough resources
4824 * freed to send all the packets.
4829 #ifdef MLX5_PMD_SOFT_COUNTERS
4830 /* Increment sent packets counter. */
4831 txq->stats.opackets += loc.pkts_sent;
4833 return loc.pkts_sent;
4836 /* Generate routines with Enhanced Multi-Packet Write support. */
4837 MLX5_TXOFF_DECL(full_empw,
4838 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4840 MLX5_TXOFF_DECL(none_empw,
4841 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4843 MLX5_TXOFF_DECL(md_empw,
4844 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4846 MLX5_TXOFF_DECL(mt_empw,
4847 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4848 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4850 MLX5_TXOFF_DECL(mtsc_empw,
4851 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4852 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4853 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4855 MLX5_TXOFF_DECL(mti_empw,
4856 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4857 MLX5_TXOFF_CONFIG_INLINE |
4858 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4860 MLX5_TXOFF_DECL(mtv_empw,
4861 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4862 MLX5_TXOFF_CONFIG_VLAN |
4863 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4865 MLX5_TXOFF_DECL(mtiv_empw,
4866 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4867 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4868 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4870 MLX5_TXOFF_DECL(sc_empw,
4871 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4872 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4874 MLX5_TXOFF_DECL(sci_empw,
4875 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4876 MLX5_TXOFF_CONFIG_INLINE |
4877 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4879 MLX5_TXOFF_DECL(scv_empw,
4880 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4881 MLX5_TXOFF_CONFIG_VLAN |
4882 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4884 MLX5_TXOFF_DECL(sciv_empw,
4885 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4886 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4887 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4889 MLX5_TXOFF_DECL(i_empw,
4890 MLX5_TXOFF_CONFIG_INLINE |
4891 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4893 MLX5_TXOFF_DECL(v_empw,
4894 MLX5_TXOFF_CONFIG_VLAN |
4895 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4897 MLX5_TXOFF_DECL(iv_empw,
4898 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4899 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4901 /* Generate routines without Enhanced Multi-Packet Write support. */
4902 MLX5_TXOFF_DECL(full,
4903 MLX5_TXOFF_CONFIG_FULL)
4905 MLX5_TXOFF_DECL(none,
4906 MLX5_TXOFF_CONFIG_NONE)
4909 MLX5_TXOFF_CONFIG_METADATA)
4912 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4913 MLX5_TXOFF_CONFIG_METADATA)
4915 MLX5_TXOFF_DECL(mtsc,
4916 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4917 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4918 MLX5_TXOFF_CONFIG_METADATA)
4920 MLX5_TXOFF_DECL(mti,
4921 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4922 MLX5_TXOFF_CONFIG_INLINE |
4923 MLX5_TXOFF_CONFIG_METADATA)
4926 MLX5_TXOFF_DECL(mtv,
4927 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4928 MLX5_TXOFF_CONFIG_VLAN |
4929 MLX5_TXOFF_CONFIG_METADATA)
4932 MLX5_TXOFF_DECL(mtiv,
4933 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4934 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4935 MLX5_TXOFF_CONFIG_METADATA)
4938 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4939 MLX5_TXOFF_CONFIG_METADATA)
4941 MLX5_TXOFF_DECL(sci,
4942 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4943 MLX5_TXOFF_CONFIG_INLINE |
4944 MLX5_TXOFF_CONFIG_METADATA)
4947 MLX5_TXOFF_DECL(scv,
4948 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4949 MLX5_TXOFF_CONFIG_VLAN |
4950 MLX5_TXOFF_CONFIG_METADATA)
4953 MLX5_TXOFF_DECL(sciv,
4954 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4955 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4956 MLX5_TXOFF_CONFIG_METADATA)
4959 MLX5_TXOFF_CONFIG_INLINE |
4960 MLX5_TXOFF_CONFIG_METADATA)
4963 MLX5_TXOFF_CONFIG_VLAN |
4964 MLX5_TXOFF_CONFIG_METADATA)
4967 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4968 MLX5_TXOFF_CONFIG_METADATA)
4971 * Generate routines with Legacy Multi-Packet Write support.
4972 * This mode is supported by ConnectX-4LX only and imposes
4973 * offload limitations, not supported:
4974 * - ACL/Flows (metadata are becoming meaningless)
4975 * - WQE Inline headers
4976 * - SRIOV (E-Switch offloads)
4978 * - tunnel encapsulation/decapsulation
4981 MLX5_TXOFF_DECL(none_mpw,
4982 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
4983 MLX5_TXOFF_CONFIG_MPW)
4985 MLX5_TXOFF_DECL(mci_mpw,
4986 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
4987 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
4988 MLX5_TXOFF_CONFIG_MPW)
4990 MLX5_TXOFF_DECL(mc_mpw,
4991 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
4992 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
4994 MLX5_TXOFF_DECL(i_mpw,
4995 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
4996 MLX5_TXOFF_CONFIG_MPW)
4999 * Array of declared and compiled Tx burst function and corresponding
5000 * supported offloads set. The array is used to select the Tx burst
5001 * function for specified offloads set at Tx queue configuration time.
5004 eth_tx_burst_t func;
5007 MLX5_TXOFF_INFO(full_empw,
5008 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5009 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5010 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5011 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5013 MLX5_TXOFF_INFO(none_empw,
5014 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5016 MLX5_TXOFF_INFO(md_empw,
5017 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5019 MLX5_TXOFF_INFO(mt_empw,
5020 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5021 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5023 MLX5_TXOFF_INFO(mtsc_empw,
5024 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5025 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5026 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5028 MLX5_TXOFF_INFO(mti_empw,
5029 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5030 MLX5_TXOFF_CONFIG_INLINE |
5031 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5033 MLX5_TXOFF_INFO(mtv_empw,
5034 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5035 MLX5_TXOFF_CONFIG_VLAN |
5036 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5038 MLX5_TXOFF_INFO(mtiv_empw,
5039 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5040 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5041 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5043 MLX5_TXOFF_INFO(sc_empw,
5044 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5045 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5047 MLX5_TXOFF_INFO(sci_empw,
5048 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5049 MLX5_TXOFF_CONFIG_INLINE |
5050 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5052 MLX5_TXOFF_INFO(scv_empw,
5053 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5054 MLX5_TXOFF_CONFIG_VLAN |
5055 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5057 MLX5_TXOFF_INFO(sciv_empw,
5058 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5059 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5060 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5062 MLX5_TXOFF_INFO(i_empw,
5063 MLX5_TXOFF_CONFIG_INLINE |
5064 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5066 MLX5_TXOFF_INFO(v_empw,
5067 MLX5_TXOFF_CONFIG_VLAN |
5068 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5070 MLX5_TXOFF_INFO(iv_empw,
5071 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5072 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5074 MLX5_TXOFF_INFO(full,
5075 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5076 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5077 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5078 MLX5_TXOFF_CONFIG_METADATA)
5080 MLX5_TXOFF_INFO(none,
5081 MLX5_TXOFF_CONFIG_NONE)
5084 MLX5_TXOFF_CONFIG_METADATA)
5087 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5088 MLX5_TXOFF_CONFIG_METADATA)
5090 MLX5_TXOFF_INFO(mtsc,
5091 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5092 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5093 MLX5_TXOFF_CONFIG_METADATA)
5095 MLX5_TXOFF_INFO(mti,
5096 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5097 MLX5_TXOFF_CONFIG_INLINE |
5098 MLX5_TXOFF_CONFIG_METADATA)
5100 MLX5_TXOFF_INFO(mtv,
5101 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5102 MLX5_TXOFF_CONFIG_VLAN |
5103 MLX5_TXOFF_CONFIG_METADATA)
5105 MLX5_TXOFF_INFO(mtiv,
5106 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5107 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5108 MLX5_TXOFF_CONFIG_METADATA)
5111 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5112 MLX5_TXOFF_CONFIG_METADATA)
5114 MLX5_TXOFF_INFO(sci,
5115 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5116 MLX5_TXOFF_CONFIG_INLINE |
5117 MLX5_TXOFF_CONFIG_METADATA)
5119 MLX5_TXOFF_INFO(scv,
5120 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5121 MLX5_TXOFF_CONFIG_VLAN |
5122 MLX5_TXOFF_CONFIG_METADATA)
5124 MLX5_TXOFF_INFO(sciv,
5125 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5126 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5127 MLX5_TXOFF_CONFIG_METADATA)
5130 MLX5_TXOFF_CONFIG_INLINE |
5131 MLX5_TXOFF_CONFIG_METADATA)
5134 MLX5_TXOFF_CONFIG_VLAN |
5135 MLX5_TXOFF_CONFIG_METADATA)
5138 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5139 MLX5_TXOFF_CONFIG_METADATA)
5141 MLX5_TXOFF_INFO(none_mpw,
5142 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5143 MLX5_TXOFF_CONFIG_MPW)
5145 MLX5_TXOFF_INFO(mci_mpw,
5146 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5147 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5148 MLX5_TXOFF_CONFIG_MPW)
5150 MLX5_TXOFF_INFO(mc_mpw,
5151 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5152 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5154 MLX5_TXOFF_INFO(i_mpw,
5155 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5156 MLX5_TXOFF_CONFIG_MPW)
5160 * Configure the Tx function to use. The routine checks configured
5161 * Tx offloads for the device and selects appropriate Tx burst
5162 * routine. There are multiple Tx burst routines compiled from
5163 * the same template in the most optimal way for the dedicated
5167 * Pointer to private data structure.
5170 * Pointer to selected Tx burst function.
5173 mlx5_select_tx_function(struct rte_eth_dev *dev)
5175 struct mlx5_priv *priv = dev->data->dev_private;
5176 struct mlx5_dev_config *config = &priv->config;
5177 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5178 unsigned int diff = 0, olx = 0, i, m;
5180 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5181 MLX5_DSEG_MAX, "invalid WQE max size");
5182 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5183 "invalid WQE Control Segment size");
5184 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5185 "invalid WQE Ethernet Segment size");
5186 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5187 "invalid WQE Data Segment size");
5188 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5189 "invalid WQE size");
5191 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5192 /* We should support Multi-Segment Packets. */
5193 olx |= MLX5_TXOFF_CONFIG_MULTI;
5195 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5196 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5197 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5198 DEV_TX_OFFLOAD_IP_TNL_TSO |
5199 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5200 /* We should support TCP Send Offload. */
5201 olx |= MLX5_TXOFF_CONFIG_TSO;
5203 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5204 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5205 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5206 /* We should support Software Parser for Tunnels. */
5207 olx |= MLX5_TXOFF_CONFIG_SWP;
5209 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5210 DEV_TX_OFFLOAD_UDP_CKSUM |
5211 DEV_TX_OFFLOAD_TCP_CKSUM |
5212 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5213 /* We should support IP/TCP/UDP Checksums. */
5214 olx |= MLX5_TXOFF_CONFIG_CSUM;
5216 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5217 /* We should support VLAN insertion. */
5218 olx |= MLX5_TXOFF_CONFIG_VLAN;
5220 if (priv->txqs_n && (*priv->txqs)[0]) {
5221 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5223 if (txd->inlen_send) {
5225 * Check the data inline requirements. Data inline
5226 * is enabled on per device basis, we can check
5227 * the first Tx queue only.
5229 * If device does not support VLAN insertion in WQE
5230 * and some queues are requested to perform VLAN
5231 * insertion offload than inline must be enabled.
5233 olx |= MLX5_TXOFF_CONFIG_INLINE;
5236 if (config->mps == MLX5_MPW_ENHANCED &&
5237 config->txq_inline_min <= 0) {
5239 * The NIC supports Enhanced Multi-Packet Write
5240 * and does not require minimal inline data.
5242 olx |= MLX5_TXOFF_CONFIG_EMPW;
5244 if (rte_flow_dynf_metadata_avail()) {
5245 /* We should support Flow metadata. */
5246 olx |= MLX5_TXOFF_CONFIG_METADATA;
5248 if (config->mps == MLX5_MPW) {
5250 * The NIC supports Legacy Multi-Packet Write.
5251 * The MLX5_TXOFF_CONFIG_MPW controls the
5252 * descriptor building method in combination
5253 * with MLX5_TXOFF_CONFIG_EMPW.
5255 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5256 MLX5_TXOFF_CONFIG_SWP |
5257 MLX5_TXOFF_CONFIG_VLAN |
5258 MLX5_TXOFF_CONFIG_METADATA)))
5259 olx |= MLX5_TXOFF_CONFIG_EMPW |
5260 MLX5_TXOFF_CONFIG_MPW;
5263 * Scan the routines table to find the minimal
5264 * satisfying routine with requested offloads.
5266 m = RTE_DIM(txoff_func);
5267 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5270 tmp = txoff_func[i].olx;
5272 /* Meets requested offloads exactly.*/
5276 if ((tmp & olx) != olx) {
5277 /* Does not meet requested offloads at all. */
5280 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5281 /* Do not enable eMPW if not configured. */
5283 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5284 /* Do not enable inlining if not configured. */
5287 * Some routine meets the requirements.
5288 * Check whether it has minimal amount
5289 * of not requested offloads.
5291 tmp = __builtin_popcountl(tmp & ~olx);
5292 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5293 /* First or better match, save and continue. */
5299 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5300 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5301 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5302 /* Lighter not requested offload. */
5307 if (m >= RTE_DIM(txoff_func)) {
5308 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5309 " for requested offloads %04X",
5310 dev->data->port_id, olx);
5313 DRV_LOG(DEBUG, "port %u has selected Tx function"
5314 " supporting offloads %04X/%04X",
5315 dev->data->port_id, olx, txoff_func[m].olx);
5316 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5317 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5318 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5319 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5320 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5321 DRV_LOG(DEBUG, "\tSWP (software parser)");
5322 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5323 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5324 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5325 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5326 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5327 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5328 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5329 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5330 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5331 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5332 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5334 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5336 return txoff_func[m].func;
git.droids-corp.org / dpdk.git / blob