drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28 #include <rte_cycles.h>
  29
  30 #include "mlx5.h"
  31 #include "mlx5_utils.h"
  32 #include "mlx5_rxtx.h"
  33 #include "mlx5_autoconf.h"
  34 #include "mlx5_defs.h"
  35 #include "mlx5_prm.h"
  36
  37 static __rte_always_inline uint32_t
  38 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  39
  40 static __rte_always_inline int
  41 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  42                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
  43
  44 static __rte_always_inline uint32_t
  45 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  46
  47 static __rte_always_inline void
  48 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  49                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  50
  51 static __rte_always_inline void
  52 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
  53
  54 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  55         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  56 };
  57
  58 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  59 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  60
  61 /**
  62  * Build a table to translate Rx completion flags to packet type.
  63  *
  64  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  65  */
  66 void
  67 mlx5_set_ptype_table(void)
  68 {
  69         unsigned int i;
  70         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  71
  72         /* Last entry must not be overwritten, reserved for errored packet. */
  73         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  74                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  75         /*
  76          * The index to the array should have:
  77          * bit[1:0] = l3_hdr_type
  78          * bit[4:2] = l4_hdr_type
  79          * bit[5] = ip_frag
  80          * bit[6] = tunneled
  81          * bit[7] = outer_l3_type
  82          */
  83         /* L2 */
  84         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  85         /* L3 */
  86         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  87                      RTE_PTYPE_L4_NONFRAG;
  88         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  89                      RTE_PTYPE_L4_NONFRAG;
  90         /* Fragmented */
  91         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  92                      RTE_PTYPE_L4_FRAG;
  93         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  94                      RTE_PTYPE_L4_FRAG;
  95         /* TCP */
  96         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  97                      RTE_PTYPE_L4_TCP;
  98         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  99                      RTE_PTYPE_L4_TCP;
 100         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_TCP;
 102         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_TCP;
 104         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_TCP;
 106         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 107                      RTE_PTYPE_L4_TCP;
 108         /* UDP */
 109         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_UDP;
 111         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 112                      RTE_PTYPE_L4_UDP;
 113         /* Repeat with outer_l3_type being set. Just in case. */
 114         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_NONFRAG;
 116         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_NONFRAG;
 118         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_FRAG;
 120         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_FRAG;
 122         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_TCP;
 124         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_TCP;
 126         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_TCP;
 128         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_TCP;
 130         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_TCP;
 132         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_TCP;
 134         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_UDP;
 136         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_UDP;
 138         /* Tunneled - L3 */
 139         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 147         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L4_NONFRAG;
 150         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_NONFRAG;
 153         /* Tunneled - Fragmented */
 154         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_FRAG;
 157         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L4_FRAG;
 160         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L4_FRAG;
 163         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L4_FRAG;
 166         /* Tunneled - TCP */
 167         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_TCP;
 170         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L4_TCP;
 173         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L4_TCP;
 176         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 178                      RTE_PTYPE_INNER_L4_TCP;
 179         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_TCP;
 182         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_TCP;
 185         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_TCP;
 188         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_TCP;
 191         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L4_TCP;
 194         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_TCP;
 197         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_TCP;
 200         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L4_TCP;
 203         /* Tunneled - UDP */
 204         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 206                      RTE_PTYPE_INNER_L4_UDP;
 207         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 209                      RTE_PTYPE_INNER_L4_UDP;
 210         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_UDP;
 213         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_UDP;
 216 }
 217
 218 /**
 219  * Build a table to translate packet to checksum type of Verbs.
 220  */
 221 void
 222 mlx5_set_cksum_table(void)
 223 {
 224         unsigned int i;
 225         uint8_t v;
 226
 227         /*
 228          * The index should have:
 229          * bit[0] = PKT_TX_TCP_SEG
 230          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 231          * bit[4] = PKT_TX_IP_CKSUM
 232          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 233          * bit[9] = tunnel
 234          */
 235         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 236                 v = 0;
 237                 if (i & (1 << 9)) {
 238                         /* Tunneled packet. */
 239                         if (i & (1 << 8)) /* Outer IP. */
 240                                 v |= MLX5_ETH_WQE_L3_CSUM;
 241                         if (i & (1 << 4)) /* Inner IP. */
 242                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 243                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 244                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 245                 } else {
 246                         /* No tunnel. */
 247                         if (i & (1 << 4)) /* IP. */
 248                                 v |= MLX5_ETH_WQE_L3_CSUM;
 249                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 250                                 v |= MLX5_ETH_WQE_L4_CSUM;
 251                 }
 252                 mlx5_cksum_table[i] = v;
 253         }
 254 }
 255
 256 /**
 257  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 258  */
 259 void
 260 mlx5_set_swp_types_table(void)
 261 {
 262         unsigned int i;
 263         uint8_t v;
 264
 265         /*
 266          * The index should have:
 267          * bit[0:1] = PKT_TX_L4_MASK
 268          * bit[4] = PKT_TX_IPV6
 269          * bit[8] = PKT_TX_OUTER_IPV6
 270          * bit[9] = PKT_TX_OUTER_UDP
 271          */
 272         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 273                 v = 0;
 274                 if (i & (1 << 8))
 275                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 276                 if (i & (1 << 9))
 277                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 278                 if (i & (1 << 4))
 279                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 280                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 281                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 282                 mlx5_swp_types_table[i] = v;
 283         }
 284 }
 285
 286 /**
 287  * Return the size of tailroom of WQ.
 288  *
 289  * @param txq
 290  *   Pointer to TX queue structure.
 291  * @param addr
 292  *   Pointer to tail of WQ.
 293  *
 294  * @return
 295  *   Size of tailroom.
 296  */
 297 static inline size_t
 298 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 299 {
 300         size_t tailroom;
 301         tailroom = (uintptr_t)(txq->wqes) +
 302                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 303                    (uintptr_t)addr;
 304         return tailroom;
 305 }
 306
 307 /**
 308  * Copy data to tailroom of circular queue.
 309  *
 310  * @param dst
 311  *   Pointer to destination.
 312  * @param src
 313  *   Pointer to source.
 314  * @param n
 315  *   Number of bytes to copy.
 316  * @param base
 317  *   Pointer to head of queue.
 318  * @param tailroom
 319  *   Size of tailroom from dst.
 320  *
 321  * @return
 322  *   Pointer after copied data.
 323  */
 324 static inline void *
 325 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 326                 void *base, size_t tailroom)
 327 {
 328         void *ret;
 329
 330         if (n > tailroom) {
 331                 rte_memcpy(dst, src, tailroom);
 332                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 333                            n - tailroom);
 334                 ret = (uint8_t *)base + n - tailroom;
 335         } else {
 336                 rte_memcpy(dst, src, n);
 337                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 338         }
 339         return ret;
 340 }
 341
 342 /**
 343  * Inline TSO headers into WQE.
 344  *
 345  * @return
 346  *   0 on success, negative errno value on failure.
 347  */
 348 static int
 349 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 350            uint32_t *length,
 351            uintptr_t *addr,
 352            uint16_t *pkt_inline_sz,
 353            uint8_t **raw,
 354            uint16_t *max_wqe,
 355            uint16_t *tso_segsz,
 356            uint16_t *tso_header_sz)
 357 {
 358         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 359                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 360         unsigned int copy_b;
 361         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 362         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 363                                  PKT_TX_TUNNEL_MASK);
 364         uint16_t n_wqe;
 365
 366         *tso_segsz = buf->tso_segsz;
 367         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 368         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 369                 txq->stats.oerrors++;
 370                 return -EINVAL;
 371         }
 372         if (tunneled)
 373                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 374         /* First seg must contain all TSO headers. */
 375         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 376                      *tso_header_sz > DATA_LEN(buf)) {
 377                 txq->stats.oerrors++;
 378                 return -EINVAL;
 379         }
 380         copy_b = *tso_header_sz - *pkt_inline_sz;
 381         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 382                 return -EAGAIN;
 383         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 384         if (unlikely(*max_wqe < n_wqe))
 385                 return -EINVAL;
 386         *max_wqe -= n_wqe;
 387         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 388         *length -= copy_b;
 389         *addr += copy_b;
 390         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 391         *pkt_inline_sz += copy_b;
 392         *raw += copy_b;
 393         return 0;
 394 }
 395
 396 /**
 397  * DPDK callback to check the status of a tx descriptor.
 398  *
 399  * @param tx_queue
 400  *   The tx queue.
 401  * @param[in] offset
 402  *   The index of the descriptor in the ring.
 403  *
 404  * @return
 405  *   The status of the tx descriptor.
 406  */
 407 int
 408 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 409 {
 410         struct mlx5_txq_data *txq = tx_queue;
 411         uint16_t used;
 412
 413         mlx5_tx_complete(txq);
 414         used = txq->elts_head - txq->elts_tail;
 415         if (offset < used)
 416                 return RTE_ETH_TX_DESC_FULL;
 417         return RTE_ETH_TX_DESC_DONE;
 418 }
 419
 420 /**
 421  * Internal function to compute the number of used descriptors in an RX queue
 422  *
 423  * @param rxq
 424  *   The Rx queue.
 425  *
 426  * @return
 427  *   The number of used rx descriptor.
 428  */
 429 static uint32_t
 430 rx_queue_count(struct mlx5_rxq_data *rxq)
 431 {
 432         struct rxq_zip *zip = &rxq->zip;
 433         volatile struct mlx5_cqe *cqe;
 434         const unsigned int cqe_n = (1 << rxq->cqe_n);
 435         const unsigned int cqe_cnt = cqe_n - 1;
 436         unsigned int cq_ci;
 437         unsigned int used;
 438
 439         /* if we are processing a compressed cqe */
 440         if (zip->ai) {
 441                 used = zip->cqe_cnt - zip->ca;
 442                 cq_ci = zip->cq_ci;
 443         } else {
 444                 used = 0;
 445                 cq_ci = rxq->cq_ci;
 446         }
 447         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 448         while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
 449                 int8_t op_own;
 450                 unsigned int n;
 451
 452                 op_own = cqe->op_own;
 453                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 454                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 455                 else
 456                         n = 1;
 457                 cq_ci += n;
 458                 used += n;
 459                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 460         }
 461         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 462         return used;
 463 }
 464
 465 /**
 466  * DPDK callback to check the status of a rx descriptor.
 467  *
 468  * @param rx_queue
 469  *   The Rx queue.
 470  * @param[in] offset
 471  *   The index of the descriptor in the ring.
 472  *
 473  * @return
 474  *   The status of the tx descriptor.
 475  */
 476 int
 477 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 478 {
 479         struct mlx5_rxq_data *rxq = rx_queue;
 480         struct mlx5_rxq_ctrl *rxq_ctrl =
 481                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 482         struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
 483
 484         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 485                 rte_errno = ENOTSUP;
 486                 return -rte_errno;
 487         }
 488         if (offset >= (1 << rxq->elts_n)) {
 489                 rte_errno = EINVAL;
 490                 return -rte_errno;
 491         }
 492         if (offset < rx_queue_count(rxq))
 493                 return RTE_ETH_RX_DESC_DONE;
 494         return RTE_ETH_RX_DESC_AVAIL;
 495 }
 496
 497 /**
 498  * DPDK callback to get the number of used descriptors in a RX queue
 499  *
 500  * @param dev
 501  *   Pointer to the device structure.
 502  *
 503  * @param rx_queue_id
 504  *   The Rx queue.
 505  *
 506  * @return
 507  *   The number of used rx descriptor.
 508  *   -EINVAL if the queue is invalid
 509  */
 510 uint32_t
 511 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 512 {
 513         struct mlx5_priv *priv = dev->data->dev_private;
 514         struct mlx5_rxq_data *rxq;
 515
 516         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 517                 rte_errno = ENOTSUP;
 518                 return -rte_errno;
 519         }
 520         rxq = (*priv->rxqs)[rx_queue_id];
 521         if (!rxq) {
 522                 rte_errno = EINVAL;
 523                 return -rte_errno;
 524         }
 525         return rx_queue_count(rxq);
 526 }
 527
 528 #define MLX5_SYSTEM_LOG_DIR "/var/log"
 529 /**
 530  * Dump debug information to log file.
 531  *
 532  * @param fname
 533  *   The file name.
 534  * @param hex_title
 535  *   If not NULL this string is printed as a header to the output
 536  *   and the output will be in hexadecimal view.
 537  * @param buf
 538  *   This is the buffer address to print out.
 539  * @param len
 540  *   The number of bytes to dump out.
 541  */
 542 void
 543 mlx5_dump_debug_information(const char *fname, const char *hex_title,
 544                             const void *buf, unsigned int hex_len)
 545 {
 546         FILE *fd;
 547
 548         MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
 549         fd = fopen(path, "a+");
 550         if (!fd) {
 551                 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
 552                         path);
 553                 MKSTR(path2, "./%s", fname);
 554                 fd = fopen(path2, "a+");
 555                 if (!fd) {
 556                         DRV_LOG(ERR, "cannot open %s for debug dump\n",
 557                                 path2);
 558                         return;
 559                 }
 560                 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
 561         } else {
 562                 DRV_LOG(INFO, "New debug dump in file %s\n", path);
 563         }
 564         if (hex_title)
 565                 rte_hexdump(fd, hex_title, buf, hex_len);
 566         else
 567                 fprintf(fd, "%s", (const char *)buf);
 568         fprintf(fd, "\n\n\n");
 569         fclose(fd);
 570 }
 571
 572 /**
 573  * Move QP from error state to running state.
 574  *
 575  * @param txq
 576  *   Pointer to TX queue structure.
 577  * @param qp
 578  *   The qp pointer for recovery.
 579  *
 580  * @return
 581  *   0 on success, else errno value.
 582  */
 583 static int
 584 tx_recover_qp(struct mlx5_txq_data *txq, struct ibv_qp *qp)
 585 {
 586         int ret;
 587         struct ibv_qp_attr mod = {
 588                                         .qp_state = IBV_QPS_RESET,
 589                                         .port_num = 1,
 590                                 };
 591         ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
 592         if (ret) {
 593                 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET %d\n",
 594                         ret);
 595                 return ret;
 596         }
 597         mod.qp_state = IBV_QPS_INIT;
 598         ret = mlx5_glue->modify_qp(qp, &mod,
 599                                    (IBV_QP_STATE | IBV_QP_PORT));
 600         if (ret) {
 601                 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %d\n", ret);
 602                 return ret;
 603         }
 604         mod.qp_state = IBV_QPS_RTR;
 605         ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
 606         if (ret) {
 607                 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %d\n", ret);
 608                 return ret;
 609         }
 610         mod.qp_state = IBV_QPS_RTS;
 611         ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
 612         if (ret) {
 613                 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %d\n", ret);
 614                 return ret;
 615         }
 616         txq->wqe_ci = 0;
 617         txq->wqe_pi = 0;
 618         txq->elts_comp = 0;
 619         return 0;
 620 }
 621
 622 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
 623 static int
 624 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
 625 {
 626         static const uint8_t magic[] = "seen";
 627         int ret = 1;
 628         unsigned int i;
 629
 630         for (i = 0; i < sizeof(magic); ++i)
 631                 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
 632                         ret = 0;
 633                         err_cqe->rsvd1[i] = magic[i];
 634                 }
 635         return ret;
 636 }
 637
 638 /**
 639  * Handle error CQE.
 640  *
 641  * @param txq
 642  *   Pointer to TX queue structure.
 643  * @param error_cqe
 644  *   Pointer to the error CQE.
 645  *
 646  * @return
 647  *   The last Tx buffer element to free.
 648  */
 649 uint16_t
 650 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *txq,
 651                          volatile struct mlx5_err_cqe *err_cqe)
 652 {
 653         if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
 654                 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
 655                 struct mlx5_txq_ctrl *txq_ctrl =
 656                                 container_of(txq, struct mlx5_txq_ctrl, txq);
 657                 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
 658                 int seen = check_err_cqe_seen(err_cqe);
 659
 660                 if (!seen && txq_ctrl->dump_file_n <
 661                     txq_ctrl->priv->config.max_dump_files_num) {
 662                         MKSTR(err_str, "Unexpected CQE error syndrome "
 663                               "0x%02x CQN = %u SQN = %u wqe_counter = %u "
 664                               "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
 665                               txq_ctrl->cqn, txq->qp_num_8s >> 8,
 666                               rte_be_to_cpu_16(err_cqe->wqe_counter),
 667                               txq->wqe_ci, txq->cq_ci);
 668                         MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
 669                               PORT_ID(txq_ctrl->priv), txq->idx,
 670                               txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
 671                         mlx5_dump_debug_information(name, NULL, err_str, 0);
 672                         mlx5_dump_debug_information(name, "MLX5 Error CQ:",
 673                                                     (const void *)((uintptr_t)
 674                                                     &(*txq->cqes)[0]),
 675                                                     sizeof(*err_cqe) *
 676                                                     (1 << txq->cqe_n));
 677                         mlx5_dump_debug_information(name, "MLX5 Error SQ:",
 678                                                     (const void *)((uintptr_t)
 679                                                     tx_mlx5_wqe(txq, 0)),
 680                                                     MLX5_WQE_SIZE *
 681                                                     (1 << txq->wqe_n));
 682                         txq_ctrl->dump_file_n++;
 683                 }
 684                 if (!seen)
 685                         /*
 686                          * Count errors in WQEs units.
 687                          * Later it can be improved to count error packets,
 688                          * for example, by SQ parsing to find how much packets
 689                          * should be counted for each WQE.
 690                          */
 691                         txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
 692                                                 new_wqe_pi) & wqe_m;
 693                 if ((rte_eal_process_type() == RTE_PROC_PRIMARY) &&
 694                     tx_recover_qp(txq, txq_ctrl->ibv->qp) == 0) {
 695                         txq->cq_ci++;
 696                         /* Release all the remaining buffers. */
 697                         return txq->elts_head;
 698                 }
 699                 /* Recovering failed - try again later on the same WQE. */
 700         } else {
 701                 txq->cq_ci++;
 702         }
 703         /* Do not release buffers. */
 704         return txq->elts_tail;
 705 }
 706
 707 /**
 708  * DPDK callback for TX.
 709  *
 710  * @param dpdk_txq
 711  *   Generic pointer to TX queue structure.
 712  * @param[in] pkts
 713  *   Packets to transmit.
 714  * @param pkts_n
 715  *   Number of packets in array.
 716  *
 717  * @return
 718  *   Number of packets successfully transmitted (<= pkts_n).
 719  */
 720 uint16_t
 721 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 722 {
 723         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 724         uint16_t elts_head = txq->elts_head;
 725         const uint16_t elts_n = 1 << txq->elts_n;
 726         const uint16_t elts_m = elts_n - 1;
 727         unsigned int i = 0;
 728         unsigned int j = 0;
 729         unsigned int k = 0;
 730         uint16_t max_elts;
 731         uint16_t max_wqe;
 732         unsigned int comp;
 733         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 734         unsigned int segs_n = 0;
 735         const unsigned int max_inline = txq->max_inline;
 736         uint64_t addr_64;
 737
 738         if (unlikely(!pkts_n))
 739                 return 0;
 740         /* Prefetch first packet cacheline. */
 741         rte_prefetch0(*pkts);
 742         /* Start processing. */
 743         mlx5_tx_complete(txq);
 744         max_elts = (elts_n - (elts_head - txq->elts_tail));
 745         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 746         if (unlikely(!max_wqe))
 747                 return 0;
 748         do {
 749                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 750                 uint8_t *raw;
 751                 volatile struct mlx5_wqe_v *wqe = NULL;
 752                 volatile rte_v128u32_t *dseg = NULL;
 753                 uint32_t length;
 754                 unsigned int ds = 0;
 755                 unsigned int sg = 0; /* counter of additional segs attached. */
 756                 uintptr_t addr;
 757                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 758                 uint16_t tso_header_sz = 0;
 759                 uint16_t ehdr;
 760                 uint8_t cs_flags;
 761                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 762                 uint32_t swp_offsets = 0;
 763                 uint8_t swp_types = 0;
 764                 rte_be32_t metadata;
 765                 uint16_t tso_segsz = 0;
 766 #ifdef MLX5_PMD_SOFT_COUNTERS
 767                 uint32_t total_length = 0;
 768 #endif
 769                 int ret;
 770
 771                 segs_n = buf->nb_segs;
 772                 /*
 773                  * Make sure there is enough room to store this packet and
 774                  * that one ring entry remains unused.
 775                  */
 776                 assert(segs_n);
 777                 if (max_elts < segs_n)
 778                         break;
 779                 max_elts -= segs_n;
 780                 sg = --segs_n;
 781                 if (unlikely(--max_wqe == 0))
 782                         break;
 783                 wqe = (volatile struct mlx5_wqe_v *)
 784                         tx_mlx5_wqe(txq, txq->wqe_ci);
 785                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 786                 if (pkts_n - i > 1)
 787                         rte_prefetch0(*(pkts + 1));
 788                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 789                 length = DATA_LEN(buf);
 790                 ehdr = (((uint8_t *)addr)[1] << 8) |
 791                        ((uint8_t *)addr)[0];
 792 #ifdef MLX5_PMD_SOFT_COUNTERS
 793                 total_length = length;
 794 #endif
 795                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 796                         txq->stats.oerrors++;
 797                         break;
 798                 }
 799                 /* Update element. */
 800                 (*txq->elts)[elts_head & elts_m] = buf;
 801                 /* Prefetch next buffer data. */
 802                 if (pkts_n - i > 1)
 803                         rte_prefetch0(
 804                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 805                 cs_flags = txq_ol_cksum_to_cs(buf);
 806                 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
 807                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 808                 /* Copy metadata from mbuf if valid */
 809                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
 810                                                              0;
 811                 /* Replace the Ethernet type by the VLAN if necessary. */
 812                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 813                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 814                                                          buf->vlan_tci);
 815                         unsigned int len = 2 * RTE_ETHER_ADDR_LEN - 2;
 816
 817                         addr += 2;
 818                         length -= 2;
 819                         /* Copy Destination and source mac address. */
 820                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 821                         /* Copy VLAN. */
 822                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 823                         /* Copy missing two bytes to end the DSeg. */
 824                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 825                                ((uint8_t *)addr) + len, 2);
 826                         addr += len + 2;
 827                         length -= (len + 2);
 828                 } else {
 829                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 830                                MLX5_WQE_DWORD_SIZE);
 831                         length -= pkt_inline_sz;
 832                         addr += pkt_inline_sz;
 833                 }
 834                 raw += MLX5_WQE_DWORD_SIZE;
 835                 if (tso) {
 836                         ret = inline_tso(txq, buf, &length,
 837                                          &addr, &pkt_inline_sz,
 838                                          &raw, &max_wqe,
 839                                          &tso_segsz, &tso_header_sz);
 840                         if (ret == -EINVAL) {
 841                                 break;
 842                         } else if (ret == -EAGAIN) {
 843                                 /* NOP WQE. */
 844                                 wqe->ctrl = (rte_v128u32_t){
 845                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 846                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 847                                         rte_cpu_to_be_32
 848                                                 (MLX5_COMP_ONLY_FIRST_ERR <<
 849                                                  MLX5_COMP_MODE_OFFSET),
 850                                         0,
 851                                 };
 852                                 ds = 1;
 853 #ifdef MLX5_PMD_SOFT_COUNTERS
 854                                 total_length = 0;
 855 #endif
 856                                 k++;
 857                                 goto next_wqe;
 858                         }
 859                 }
 860                 /* Inline if enough room. */
 861                 if (max_inline || tso) {
 862                         uint32_t inl = 0;
 863                         uintptr_t end = (uintptr_t)
 864                                 (((uintptr_t)txq->wqes) +
 865                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 866                         unsigned int inline_room = max_inline *
 867                                                    RTE_CACHE_LINE_SIZE -
 868                                                    (pkt_inline_sz - 2) -
 869                                                    !!tso * sizeof(inl);
 870                         uintptr_t addr_end;
 871                         unsigned int copy_b;
 872
 873 pkt_inline:
 874                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 875                                                    RTE_CACHE_LINE_SIZE);
 876                         copy_b = (addr_end > addr) ?
 877                                  RTE_MIN((addr_end - addr), length) : 0;
 878                         if (copy_b && ((end - (uintptr_t)raw) >
 879                                        (copy_b + sizeof(inl)))) {
 880                                 /*
 881                                  * One Dseg remains in the current WQE.  To
 882                                  * keep the computation positive, it is
 883                                  * removed after the bytes to Dseg conversion.
 884                                  */
 885                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 886
 887                                 if (unlikely(max_wqe < n))
 888                                         break;
 889                                 max_wqe -= n;
 890                                 if (tso) {
 891                                         assert(inl == 0);
 892                                         inl = rte_cpu_to_be_32(copy_b |
 893                                                                MLX5_INLINE_SEG);
 894                                         rte_memcpy((void *)raw,
 895                                                    (void *)&inl, sizeof(inl));
 896                                         raw += sizeof(inl);
 897                                         pkt_inline_sz += sizeof(inl);
 898                                 }
 899                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 900                                 addr += copy_b;
 901                                 length -= copy_b;
 902                                 pkt_inline_sz += copy_b;
 903                         }
 904                         /*
 905                          * 2 DWORDs consumed by the WQE header + ETH segment +
 906                          * the size of the inline part of the packet.
 907                          */
 908                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 909                         if (length > 0) {
 910                                 if (ds % (MLX5_WQE_SIZE /
 911                                           MLX5_WQE_DWORD_SIZE) == 0) {
 912                                         if (unlikely(--max_wqe == 0))
 913                                                 break;
 914                                         dseg = (volatile rte_v128u32_t *)
 915                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 916                                                            ds / 4);
 917                                 } else {
 918                                         dseg = (volatile rte_v128u32_t *)
 919                                                 ((uintptr_t)wqe +
 920                                                  (ds * MLX5_WQE_DWORD_SIZE));
 921                                 }
 922                                 goto use_dseg;
 923                         } else if (!segs_n) {
 924                                 goto next_pkt;
 925                         } else {
 926                                 /*
 927                                  * Further inline the next segment only for
 928                                  * non-TSO packets.
 929                                  */
 930                                 if (!tso) {
 931                                         raw += copy_b;
 932                                         inline_room -= copy_b;
 933                                 } else {
 934                                         inline_room = 0;
 935                                 }
 936                                 /* Move to the next segment. */
 937                                 --segs_n;
 938                                 buf = buf->next;
 939                                 assert(buf);
 940                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 941                                 length = DATA_LEN(buf);
 942 #ifdef MLX5_PMD_SOFT_COUNTERS
 943                                 total_length += length;
 944 #endif
 945                                 (*txq->elts)[++elts_head & elts_m] = buf;
 946                                 goto pkt_inline;
 947                         }
 948                 } else {
 949                         /*
 950                          * No inline has been done in the packet, only the
 951                          * Ethernet Header as been stored.
 952                          */
 953                         dseg = (volatile rte_v128u32_t *)
 954                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 955                         ds = 3;
 956 use_dseg:
 957                         /* Add the remaining packet as a simple ds. */
 958                         addr_64 = rte_cpu_to_be_64(addr);
 959                         *dseg = (rte_v128u32_t){
 960                                 rte_cpu_to_be_32(length),
 961                                 mlx5_tx_mb2mr(txq, buf),
 962                                 addr_64,
 963                                 addr_64 >> 32,
 964                         };
 965                         ++ds;
 966                         if (!segs_n)
 967                                 goto next_pkt;
 968                 }
 969 next_seg:
 970                 assert(buf);
 971                 assert(ds);
 972                 assert(wqe);
 973                 /*
 974                  * Spill on next WQE when the current one does not have
 975                  * enough room left. Size of WQE must a be a multiple
 976                  * of data segment size.
 977                  */
 978                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 979                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 980                         if (unlikely(--max_wqe == 0))
 981                                 break;
 982                         dseg = (volatile rte_v128u32_t *)
 983                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 984                         rte_prefetch0(tx_mlx5_wqe(txq,
 985                                                   txq->wqe_ci + ds / 4 + 1));
 986                 } else {
 987                         ++dseg;
 988                 }
 989                 ++ds;
 990                 buf = buf->next;
 991                 assert(buf);
 992                 length = DATA_LEN(buf);
 993 #ifdef MLX5_PMD_SOFT_COUNTERS
 994                 total_length += length;
 995 #endif
 996                 /* Store segment information. */
 997                 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 998                 *dseg = (rte_v128u32_t){
 999                         rte_cpu_to_be_32(length),
1000                         mlx5_tx_mb2mr(txq, buf),
1001                         addr_64,
1002                         addr_64 >> 32,
1003                 };
1004                 (*txq->elts)[++elts_head & elts_m] = buf;
1005                 if (--segs_n)
1006                         goto next_seg;
1007 next_pkt:
1008                 if (ds > MLX5_DSEG_MAX) {
1009                         txq->stats.oerrors++;
1010                         break;
1011                 }
1012                 ++elts_head;
1013                 ++pkts;
1014                 ++i;
1015                 j += sg;
1016                 /* Initialize known and common part of the WQE structure. */
1017                 if (tso) {
1018                         wqe->ctrl = (rte_v128u32_t){
1019                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
1020                                                  MLX5_OPCODE_TSO),
1021                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
1022                                 rte_cpu_to_be_32(MLX5_COMP_ONLY_FIRST_ERR <<
1023                                                  MLX5_COMP_MODE_OFFSET),
1024                                 0,
1025                         };
1026                         wqe->eseg = (rte_v128u32_t){
1027                                 swp_offsets,
1028                                 cs_flags | (swp_types << 8) |
1029                                 (rte_cpu_to_be_16(tso_segsz) << 16),
1030                                 metadata,
1031                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
1032                         };
1033                 } else {
1034                         wqe->ctrl = (rte_v128u32_t){
1035                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
1036                                                  MLX5_OPCODE_SEND),
1037                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
1038                                 rte_cpu_to_be_32(MLX5_COMP_ONLY_FIRST_ERR <<
1039                                                  MLX5_COMP_MODE_OFFSET),
1040                                 0,
1041                         };
1042                         wqe->eseg = (rte_v128u32_t){
1043                                 swp_offsets,
1044                                 cs_flags | (swp_types << 8),
1045                                 metadata,
1046                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
1047                         };
1048                 }
1049 next_wqe:
1050                 txq->wqe_ci += (ds + 3) / 4;
1051                 /* Save the last successful WQE for completion request */
1052                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
1053 #ifdef MLX5_PMD_SOFT_COUNTERS
1054                 /* Increment sent bytes counter. */
1055                 txq->stats.obytes += total_length;
1056 #endif
1057         } while (i < pkts_n);
1058         /* Take a shortcut if nothing must be sent. */
1059         if (unlikely((i + k) == 0))
1060                 return 0;
1061         txq->elts_head += (i + j);
1062         /* Check whether completion threshold has been reached. */
1063         comp = txq->elts_comp + i + j + k;
1064         if (comp >= MLX5_TX_COMP_THRESH) {
1065                 /* A CQE slot must always be available. */
1066                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1067                 /* Request completion on last WQE. */
1068                 last_wqe->ctrl2 = rte_cpu_to_be_32(MLX5_COMP_ALWAYS <<
1069                                                    MLX5_COMP_MODE_OFFSET);
1070                 /* Save elts_head in unused "immediate" field of WQE. */
1071                 last_wqe->ctrl3 = txq->elts_head;
1072                 txq->elts_comp = 0;
1073         } else {
1074                 txq->elts_comp = comp;
1075         }
1076 #ifdef MLX5_PMD_SOFT_COUNTERS
1077         /* Increment sent packets counter. */
1078         txq->stats.opackets += i;
1079 #endif
1080         /* Ring QP doorbell. */
1081         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
1082         return i;
1083 }
1084
1085 /**
1086  * Open a MPW session.
1087  *
1088  * @param txq
1089  *   Pointer to TX queue structure.
1090  * @param mpw
1091  *   Pointer to MPW session structure.
1092  * @param length
1093  *   Packet length.
1094  */
1095 static inline void
1096 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
1097 {
1098         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1099         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
1100                 (volatile struct mlx5_wqe_data_seg (*)[])
1101                 tx_mlx5_wqe(txq, idx + 1);
1102
1103         mpw->state = MLX5_MPW_STATE_OPENED;
1104         mpw->pkts_n = 0;
1105         mpw->len = length;
1106         mpw->total_len = 0;
1107         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1108         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1109         mpw->wqe->eseg.inline_hdr_sz = 0;
1110         mpw->wqe->eseg.rsvd0 = 0;
1111         mpw->wqe->eseg.rsvd1 = 0;
1112         mpw->wqe->eseg.flow_table_metadata = 0;
1113         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1114                                              (txq->wqe_ci << 8) |
1115                                              MLX5_OPCODE_TSO);
1116         mpw->wqe->ctrl[2] = rte_cpu_to_be_32(MLX5_COMP_ONLY_FIRST_ERR <<
1117                                              MLX5_COMP_MODE_OFFSET);
1118         mpw->wqe->ctrl[3] = 0;
1119         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
1120                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1121         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
1122                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
1123         mpw->data.dseg[2] = &(*dseg)[0];
1124         mpw->data.dseg[3] = &(*dseg)[1];
1125         mpw->data.dseg[4] = &(*dseg)[2];
1126 }
1127
1128 /**
1129  * Close a MPW session.
1130  *
1131  * @param txq
1132  *   Pointer to TX queue structure.
1133  * @param mpw
1134  *   Pointer to MPW session structure.
1135  */
1136 static inline void
1137 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1138 {
1139         unsigned int num = mpw->pkts_n;
1140
1141         /*
1142          * Store size in multiple of 16 bytes. Control and Ethernet segments
1143          * count as 2.
1144          */
1145         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
1146         mpw->state = MLX5_MPW_STATE_CLOSED;
1147         if (num < 3)
1148                 ++txq->wqe_ci;
1149         else
1150                 txq->wqe_ci += 2;
1151         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1152         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1153 }
1154
1155 /**
1156  * DPDK callback for TX with MPW support.
1157  *
1158  * @param dpdk_txq
1159  *   Generic pointer to TX queue structure.
1160  * @param[in] pkts
1161  *   Packets to transmit.
1162  * @param pkts_n
1163  *   Number of packets in array.
1164  *
1165  * @return
1166  *   Number of packets successfully transmitted (<= pkts_n).
1167  */
1168 uint16_t
1169 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1170 {
1171         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1172         uint16_t elts_head = txq->elts_head;
1173         const uint16_t elts_n = 1 << txq->elts_n;
1174         const uint16_t elts_m = elts_n - 1;
1175         unsigned int i = 0;
1176         unsigned int j = 0;
1177         uint16_t max_elts;
1178         uint16_t max_wqe;
1179         unsigned int comp;
1180         struct mlx5_mpw mpw = {
1181                 .state = MLX5_MPW_STATE_CLOSED,
1182         };
1183
1184         if (unlikely(!pkts_n))
1185                 return 0;
1186         /* Prefetch first packet cacheline. */
1187         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1188         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1189         /* Start processing. */
1190         mlx5_tx_complete(txq);
1191         max_elts = (elts_n - (elts_head - txq->elts_tail));
1192         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1193         if (unlikely(!max_wqe))
1194                 return 0;
1195         do {
1196                 struct rte_mbuf *buf = *(pkts++);
1197                 uint32_t length;
1198                 unsigned int segs_n = buf->nb_segs;
1199                 uint32_t cs_flags;
1200                 rte_be32_t metadata;
1201
1202                 /*
1203                  * Make sure there is enough room to store this packet and
1204                  * that one ring entry remains unused.
1205                  */
1206                 assert(segs_n);
1207                 if (max_elts < segs_n)
1208                         break;
1209                 /* Do not bother with large packets MPW cannot handle. */
1210                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1211                         txq->stats.oerrors++;
1212                         break;
1213                 }
1214                 max_elts -= segs_n;
1215                 --pkts_n;
1216                 cs_flags = txq_ol_cksum_to_cs(buf);
1217                 /* Copy metadata from mbuf if valid */
1218                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1219                                                              0;
1220                 /* Retrieve packet information. */
1221                 length = PKT_LEN(buf);
1222                 assert(length);
1223                 /* Start new session if packet differs. */
1224                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1225                     ((mpw.len != length) ||
1226                      (segs_n != 1) ||
1227                      (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1228                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1229                         mlx5_mpw_close(txq, &mpw);
1230                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1231                         /*
1232                          * Multi-Packet WQE consumes at most two WQE.
1233                          * mlx5_mpw_new() expects to be able to use such
1234                          * resources.
1235                          */
1236                         if (unlikely(max_wqe < 2))
1237                                 break;
1238                         max_wqe -= 2;
1239                         mlx5_mpw_new(txq, &mpw, length);
1240                         mpw.wqe->eseg.cs_flags = cs_flags;
1241                         mpw.wqe->eseg.flow_table_metadata = metadata;
1242                 }
1243                 /* Multi-segment packets must be alone in their MPW. */
1244                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1245 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1246                 length = 0;
1247 #endif
1248                 do {
1249                         volatile struct mlx5_wqe_data_seg *dseg;
1250                         uintptr_t addr;
1251
1252                         assert(buf);
1253                         (*txq->elts)[elts_head++ & elts_m] = buf;
1254                         dseg = mpw.data.dseg[mpw.pkts_n];
1255                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1256                         *dseg = (struct mlx5_wqe_data_seg){
1257                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1258                                 .lkey = mlx5_tx_mb2mr(txq, buf),
1259                                 .addr = rte_cpu_to_be_64(addr),
1260                         };
1261 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1262                         length += DATA_LEN(buf);
1263 #endif
1264                         buf = buf->next;
1265                         ++mpw.pkts_n;
1266                         ++j;
1267                 } while (--segs_n);
1268                 assert(length == mpw.len);
1269                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1270                         mlx5_mpw_close(txq, &mpw);
1271 #ifdef MLX5_PMD_SOFT_COUNTERS
1272                 /* Increment sent bytes counter. */
1273                 txq->stats.obytes += length;
1274 #endif
1275                 ++i;
1276         } while (pkts_n);
1277         /* Take a shortcut if nothing must be sent. */
1278         if (unlikely(i == 0))
1279                 return 0;
1280         /* Check whether completion threshold has been reached. */
1281         /* "j" includes both packets and segments. */
1282         comp = txq->elts_comp + j;
1283         if (comp >= MLX5_TX_COMP_THRESH) {
1284                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1285
1286                 /* A CQE slot must always be available. */
1287                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1288                 /* Request completion on last WQE. */
1289                 wqe->ctrl[2] = rte_cpu_to_be_32(MLX5_COMP_ALWAYS <<
1290                                                 MLX5_COMP_MODE_OFFSET);
1291                 /* Save elts_head in unused "immediate" field of WQE. */
1292                 wqe->ctrl[3] = elts_head;
1293                 txq->elts_comp = 0;
1294         } else {
1295                 txq->elts_comp = comp;
1296         }
1297 #ifdef MLX5_PMD_SOFT_COUNTERS
1298         /* Increment sent packets counter. */
1299         txq->stats.opackets += i;
1300 #endif
1301         /* Ring QP doorbell. */
1302         if (mpw.state == MLX5_MPW_STATE_OPENED)
1303                 mlx5_mpw_close(txq, &mpw);
1304         mlx5_tx_dbrec(txq, mpw.wqe);
1305         txq->elts_head = elts_head;
1306         return i;
1307 }
1308
1309 /**
1310  * Open a MPW inline session.
1311  *
1312  * @param txq
1313  *   Pointer to TX queue structure.
1314  * @param mpw
1315  *   Pointer to MPW session structure.
1316  * @param length
1317  *   Packet length.
1318  */
1319 static inline void
1320 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1321                     uint32_t length)
1322 {
1323         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1324         struct mlx5_wqe_inl_small *inl;
1325
1326         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1327         mpw->pkts_n = 0;
1328         mpw->len = length;
1329         mpw->total_len = 0;
1330         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1331         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1332                                              (txq->wqe_ci << 8) |
1333                                              MLX5_OPCODE_TSO);
1334         mpw->wqe->ctrl[2] = rte_cpu_to_be_32(MLX5_COMP_ONLY_FIRST_ERR <<
1335                                              MLX5_COMP_MODE_OFFSET);
1336         mpw->wqe->ctrl[3] = 0;
1337         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1338         mpw->wqe->eseg.inline_hdr_sz = 0;
1339         mpw->wqe->eseg.cs_flags = 0;
1340         mpw->wqe->eseg.rsvd0 = 0;
1341         mpw->wqe->eseg.rsvd1 = 0;
1342         mpw->wqe->eseg.flow_table_metadata = 0;
1343         inl = (struct mlx5_wqe_inl_small *)
1344                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1345         mpw->data.raw = (uint8_t *)&inl->raw;
1346 }
1347
1348 /**
1349  * Close a MPW inline session.
1350  *
1351  * @param txq
1352  *   Pointer to TX queue structure.
1353  * @param mpw
1354  *   Pointer to MPW session structure.
1355  */
1356 static inline void
1357 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1358 {
1359         unsigned int size;
1360         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1361                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1362
1363         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1364         /*
1365          * Store size in multiple of 16 bytes. Control and Ethernet segments
1366          * count as 2.
1367          */
1368         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1369                                              MLX5_WQE_DS(size));
1370         mpw->state = MLX5_MPW_STATE_CLOSED;
1371         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1372         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1373 }
1374
1375 /**
1376  * DPDK callback for TX with MPW inline support.
1377  *
1378  * @param dpdk_txq
1379  *   Generic pointer to TX queue structure.
1380  * @param[in] pkts
1381  *   Packets to transmit.
1382  * @param pkts_n
1383  *   Number of packets in array.
1384  *
1385  * @return
1386  *   Number of packets successfully transmitted (<= pkts_n).
1387  */
1388 uint16_t
1389 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1390                          uint16_t pkts_n)
1391 {
1392         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1393         uint16_t elts_head = txq->elts_head;
1394         const uint16_t elts_n = 1 << txq->elts_n;
1395         const uint16_t elts_m = elts_n - 1;
1396         unsigned int i = 0;
1397         unsigned int j = 0;
1398         uint16_t max_elts;
1399         uint16_t max_wqe;
1400         unsigned int comp;
1401         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1402         struct mlx5_mpw mpw = {
1403                 .state = MLX5_MPW_STATE_CLOSED,
1404         };
1405         /*
1406          * Compute the maximum number of WQE which can be consumed by inline
1407          * code.
1408          * - 2 DSEG for:
1409          *   - 1 control segment,
1410          *   - 1 Ethernet segment,
1411          * - N Dseg from the inline request.
1412          */
1413         const unsigned int wqe_inl_n =
1414                 ((2 * MLX5_WQE_DWORD_SIZE +
1415                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1416                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1417
1418         if (unlikely(!pkts_n))
1419                 return 0;
1420         /* Prefetch first packet cacheline. */
1421         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1422         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1423         /* Start processing. */
1424         mlx5_tx_complete(txq);
1425         max_elts = (elts_n - (elts_head - txq->elts_tail));
1426         do {
1427                 struct rte_mbuf *buf = *(pkts++);
1428                 uintptr_t addr;
1429                 uint32_t length;
1430                 unsigned int segs_n = buf->nb_segs;
1431                 uint8_t cs_flags;
1432                 rte_be32_t metadata;
1433
1434                 /*
1435                  * Make sure there is enough room to store this packet and
1436                  * that one ring entry remains unused.
1437                  */
1438                 assert(segs_n);
1439                 if (max_elts < segs_n)
1440                         break;
1441                 /* Do not bother with large packets MPW cannot handle. */
1442                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1443                         txq->stats.oerrors++;
1444                         break;
1445                 }
1446                 max_elts -= segs_n;
1447                 --pkts_n;
1448                 /*
1449                  * Compute max_wqe in case less WQE were consumed in previous
1450                  * iteration.
1451                  */
1452                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1453                 cs_flags = txq_ol_cksum_to_cs(buf);
1454                 /* Copy metadata from mbuf if valid */
1455                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1456                                                              0;
1457                 /* Retrieve packet information. */
1458                 length = PKT_LEN(buf);
1459                 /* Start new session if packet differs. */
1460                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1461                         if ((mpw.len != length) ||
1462                             (segs_n != 1) ||
1463                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1464                             (mpw.wqe->eseg.cs_flags != cs_flags))
1465                                 mlx5_mpw_close(txq, &mpw);
1466                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1467                         if ((mpw.len != length) ||
1468                             (segs_n != 1) ||
1469                             (length > inline_room) ||
1470                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1471                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1472                                 mlx5_mpw_inline_close(txq, &mpw);
1473                                 inline_room =
1474                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1475                         }
1476                 }
1477                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1478                         if ((segs_n != 1) ||
1479                             (length > inline_room)) {
1480                                 /*
1481                                  * Multi-Packet WQE consumes at most two WQE.
1482                                  * mlx5_mpw_new() expects to be able to use
1483                                  * such resources.
1484                                  */
1485                                 if (unlikely(max_wqe < 2))
1486                                         break;
1487                                 max_wqe -= 2;
1488                                 mlx5_mpw_new(txq, &mpw, length);
1489                                 mpw.wqe->eseg.cs_flags = cs_flags;
1490                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1491                         } else {
1492                                 if (unlikely(max_wqe < wqe_inl_n))
1493                                         break;
1494                                 max_wqe -= wqe_inl_n;
1495                                 mlx5_mpw_inline_new(txq, &mpw, length);
1496                                 mpw.wqe->eseg.cs_flags = cs_flags;
1497                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1498                         }
1499                 }
1500                 /* Multi-segment packets must be alone in their MPW. */
1501                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1502                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1503                         assert(inline_room ==
1504                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1505 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1506                         length = 0;
1507 #endif
1508                         do {
1509                                 volatile struct mlx5_wqe_data_seg *dseg;
1510
1511                                 assert(buf);
1512                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1513                                 dseg = mpw.data.dseg[mpw.pkts_n];
1514                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1515                                 *dseg = (struct mlx5_wqe_data_seg){
1516                                         .byte_count =
1517                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1518                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1519                                         .addr = rte_cpu_to_be_64(addr),
1520                                 };
1521 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1522                                 length += DATA_LEN(buf);
1523 #endif
1524                                 buf = buf->next;
1525                                 ++mpw.pkts_n;
1526                                 ++j;
1527                         } while (--segs_n);
1528                         assert(length == mpw.len);
1529                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1530                                 mlx5_mpw_close(txq, &mpw);
1531                 } else {
1532                         unsigned int max;
1533
1534                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1535                         assert(length <= inline_room);
1536                         assert(length == DATA_LEN(buf));
1537                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1538                         (*txq->elts)[elts_head++ & elts_m] = buf;
1539                         /* Maximum number of bytes before wrapping. */
1540                         max = ((((uintptr_t)(txq->wqes)) +
1541                                 (1 << txq->wqe_n) *
1542                                 MLX5_WQE_SIZE) -
1543                                (uintptr_t)mpw.data.raw);
1544                         if (length > max) {
1545                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1546                                            (void *)addr,
1547                                            max);
1548                                 mpw.data.raw = (volatile void *)txq->wqes;
1549                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1550                                            (void *)(addr + max),
1551                                            length - max);
1552                                 mpw.data.raw += length - max;
1553                         } else {
1554                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1555                                            (void *)addr,
1556                                            length);
1557
1558                                 if (length == max)
1559                                         mpw.data.raw =
1560                                                 (volatile void *)txq->wqes;
1561                                 else
1562                                         mpw.data.raw += length;
1563                         }
1564                         ++mpw.pkts_n;
1565                         mpw.total_len += length;
1566                         ++j;
1567                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1568                                 mlx5_mpw_inline_close(txq, &mpw);
1569                                 inline_room =
1570                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1571                         } else {
1572                                 inline_room -= length;
1573                         }
1574                 }
1575 #ifdef MLX5_PMD_SOFT_COUNTERS
1576                 /* Increment sent bytes counter. */
1577                 txq->stats.obytes += length;
1578 #endif
1579                 ++i;
1580         } while (pkts_n);
1581         /* Take a shortcut if nothing must be sent. */
1582         if (unlikely(i == 0))
1583                 return 0;
1584         /* Check whether completion threshold has been reached. */
1585         /* "j" includes both packets and segments. */
1586         comp = txq->elts_comp + j;
1587         if (comp >= MLX5_TX_COMP_THRESH) {
1588                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1589
1590                 /* A CQE slot must always be available. */
1591                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1592                 /* Request completion on last WQE. */
1593                 wqe->ctrl[2] = rte_cpu_to_be_32(MLX5_COMP_ALWAYS <<
1594                                                 MLX5_COMP_MODE_OFFSET);
1595                 /* Save elts_head in unused "immediate" field of WQE. */
1596                 wqe->ctrl[3] = elts_head;
1597                 txq->elts_comp = 0;
1598         } else {
1599                 txq->elts_comp = comp;
1600         }
1601 #ifdef MLX5_PMD_SOFT_COUNTERS
1602         /* Increment sent packets counter. */
1603         txq->stats.opackets += i;
1604 #endif
1605         /* Ring QP doorbell. */
1606         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1607                 mlx5_mpw_inline_close(txq, &mpw);
1608         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1609                 mlx5_mpw_close(txq, &mpw);
1610         mlx5_tx_dbrec(txq, mpw.wqe);
1611         txq->elts_head = elts_head;
1612         return i;
1613 }
1614
1615 /**
1616  * Open an Enhanced MPW session.
1617  *
1618  * @param txq
1619  *   Pointer to TX queue structure.
1620  * @param mpw
1621  *   Pointer to MPW session structure.
1622  * @param length
1623  *   Packet length.
1624  */
1625 static inline void
1626 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1627 {
1628         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1629
1630         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1631         mpw->pkts_n = 0;
1632         mpw->total_len = sizeof(struct mlx5_wqe);
1633         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1634         mpw->wqe->ctrl[0] =
1635                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1636                                  (txq->wqe_ci << 8) |
1637                                  MLX5_OPCODE_ENHANCED_MPSW);
1638         mpw->wqe->ctrl[2] = rte_cpu_to_be_32(MLX5_COMP_ONLY_FIRST_ERR <<
1639                                              MLX5_COMP_MODE_OFFSET);
1640         mpw->wqe->ctrl[3] = 0;
1641         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1642         if (unlikely(padding)) {
1643                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1644
1645                 /* Pad the first 2 DWORDs with zero-length inline header. */
1646                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1647                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1648                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1649                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1650                 /* Start from the next WQEBB. */
1651                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1652         } else {
1653                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1654         }
1655 }
1656
1657 /**
1658  * Close an Enhanced MPW session.
1659  *
1660  * @param txq
1661  *   Pointer to TX queue structure.
1662  * @param mpw
1663  *   Pointer to MPW session structure.
1664  *
1665  * @return
1666  *   Number of consumed WQEs.
1667  */
1668 static inline uint16_t
1669 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1670 {
1671         uint16_t ret;
1672
1673         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1674          * count as 2.
1675          */
1676         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1677                                              MLX5_WQE_DS(mpw->total_len));
1678         mpw->state = MLX5_MPW_STATE_CLOSED;
1679         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1680         txq->wqe_ci += ret;
1681         return ret;
1682 }
1683
1684 /**
1685  * TX with Enhanced MPW support.
1686  *
1687  * @param txq
1688  *   Pointer to TX queue structure.
1689  * @param[in] pkts
1690  *   Packets to transmit.
1691  * @param pkts_n
1692  *   Number of packets in array.
1693  *
1694  * @return
1695  *   Number of packets successfully transmitted (<= pkts_n).
1696  */
1697 static inline uint16_t
1698 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1699                uint16_t pkts_n)
1700 {
1701         uint16_t elts_head = txq->elts_head;
1702         const uint16_t elts_n = 1 << txq->elts_n;
1703         const uint16_t elts_m = elts_n - 1;
1704         unsigned int i = 0;
1705         unsigned int j = 0;
1706         uint16_t max_elts;
1707         uint16_t max_wqe;
1708         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1709         unsigned int mpw_room = 0;
1710         unsigned int inl_pad = 0;
1711         uint32_t inl_hdr;
1712         uint64_t addr_64;
1713         struct mlx5_mpw mpw = {
1714                 .state = MLX5_MPW_STATE_CLOSED,
1715         };
1716
1717         if (unlikely(!pkts_n))
1718                 return 0;
1719         /* Start processing. */
1720         mlx5_tx_complete(txq);
1721         max_elts = (elts_n - (elts_head - txq->elts_tail));
1722         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1723         if (unlikely(!max_wqe))
1724                 return 0;
1725         do {
1726                 struct rte_mbuf *buf = *(pkts++);
1727                 uintptr_t addr;
1728                 unsigned int do_inline = 0; /* Whether inline is possible. */
1729                 uint32_t length;
1730                 uint8_t cs_flags;
1731                 rte_be32_t metadata;
1732
1733                 /* Multi-segmented packet is handled in slow-path outside. */
1734                 assert(NB_SEGS(buf) == 1);
1735                 /* Make sure there is enough room to store this packet. */
1736                 if (max_elts - j == 0)
1737                         break;
1738                 cs_flags = txq_ol_cksum_to_cs(buf);
1739                 /* Copy metadata from mbuf if valid */
1740                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1741                                                              0;
1742                 /* Retrieve packet information. */
1743                 length = PKT_LEN(buf);
1744                 /* Start new session if:
1745                  * - multi-segment packet
1746                  * - no space left even for a dseg
1747                  * - next packet can be inlined with a new WQE
1748                  * - cs_flag differs
1749                  */
1750                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1751                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1752                              mpw_room) ||
1753                             (length <= txq->inline_max_packet_sz &&
1754                              inl_pad + sizeof(inl_hdr) + length >
1755                              mpw_room) ||
1756                              (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1757                             (mpw.wqe->eseg.cs_flags != cs_flags))
1758                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1759                 }
1760                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1761                         /* In Enhanced MPW, inline as much as the budget is
1762                          * allowed. The remaining space is to be filled with
1763                          * dsegs. If the title WQEBB isn't padded, it will have
1764                          * 2 dsegs there.
1765                          */
1766                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1767                                            (max_inline ? max_inline :
1768                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1769                                            MLX5_WQE_SIZE);
1770                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1771                                 break;
1772                         /* Don't pad the title WQEBB to not waste WQ. */
1773                         mlx5_empw_new(txq, &mpw, 0);
1774                         mpw_room -= mpw.total_len;
1775                         inl_pad = 0;
1776                         do_inline = length <= txq->inline_max_packet_sz &&
1777                                     sizeof(inl_hdr) + length <= mpw_room &&
1778                                     !txq->mpw_hdr_dseg;
1779                         mpw.wqe->eseg.cs_flags = cs_flags;
1780                         mpw.wqe->eseg.flow_table_metadata = metadata;
1781                 } else {
1782                         /* Evaluate whether the next packet can be inlined.
1783                          * Inlininig is possible when:
1784                          * - length is less than configured value
1785                          * - length fits for remaining space
1786                          * - not required to fill the title WQEBB with dsegs
1787                          */
1788                         do_inline =
1789                                 length <= txq->inline_max_packet_sz &&
1790                                 inl_pad + sizeof(inl_hdr) + length <=
1791                                  mpw_room &&
1792                                 (!txq->mpw_hdr_dseg ||
1793                                  mpw.total_len >= MLX5_WQE_SIZE);
1794                 }
1795                 if (max_inline && do_inline) {
1796                         /* Inline packet into WQE. */
1797                         unsigned int max;
1798
1799                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1800                         assert(length == DATA_LEN(buf));
1801                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1802                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1803                         mpw.data.raw = (volatile void *)
1804                                 ((uintptr_t)mpw.data.raw + inl_pad);
1805                         max = tx_mlx5_wq_tailroom(txq,
1806                                         (void *)(uintptr_t)mpw.data.raw);
1807                         /* Copy inline header. */
1808                         mpw.data.raw = (volatile void *)
1809                                 mlx5_copy_to_wq(
1810                                           (void *)(uintptr_t)mpw.data.raw,
1811                                           &inl_hdr,
1812                                           sizeof(inl_hdr),
1813                                           (void *)(uintptr_t)txq->wqes,
1814                                           max);
1815                         max = tx_mlx5_wq_tailroom(txq,
1816                                         (void *)(uintptr_t)mpw.data.raw);
1817                         /* Copy packet data. */
1818                         mpw.data.raw = (volatile void *)
1819                                 mlx5_copy_to_wq(
1820                                           (void *)(uintptr_t)mpw.data.raw,
1821                                           (void *)addr,
1822                                           length,
1823                                           (void *)(uintptr_t)txq->wqes,
1824                                           max);
1825                         ++mpw.pkts_n;
1826                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1827                         /* No need to get completion as the entire packet is
1828                          * copied to WQ. Free the buf right away.
1829                          */
1830                         rte_pktmbuf_free_seg(buf);
1831                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1832                         /* Add pad in the next packet if any. */
1833                         inl_pad = (((uintptr_t)mpw.data.raw +
1834                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1835                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1836                                   (uintptr_t)mpw.data.raw;
1837                 } else {
1838                         /* No inline. Load a dseg of packet pointer. */
1839                         volatile rte_v128u32_t *dseg;
1840
1841                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1842                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1843                         assert(length == DATA_LEN(buf));
1844                         if (!tx_mlx5_wq_tailroom(txq,
1845                                         (void *)((uintptr_t)mpw.data.raw
1846                                                 + inl_pad)))
1847                                 dseg = (volatile void *)txq->wqes;
1848                         else
1849                                 dseg = (volatile void *)
1850                                         ((uintptr_t)mpw.data.raw +
1851                                          inl_pad);
1852                         (*txq->elts)[elts_head++ & elts_m] = buf;
1853                         addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1854                                                                     uintptr_t));
1855                         *dseg = (rte_v128u32_t) {
1856                                 rte_cpu_to_be_32(length),
1857                                 mlx5_tx_mb2mr(txq, buf),
1858                                 addr_64,
1859                                 addr_64 >> 32,
1860                         };
1861                         mpw.data.raw = (volatile void *)(dseg + 1);
1862                         mpw.total_len += (inl_pad + sizeof(*dseg));
1863                         ++j;
1864                         ++mpw.pkts_n;
1865                         mpw_room -= (inl_pad + sizeof(*dseg));
1866                         inl_pad = 0;
1867                 }
1868 #ifdef MLX5_PMD_SOFT_COUNTERS
1869                 /* Increment sent bytes counter. */
1870                 txq->stats.obytes += length;
1871 #endif
1872                 ++i;
1873         } while (i < pkts_n);
1874         /* Take a shortcut if nothing must be sent. */
1875         if (unlikely(i == 0))
1876                 return 0;
1877         /* Check whether completion threshold has been reached. */
1878         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1879                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1880                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1881                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1882
1883                 /* A CQE slot must always be available. */
1884                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1885                 /* Request completion on last WQE. */
1886                 wqe->ctrl[2] = rte_cpu_to_be_32(MLX5_COMP_ALWAYS <<
1887                                                 MLX5_COMP_MODE_OFFSET);
1888                 /* Save elts_head in unused "immediate" field of WQE. */
1889                 wqe->ctrl[3] = elts_head;
1890                 txq->elts_comp = 0;
1891                 txq->mpw_comp = txq->wqe_ci;
1892         } else {
1893                 txq->elts_comp += j;
1894         }
1895 #ifdef MLX5_PMD_SOFT_COUNTERS
1896         /* Increment sent packets counter. */
1897         txq->stats.opackets += i;
1898 #endif
1899         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1900                 mlx5_empw_close(txq, &mpw);
1901         /* Ring QP doorbell. */
1902         mlx5_tx_dbrec(txq, mpw.wqe);
1903         txq->elts_head = elts_head;
1904         return i;
1905 }
1906
1907 /**
1908  * DPDK callback for TX with Enhanced MPW support.
1909  *
1910  * @param dpdk_txq
1911  *   Generic pointer to TX queue structure.
1912  * @param[in] pkts
1913  *   Packets to transmit.
1914  * @param pkts_n
1915  *   Number of packets in array.
1916  *
1917  * @return
1918  *   Number of packets successfully transmitted (<= pkts_n).
1919  */
1920 uint16_t
1921 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1922 {
1923         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1924         uint16_t nb_tx = 0;
1925
1926         while (pkts_n > nb_tx) {
1927                 uint16_t n;
1928                 uint16_t ret;
1929
1930                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1931                 if (n) {
1932                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1933                         if (!ret)
1934                                 break;
1935                         nb_tx += ret;
1936                 }
1937                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1938                 if (n) {
1939                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1940                         if (!ret)
1941                                 break;
1942                         nb_tx += ret;
1943                 }
1944         }
1945         return nb_tx;
1946 }
1947
1948 /**
1949  * Translate RX completion flags to packet type.
1950  *
1951  * @param[in] rxq
1952  *   Pointer to RX queue structure.
1953  * @param[in] cqe
1954  *   Pointer to CQE.
1955  *
1956  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1957  *
1958  * @return
1959  *   Packet type for struct rte_mbuf.
1960  */
1961 static inline uint32_t
1962 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1963 {
1964         uint8_t idx;
1965         uint8_t pinfo = cqe->pkt_info;
1966         uint16_t ptype = cqe->hdr_type_etc;
1967
1968         /*
1969          * The index to the array should have:
1970          * bit[1:0] = l3_hdr_type
1971          * bit[4:2] = l4_hdr_type
1972          * bit[5] = ip_frag
1973          * bit[6] = tunneled
1974          * bit[7] = outer_l3_type
1975          */
1976         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1977         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1978 }
1979
1980 /**
1981  * Initialize Rx WQ and indexes.
1982  *
1983  * @param[in] rxq
1984  *   Pointer to RX queue structure.
1985  */
1986 void
1987 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
1988 {
1989         const unsigned int wqe_n = 1 << rxq->elts_n;
1990         unsigned int i;
1991
1992         for (i = 0; (i != wqe_n); ++i) {
1993                 volatile struct mlx5_wqe_data_seg *scat;
1994                 uintptr_t addr;
1995                 uint32_t byte_count;
1996
1997                 if (mlx5_rxq_mprq_enabled(rxq)) {
1998                         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
1999
2000                         scat = &((volatile struct mlx5_wqe_mprq *)
2001                                 rxq->wqes)[i].dseg;
2002                         addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
2003                         byte_count = (1 << rxq->strd_sz_n) *
2004                                         (1 << rxq->strd_num_n);
2005                 } else {
2006                         struct rte_mbuf *buf = (*rxq->elts)[i];
2007
2008                         scat = &((volatile struct mlx5_wqe_data_seg *)
2009                                         rxq->wqes)[i];
2010                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
2011                         byte_count = DATA_LEN(buf);
2012                 }
2013                 /* scat->addr must be able to store a pointer. */
2014                 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
2015                 *scat = (struct mlx5_wqe_data_seg){
2016                         .addr = rte_cpu_to_be_64(addr),
2017                         .byte_count = rte_cpu_to_be_32(byte_count),
2018                         .lkey = mlx5_rx_addr2mr(rxq, addr),
2019                 };
2020         }
2021         rxq->consumed_strd = 0;
2022         rxq->decompressed = 0;
2023         rxq->rq_pi = 0;
2024         rxq->zip = (struct rxq_zip){
2025                 .ai = 0,
2026         };
2027         /* Update doorbell counter. */
2028         rxq->rq_ci = wqe_n >> rxq->sges_n;
2029         rte_cio_wmb();
2030         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2031 }
2032
2033 /**
2034  * Handle a Rx error.
2035  * The function inserts the RQ state to reset when the first error CQE is
2036  * shown, then drains the CQ by the caller function loop. When the CQ is empty,
2037  * it moves the RQ state to ready and initializes the RQ.
2038  * Next CQE identification and error counting are in the caller responsibility.
2039  *
2040  * @param[in] rxq
2041  *   Pointer to RX queue structure.
2042  * @param[in] mbuf_prepare
2043  *   Whether to prepare mbufs for the RQ.
2044  *
2045  * @return
2046  *   -1 in case of recovery error, otherwise the CQE status.
2047  */
2048 int
2049 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
2050 {
2051         const uint16_t cqe_n = 1 << rxq->cqe_n;
2052         const uint16_t cqe_mask = cqe_n - 1;
2053         const unsigned int wqe_n = 1 << rxq->elts_n;
2054         struct mlx5_rxq_ctrl *rxq_ctrl =
2055                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
2056         struct ibv_wq_attr mod = {
2057                 .attr_mask = IBV_WQ_ATTR_STATE,
2058         };
2059         union {
2060                 volatile struct mlx5_cqe *cqe;
2061                 volatile struct mlx5_err_cqe *err_cqe;
2062         } u = {
2063                 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
2064         };
2065         int ret;
2066
2067         switch (rxq->err_state) {
2068         case MLX5_RXQ_ERR_STATE_NO_ERROR:
2069                 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
2070                 /* Fall-through */
2071         case MLX5_RXQ_ERR_STATE_NEED_RESET:
2072                 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2073                         return -1;
2074                 mod.wq_state = IBV_WQS_RESET;
2075                 ret = mlx5_glue->modify_wq(rxq_ctrl->ibv->wq, &mod);
2076                 if (ret) {
2077                         DRV_LOG(ERR, "Cannot change Rx WQ state to RESET %s\n",
2078                                 strerror(errno));
2079                         return -1;
2080                 }
2081                 if (rxq_ctrl->dump_file_n <
2082                     rxq_ctrl->priv->config.max_dump_files_num) {
2083                         MKSTR(err_str, "Unexpected CQE error syndrome "
2084                               "0x%02x CQN = %u RQN = %u wqe_counter = %u"
2085                               " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
2086                               rxq->cqn, rxq_ctrl->ibv->wq->wq_num,
2087                               rte_be_to_cpu_16(u.err_cqe->wqe_counter),
2088                               rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
2089                         MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
2090                               rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
2091                         mlx5_dump_debug_information(name, NULL, err_str, 0);
2092                         mlx5_dump_debug_information(name, "MLX5 Error CQ:",
2093                                                     (const void *)((uintptr_t)
2094                                                                     rxq->cqes),
2095                                                     sizeof(*u.cqe) * cqe_n);
2096                         mlx5_dump_debug_information(name, "MLX5 Error RQ:",
2097                                                     (const void *)((uintptr_t)
2098                                                                     rxq->wqes),
2099                                                     16 * wqe_n);
2100                         rxq_ctrl->dump_file_n++;
2101                 }
2102                 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
2103                 /* Fall-through */
2104         case MLX5_RXQ_ERR_STATE_NEED_READY:
2105                 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
2106                 if (ret == MLX5_CQE_STATUS_HW_OWN) {
2107                         rte_cio_wmb();
2108                         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2109                         rte_cio_wmb();
2110                         /*
2111                          * The RQ consumer index must be zeroed while moving
2112                          * from RESET state to RDY state.
2113                          */
2114                         *rxq->rq_db = rte_cpu_to_be_32(0);
2115                         rte_cio_wmb();
2116                         mod.wq_state = IBV_WQS_RDY;
2117                         ret = mlx5_glue->modify_wq(rxq_ctrl->ibv->wq, &mod);
2118                         if (ret) {
2119                                 DRV_LOG(ERR, "Cannot change Rx WQ state to RDY"
2120                                         " %s\n", strerror(errno));
2121                                 return -1;
2122                         }
2123                         if (mbuf_prepare) {
2124                                 const uint16_t q_mask = wqe_n - 1;
2125                                 uint16_t elt_idx;
2126                                 struct rte_mbuf **elt;
2127                                 int i;
2128                                 unsigned int n = wqe_n - (rxq->rq_ci -
2129                                                           rxq->rq_pi);
2130
2131                                 for (i = 0; i < (int)n; ++i) {
2132                                         elt_idx = (rxq->rq_ci + i) & q_mask;
2133                                         elt = &(*rxq->elts)[elt_idx];
2134                                         *elt = rte_mbuf_raw_alloc(rxq->mp);
2135                                         if (!*elt) {
2136                                                 for (i--; i >= 0; --i) {
2137                                                         elt_idx = (rxq->rq_ci +
2138                                                                    i) & q_mask;
2139                                                         elt = &(*rxq->elts)
2140                                                                 [elt_idx];
2141                                                         rte_pktmbuf_free_seg
2142                                                                 (*elt);
2143                                                 }
2144                                                 return -1;
2145                                         }
2146                                 }
2147                         }
2148                         mlx5_rxq_initialize(rxq);
2149                         rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
2150                 }
2151                 return ret;
2152         default:
2153                 return -1;
2154         }
2155 }
2156
2157 /**
2158  * Get size of the next packet for a given CQE. For compressed CQEs, the
2159  * consumer index is updated only once all packets of the current one have
2160  * been processed.
2161  *
2162  * @param rxq
2163  *   Pointer to RX queue.
2164  * @param cqe
2165  *   CQE to process.
2166  * @param[out] mcqe
2167  *   Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
2168  *   written.
2169  *
2170  * @return
2171  *   0 in case of empty CQE, otherwise the packet size in bytes.
2172  */
2173 static inline int
2174 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
2175                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
2176 {
2177         struct rxq_zip *zip = &rxq->zip;
2178         uint16_t cqe_n = cqe_cnt + 1;
2179         int len;
2180         uint16_t idx, end;
2181
2182         do {
2183                 len = 0;
2184                 /* Process compressed data in the CQE and mini arrays. */
2185                 if (zip->ai) {
2186                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
2187                                 (volatile struct mlx5_mini_cqe8 (*)[8])
2188                                 (uintptr_t)(&(*rxq->cqes)[zip->ca &
2189                                                           cqe_cnt].pkt_info);
2190
2191                         len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
2192                         *mcqe = &(*mc)[zip->ai & 7];
2193                         if ((++zip->ai & 7) == 0) {
2194                                 /* Invalidate consumed CQEs */
2195                                 idx = zip->ca;
2196                                 end = zip->na;
2197                                 while (idx != end) {
2198                                         (*rxq->cqes)[idx & cqe_cnt].op_own =
2199                                                 MLX5_CQE_INVALIDATE;
2200                                         ++idx;
2201                                 }
2202                                 /*
2203                                  * Increment consumer index to skip the number
2204                                  * of CQEs consumed. Hardware leaves holes in
2205                                  * the CQ ring for software use.
2206                                  */
2207                                 zip->ca = zip->na;
2208                                 zip->na += 8;
2209                         }
2210                         if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
2211                                 /* Invalidate the rest */
2212                                 idx = zip->ca;
2213                                 end = zip->cq_ci;
2214
2215                                 while (idx != end) {
2216                                         (*rxq->cqes)[idx & cqe_cnt].op_own =
2217                                                 MLX5_CQE_INVALIDATE;
2218                                         ++idx;
2219                                 }
2220                                 rxq->cq_ci = zip->cq_ci;
2221                                 zip->ai = 0;
2222                         }
2223                 /*
2224                  * No compressed data, get next CQE and verify if it is
2225                  * compressed.
2226                  */
2227                 } else {
2228                         int ret;
2229                         int8_t op_own;
2230
2231                         ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
2232                         if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2233                                 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
2234                                              rxq->err_state)) {
2235                                         ret = mlx5_rx_err_handle(rxq, 0);
2236                                         if (ret == MLX5_CQE_STATUS_HW_OWN ||
2237                                             ret == -1)
2238                                                 return 0;
2239                                 } else {
2240                                         return 0;
2241                                 }
2242                         }
2243                         ++rxq->cq_ci;
2244                         op_own = cqe->op_own;
2245                         if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
2246                                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
2247                                         (volatile struct mlx5_mini_cqe8 (*)[8])
2248                                         (uintptr_t)(&(*rxq->cqes)
2249                                                 [rxq->cq_ci &
2250                                                  cqe_cnt].pkt_info);
2251
2252                                 /* Fix endianness. */
2253                                 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
2254                                 /*
2255                                  * Current mini array position is the one
2256                                  * returned by check_cqe64().
2257                                  *
2258                                  * If completion comprises several mini arrays,
2259                                  * as a special case the second one is located
2260                                  * 7 CQEs after the initial CQE instead of 8
2261                                  * for subsequent ones.
2262                                  */
2263                                 zip->ca = rxq->cq_ci;
2264                                 zip->na = zip->ca + 7;
2265                                 /* Compute the next non compressed CQE. */
2266                                 --rxq->cq_ci;
2267                                 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
2268                                 /* Get packet size to return. */
2269                                 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
2270                                 *mcqe = &(*mc)[0];
2271                                 zip->ai = 1;
2272                                 /* Prefetch all to be invalidated */
2273                                 idx = zip->ca;
2274                                 end = zip->cq_ci;
2275                                 while (idx != end) {
2276                                         rte_prefetch0(&(*rxq->cqes)[(idx) &
2277                                                                     cqe_cnt]);
2278                                         ++idx;
2279                                 }
2280                         } else {
2281                                 len = rte_be_to_cpu_32(cqe->byte_cnt);
2282                         }
2283                 }
2284                 if (unlikely(rxq->err_state)) {
2285                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2286                         ++rxq->stats.idropped;
2287                 } else {
2288                         return len;
2289                 }
2290         } while (1);
2291 }
2292
2293 /**
2294  * Translate RX completion flags to offload flags.
2295  *
2296  * @param[in] cqe
2297  *   Pointer to CQE.
2298  *
2299  * @return
2300  *   Offload flags (ol_flags) for struct rte_mbuf.
2301  */
2302 static inline uint32_t
2303 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
2304 {
2305         uint32_t ol_flags = 0;
2306         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
2307
2308         ol_flags =
2309                 TRANSPOSE(flags,
2310                           MLX5_CQE_RX_L3_HDR_VALID,
2311                           PKT_RX_IP_CKSUM_GOOD) |
2312                 TRANSPOSE(flags,
2313                           MLX5_CQE_RX_L4_HDR_VALID,
2314                           PKT_RX_L4_CKSUM_GOOD);
2315         return ol_flags;
2316 }
2317
2318 /**
2319  * Fill in mbuf fields from RX completion flags.
2320  * Note that pkt->ol_flags should be initialized outside of this function.
2321  *
2322  * @param rxq
2323  *   Pointer to RX queue.
2324  * @param pkt
2325  *   mbuf to fill.
2326  * @param cqe
2327  *   CQE to process.
2328  * @param rss_hash_res
2329  *   Packet RSS Hash result.
2330  */
2331 static inline void
2332 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
2333                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
2334 {
2335         /* Update packet information. */
2336         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
2337         if (rss_hash_res && rxq->rss_hash) {
2338                 pkt->hash.rss = rss_hash_res;
2339                 pkt->ol_flags |= PKT_RX_RSS_HASH;
2340         }
2341         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2342                 pkt->ol_flags |= PKT_RX_FDIR;
2343                 if (cqe->sop_drop_qpn !=
2344                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
2345                         uint32_t mark = cqe->sop_drop_qpn;
2346
2347                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2348                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
2349                 }
2350         }
2351         if (rxq->csum)
2352                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
2353         if (rxq->vlan_strip &&
2354             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
2355                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2356                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
2357         }
2358         if (rxq->hw_timestamp) {
2359                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
2360                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
2361         }
2362 }
2363
2364 /**
2365  * DPDK callback for RX.
2366  *
2367  * @param dpdk_rxq
2368  *   Generic pointer to RX queue structure.
2369  * @param[out] pkts
2370  *   Array to store received packets.
2371  * @param pkts_n
2372  *   Maximum number of packets in array.
2373  *
2374  * @return
2375  *   Number of packets successfully received (<= pkts_n).
2376  */
2377 uint16_t
2378 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2379 {
2380         struct mlx5_rxq_data *rxq = dpdk_rxq;
2381         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
2382         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
2383         const unsigned int sges_n = rxq->sges_n;
2384         struct rte_mbuf *pkt = NULL;
2385         struct rte_mbuf *seg = NULL;
2386         volatile struct mlx5_cqe *cqe =
2387                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2388         unsigned int i = 0;
2389         unsigned int rq_ci = rxq->rq_ci << sges_n;
2390         int len = 0; /* keep its value across iterations. */
2391
2392         while (pkts_n) {
2393                 unsigned int idx = rq_ci & wqe_cnt;
2394                 volatile struct mlx5_wqe_data_seg *wqe =
2395                         &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
2396                 struct rte_mbuf *rep = (*rxq->elts)[idx];
2397                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2398                 uint32_t rss_hash_res;
2399
2400                 if (pkt)
2401                         NEXT(seg) = rep;
2402                 seg = rep;
2403                 rte_prefetch0(seg);
2404                 rte_prefetch0(cqe);
2405                 rte_prefetch0(wqe);
2406                 rep = rte_mbuf_raw_alloc(rxq->mp);
2407                 if (unlikely(rep == NULL)) {
2408                         ++rxq->stats.rx_nombuf;
2409                         if (!pkt) {
2410                                 /*
2411                                  * no buffers before we even started,
2412                                  * bail out silently.
2413                                  */
2414                                 break;
2415                         }
2416                         while (pkt != seg) {
2417                                 assert(pkt != (*rxq->elts)[idx]);
2418                                 rep = NEXT(pkt);
2419                                 NEXT(pkt) = NULL;
2420                                 NB_SEGS(pkt) = 1;
2421                                 rte_mbuf_raw_free(pkt);
2422                                 pkt = rep;
2423                         }
2424                         break;
2425                 }
2426                 if (!pkt) {
2427                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2428                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
2429                         if (!len) {
2430                                 rte_mbuf_raw_free(rep);
2431                                 break;
2432                         }
2433                         pkt = seg;
2434                         assert(len >= (rxq->crc_present << 2));
2435                         pkt->ol_flags = 0;
2436                         /* If compressed, take hash result from mini-CQE. */
2437                         rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
2438                                                         cqe->rx_hash_res :
2439                                                         mcqe->rx_hash_result);
2440                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2441                         if (rxq->crc_present)
2442                                 len -= RTE_ETHER_CRC_LEN;
2443                         PKT_LEN(pkt) = len;
2444                 }
2445                 DATA_LEN(rep) = DATA_LEN(seg);
2446                 PKT_LEN(rep) = PKT_LEN(seg);
2447                 SET_DATA_OFF(rep, DATA_OFF(seg));
2448                 PORT(rep) = PORT(seg);
2449                 (*rxq->elts)[idx] = rep;
2450                 /*
2451                  * Fill NIC descriptor with the new buffer.  The lkey and size
2452                  * of the buffers are already known, only the buffer address
2453                  * changes.
2454                  */
2455                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2456                 /* If there's only one MR, no need to replace LKey in WQE. */
2457                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2458                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2459                 if (len > DATA_LEN(seg)) {
2460                         len -= DATA_LEN(seg);
2461                         ++NB_SEGS(pkt);
2462                         ++rq_ci;
2463                         continue;
2464                 }
2465                 DATA_LEN(seg) = len;
2466 #ifdef MLX5_PMD_SOFT_COUNTERS
2467                 /* Increment bytes counter. */
2468                 rxq->stats.ibytes += PKT_LEN(pkt);
2469 #endif
2470                 /* Return packet. */
2471                 *(pkts++) = pkt;
2472                 pkt = NULL;
2473                 --pkts_n;
2474                 ++i;
2475                 /* Align consumer index to the next stride. */
2476                 rq_ci >>= sges_n;
2477                 ++rq_ci;
2478                 rq_ci <<= sges_n;
2479         }
2480         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2481                 return 0;
2482         /* Update the consumer index. */
2483         rxq->rq_ci = rq_ci >> sges_n;
2484         rte_cio_wmb();
2485         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2486         rte_cio_wmb();
2487         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2488 #ifdef MLX5_PMD_SOFT_COUNTERS
2489         /* Increment packets counter. */
2490         rxq->stats.ipackets += i;
2491 #endif
2492         return i;
2493 }
2494
2495 void
2496 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2497 {
2498         struct mlx5_mprq_buf *buf = opaque;
2499
2500         if (rte_atomic16_read(&buf->refcnt) == 1) {
2501                 rte_mempool_put(buf->mp, buf);
2502         } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2503                 rte_atomic16_set(&buf->refcnt, 1);
2504                 rte_mempool_put(buf->mp, buf);
2505         }
2506 }
2507
2508 void
2509 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2510 {
2511         mlx5_mprq_buf_free_cb(NULL, buf);
2512 }
2513
2514 static inline void
2515 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2516 {
2517         struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2518         volatile struct mlx5_wqe_data_seg *wqe =
2519                 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2520         void *addr;
2521
2522         assert(rep != NULL);
2523         /* Replace MPRQ buf. */
2524         (*rxq->mprq_bufs)[rq_idx] = rep;
2525         /* Replace WQE. */
2526         addr = mlx5_mprq_buf_addr(rep);
2527         wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2528         /* If there's only one MR, no need to replace LKey in WQE. */
2529         if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2530                 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2531         /* Stash a mbuf for next replacement. */
2532         if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2533                 rxq->mprq_repl = rep;
2534         else
2535                 rxq->mprq_repl = NULL;
2536 }
2537
2538 /**
2539  * DPDK callback for RX with Multi-Packet RQ support.
2540  *
2541  * @param dpdk_rxq
2542  *   Generic pointer to RX queue structure.
2543  * @param[out] pkts
2544  *   Array to store received packets.
2545  * @param pkts_n
2546  *   Maximum number of packets in array.
2547  *
2548  * @return
2549  *   Number of packets successfully received (<= pkts_n).
2550  */
2551 uint16_t
2552 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2553 {
2554         struct mlx5_rxq_data *rxq = dpdk_rxq;
2555         const unsigned int strd_n = 1 << rxq->strd_num_n;
2556         const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2557         const unsigned int strd_shift =
2558                 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2559         const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2560         const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2561         volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2562         unsigned int i = 0;
2563         uint32_t rq_ci = rxq->rq_ci;
2564         uint16_t consumed_strd = rxq->consumed_strd;
2565         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2566
2567         while (i < pkts_n) {
2568                 struct rte_mbuf *pkt;
2569                 void *addr;
2570                 int ret;
2571                 unsigned int len;
2572                 uint16_t strd_cnt;
2573                 uint16_t strd_idx;
2574                 uint32_t offset;
2575                 uint32_t byte_cnt;
2576                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2577                 uint32_t rss_hash_res = 0;
2578
2579                 if (consumed_strd == strd_n) {
2580                         /* Replace WQE only if the buffer is still in use. */
2581                         if (rte_atomic16_read(&buf->refcnt) > 1) {
2582                                 mprq_buf_replace(rxq, rq_ci & wq_mask);
2583                                 /* Release the old buffer. */
2584                                 mlx5_mprq_buf_free(buf);
2585                         } else if (unlikely(rxq->mprq_repl == NULL)) {
2586                                 struct mlx5_mprq_buf *rep;
2587
2588                                 /*
2589                                  * Currently, the MPRQ mempool is out of buffer
2590                                  * and doing memcpy regardless of the size of Rx
2591                                  * packet. Retry allocation to get back to
2592                                  * normal.
2593                                  */
2594                                 if (!rte_mempool_get(rxq->mprq_mp,
2595                                                      (void **)&rep))
2596                                         rxq->mprq_repl = rep;
2597                         }
2598                         /* Advance to the next WQE. */
2599                         consumed_strd = 0;
2600                         ++rq_ci;
2601                         buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2602                 }
2603                 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2604                 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2605                 if (!ret)
2606                         break;
2607                 byte_cnt = ret;
2608                 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2609                            MLX5_MPRQ_STRIDE_NUM_SHIFT;
2610                 assert(strd_cnt);
2611                 consumed_strd += strd_cnt;
2612                 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2613                         continue;
2614                 if (mcqe == NULL) {
2615                         rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2616                         strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2617                 } else {
2618                         /* mini-CQE for MPRQ doesn't have hash result. */
2619                         strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2620                 }
2621                 assert(strd_idx < strd_n);
2622                 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2623                 /*
2624                  * Currently configured to receive a packet per a stride. But if
2625                  * MTU is adjusted through kernel interface, device could
2626                  * consume multiple strides without raising an error. In this
2627                  * case, the packet should be dropped because it is bigger than
2628                  * the max_rx_pkt_len.
2629                  */
2630                 if (unlikely(strd_cnt > 1)) {
2631                         ++rxq->stats.idropped;
2632                         continue;
2633                 }
2634                 pkt = rte_pktmbuf_alloc(rxq->mp);
2635                 if (unlikely(pkt == NULL)) {
2636                         ++rxq->stats.rx_nombuf;
2637                         break;
2638                 }
2639                 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2640                 assert((int)len >= (rxq->crc_present << 2));
2641                 if (rxq->crc_present)
2642                         len -= RTE_ETHER_CRC_LEN;
2643                 offset = strd_idx * strd_sz + strd_shift;
2644                 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2645                 /* Initialize the offload flag. */
2646                 pkt->ol_flags = 0;
2647                 /*
2648                  * Memcpy packets to the target mbuf if:
2649                  * - The size of packet is smaller than mprq_max_memcpy_len.
2650                  * - Out of buffer in the Mempool for Multi-Packet RQ.
2651                  */
2652                 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2653                         /*
2654                          * When memcpy'ing packet due to out-of-buffer, the
2655                          * packet must be smaller than the target mbuf.
2656                          */
2657                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2658                                 rte_pktmbuf_free_seg(pkt);
2659                                 ++rxq->stats.idropped;
2660                                 continue;
2661                         }
2662                         rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2663                 } else {
2664                         rte_iova_t buf_iova;
2665                         struct rte_mbuf_ext_shared_info *shinfo;
2666                         uint16_t buf_len = strd_cnt * strd_sz;
2667
2668                         /* Increment the refcnt of the whole chunk. */
2669                         rte_atomic16_add_return(&buf->refcnt, 1);
2670                         assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2671                                strd_n + 1);
2672                         addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2673                         /*
2674                          * MLX5 device doesn't use iova but it is necessary in a
2675                          * case where the Rx packet is transmitted via a
2676                          * different PMD.
2677                          */
2678                         buf_iova = rte_mempool_virt2iova(buf) +
2679                                    RTE_PTR_DIFF(addr, buf);
2680                         shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2681                                         &buf_len, mlx5_mprq_buf_free_cb, buf);
2682                         /*
2683                          * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2684                          * attaching the stride to mbuf and more offload flags
2685                          * will be added below by calling rxq_cq_to_mbuf().
2686                          * Other fields will be overwritten.
2687                          */
2688                         rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2689                                                   shinfo);
2690                         rte_pktmbuf_reset_headroom(pkt);
2691                         assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2692                         /*
2693                          * Prevent potential overflow due to MTU change through
2694                          * kernel interface.
2695                          */
2696                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2697                                 rte_pktmbuf_free_seg(pkt);
2698                                 ++rxq->stats.idropped;
2699                                 continue;
2700                         }
2701                 }
2702                 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2703                 PKT_LEN(pkt) = len;
2704                 DATA_LEN(pkt) = len;
2705                 PORT(pkt) = rxq->port_id;
2706 #ifdef MLX5_PMD_SOFT_COUNTERS
2707                 /* Increment bytes counter. */
2708                 rxq->stats.ibytes += PKT_LEN(pkt);
2709 #endif
2710                 /* Return packet. */
2711                 *(pkts++) = pkt;
2712                 ++i;
2713         }
2714         /* Update the consumer indexes. */
2715         rxq->consumed_strd = consumed_strd;
2716         rte_cio_wmb();
2717         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2718         if (rq_ci != rxq->rq_ci) {
2719                 rxq->rq_ci = rq_ci;
2720                 rte_cio_wmb();
2721                 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2722         }
2723 #ifdef MLX5_PMD_SOFT_COUNTERS
2724         /* Increment packets counter. */
2725         rxq->stats.ipackets += i;
2726 #endif
2727         return i;
2728 }
2729
2730 /**
2731  * Dummy DPDK callback for TX.
2732  *
2733  * This function is used to temporarily replace the real callback during
2734  * unsafe control operations on the queue, or in case of error.
2735  *
2736  * @param dpdk_txq
2737  *   Generic pointer to TX queue structure.
2738  * @param[in] pkts
2739  *   Packets to transmit.
2740  * @param pkts_n
2741  *   Number of packets in array.
2742  *
2743  * @return
2744  *   Number of packets successfully transmitted (<= pkts_n).
2745  */
2746 uint16_t
2747 removed_tx_burst(void *dpdk_txq __rte_unused,
2748                  struct rte_mbuf **pkts __rte_unused,
2749                  uint16_t pkts_n __rte_unused)
2750 {
2751         rte_mb();
2752         return 0;
2753 }
2754
2755 /**
2756  * Dummy DPDK callback for RX.
2757  *
2758  * This function is used to temporarily replace the real callback during
2759  * unsafe control operations on the queue, or in case of error.
2760  *
2761  * @param dpdk_rxq
2762  *   Generic pointer to RX queue structure.
2763  * @param[out] pkts
2764  *   Array to store received packets.
2765  * @param pkts_n
2766  *   Maximum number of packets in array.
2767  *
2768  * @return
2769  *   Number of packets successfully received (<= pkts_n).
2770  */
2771 uint16_t
2772 removed_rx_burst(void *dpdk_txq __rte_unused,
2773                  struct rte_mbuf **pkts __rte_unused,
2774                  uint16_t pkts_n __rte_unused)
2775 {
2776         rte_mb();
2777         return 0;
2778 }
2779
2780 /*
2781  * Vectorized Rx/Tx routines are not compiled in when required vector
2782  * instructions are not supported on a target architecture. The following null
2783  * stubs are needed for linkage when those are not included outside of this file
2784  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2785  */
2786
2787 __rte_weak uint16_t
2788 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2789                       struct rte_mbuf **pkts __rte_unused,
2790                       uint16_t pkts_n __rte_unused)
2791 {
2792         return 0;
2793 }
2794
2795 __rte_weak uint16_t
2796 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2797                   struct rte_mbuf **pkts __rte_unused,
2798                   uint16_t pkts_n __rte_unused)
2799 {
2800         return 0;
2801 }
2802
2803 __rte_weak uint16_t
2804 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2805                   struct rte_mbuf **pkts __rte_unused,
2806                   uint16_t pkts_n __rte_unused)
2807 {
2808         return 0;
2809 }
2810
2811 __rte_weak int
2812 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2813 {
2814         return -ENOTSUP;
2815 }
2816
2817 __rte_weak int
2818 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2819 {
2820         return -ENOTSUP;
2821 }
2822
2823 __rte_weak int
2824 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2825 {
2826         return -ENOTSUP;
2827 }
2828
2829 __rte_weak int
2830 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2831 {
2832         return -ENOTSUP;
2833 }