drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 #include <rte_mbuf.h>
  52 #include <rte_mempool.h>
  53 #include <rte_prefetch.h>
  54 #include <rte_common.h>
  55 #include <rte_branch_prediction.h>
  56 #include <rte_ether.h>
  57
  58 #include "mlx5.h"
  59 #include "mlx5_utils.h"
  60 #include "mlx5_rxtx.h"
  61 #include "mlx5_autoconf.h"
  62 #include "mlx5_defs.h"
  63 #include "mlx5_prm.h"
  64
  65 static __rte_always_inline uint32_t
  66 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  67
  68 static __rte_always_inline int
  69 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  70                  uint16_t cqe_cnt, uint32_t *rss_hash);
  71
  72 static __rte_always_inline uint32_t
  73 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  74
  75 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  76         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  77 };
  78
  79 /**
  80  * Build a table to translate Rx completion flags to packet type.
  81  *
  82  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  83  */
  84 void
  85 mlx5_set_ptype_table(void)
  86 {
  87         unsigned int i;
  88         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  89
  90         /* Last entry must not be overwritten, reserved for errored packet. */
  91         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  92                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  93         /*
  94          * The index to the array should have:
  95          * bit[1:0] = l3_hdr_type
  96          * bit[4:2] = l4_hdr_type
  97          * bit[5] = ip_frag
  98          * bit[6] = tunneled
  99          * bit[7] = outer_l3_type
 100          */
 101         /* L3 */
 102         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_NONFRAG;
 104         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_NONFRAG;
 106         /* Fragmented */
 107         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 108                      RTE_PTYPE_L4_FRAG;
 109         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_FRAG;
 111         /* TCP */
 112         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_TCP;
 114         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_TCP;
 116         /* UDP */
 117         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_UDP;
 119         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_UDP;
 121         /* Repeat with outer_l3_type being set. Just in case. */
 122         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_NONFRAG;
 124         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_NONFRAG;
 126         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_FRAG;
 128         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_FRAG;
 130         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_TCP;
 132         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_TCP;
 134         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_UDP;
 136         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_UDP;
 138         /* Tunneled - L3 */
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L4_NONFRAG;
 148         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L4_NONFRAG;
 151         /* Tunneled - Fragmented */
 152         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L4_FRAG;
 155         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L4_FRAG;
 158         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L4_FRAG;
 161         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L4_FRAG;
 164         /* Tunneled - TCP */
 165         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 167                      RTE_PTYPE_L4_TCP;
 168         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_L4_TCP;
 171         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_L4_TCP;
 174         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_L4_TCP;
 177         /* Tunneled - UDP */
 178         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_L4_UDP;
 181         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_L4_UDP;
 184         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_L4_UDP;
 187         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_L4_UDP;
 190 }
 191
 192 /**
 193  * Return the size of tailroom of WQ.
 194  *
 195  * @param txq
 196  *   Pointer to TX queue structure.
 197  * @param addr
 198  *   Pointer to tail of WQ.
 199  *
 200  * @return
 201  *   Size of tailroom.
 202  */
 203 static inline size_t
 204 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 205 {
 206         size_t tailroom;
 207         tailroom = (uintptr_t)(txq->wqes) +
 208                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 209                    (uintptr_t)addr;
 210         return tailroom;
 211 }
 212
 213 /**
 214  * Copy data to tailroom of circular queue.
 215  *
 216  * @param dst
 217  *   Pointer to destination.
 218  * @param src
 219  *   Pointer to source.
 220  * @param n
 221  *   Number of bytes to copy.
 222  * @param base
 223  *   Pointer to head of queue.
 224  * @param tailroom
 225  *   Size of tailroom from dst.
 226  *
 227  * @return
 228  *   Pointer after copied data.
 229  */
 230 static inline void *
 231 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 232                 void *base, size_t tailroom)
 233 {
 234         void *ret;
 235
 236         if (n > tailroom) {
 237                 rte_memcpy(dst, src, tailroom);
 238                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 239                            n - tailroom);
 240                 ret = (uint8_t *)base + n - tailroom;
 241         } else {
 242                 rte_memcpy(dst, src, n);
 243                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 244         }
 245         return ret;
 246 }
 247
 248 /**
 249  * DPDK callback to check the status of a tx descriptor.
 250  *
 251  * @param tx_queue
 252  *   The tx queue.
 253  * @param[in] offset
 254  *   The index of the descriptor in the ring.
 255  *
 256  * @return
 257  *   The status of the tx descriptor.
 258  */
 259 int
 260 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 261 {
 262         struct txq *txq = tx_queue;
 263         uint16_t used;
 264
 265         mlx5_tx_complete(txq);
 266         used = txq->elts_head - txq->elts_tail;
 267         if (offset < used)
 268                 return RTE_ETH_TX_DESC_FULL;
 269         return RTE_ETH_TX_DESC_DONE;
 270 }
 271
 272 /**
 273  * DPDK callback to check the status of a rx descriptor.
 274  *
 275  * @param rx_queue
 276  *   The rx queue.
 277  * @param[in] offset
 278  *   The index of the descriptor in the ring.
 279  *
 280  * @return
 281  *   The status of the tx descriptor.
 282  */
 283 int
 284 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 285 {
 286         struct rxq *rxq = rx_queue;
 287         struct rxq_zip *zip = &rxq->zip;
 288         volatile struct mlx5_cqe *cqe;
 289         const unsigned int cqe_n = (1 << rxq->cqe_n);
 290         const unsigned int cqe_cnt = cqe_n - 1;
 291         unsigned int cq_ci;
 292         unsigned int used;
 293
 294         /* if we are processing a compressed cqe */
 295         if (zip->ai) {
 296                 used = zip->cqe_cnt - zip->ca;
 297                 cq_ci = zip->cq_ci;
 298         } else {
 299                 used = 0;
 300                 cq_ci = rxq->cq_ci;
 301         }
 302         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 303         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 304                 int8_t op_own;
 305                 unsigned int n;
 306
 307                 op_own = cqe->op_own;
 308                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 309                         n = ntohl(cqe->byte_cnt);
 310                 else
 311                         n = 1;
 312                 cq_ci += n;
 313                 used += n;
 314                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 315         }
 316         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 317         if (offset < used)
 318                 return RTE_ETH_RX_DESC_DONE;
 319         return RTE_ETH_RX_DESC_AVAIL;
 320 }
 321
 322 /**
 323  * DPDK callback for TX.
 324  *
 325  * @param dpdk_txq
 326  *   Generic pointer to TX queue structure.
 327  * @param[in] pkts
 328  *   Packets to transmit.
 329  * @param pkts_n
 330  *   Number of packets in array.
 331  *
 332  * @return
 333  *   Number of packets successfully transmitted (<= pkts_n).
 334  */
 335 uint16_t
 336 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 337 {
 338         struct txq *txq = (struct txq *)dpdk_txq;
 339         uint16_t elts_head = txq->elts_head;
 340         const uint16_t elts_n = 1 << txq->elts_n;
 341         const uint16_t elts_m = elts_n - 1;
 342         unsigned int i = 0;
 343         unsigned int j = 0;
 344         unsigned int k = 0;
 345         uint16_t max_elts;
 346         unsigned int max_inline = txq->max_inline;
 347         const unsigned int inline_en = !!max_inline && txq->inline_en;
 348         uint16_t max_wqe;
 349         unsigned int comp;
 350         volatile struct mlx5_wqe_v *wqe = NULL;
 351         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 352         unsigned int segs_n = 0;
 353         struct rte_mbuf *buf = NULL;
 354         uint8_t *raw;
 355
 356         if (unlikely(!pkts_n))
 357                 return 0;
 358         /* Prefetch first packet cacheline. */
 359         rte_prefetch0(*pkts);
 360         /* Start processing. */
 361         mlx5_tx_complete(txq);
 362         max_elts = (elts_n - (elts_head - txq->elts_tail));
 363         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 364         if (unlikely(!max_wqe))
 365                 return 0;
 366         do {
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint64_t naddr;
 373                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 374                 uint16_t tso_header_sz = 0;
 375                 uint16_t ehdr;
 376                 uint8_t cs_flags = 0;
 377                 uint64_t tso = 0;
 378                 uint16_t tso_segsz = 0;
 379 #ifdef MLX5_PMD_SOFT_COUNTERS
 380                 uint32_t total_length = 0;
 381 #endif
 382
 383                 /* first_seg */
 384                 buf = *pkts;
 385                 segs_n = buf->nb_segs;
 386                 /*
 387                  * Make sure there is enough room to store this packet and
 388                  * that one ring entry remains unused.
 389                  */
 390                 assert(segs_n);
 391                 if (max_elts < segs_n)
 392                         break;
 393                 max_elts -= segs_n;
 394                 --segs_n;
 395                 if (unlikely(--max_wqe == 0))
 396                         break;
 397                 wqe = (volatile struct mlx5_wqe_v *)
 398                         tx_mlx5_wqe(txq, txq->wqe_ci);
 399                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 400                 if (pkts_n - i > 1)
 401                         rte_prefetch0(*(pkts + 1));
 402                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 403                 length = DATA_LEN(buf);
 404                 ehdr = (((uint8_t *)addr)[1] << 8) |
 405                        ((uint8_t *)addr)[0];
 406 #ifdef MLX5_PMD_SOFT_COUNTERS
 407                 total_length = length;
 408 #endif
 409                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 410                         txq->stats.oerrors++;
 411                         break;
 412                 }
 413                 /* Update element. */
 414                 (*txq->elts)[elts_head & elts_m] = buf;
 415                 /* Prefetch next buffer data. */
 416                 if (pkts_n - i > 1)
 417                         rte_prefetch0(
 418                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 419                 /* Should we enable HW CKSUM offload */
 420                 if (buf->ol_flags &
 421                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 422                         const uint64_t is_tunneled = buf->ol_flags &
 423                                                      (PKT_TX_TUNNEL_GRE |
 424                                                       PKT_TX_TUNNEL_VXLAN);
 425
 426                         if (is_tunneled && txq->tunnel_en) {
 427                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 428                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 429                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 430                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 431                         } else {
 432                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 433                                            MLX5_ETH_WQE_L4_CSUM;
 434                         }
 435                 }
 436                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 437                 /* Replace the Ethernet type by the VLAN if necessary. */
 438                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 439                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 440                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 441
 442                         addr += 2;
 443                         length -= 2;
 444                         /* Copy Destination and source mac address. */
 445                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 446                         /* Copy VLAN. */
 447                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 448                         /* Copy missing two bytes to end the DSeg. */
 449                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 450                                ((uint8_t *)addr) + len, 2);
 451                         addr += len + 2;
 452                         length -= (len + 2);
 453                 } else {
 454                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 455                                MLX5_WQE_DWORD_SIZE);
 456                         length -= pkt_inline_sz;
 457                         addr += pkt_inline_sz;
 458                 }
 459                 raw += MLX5_WQE_DWORD_SIZE;
 460                 if (txq->tso_en) {
 461                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 462                         if (tso) {
 463                                 uintptr_t end = (uintptr_t)
 464                                                 (((uintptr_t)txq->wqes) +
 465                                                 (1 << txq->wqe_n) *
 466                                                 MLX5_WQE_SIZE);
 467                                 unsigned int copy_b;
 468                                 uint8_t vlan_sz = (buf->ol_flags &
 469                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 470                                 const uint64_t is_tunneled =
 471                                                         buf->ol_flags &
 472                                                         (PKT_TX_TUNNEL_GRE |
 473                                                          PKT_TX_TUNNEL_VXLAN);
 474
 475                                 tso_header_sz = buf->l2_len + vlan_sz +
 476                                                 buf->l3_len + buf->l4_len;
 477                                 tso_segsz = buf->tso_segsz;
 478                                 if (unlikely(tso_segsz == 0)) {
 479                                         txq->stats.oerrors++;
 480                                         break;
 481                                 }
 482                                 if (is_tunneled && txq->tunnel_en) {
 483                                         tso_header_sz += buf->outer_l2_len +
 484                                                          buf->outer_l3_len;
 485                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 486                                 } else {
 487                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 488                                 }
 489                                 if (unlikely(tso_header_sz >
 490                                              MLX5_MAX_TSO_HEADER)) {
 491                                         txq->stats.oerrors++;
 492                                         break;
 493                                 }
 494                                 copy_b = tso_header_sz - pkt_inline_sz;
 495                                 /* First seg must contain all headers. */
 496                                 assert(copy_b <= length);
 497                                 if (copy_b &&
 498                                    ((end - (uintptr_t)raw) > copy_b)) {
 499                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 500                                                       1 + 3) / 4;
 501
 502                                         if (unlikely(max_wqe < n))
 503                                                 break;
 504                                         max_wqe -= n;
 505                                         rte_memcpy((void *)raw,
 506                                                    (void *)addr, copy_b);
 507                                         addr += copy_b;
 508                                         length -= copy_b;
 509                                         /* Include padding for TSO header. */
 510                                         copy_b = MLX5_WQE_DS(copy_b) *
 511                                                  MLX5_WQE_DWORD_SIZE;
 512                                         pkt_inline_sz += copy_b;
 513                                         raw += copy_b;
 514                                 } else {
 515                                         /* NOP WQE. */
 516                                         wqe->ctrl = (rte_v128u32_t){
 517                                                      htonl(txq->wqe_ci << 8),
 518                                                      htonl(txq->qp_num_8s | 1),
 519                                                      0,
 520                                                      0,
 521                                         };
 522                                         ds = 1;
 523                                         total_length = 0;
 524                                         k++;
 525                                         goto next_wqe;
 526                                 }
 527                         }
 528                 }
 529                 /* Inline if enough room. */
 530                 if (inline_en || tso) {
 531                         uint32_t inl;
 532                         uintptr_t end = (uintptr_t)
 533                                 (((uintptr_t)txq->wqes) +
 534                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 535                         unsigned int inline_room = max_inline *
 536                                                    RTE_CACHE_LINE_SIZE -
 537                                                    (pkt_inline_sz - 2) -
 538                                                    !!tso * sizeof(inl);
 539                         uintptr_t addr_end = (addr + inline_room) &
 540                                              ~(RTE_CACHE_LINE_SIZE - 1);
 541                         unsigned int copy_b = (addr_end > addr) ?
 542                                 RTE_MIN((addr_end - addr), length) :
 543                                 0;
 544
 545                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 546                                 /*
 547                                  * One Dseg remains in the current WQE.  To
 548                                  * keep the computation positive, it is
 549                                  * removed after the bytes to Dseg conversion.
 550                                  */
 551                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 552
 553                                 if (unlikely(max_wqe < n))
 554                                         break;
 555                                 max_wqe -= n;
 556                                 if (tso) {
 557                                         inl = htonl(copy_b | MLX5_INLINE_SEG);
 558                                         rte_memcpy((void *)raw,
 559                                                    (void *)&inl, sizeof(inl));
 560                                         raw += sizeof(inl);
 561                                         pkt_inline_sz += sizeof(inl);
 562                                 }
 563                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 564                                 addr += copy_b;
 565                                 length -= copy_b;
 566                                 pkt_inline_sz += copy_b;
 567                         }
 568                         /*
 569                          * 2 DWORDs consumed by the WQE header + ETH segment +
 570                          * the size of the inline part of the packet.
 571                          */
 572                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 573                         if (length > 0) {
 574                                 if (ds % (MLX5_WQE_SIZE /
 575                                           MLX5_WQE_DWORD_SIZE) == 0) {
 576                                         if (unlikely(--max_wqe == 0))
 577                                                 break;
 578                                         dseg = (volatile rte_v128u32_t *)
 579                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 580                                                            ds / 4);
 581                                 } else {
 582                                         dseg = (volatile rte_v128u32_t *)
 583                                                 ((uintptr_t)wqe +
 584                                                  (ds * MLX5_WQE_DWORD_SIZE));
 585                                 }
 586                                 goto use_dseg;
 587                         } else if (!segs_n) {
 588                                 goto next_pkt;
 589                         } else {
 590                                 /* dseg will be advance as part of next_seg */
 591                                 dseg = (volatile rte_v128u32_t *)
 592                                         ((uintptr_t)wqe +
 593                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 594                                 goto next_seg;
 595                         }
 596                 } else {
 597                         /*
 598                          * No inline has been done in the packet, only the
 599                          * Ethernet Header as been stored.
 600                          */
 601                         dseg = (volatile rte_v128u32_t *)
 602                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 603                         ds = 3;
 604 use_dseg:
 605                         /* Add the remaining packet as a simple ds. */
 606                         naddr = htonll(addr);
 607                         *dseg = (rte_v128u32_t){
 608                                 htonl(length),
 609                                 mlx5_tx_mb2mr(txq, buf),
 610                                 naddr,
 611                                 naddr >> 32,
 612                         };
 613                         ++ds;
 614                         if (!segs_n)
 615                                 goto next_pkt;
 616                 }
 617 next_seg:
 618                 assert(buf);
 619                 assert(ds);
 620                 assert(wqe);
 621                 /*
 622                  * Spill on next WQE when the current one does not have
 623                  * enough room left. Size of WQE must a be a multiple
 624                  * of data segment size.
 625                  */
 626                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 627                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 628                         if (unlikely(--max_wqe == 0))
 629                                 break;
 630                         dseg = (volatile rte_v128u32_t *)
 631                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 632                         rte_prefetch0(tx_mlx5_wqe(txq,
 633                                                   txq->wqe_ci + ds / 4 + 1));
 634                 } else {
 635                         ++dseg;
 636                 }
 637                 ++ds;
 638                 buf = buf->next;
 639                 assert(buf);
 640                 length = DATA_LEN(buf);
 641 #ifdef MLX5_PMD_SOFT_COUNTERS
 642                 total_length += length;
 643 #endif
 644                 /* Store segment information. */
 645                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 646                 *dseg = (rte_v128u32_t){
 647                         htonl(length),
 648                         mlx5_tx_mb2mr(txq, buf),
 649                         naddr,
 650                         naddr >> 32,
 651                 };
 652                 (*txq->elts)[++elts_head & elts_m] = buf;
 653                 ++sg;
 654                 /* Advance counter only if all segs are successfully posted. */
 655                 if (sg < segs_n)
 656                         goto next_seg;
 657                 else
 658                         j += sg;
 659 next_pkt:
 660                 if (ds > MLX5_DSEG_MAX) {
 661                         txq->stats.oerrors++;
 662                         break;
 663                 }
 664                 ++elts_head;
 665                 ++pkts;
 666                 ++i;
 667                 /* Initialize known and common part of the WQE structure. */
 668                 if (tso) {
 669                         wqe->ctrl = (rte_v128u32_t){
 670                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 671                                 htonl(txq->qp_num_8s | ds),
 672                                 0,
 673                                 0,
 674                         };
 675                         wqe->eseg = (rte_v128u32_t){
 676                                 0,
 677                                 cs_flags | (htons(tso_segsz) << 16),
 678                                 0,
 679                                 (ehdr << 16) | htons(tso_header_sz),
 680                         };
 681                 } else {
 682                         wqe->ctrl = (rte_v128u32_t){
 683                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 684                                 htonl(txq->qp_num_8s | ds),
 685                                 0,
 686                                 0,
 687                         };
 688                         wqe->eseg = (rte_v128u32_t){
 689                                 0,
 690                                 cs_flags,
 691                                 0,
 692                                 (ehdr << 16) | htons(pkt_inline_sz),
 693                         };
 694                 }
 695 next_wqe:
 696                 txq->wqe_ci += (ds + 3) / 4;
 697                 /* Save the last successful WQE for completion request */
 698                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 699 #ifdef MLX5_PMD_SOFT_COUNTERS
 700                 /* Increment sent bytes counter. */
 701                 txq->stats.obytes += total_length;
 702 #endif
 703         } while (i < pkts_n);
 704         /* Take a shortcut if nothing must be sent. */
 705         if (unlikely((i + k) == 0))
 706                 return 0;
 707         txq->elts_head += (i + j);
 708         /* Check whether completion threshold has been reached. */
 709         comp = txq->elts_comp + i + j + k;
 710         if (comp >= MLX5_TX_COMP_THRESH) {
 711                 /* Request completion on last WQE. */
 712                 last_wqe->ctrl2 = htonl(8);
 713                 /* Save elts_head in unused "immediate" field of WQE. */
 714                 last_wqe->ctrl3 = txq->elts_head;
 715                 txq->elts_comp = 0;
 716         } else {
 717                 txq->elts_comp = comp;
 718         }
 719 #ifdef MLX5_PMD_SOFT_COUNTERS
 720         /* Increment sent packets counter. */
 721         txq->stats.opackets += i;
 722 #endif
 723         /* Ring QP doorbell. */
 724         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 725         return i;
 726 }
 727
 728 /**
 729  * Open a MPW session.
 730  *
 731  * @param txq
 732  *   Pointer to TX queue structure.
 733  * @param mpw
 734  *   Pointer to MPW session structure.
 735  * @param length
 736  *   Packet length.
 737  */
 738 static inline void
 739 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 740 {
 741         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 742         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 743                 (volatile struct mlx5_wqe_data_seg (*)[])
 744                 tx_mlx5_wqe(txq, idx + 1);
 745
 746         mpw->state = MLX5_MPW_STATE_OPENED;
 747         mpw->pkts_n = 0;
 748         mpw->len = length;
 749         mpw->total_len = 0;
 750         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 751         mpw->wqe->eseg.mss = htons(length);
 752         mpw->wqe->eseg.inline_hdr_sz = 0;
 753         mpw->wqe->eseg.rsvd0 = 0;
 754         mpw->wqe->eseg.rsvd1 = 0;
 755         mpw->wqe->eseg.rsvd2 = 0;
 756         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 757                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 758         mpw->wqe->ctrl[2] = 0;
 759         mpw->wqe->ctrl[3] = 0;
 760         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 761                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 762         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 763                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 764         mpw->data.dseg[2] = &(*dseg)[0];
 765         mpw->data.dseg[3] = &(*dseg)[1];
 766         mpw->data.dseg[4] = &(*dseg)[2];
 767 }
 768
 769 /**
 770  * Close a MPW session.
 771  *
 772  * @param txq
 773  *   Pointer to TX queue structure.
 774  * @param mpw
 775  *   Pointer to MPW session structure.
 776  */
 777 static inline void
 778 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 779 {
 780         unsigned int num = mpw->pkts_n;
 781
 782         /*
 783          * Store size in multiple of 16 bytes. Control and Ethernet segments
 784          * count as 2.
 785          */
 786         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 787         mpw->state = MLX5_MPW_STATE_CLOSED;
 788         if (num < 3)
 789                 ++txq->wqe_ci;
 790         else
 791                 txq->wqe_ci += 2;
 792         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 793         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 794 }
 795
 796 /**
 797  * DPDK callback for TX with MPW support.
 798  *
 799  * @param dpdk_txq
 800  *   Generic pointer to TX queue structure.
 801  * @param[in] pkts
 802  *   Packets to transmit.
 803  * @param pkts_n
 804  *   Number of packets in array.
 805  *
 806  * @return
 807  *   Number of packets successfully transmitted (<= pkts_n).
 808  */
 809 uint16_t
 810 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 811 {
 812         struct txq *txq = (struct txq *)dpdk_txq;
 813         uint16_t elts_head = txq->elts_head;
 814         const uint16_t elts_n = 1 << txq->elts_n;
 815         const uint16_t elts_m = elts_n - 1;
 816         unsigned int i = 0;
 817         unsigned int j = 0;
 818         uint16_t max_elts;
 819         uint16_t max_wqe;
 820         unsigned int comp;
 821         struct mlx5_mpw mpw = {
 822                 .state = MLX5_MPW_STATE_CLOSED,
 823         };
 824
 825         if (unlikely(!pkts_n))
 826                 return 0;
 827         /* Prefetch first packet cacheline. */
 828         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 829         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 830         /* Start processing. */
 831         mlx5_tx_complete(txq);
 832         max_elts = (elts_n - (elts_head - txq->elts_tail));
 833         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 834         if (unlikely(!max_wqe))
 835                 return 0;
 836         do {
 837                 struct rte_mbuf *buf = *(pkts++);
 838                 uint32_t length;
 839                 unsigned int segs_n = buf->nb_segs;
 840                 uint32_t cs_flags = 0;
 841
 842                 /*
 843                  * Make sure there is enough room to store this packet and
 844                  * that one ring entry remains unused.
 845                  */
 846                 assert(segs_n);
 847                 if (max_elts < segs_n)
 848                         break;
 849                 /* Do not bother with large packets MPW cannot handle. */
 850                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 851                         txq->stats.oerrors++;
 852                         break;
 853                 }
 854                 max_elts -= segs_n;
 855                 --pkts_n;
 856                 /* Should we enable HW CKSUM offload */
 857                 if (buf->ol_flags &
 858                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 859                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 860                 /* Retrieve packet information. */
 861                 length = PKT_LEN(buf);
 862                 assert(length);
 863                 /* Start new session if packet differs. */
 864                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 865                     ((mpw.len != length) ||
 866                      (segs_n != 1) ||
 867                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 868                         mlx5_mpw_close(txq, &mpw);
 869                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 870                         /*
 871                          * Multi-Packet WQE consumes at most two WQE.
 872                          * mlx5_mpw_new() expects to be able to use such
 873                          * resources.
 874                          */
 875                         if (unlikely(max_wqe < 2))
 876                                 break;
 877                         max_wqe -= 2;
 878                         mlx5_mpw_new(txq, &mpw, length);
 879                         mpw.wqe->eseg.cs_flags = cs_flags;
 880                 }
 881                 /* Multi-segment packets must be alone in their MPW. */
 882                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 883 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 884                 length = 0;
 885 #endif
 886                 do {
 887                         volatile struct mlx5_wqe_data_seg *dseg;
 888                         uintptr_t addr;
 889
 890                         assert(buf);
 891                         (*txq->elts)[elts_head++ & elts_m] = buf;
 892                         dseg = mpw.data.dseg[mpw.pkts_n];
 893                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 894                         *dseg = (struct mlx5_wqe_data_seg){
 895                                 .byte_count = htonl(DATA_LEN(buf)),
 896                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 897                                 .addr = htonll(addr),
 898                         };
 899 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 900                         length += DATA_LEN(buf);
 901 #endif
 902                         buf = buf->next;
 903                         ++mpw.pkts_n;
 904                         ++j;
 905                 } while (--segs_n);
 906                 assert(length == mpw.len);
 907                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 908                         mlx5_mpw_close(txq, &mpw);
 909 #ifdef MLX5_PMD_SOFT_COUNTERS
 910                 /* Increment sent bytes counter. */
 911                 txq->stats.obytes += length;
 912 #endif
 913                 ++i;
 914         } while (pkts_n);
 915         /* Take a shortcut if nothing must be sent. */
 916         if (unlikely(i == 0))
 917                 return 0;
 918         /* Check whether completion threshold has been reached. */
 919         /* "j" includes both packets and segments. */
 920         comp = txq->elts_comp + j;
 921         if (comp >= MLX5_TX_COMP_THRESH) {
 922                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 923
 924                 /* Request completion on last WQE. */
 925                 wqe->ctrl[2] = htonl(8);
 926                 /* Save elts_head in unused "immediate" field of WQE. */
 927                 wqe->ctrl[3] = elts_head;
 928                 txq->elts_comp = 0;
 929         } else {
 930                 txq->elts_comp = comp;
 931         }
 932 #ifdef MLX5_PMD_SOFT_COUNTERS
 933         /* Increment sent packets counter. */
 934         txq->stats.opackets += i;
 935 #endif
 936         /* Ring QP doorbell. */
 937         if (mpw.state == MLX5_MPW_STATE_OPENED)
 938                 mlx5_mpw_close(txq, &mpw);
 939         mlx5_tx_dbrec(txq, mpw.wqe);
 940         txq->elts_head = elts_head;
 941         return i;
 942 }
 943
 944 /**
 945  * Open a MPW inline session.
 946  *
 947  * @param txq
 948  *   Pointer to TX queue structure.
 949  * @param mpw
 950  *   Pointer to MPW session structure.
 951  * @param length
 952  *   Packet length.
 953  */
 954 static inline void
 955 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 956 {
 957         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 958         struct mlx5_wqe_inl_small *inl;
 959
 960         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 961         mpw->pkts_n = 0;
 962         mpw->len = length;
 963         mpw->total_len = 0;
 964         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 965         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 966                                   (txq->wqe_ci << 8) |
 967                                   MLX5_OPCODE_TSO);
 968         mpw->wqe->ctrl[2] = 0;
 969         mpw->wqe->ctrl[3] = 0;
 970         mpw->wqe->eseg.mss = htons(length);
 971         mpw->wqe->eseg.inline_hdr_sz = 0;
 972         mpw->wqe->eseg.cs_flags = 0;
 973         mpw->wqe->eseg.rsvd0 = 0;
 974         mpw->wqe->eseg.rsvd1 = 0;
 975         mpw->wqe->eseg.rsvd2 = 0;
 976         inl = (struct mlx5_wqe_inl_small *)
 977                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 978         mpw->data.raw = (uint8_t *)&inl->raw;
 979 }
 980
 981 /**
 982  * Close a MPW inline session.
 983  *
 984  * @param txq
 985  *   Pointer to TX queue structure.
 986  * @param mpw
 987  *   Pointer to MPW session structure.
 988  */
 989 static inline void
 990 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
 991 {
 992         unsigned int size;
 993         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 994                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 995
 996         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 997         /*
 998          * Store size in multiple of 16 bytes. Control and Ethernet segments
 999          * count as 2.
1000          */
1001         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1002         mpw->state = MLX5_MPW_STATE_CLOSED;
1003         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1004         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1005 }
1006
1007 /**
1008  * DPDK callback for TX with MPW inline support.
1009  *
1010  * @param dpdk_txq
1011  *   Generic pointer to TX queue structure.
1012  * @param[in] pkts
1013  *   Packets to transmit.
1014  * @param pkts_n
1015  *   Number of packets in array.
1016  *
1017  * @return
1018  *   Number of packets successfully transmitted (<= pkts_n).
1019  */
1020 uint16_t
1021 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1022                          uint16_t pkts_n)
1023 {
1024         struct txq *txq = (struct txq *)dpdk_txq;
1025         uint16_t elts_head = txq->elts_head;
1026         const uint16_t elts_n = 1 << txq->elts_n;
1027         const uint16_t elts_m = elts_n - 1;
1028         unsigned int i = 0;
1029         unsigned int j = 0;
1030         uint16_t max_elts;
1031         uint16_t max_wqe;
1032         unsigned int comp;
1033         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1034         struct mlx5_mpw mpw = {
1035                 .state = MLX5_MPW_STATE_CLOSED,
1036         };
1037         /*
1038          * Compute the maximum number of WQE which can be consumed by inline
1039          * code.
1040          * - 2 DSEG for:
1041          *   - 1 control segment,
1042          *   - 1 Ethernet segment,
1043          * - N Dseg from the inline request.
1044          */
1045         const unsigned int wqe_inl_n =
1046                 ((2 * MLX5_WQE_DWORD_SIZE +
1047                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1048                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1049
1050         if (unlikely(!pkts_n))
1051                 return 0;
1052         /* Prefetch first packet cacheline. */
1053         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1054         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1055         /* Start processing. */
1056         mlx5_tx_complete(txq);
1057         max_elts = (elts_n - (elts_head - txq->elts_tail));
1058         do {
1059                 struct rte_mbuf *buf = *(pkts++);
1060                 uintptr_t addr;
1061                 uint32_t length;
1062                 unsigned int segs_n = buf->nb_segs;
1063                 uint32_t cs_flags = 0;
1064
1065                 /*
1066                  * Make sure there is enough room to store this packet and
1067                  * that one ring entry remains unused.
1068                  */
1069                 assert(segs_n);
1070                 if (max_elts < segs_n)
1071                         break;
1072                 /* Do not bother with large packets MPW cannot handle. */
1073                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1074                         txq->stats.oerrors++;
1075                         break;
1076                 }
1077                 max_elts -= segs_n;
1078                 --pkts_n;
1079                 /*
1080                  * Compute max_wqe in case less WQE were consumed in previous
1081                  * iteration.
1082                  */
1083                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1084                 /* Should we enable HW CKSUM offload */
1085                 if (buf->ol_flags &
1086                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1087                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1088                 /* Retrieve packet information. */
1089                 length = PKT_LEN(buf);
1090                 /* Start new session if packet differs. */
1091                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1092                         if ((mpw.len != length) ||
1093                             (segs_n != 1) ||
1094                             (mpw.wqe->eseg.cs_flags != cs_flags))
1095                                 mlx5_mpw_close(txq, &mpw);
1096                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1097                         if ((mpw.len != length) ||
1098                             (segs_n != 1) ||
1099                             (length > inline_room) ||
1100                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1101                                 mlx5_mpw_inline_close(txq, &mpw);
1102                                 inline_room =
1103                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1104                         }
1105                 }
1106                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1107                         if ((segs_n != 1) ||
1108                             (length > inline_room)) {
1109                                 /*
1110                                  * Multi-Packet WQE consumes at most two WQE.
1111                                  * mlx5_mpw_new() expects to be able to use
1112                                  * such resources.
1113                                  */
1114                                 if (unlikely(max_wqe < 2))
1115                                         break;
1116                                 max_wqe -= 2;
1117                                 mlx5_mpw_new(txq, &mpw, length);
1118                                 mpw.wqe->eseg.cs_flags = cs_flags;
1119                         } else {
1120                                 if (unlikely(max_wqe < wqe_inl_n))
1121                                         break;
1122                                 max_wqe -= wqe_inl_n;
1123                                 mlx5_mpw_inline_new(txq, &mpw, length);
1124                                 mpw.wqe->eseg.cs_flags = cs_flags;
1125                         }
1126                 }
1127                 /* Multi-segment packets must be alone in their MPW. */
1128                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1129                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1130                         assert(inline_room ==
1131                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1132 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1133                         length = 0;
1134 #endif
1135                         do {
1136                                 volatile struct mlx5_wqe_data_seg *dseg;
1137
1138                                 assert(buf);
1139                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1140                                 dseg = mpw.data.dseg[mpw.pkts_n];
1141                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1142                                 *dseg = (struct mlx5_wqe_data_seg){
1143                                         .byte_count = htonl(DATA_LEN(buf)),
1144                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1145                                         .addr = htonll(addr),
1146                                 };
1147 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1148                                 length += DATA_LEN(buf);
1149 #endif
1150                                 buf = buf->next;
1151                                 ++mpw.pkts_n;
1152                                 ++j;
1153                         } while (--segs_n);
1154                         assert(length == mpw.len);
1155                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1156                                 mlx5_mpw_close(txq, &mpw);
1157                 } else {
1158                         unsigned int max;
1159
1160                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1161                         assert(length <= inline_room);
1162                         assert(length == DATA_LEN(buf));
1163                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1164                         (*txq->elts)[elts_head++ & elts_m] = buf;
1165                         /* Maximum number of bytes before wrapping. */
1166                         max = ((((uintptr_t)(txq->wqes)) +
1167                                 (1 << txq->wqe_n) *
1168                                 MLX5_WQE_SIZE) -
1169                                (uintptr_t)mpw.data.raw);
1170                         if (length > max) {
1171                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1172                                            (void *)addr,
1173                                            max);
1174                                 mpw.data.raw = (volatile void *)txq->wqes;
1175                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1176                                            (void *)(addr + max),
1177                                            length - max);
1178                                 mpw.data.raw += length - max;
1179                         } else {
1180                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1181                                            (void *)addr,
1182                                            length);
1183
1184                                 if (length == max)
1185                                         mpw.data.raw =
1186                                                 (volatile void *)txq->wqes;
1187                                 else
1188                                         mpw.data.raw += length;
1189                         }
1190                         ++mpw.pkts_n;
1191                         mpw.total_len += length;
1192                         ++j;
1193                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1194                                 mlx5_mpw_inline_close(txq, &mpw);
1195                                 inline_room =
1196                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1197                         } else {
1198                                 inline_room -= length;
1199                         }
1200                 }
1201 #ifdef MLX5_PMD_SOFT_COUNTERS
1202                 /* Increment sent bytes counter. */
1203                 txq->stats.obytes += length;
1204 #endif
1205                 ++i;
1206         } while (pkts_n);
1207         /* Take a shortcut if nothing must be sent. */
1208         if (unlikely(i == 0))
1209                 return 0;
1210         /* Check whether completion threshold has been reached. */
1211         /* "j" includes both packets and segments. */
1212         comp = txq->elts_comp + j;
1213         if (comp >= MLX5_TX_COMP_THRESH) {
1214                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1215
1216                 /* Request completion on last WQE. */
1217                 wqe->ctrl[2] = htonl(8);
1218                 /* Save elts_head in unused "immediate" field of WQE. */
1219                 wqe->ctrl[3] = elts_head;
1220                 txq->elts_comp = 0;
1221         } else {
1222                 txq->elts_comp = comp;
1223         }
1224 #ifdef MLX5_PMD_SOFT_COUNTERS
1225         /* Increment sent packets counter. */
1226         txq->stats.opackets += i;
1227 #endif
1228         /* Ring QP doorbell. */
1229         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1230                 mlx5_mpw_inline_close(txq, &mpw);
1231         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1232                 mlx5_mpw_close(txq, &mpw);
1233         mlx5_tx_dbrec(txq, mpw.wqe);
1234         txq->elts_head = elts_head;
1235         return i;
1236 }
1237
1238 /**
1239  * Open an Enhanced MPW session.
1240  *
1241  * @param txq
1242  *   Pointer to TX queue structure.
1243  * @param mpw
1244  *   Pointer to MPW session structure.
1245  * @param length
1246  *   Packet length.
1247  */
1248 static inline void
1249 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1250 {
1251         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1252
1253         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1254         mpw->pkts_n = 0;
1255         mpw->total_len = sizeof(struct mlx5_wqe);
1256         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1257         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1258                                   (txq->wqe_ci << 8) |
1259                                   MLX5_OPCODE_ENHANCED_MPSW);
1260         mpw->wqe->ctrl[2] = 0;
1261         mpw->wqe->ctrl[3] = 0;
1262         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1263         if (unlikely(padding)) {
1264                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1265
1266                 /* Pad the first 2 DWORDs with zero-length inline header. */
1267                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1268                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1269                         htonl(MLX5_INLINE_SEG);
1270                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1271                 /* Start from the next WQEBB. */
1272                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1273         } else {
1274                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1275         }
1276 }
1277
1278 /**
1279  * Close an Enhanced MPW session.
1280  *
1281  * @param txq
1282  *   Pointer to TX queue structure.
1283  * @param mpw
1284  *   Pointer to MPW session structure.
1285  *
1286  * @return
1287  *   Number of consumed WQEs.
1288  */
1289 static inline uint16_t
1290 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1291 {
1292         uint16_t ret;
1293
1294         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1295          * count as 2.
1296          */
1297         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1298         mpw->state = MLX5_MPW_STATE_CLOSED;
1299         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1300         txq->wqe_ci += ret;
1301         return ret;
1302 }
1303
1304 /**
1305  * DPDK callback for TX with Enhanced MPW support.
1306  *
1307  * @param dpdk_txq
1308  *   Generic pointer to TX queue structure.
1309  * @param[in] pkts
1310  *   Packets to transmit.
1311  * @param pkts_n
1312  *   Number of packets in array.
1313  *
1314  * @return
1315  *   Number of packets successfully transmitted (<= pkts_n).
1316  */
1317 uint16_t
1318 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1319 {
1320         struct txq *txq = (struct txq *)dpdk_txq;
1321         uint16_t elts_head = txq->elts_head;
1322         const uint16_t elts_n = 1 << txq->elts_n;
1323         const uint16_t elts_m = elts_n - 1;
1324         unsigned int i = 0;
1325         unsigned int j = 0;
1326         uint16_t max_elts;
1327         uint16_t max_wqe;
1328         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1329         unsigned int mpw_room = 0;
1330         unsigned int inl_pad = 0;
1331         uint32_t inl_hdr;
1332         struct mlx5_mpw mpw = {
1333                 .state = MLX5_MPW_STATE_CLOSED,
1334         };
1335
1336         if (unlikely(!pkts_n))
1337                 return 0;
1338         /* Start processing. */
1339         mlx5_tx_complete(txq);
1340         max_elts = (elts_n - (elts_head - txq->elts_tail));
1341         /* A CQE slot must always be available. */
1342         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1343         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1344         if (unlikely(!max_wqe))
1345                 return 0;
1346         do {
1347                 struct rte_mbuf *buf = *(pkts++);
1348                 uintptr_t addr;
1349                 uint64_t naddr;
1350                 unsigned int n;
1351                 unsigned int do_inline = 0; /* Whether inline is possible. */
1352                 uint32_t length;
1353                 unsigned int segs_n = buf->nb_segs;
1354                 uint32_t cs_flags = 0;
1355
1356                 /*
1357                  * Make sure there is enough room to store this packet and
1358                  * that one ring entry remains unused.
1359                  */
1360                 assert(segs_n);
1361                 if (max_elts - j < segs_n)
1362                         break;
1363                 /* Do not bother with large packets MPW cannot handle. */
1364                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1365                         txq->stats.oerrors++;
1366                         break;
1367                 }
1368                 /* Should we enable HW CKSUM offload. */
1369                 if (buf->ol_flags &
1370                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1371                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1372                 /* Retrieve packet information. */
1373                 length = PKT_LEN(buf);
1374                 /* Start new session if:
1375                  * - multi-segment packet
1376                  * - no space left even for a dseg
1377                  * - next packet can be inlined with a new WQE
1378                  * - cs_flag differs
1379                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1380                  * segmented packet.
1381                  */
1382                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1383                         if ((segs_n != 1) ||
1384                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1385                               mpw_room) ||
1386                             (length <= txq->inline_max_packet_sz &&
1387                              inl_pad + sizeof(inl_hdr) + length >
1388                               mpw_room) ||
1389                             (mpw.wqe->eseg.cs_flags != cs_flags))
1390                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1391                 }
1392                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1393                         if (unlikely(segs_n != 1)) {
1394                                 /* Fall back to legacy MPW.
1395                                  * A MPW session consumes 2 WQEs at most to
1396                                  * include MLX5_MPW_DSEG_MAX pointers.
1397                                  */
1398                                 if (unlikely(max_wqe < 2))
1399                                         break;
1400                                 mlx5_mpw_new(txq, &mpw, length);
1401                         } else {
1402                                 /* In Enhanced MPW, inline as much as the budget
1403                                  * is allowed. The remaining space is to be
1404                                  * filled with dsegs. If the title WQEBB isn't
1405                                  * padded, it will have 2 dsegs there.
1406                                  */
1407                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1408                                             (max_inline ? max_inline :
1409                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1410                                             MLX5_WQE_SIZE);
1411                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1412                                               mpw_room))
1413                                         break;
1414                                 /* Don't pad the title WQEBB to not waste WQ. */
1415                                 mlx5_empw_new(txq, &mpw, 0);
1416                                 mpw_room -= mpw.total_len;
1417                                 inl_pad = 0;
1418                                 do_inline =
1419                                         length <= txq->inline_max_packet_sz &&
1420                                         sizeof(inl_hdr) + length <= mpw_room &&
1421                                         !txq->mpw_hdr_dseg;
1422                         }
1423                         mpw.wqe->eseg.cs_flags = cs_flags;
1424                 } else {
1425                         /* Evaluate whether the next packet can be inlined.
1426                          * Inlininig is possible when:
1427                          * - length is less than configured value
1428                          * - length fits for remaining space
1429                          * - not required to fill the title WQEBB with dsegs
1430                          */
1431                         do_inline =
1432                                 length <= txq->inline_max_packet_sz &&
1433                                 inl_pad + sizeof(inl_hdr) + length <=
1434                                  mpw_room &&
1435                                 (!txq->mpw_hdr_dseg ||
1436                                  mpw.total_len >= MLX5_WQE_SIZE);
1437                 }
1438                 /* Multi-segment packets must be alone in their MPW. */
1439                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1440                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1441 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1442                         length = 0;
1443 #endif
1444                         do {
1445                                 volatile struct mlx5_wqe_data_seg *dseg;
1446
1447                                 assert(buf);
1448                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1449                                 dseg = mpw.data.dseg[mpw.pkts_n];
1450                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1451                                 *dseg = (struct mlx5_wqe_data_seg){
1452                                         .byte_count = htonl(DATA_LEN(buf)),
1453                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1454                                         .addr = htonll(addr),
1455                                 };
1456 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1457                                 length += DATA_LEN(buf);
1458 #endif
1459                                 buf = buf->next;
1460                                 ++j;
1461                                 ++mpw.pkts_n;
1462                         } while (--segs_n);
1463                         /* A multi-segmented packet takes one MPW session.
1464                          * TODO: Pack more multi-segmented packets if possible.
1465                          */
1466                         mlx5_mpw_close(txq, &mpw);
1467                         if (mpw.pkts_n < 3)
1468                                 max_wqe--;
1469                         else
1470                                 max_wqe -= 2;
1471                 } else if (do_inline) {
1472                         /* Inline packet into WQE. */
1473                         unsigned int max;
1474
1475                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1476                         assert(length == DATA_LEN(buf));
1477                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1478                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1479                         mpw.data.raw = (volatile void *)
1480                                 ((uintptr_t)mpw.data.raw + inl_pad);
1481                         max = tx_mlx5_wq_tailroom(txq,
1482                                         (void *)(uintptr_t)mpw.data.raw);
1483                         /* Copy inline header. */
1484                         mpw.data.raw = (volatile void *)
1485                                 mlx5_copy_to_wq(
1486                                           (void *)(uintptr_t)mpw.data.raw,
1487                                           &inl_hdr,
1488                                           sizeof(inl_hdr),
1489                                           (void *)(uintptr_t)txq->wqes,
1490                                           max);
1491                         max = tx_mlx5_wq_tailroom(txq,
1492                                         (void *)(uintptr_t)mpw.data.raw);
1493                         /* Copy packet data. */
1494                         mpw.data.raw = (volatile void *)
1495                                 mlx5_copy_to_wq(
1496                                           (void *)(uintptr_t)mpw.data.raw,
1497                                           (void *)addr,
1498                                           length,
1499                                           (void *)(uintptr_t)txq->wqes,
1500                                           max);
1501                         ++mpw.pkts_n;
1502                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1503                         /* No need to get completion as the entire packet is
1504                          * copied to WQ. Free the buf right away.
1505                          */
1506                         rte_pktmbuf_free_seg(buf);
1507                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1508                         /* Add pad in the next packet if any. */
1509                         inl_pad = (((uintptr_t)mpw.data.raw +
1510                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1511                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1512                                   (uintptr_t)mpw.data.raw;
1513                 } else {
1514                         /* No inline. Load a dseg of packet pointer. */
1515                         volatile rte_v128u32_t *dseg;
1516
1517                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1518                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1519                         assert(length == DATA_LEN(buf));
1520                         if (!tx_mlx5_wq_tailroom(txq,
1521                                         (void *)((uintptr_t)mpw.data.raw
1522                                                 + inl_pad)))
1523                                 dseg = (volatile void *)txq->wqes;
1524                         else
1525                                 dseg = (volatile void *)
1526                                         ((uintptr_t)mpw.data.raw +
1527                                          inl_pad);
1528                         (*txq->elts)[elts_head++ & elts_m] = buf;
1529                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1530                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1531                                 rte_prefetch2((void *)(addr +
1532                                                 n * RTE_CACHE_LINE_SIZE));
1533                         naddr = htonll(addr);
1534                         *dseg = (rte_v128u32_t) {
1535                                 htonl(length),
1536                                 mlx5_tx_mb2mr(txq, buf),
1537                                 naddr,
1538                                 naddr >> 32,
1539                         };
1540                         mpw.data.raw = (volatile void *)(dseg + 1);
1541                         mpw.total_len += (inl_pad + sizeof(*dseg));
1542                         ++j;
1543                         ++mpw.pkts_n;
1544                         mpw_room -= (inl_pad + sizeof(*dseg));
1545                         inl_pad = 0;
1546                 }
1547 #ifdef MLX5_PMD_SOFT_COUNTERS
1548                 /* Increment sent bytes counter. */
1549                 txq->stats.obytes += length;
1550 #endif
1551                 ++i;
1552         } while (i < pkts_n);
1553         /* Take a shortcut if nothing must be sent. */
1554         if (unlikely(i == 0))
1555                 return 0;
1556         /* Check whether completion threshold has been reached. */
1557         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1558                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1559                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1560                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1561
1562                 /* Request completion on last WQE. */
1563                 wqe->ctrl[2] = htonl(8);
1564                 /* Save elts_head in unused "immediate" field of WQE. */
1565                 wqe->ctrl[3] = elts_head;
1566                 txq->elts_comp = 0;
1567                 txq->mpw_comp = txq->wqe_ci;
1568                 txq->cq_pi++;
1569         } else {
1570                 txq->elts_comp += j;
1571         }
1572 #ifdef MLX5_PMD_SOFT_COUNTERS
1573         /* Increment sent packets counter. */
1574         txq->stats.opackets += i;
1575 #endif
1576         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1577                 mlx5_empw_close(txq, &mpw);
1578         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1579                 mlx5_mpw_close(txq, &mpw);
1580         /* Ring QP doorbell. */
1581         mlx5_tx_dbrec(txq, mpw.wqe);
1582         txq->elts_head = elts_head;
1583         return i;
1584 }
1585
1586 /**
1587  * Translate RX completion flags to packet type.
1588  *
1589  * @param[in] cqe
1590  *   Pointer to CQE.
1591  *
1592  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1593  *
1594  * @return
1595  *   Packet type for struct rte_mbuf.
1596  */
1597 static inline uint32_t
1598 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1599 {
1600         uint8_t idx;
1601         uint8_t pinfo = cqe->pkt_info;
1602         uint16_t ptype = cqe->hdr_type_etc;
1603
1604         /*
1605          * The index to the array should have:
1606          * bit[1:0] = l3_hdr_type
1607          * bit[4:2] = l4_hdr_type
1608          * bit[5] = ip_frag
1609          * bit[6] = tunneled
1610          * bit[7] = outer_l3_type
1611          */
1612         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1613         return mlx5_ptype_table[idx];
1614 }
1615
1616 /**
1617  * Get size of the next packet for a given CQE. For compressed CQEs, the
1618  * consumer index is updated only once all packets of the current one have
1619  * been processed.
1620  *
1621  * @param rxq
1622  *   Pointer to RX queue.
1623  * @param cqe
1624  *   CQE to process.
1625  * @param[out] rss_hash
1626  *   Packet RSS Hash result.
1627  *
1628  * @return
1629  *   Packet size in bytes (0 if there is none), -1 in case of completion
1630  *   with error.
1631  */
1632 static inline int
1633 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1634                  uint16_t cqe_cnt, uint32_t *rss_hash)
1635 {
1636         struct rxq_zip *zip = &rxq->zip;
1637         uint16_t cqe_n = cqe_cnt + 1;
1638         int len = 0;
1639         uint16_t idx, end;
1640
1641         /* Process compressed data in the CQE and mini arrays. */
1642         if (zip->ai) {
1643                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1644                         (volatile struct mlx5_mini_cqe8 (*)[8])
1645                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1646
1647                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1648                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1649                 if ((++zip->ai & 7) == 0) {
1650                         /* Invalidate consumed CQEs */
1651                         idx = zip->ca;
1652                         end = zip->na;
1653                         while (idx != end) {
1654                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1655                                         MLX5_CQE_INVALIDATE;
1656                                 ++idx;
1657                         }
1658                         /*
1659                          * Increment consumer index to skip the number of
1660                          * CQEs consumed. Hardware leaves holes in the CQ
1661                          * ring for software use.
1662                          */
1663                         zip->ca = zip->na;
1664                         zip->na += 8;
1665                 }
1666                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1667                         /* Invalidate the rest */
1668                         idx = zip->ca;
1669                         end = zip->cq_ci;
1670
1671                         while (idx != end) {
1672                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1673                                         MLX5_CQE_INVALIDATE;
1674                                 ++idx;
1675                         }
1676                         rxq->cq_ci = zip->cq_ci;
1677                         zip->ai = 0;
1678                 }
1679         /* No compressed data, get next CQE and verify if it is compressed. */
1680         } else {
1681                 int ret;
1682                 int8_t op_own;
1683
1684                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1685                 if (unlikely(ret == 1))
1686                         return 0;
1687                 ++rxq->cq_ci;
1688                 op_own = cqe->op_own;
1689                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1690                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1691                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1692                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1693                                                           cqe_cnt].pkt_info);
1694
1695                         /* Fix endianness. */
1696                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1697                         /*
1698                          * Current mini array position is the one returned by
1699                          * check_cqe64().
1700                          *
1701                          * If completion comprises several mini arrays, as a
1702                          * special case the second one is located 7 CQEs after
1703                          * the initial CQE instead of 8 for subsequent ones.
1704                          */
1705                         zip->ca = rxq->cq_ci;
1706                         zip->na = zip->ca + 7;
1707                         /* Compute the next non compressed CQE. */
1708                         --rxq->cq_ci;
1709                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1710                         /* Get packet size to return. */
1711                         len = ntohl((*mc)[0].byte_cnt);
1712                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1713                         zip->ai = 1;
1714                         /* Prefetch all the entries to be invalidated */
1715                         idx = zip->ca;
1716                         end = zip->cq_ci;
1717                         while (idx != end) {
1718                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1719                                 ++idx;
1720                         }
1721                 } else {
1722                         len = ntohl(cqe->byte_cnt);
1723                         *rss_hash = ntohl(cqe->rx_hash_res);
1724                 }
1725                 /* Error while receiving packet. */
1726                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1727                         return -1;
1728         }
1729         return len;
1730 }
1731
1732 /**
1733  * Translate RX completion flags to offload flags.
1734  *
1735  * @param[in] rxq
1736  *   Pointer to RX queue structure.
1737  * @param[in] cqe
1738  *   Pointer to CQE.
1739  *
1740  * @return
1741  *   Offload flags (ol_flags) for struct rte_mbuf.
1742  */
1743 static inline uint32_t
1744 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1745 {
1746         uint32_t ol_flags = 0;
1747         uint16_t flags = ntohs(cqe->hdr_type_etc);
1748
1749         ol_flags =
1750                 TRANSPOSE(flags,
1751                           MLX5_CQE_RX_L3_HDR_VALID,
1752                           PKT_RX_IP_CKSUM_GOOD) |
1753                 TRANSPOSE(flags,
1754                           MLX5_CQE_RX_L4_HDR_VALID,
1755                           PKT_RX_L4_CKSUM_GOOD);
1756         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1757                 ol_flags |=
1758                         TRANSPOSE(flags,
1759                                   MLX5_CQE_RX_L3_HDR_VALID,
1760                                   PKT_RX_IP_CKSUM_GOOD) |
1761                         TRANSPOSE(flags,
1762                                   MLX5_CQE_RX_L4_HDR_VALID,
1763                                   PKT_RX_L4_CKSUM_GOOD);
1764         return ol_flags;
1765 }
1766
1767 /**
1768  * DPDK callback for RX.
1769  *
1770  * @param dpdk_rxq
1771  *   Generic pointer to RX queue structure.
1772  * @param[out] pkts
1773  *   Array to store received packets.
1774  * @param pkts_n
1775  *   Maximum number of packets in array.
1776  *
1777  * @return
1778  *   Number of packets successfully received (<= pkts_n).
1779  */
1780 uint16_t
1781 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1782 {
1783         struct rxq *rxq = dpdk_rxq;
1784         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1785         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1786         const unsigned int sges_n = rxq->sges_n;
1787         struct rte_mbuf *pkt = NULL;
1788         struct rte_mbuf *seg = NULL;
1789         volatile struct mlx5_cqe *cqe =
1790                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1791         unsigned int i = 0;
1792         unsigned int rq_ci = rxq->rq_ci << sges_n;
1793         int len = 0; /* keep its value across iterations. */
1794
1795         while (pkts_n) {
1796                 unsigned int idx = rq_ci & wqe_cnt;
1797                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1798                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1799                 uint32_t rss_hash_res = 0;
1800
1801                 if (pkt)
1802                         NEXT(seg) = rep;
1803                 seg = rep;
1804                 rte_prefetch0(seg);
1805                 rte_prefetch0(cqe);
1806                 rte_prefetch0(wqe);
1807                 rep = rte_mbuf_raw_alloc(rxq->mp);
1808                 if (unlikely(rep == NULL)) {
1809                         ++rxq->stats.rx_nombuf;
1810                         if (!pkt) {
1811                                 /*
1812                                  * no buffers before we even started,
1813                                  * bail out silently.
1814                                  */
1815                                 break;
1816                         }
1817                         while (pkt != seg) {
1818                                 assert(pkt != (*rxq->elts)[idx]);
1819                                 rep = NEXT(pkt);
1820                                 NEXT(pkt) = NULL;
1821                                 NB_SEGS(pkt) = 1;
1822                                 rte_mbuf_raw_free(pkt);
1823                                 pkt = rep;
1824                         }
1825                         break;
1826                 }
1827                 if (!pkt) {
1828                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1829                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1830                                                &rss_hash_res);
1831                         if (!len) {
1832                                 rte_mbuf_raw_free(rep);
1833                                 break;
1834                         }
1835                         if (unlikely(len == -1)) {
1836                                 /* RX error, packet is likely too large. */
1837                                 rte_mbuf_raw_free(rep);
1838                                 ++rxq->stats.idropped;
1839                                 goto skip;
1840                         }
1841                         pkt = seg;
1842                         assert(len >= (rxq->crc_present << 2));
1843                         /* Update packet information. */
1844                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1845                         pkt->ol_flags = 0;
1846                         if (rss_hash_res && rxq->rss_hash) {
1847                                 pkt->hash.rss = rss_hash_res;
1848                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1849                         }
1850                         if (rxq->mark &&
1851                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1852                                 pkt->ol_flags |= PKT_RX_FDIR;
1853                                 if (cqe->sop_drop_qpn !=
1854                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1855                                         uint32_t mark = cqe->sop_drop_qpn;
1856
1857                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1858                                         pkt->hash.fdir.hi =
1859                                                 mlx5_flow_mark_get(mark);
1860                                 }
1861                         }
1862                         if (rxq->csum | rxq->csum_l2tun)
1863                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1864                         if (rxq->vlan_strip &&
1865                             (cqe->hdr_type_etc &
1866                              htons(MLX5_CQE_VLAN_STRIPPED))) {
1867                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1868                                         PKT_RX_VLAN_STRIPPED;
1869                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
1870                         }
1871                         if (rxq->crc_present)
1872                                 len -= ETHER_CRC_LEN;
1873                         PKT_LEN(pkt) = len;
1874                 }
1875                 DATA_LEN(rep) = DATA_LEN(seg);
1876                 PKT_LEN(rep) = PKT_LEN(seg);
1877                 SET_DATA_OFF(rep, DATA_OFF(seg));
1878                 PORT(rep) = PORT(seg);
1879                 (*rxq->elts)[idx] = rep;
1880                 /*
1881                  * Fill NIC descriptor with the new buffer.  The lkey and size
1882                  * of the buffers are already known, only the buffer address
1883                  * changes.
1884                  */
1885                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1886                 if (len > DATA_LEN(seg)) {
1887                         len -= DATA_LEN(seg);
1888                         ++NB_SEGS(pkt);
1889                         ++rq_ci;
1890                         continue;
1891                 }
1892                 DATA_LEN(seg) = len;
1893 #ifdef MLX5_PMD_SOFT_COUNTERS
1894                 /* Increment bytes counter. */
1895                 rxq->stats.ibytes += PKT_LEN(pkt);
1896 #endif
1897                 /* Return packet. */
1898                 *(pkts++) = pkt;
1899                 pkt = NULL;
1900                 --pkts_n;
1901                 ++i;
1902 skip:
1903                 /* Align consumer index to the next stride. */
1904                 rq_ci >>= sges_n;
1905                 ++rq_ci;
1906                 rq_ci <<= sges_n;
1907         }
1908         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1909                 return 0;
1910         /* Update the consumer index. */
1911         rxq->rq_ci = rq_ci >> sges_n;
1912         rte_wmb();
1913         *rxq->cq_db = htonl(rxq->cq_ci);
1914         rte_wmb();
1915         *rxq->rq_db = htonl(rxq->rq_ci);
1916 #ifdef MLX5_PMD_SOFT_COUNTERS
1917         /* Increment packets counter. */
1918         rxq->stats.ipackets += i;
1919 #endif
1920         return i;
1921 }
1922
1923 /**
1924  * Dummy DPDK callback for TX.
1925  *
1926  * This function is used to temporarily replace the real callback during
1927  * unsafe control operations on the queue, or in case of error.
1928  *
1929  * @param dpdk_txq
1930  *   Generic pointer to TX queue structure.
1931  * @param[in] pkts
1932  *   Packets to transmit.
1933  * @param pkts_n
1934  *   Number of packets in array.
1935  *
1936  * @return
1937  *   Number of packets successfully transmitted (<= pkts_n).
1938  */
1939 uint16_t
1940 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1941 {
1942         (void)dpdk_txq;
1943         (void)pkts;
1944         (void)pkts_n;
1945         return 0;
1946 }
1947
1948 /**
1949  * Dummy DPDK callback for RX.
1950  *
1951  * This function is used to temporarily replace the real callback during
1952  * unsafe control operations on the queue, or in case of error.
1953  *
1954  * @param dpdk_rxq
1955  *   Generic pointer to RX queue structure.
1956  * @param[out] pkts
1957  *   Array to store received packets.
1958  * @param pkts_n
1959  *   Maximum number of packets in array.
1960  *
1961  * @return
1962  *   Number of packets successfully received (<= pkts_n).
1963  */
1964 uint16_t
1965 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1966 {
1967         (void)dpdk_rxq;
1968         (void)pkts;
1969         (void)pkts_n;
1970         return 0;
1971 }
1972
1973 /*
1974  * Vectorized Rx/Tx routines are not compiled in when required vector
1975  * instructions are not supported on a target architecture. The following null
1976  * stubs are needed for linkage when those are not included outside of this file
1977  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1978  */
1979
1980 uint16_t __attribute__((weak))
1981 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1982 {
1983         (void)dpdk_txq;
1984         (void)pkts;
1985         (void)pkts_n;
1986         return 0;
1987 }
1988
1989 uint16_t __attribute__((weak))
1990 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1991 {
1992         (void)dpdk_txq;
1993         (void)pkts;
1994         (void)pkts_n;
1995         return 0;
1996 }
1997
1998 uint16_t __attribute__((weak))
1999 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2000 {
2001         (void)dpdk_rxq;
2002         (void)pkts;
2003         (void)pkts_n;
2004         return 0;
2005 }
2006
2007 int __attribute__((weak))
2008 priv_check_raw_vec_tx_support(struct priv *priv)
2009 {
2010         (void)priv;
2011         return -ENOTSUP;
2012 }
2013
2014 int __attribute__((weak))
2015 priv_check_vec_tx_support(struct priv *priv)
2016 {
2017         (void)priv;
2018         return -ENOTSUP;
2019 }
2020
2021 int __attribute__((weak))
2022 rxq_check_vec_support(struct rxq *rxq)
2023 {
2024         (void)rxq;
2025         return -ENOTSUP;
2026 }
2027
2028 int __attribute__((weak))
2029 priv_check_vec_rx_support(struct priv *priv)
2030 {
2031         (void)priv;
2032         return -ENOTSUP;
2033 }