drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Return the size of tailroom of WQ.
 199  *
 200  * @param txq
 201  *   Pointer to TX queue structure.
 202  * @param addr
 203  *   Pointer to tail of WQ.
 204  *
 205  * @return
 206  *   Size of tailroom.
 207  */
 208 static inline size_t
 209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 210 {
 211         size_t tailroom;
 212         tailroom = (uintptr_t)(txq->wqes) +
 213                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 214                    (uintptr_t)addr;
 215         return tailroom;
 216 }
 217
 218 /**
 219  * Copy data to tailroom of circular queue.
 220  *
 221  * @param dst
 222  *   Pointer to destination.
 223  * @param src
 224  *   Pointer to source.
 225  * @param n
 226  *   Number of bytes to copy.
 227  * @param base
 228  *   Pointer to head of queue.
 229  * @param tailroom
 230  *   Size of tailroom from dst.
 231  *
 232  * @return
 233  *   Pointer after copied data.
 234  */
 235 static inline void *
 236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 237                 void *base, size_t tailroom)
 238 {
 239         void *ret;
 240
 241         if (n > tailroom) {
 242                 rte_memcpy(dst, src, tailroom);
 243                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 244                            n - tailroom);
 245                 ret = (uint8_t *)base + n - tailroom;
 246         } else {
 247                 rte_memcpy(dst, src, n);
 248                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 249         }
 250         return ret;
 251 }
 252
 253 /**
 254  * Manage TX completions.
 255  *
 256  * When sending a burst, mlx5_tx_burst() posts several WRs.
 257  *
 258  * @param txq
 259  *   Pointer to TX queue structure.
 260  */
 261 static inline void
 262 txq_complete(struct txq *txq)
 263 {
 264         const unsigned int elts_n = 1 << txq->elts_n;
 265         const unsigned int cqe_n = 1 << txq->cqe_n;
 266         const unsigned int cqe_cnt = cqe_n - 1;
 267         uint16_t elts_free = txq->elts_tail;
 268         uint16_t elts_tail;
 269         uint16_t cq_ci = txq->cq_ci;
 270         volatile struct mlx5_cqe *cqe = NULL;
 271         volatile struct mlx5_wqe_ctrl *ctrl;
 272
 273         do {
 274                 volatile struct mlx5_cqe *tmp;
 275
 276                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 277                 if (check_cqe(tmp, cqe_n, cq_ci))
 278                         break;
 279                 cqe = tmp;
 280 #ifndef NDEBUG
 281                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 282                         if (!check_cqe_seen(cqe))
 283                                 ERROR("unexpected compressed CQE, TX stopped");
 284                         return;
 285                 }
 286                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 287                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 288                         if (!check_cqe_seen(cqe))
 289                                 ERROR("unexpected error CQE, TX stopped");
 290                         return;
 291                 }
 292 #endif /* NDEBUG */
 293                 ++cq_ci;
 294         } while (1);
 295         if (unlikely(cqe == NULL))
 296                 return;
 297         txq->wqe_pi = ntohs(cqe->wqe_counter);
 298         ctrl = (volatile struct mlx5_wqe_ctrl *)
 299                 tx_mlx5_wqe(txq, txq->wqe_pi);
 300         elts_tail = ctrl->ctrl3;
 301         assert(elts_tail < (1 << txq->wqe_n));
 302         /* Free buffers. */
 303         while (elts_free != elts_tail) {
 304                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 305                 unsigned int elts_free_next =
 306                         (elts_free + 1) & (elts_n - 1);
 307                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 308
 309 #ifndef NDEBUG
 310                 /* Poisoning. */
 311                 memset(&(*txq->elts)[elts_free],
 312                        0x66,
 313                        sizeof((*txq->elts)[elts_free]));
 314 #endif
 315                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 316                 /* Only one segment needs to be freed. */
 317                 rte_pktmbuf_free_seg(elt);
 318                 elts_free = elts_free_next;
 319         }
 320         txq->cq_ci = cq_ci;
 321         txq->elts_tail = elts_tail;
 322         /* Update the consumer index. */
 323         rte_wmb();
 324         *txq->cq_db = htonl(cq_ci);
 325 }
 326
 327 /**
 328  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 329  * the cloned mbuf is allocated is returned instead.
 330  *
 331  * @param buf
 332  *   Pointer to mbuf.
 333  *
 334  * @return
 335  *   Memory pool where data is located for given mbuf.
 336  */
 337 static struct rte_mempool *
 338 txq_mb2mp(struct rte_mbuf *buf)
 339 {
 340         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 341                 return rte_mbuf_from_indirect(buf)->pool;
 342         return buf->pool;
 343 }
 344
 345 /**
 346  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 347  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 348  * remove an entry first.
 349  *
 350  * @param txq
 351  *   Pointer to TX queue structure.
 352  * @param[in] mp
 353  *   Memory Pool for which a Memory Region lkey must be returned.
 354  *
 355  * @return
 356  *   mr->lkey on success, (uint32_t)-1 on failure.
 357  */
 358 static inline uint32_t
 359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 360 {
 361         unsigned int i;
 362         uint32_t lkey = (uint32_t)-1;
 363
 364         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 365                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 366                         /* Unknown MP, add a new MR for it. */
 367                         break;
 368                 }
 369                 if (txq->mp2mr[i].mp == mp) {
 370                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 371                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 372                                txq->mp2mr[i].lkey);
 373                         lkey = txq->mp2mr[i].lkey;
 374                         break;
 375                 }
 376         }
 377         if (unlikely(lkey == (uint32_t)-1))
 378                 lkey = txq_mp2mr_reg(txq, mp, i);
 379         return lkey;
 380 }
 381
 382 /**
 383  * Ring TX queue doorbell.
 384  *
 385  * @param txq
 386  *   Pointer to TX queue structure.
 387  * @param wqe
 388  *   Pointer to the last WQE posted in the NIC.
 389  */
 390 static inline void
 391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 392 {
 393         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 394         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 395
 396         rte_wmb();
 397         *txq->qp_db = htonl(txq->wqe_ci);
 398         /* Ensure ordering between DB record and BF copy. */
 399         rte_wmb();
 400         *dst = *src;
 401 }
 402
 403 /**
 404  * DPDK callback to check the status of a tx descriptor.
 405  *
 406  * @param tx_queue
 407  *   The tx queue.
 408  * @param[in] offset
 409  *   The index of the descriptor in the ring.
 410  *
 411  * @return
 412  *   The status of the tx descriptor.
 413  */
 414 int
 415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 416 {
 417         struct txq *txq = tx_queue;
 418         const unsigned int elts_n = 1 << txq->elts_n;
 419         const unsigned int elts_cnt = elts_n - 1;
 420         unsigned int used;
 421
 422         txq_complete(txq);
 423         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 424         if (offset < used)
 425                 return RTE_ETH_TX_DESC_FULL;
 426         return RTE_ETH_TX_DESC_DONE;
 427 }
 428
 429 /**
 430  * DPDK callback to check the status of a rx descriptor.
 431  *
 432  * @param rx_queue
 433  *   The rx queue.
 434  * @param[in] offset
 435  *   The index of the descriptor in the ring.
 436  *
 437  * @return
 438  *   The status of the tx descriptor.
 439  */
 440 int
 441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 442 {
 443         struct rxq *rxq = rx_queue;
 444         struct rxq_zip *zip = &rxq->zip;
 445         volatile struct mlx5_cqe *cqe;
 446         const unsigned int cqe_n = (1 << rxq->cqe_n);
 447         const unsigned int cqe_cnt = cqe_n - 1;
 448         unsigned int cq_ci;
 449         unsigned int used;
 450
 451         /* if we are processing a compressed cqe */
 452         if (zip->ai) {
 453                 used = zip->cqe_cnt - zip->ca;
 454                 cq_ci = zip->cq_ci;
 455         } else {
 456                 used = 0;
 457                 cq_ci = rxq->cq_ci;
 458         }
 459         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 460         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 461                 int8_t op_own;
 462                 unsigned int n;
 463
 464                 op_own = cqe->op_own;
 465                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 466                         n = ntohl(cqe->byte_cnt);
 467                 else
 468                         n = 1;
 469                 cq_ci += n;
 470                 used += n;
 471                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 472         }
 473         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 474         if (offset < used)
 475                 return RTE_ETH_RX_DESC_DONE;
 476         return RTE_ETH_RX_DESC_AVAIL;
 477 }
 478
 479 /**
 480  * DPDK callback for TX.
 481  *
 482  * @param dpdk_txq
 483  *   Generic pointer to TX queue structure.
 484  * @param[in] pkts
 485  *   Packets to transmit.
 486  * @param pkts_n
 487  *   Number of packets in array.
 488  *
 489  * @return
 490  *   Number of packets successfully transmitted (<= pkts_n).
 491  */
 492 uint16_t
 493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 494 {
 495         struct txq *txq = (struct txq *)dpdk_txq;
 496         uint16_t elts_head = txq->elts_head;
 497         const unsigned int elts_n = 1 << txq->elts_n;
 498         unsigned int i = 0;
 499         unsigned int j = 0;
 500         unsigned int k = 0;
 501         unsigned int max;
 502         unsigned int max_inline = txq->max_inline;
 503         const unsigned int inline_en = !!max_inline && txq->inline_en;
 504         uint16_t max_wqe;
 505         unsigned int comp;
 506         volatile struct mlx5_wqe_v *wqe = NULL;
 507         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 508         unsigned int segs_n = 0;
 509         struct rte_mbuf *buf = NULL;
 510         uint8_t *raw;
 511
 512         if (unlikely(!pkts_n))
 513                 return 0;
 514         /* Prefetch first packet cacheline. */
 515         rte_prefetch0(*pkts);
 516         /* Start processing. */
 517         txq_complete(txq);
 518         max = (elts_n - (elts_head - txq->elts_tail));
 519         if (max > elts_n)
 520                 max -= elts_n;
 521         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 522         if (unlikely(!max_wqe))
 523                 return 0;
 524         do {
 525                 volatile rte_v128u32_t *dseg = NULL;
 526                 uint32_t length;
 527                 unsigned int ds = 0;
 528                 unsigned int sg = 0; /* counter of additional segs attached. */
 529                 uintptr_t addr;
 530                 uint64_t naddr;
 531                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 532                 uint16_t tso_header_sz = 0;
 533                 uint16_t ehdr;
 534                 uint8_t cs_flags = 0;
 535                 uint64_t tso = 0;
 536 #ifdef MLX5_PMD_SOFT_COUNTERS
 537                 uint32_t total_length = 0;
 538 #endif
 539
 540                 /* first_seg */
 541                 buf = *(pkts++);
 542                 segs_n = buf->nb_segs;
 543                 /*
 544                  * Make sure there is enough room to store this packet and
 545                  * that one ring entry remains unused.
 546                  */
 547                 assert(segs_n);
 548                 if (max < segs_n + 1)
 549                         break;
 550                 max -= segs_n;
 551                 --segs_n;
 552                 if (!segs_n)
 553                         --pkts_n;
 554                 if (unlikely(--max_wqe == 0))
 555                         break;
 556                 wqe = (volatile struct mlx5_wqe_v *)
 557                         tx_mlx5_wqe(txq, txq->wqe_ci);
 558                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 559                 if (pkts_n > 1)
 560                         rte_prefetch0(*pkts);
 561                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 562                 length = DATA_LEN(buf);
 563                 ehdr = (((uint8_t *)addr)[1] << 8) |
 564                        ((uint8_t *)addr)[0];
 565 #ifdef MLX5_PMD_SOFT_COUNTERS
 566                 total_length = length;
 567 #endif
 568                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 569                         break;
 570                 /* Update element. */
 571                 (*txq->elts)[elts_head] = buf;
 572                 elts_head = (elts_head + 1) & (elts_n - 1);
 573                 /* Prefetch next buffer data. */
 574                 if (pkts_n > 1) {
 575                         volatile void *pkt_addr;
 576
 577                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 578                         rte_prefetch0(pkt_addr);
 579                 }
 580                 /* Should we enable HW CKSUM offload */
 581                 if (buf->ol_flags &
 582                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 583                         const uint64_t is_tunneled = buf->ol_flags &
 584                                                      (PKT_TX_TUNNEL_GRE |
 585                                                       PKT_TX_TUNNEL_VXLAN);
 586
 587                         if (is_tunneled && txq->tunnel_en) {
 588                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 589                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 590                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 591                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 592                         } else {
 593                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 594                                            MLX5_ETH_WQE_L4_CSUM;
 595                         }
 596                 }
 597                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 598                 /* Replace the Ethernet type by the VLAN if necessary. */
 599                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 600                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 601                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 602
 603                         addr += 2;
 604                         length -= 2;
 605                         /* Copy Destination and source mac address. */
 606                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 607                         /* Copy VLAN. */
 608                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 609                         /* Copy missing two bytes to end the DSeg. */
 610                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 611                                ((uint8_t *)addr) + len, 2);
 612                         addr += len + 2;
 613                         length -= (len + 2);
 614                 } else {
 615                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 616                                MLX5_WQE_DWORD_SIZE);
 617                         length -= pkt_inline_sz;
 618                         addr += pkt_inline_sz;
 619                 }
 620                 if (txq->tso_en) {
 621                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 622                         if (tso) {
 623                                 uintptr_t end = (uintptr_t)
 624                                                 (((uintptr_t)txq->wqes) +
 625                                                 (1 << txq->wqe_n) *
 626                                                 MLX5_WQE_SIZE);
 627                                 unsigned int copy_b;
 628                                 uint8_t vlan_sz = (buf->ol_flags &
 629                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 630                                 const uint64_t is_tunneled =
 631                                                         buf->ol_flags &
 632                                                         (PKT_TX_TUNNEL_GRE |
 633                                                          PKT_TX_TUNNEL_VXLAN);
 634
 635                                 tso_header_sz = buf->l2_len + vlan_sz +
 636                                                 buf->l3_len + buf->l4_len;
 637
 638                                 if (is_tunneled && txq->tunnel_en) {
 639                                         tso_header_sz += buf->outer_l2_len +
 640                                                          buf->outer_l3_len;
 641                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 642                                 } else {
 643                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 644                                 }
 645                                 if (unlikely(tso_header_sz >
 646                                              MLX5_MAX_TSO_HEADER))
 647                                         break;
 648                                 copy_b = tso_header_sz - pkt_inline_sz;
 649                                 /* First seg must contain all headers. */
 650                                 assert(copy_b <= length);
 651                                 raw += MLX5_WQE_DWORD_SIZE;
 652                                 if (copy_b &&
 653                                    ((end - (uintptr_t)raw) > copy_b)) {
 654                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 655                                                       1 + 3) / 4;
 656
 657                                         if (unlikely(max_wqe < n))
 658                                                 break;
 659                                         max_wqe -= n;
 660                                         rte_memcpy((void *)raw,
 661                                                    (void *)addr, copy_b);
 662                                         addr += copy_b;
 663                                         length -= copy_b;
 664                                         pkt_inline_sz += copy_b;
 665                                         /*
 666                                          * Another DWORD will be added
 667                                          * in the inline part.
 668                                          */
 669                                         raw += MLX5_WQE_DS(copy_b) *
 670                                                MLX5_WQE_DWORD_SIZE -
 671                                                MLX5_WQE_DWORD_SIZE;
 672                                 } else {
 673                                         /* NOP WQE. */
 674                                         wqe->ctrl = (rte_v128u32_t){
 675                                                      htonl(txq->wqe_ci << 8),
 676                                                      htonl(txq->qp_num_8s | 1),
 677                                                      0,
 678                                                      0,
 679                                         };
 680                                         ds = 1;
 681                                         total_length = 0;
 682                                         pkts--;
 683                                         pkts_n++;
 684                                         elts_head = (elts_head - 1) &
 685                                                     (elts_n - 1);
 686                                         k++;
 687                                         goto next_wqe;
 688                                 }
 689                         }
 690                 }
 691                 /* Inline if enough room. */
 692                 if (inline_en || tso) {
 693                         uintptr_t end = (uintptr_t)
 694                                 (((uintptr_t)txq->wqes) +
 695                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 696                         unsigned int inline_room = max_inline *
 697                                                    RTE_CACHE_LINE_SIZE -
 698                                                    (pkt_inline_sz - 2);
 699                         uintptr_t addr_end = (addr + inline_room) &
 700                                              ~(RTE_CACHE_LINE_SIZE - 1);
 701                         unsigned int copy_b = (addr_end > addr) ?
 702                                 RTE_MIN((addr_end - addr), length) :
 703                                 0;
 704
 705                         raw += MLX5_WQE_DWORD_SIZE;
 706                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 707                                 /*
 708                                  * One Dseg remains in the current WQE.  To
 709                                  * keep the computation positive, it is
 710                                  * removed after the bytes to Dseg conversion.
 711                                  */
 712                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 713
 714                                 if (unlikely(max_wqe < n))
 715                                         break;
 716                                 max_wqe -= n;
 717                                 if (tso) {
 718                                         uint32_t inl =
 719                                                 htonl(copy_b | MLX5_INLINE_SEG);
 720
 721                                         pkt_inline_sz =
 722                                                 MLX5_WQE_DS(tso_header_sz) *
 723                                                 MLX5_WQE_DWORD_SIZE;
 724                                         rte_memcpy((void *)raw,
 725                                                    (void *)&inl, sizeof(inl));
 726                                         raw += sizeof(inl);
 727                                         pkt_inline_sz += sizeof(inl);
 728                                 }
 729                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 730                                 addr += copy_b;
 731                                 length -= copy_b;
 732                                 pkt_inline_sz += copy_b;
 733                         }
 734                         /*
 735                          * 2 DWORDs consumed by the WQE header + ETH segment +
 736                          * the size of the inline part of the packet.
 737                          */
 738                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 739                         if (length > 0) {
 740                                 if (ds % (MLX5_WQE_SIZE /
 741                                           MLX5_WQE_DWORD_SIZE) == 0) {
 742                                         if (unlikely(--max_wqe == 0))
 743                                                 break;
 744                                         dseg = (volatile rte_v128u32_t *)
 745                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 746                                                            ds / 4);
 747                                 } else {
 748                                         dseg = (volatile rte_v128u32_t *)
 749                                                 ((uintptr_t)wqe +
 750                                                  (ds * MLX5_WQE_DWORD_SIZE));
 751                                 }
 752                                 goto use_dseg;
 753                         } else if (!segs_n) {
 754                                 goto next_pkt;
 755                         } else {
 756                                 /* dseg will be advance as part of next_seg */
 757                                 dseg = (volatile rte_v128u32_t *)
 758                                         ((uintptr_t)wqe +
 759                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 760                                 goto next_seg;
 761                         }
 762                 } else {
 763                         /*
 764                          * No inline has been done in the packet, only the
 765                          * Ethernet Header as been stored.
 766                          */
 767                         dseg = (volatile rte_v128u32_t *)
 768                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 769                         ds = 3;
 770 use_dseg:
 771                         /* Add the remaining packet as a simple ds. */
 772                         naddr = htonll(addr);
 773                         *dseg = (rte_v128u32_t){
 774                                 htonl(length),
 775                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 776                                 naddr,
 777                                 naddr >> 32,
 778                         };
 779                         ++ds;
 780                         if (!segs_n)
 781                                 goto next_pkt;
 782                 }
 783 next_seg:
 784                 assert(buf);
 785                 assert(ds);
 786                 assert(wqe);
 787                 /*
 788                  * Spill on next WQE when the current one does not have
 789                  * enough room left. Size of WQE must a be a multiple
 790                  * of data segment size.
 791                  */
 792                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 793                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 794                         if (unlikely(--max_wqe == 0))
 795                                 break;
 796                         dseg = (volatile rte_v128u32_t *)
 797                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 798                         rte_prefetch0(tx_mlx5_wqe(txq,
 799                                                   txq->wqe_ci + ds / 4 + 1));
 800                 } else {
 801                         ++dseg;
 802                 }
 803                 ++ds;
 804                 buf = buf->next;
 805                 assert(buf);
 806                 length = DATA_LEN(buf);
 807 #ifdef MLX5_PMD_SOFT_COUNTERS
 808                 total_length += length;
 809 #endif
 810                 /* Store segment information. */
 811                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 812                 *dseg = (rte_v128u32_t){
 813                         htonl(length),
 814                         txq_mp2mr(txq, txq_mb2mp(buf)),
 815                         naddr,
 816                         naddr >> 32,
 817                 };
 818                 (*txq->elts)[elts_head] = buf;
 819                 elts_head = (elts_head + 1) & (elts_n - 1);
 820                 ++sg;
 821                 /* Advance counter only if all segs are successfully posted. */
 822                 if (sg < segs_n) {
 823                         goto next_seg;
 824                 } else {
 825                         --pkts_n;
 826                         j += sg;
 827                 }
 828 next_pkt:
 829                 ++i;
 830                 /* Initialize known and common part of the WQE structure. */
 831                 if (tso) {
 832                         wqe->ctrl = (rte_v128u32_t){
 833                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 834                                 htonl(txq->qp_num_8s | ds),
 835                                 0,
 836                                 0,
 837                         };
 838                         wqe->eseg = (rte_v128u32_t){
 839                                 0,
 840                                 cs_flags | (htons(buf->tso_segsz) << 16),
 841                                 0,
 842                                 (ehdr << 16) | htons(tso_header_sz),
 843                         };
 844                 } else {
 845                         wqe->ctrl = (rte_v128u32_t){
 846                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 847                                 htonl(txq->qp_num_8s | ds),
 848                                 0,
 849                                 0,
 850                         };
 851                         wqe->eseg = (rte_v128u32_t){
 852                                 0,
 853                                 cs_flags,
 854                                 0,
 855                                 (ehdr << 16) | htons(pkt_inline_sz),
 856                         };
 857                 }
 858 next_wqe:
 859                 txq->wqe_ci += (ds + 3) / 4;
 860                 /* Save the last successful WQE for completion request */
 861                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 862 #ifdef MLX5_PMD_SOFT_COUNTERS
 863                 /* Increment sent bytes counter. */
 864                 txq->stats.obytes += total_length;
 865 #endif
 866         } while (pkts_n);
 867         /* Take a shortcut if nothing must be sent. */
 868         if (unlikely((i + k) == 0))
 869                 return 0;
 870         txq->elts_head = (txq->elts_head + i + j) & (elts_n - 1);
 871         /* Check whether completion threshold has been reached. */
 872         comp = txq->elts_comp + i + j + k;
 873         if (comp >= MLX5_TX_COMP_THRESH) {
 874                 /* Request completion on last WQE. */
 875                 last_wqe->ctrl2 = htonl(8);
 876                 /* Save elts_head in unused "immediate" field of WQE. */
 877                 last_wqe->ctrl3 = txq->elts_head;
 878                 txq->elts_comp = 0;
 879         } else {
 880                 txq->elts_comp = comp;
 881         }
 882 #ifdef MLX5_PMD_SOFT_COUNTERS
 883         /* Increment sent packets counter. */
 884         txq->stats.opackets += i;
 885 #endif
 886         /* Ring QP doorbell. */
 887         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 888         return i;
 889 }
 890
 891 /**
 892  * Open a MPW session.
 893  *
 894  * @param txq
 895  *   Pointer to TX queue structure.
 896  * @param mpw
 897  *   Pointer to MPW session structure.
 898  * @param length
 899  *   Packet length.
 900  */
 901 static inline void
 902 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 903 {
 904         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 905         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 906                 (volatile struct mlx5_wqe_data_seg (*)[])
 907                 tx_mlx5_wqe(txq, idx + 1);
 908
 909         mpw->state = MLX5_MPW_STATE_OPENED;
 910         mpw->pkts_n = 0;
 911         mpw->len = length;
 912         mpw->total_len = 0;
 913         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 914         mpw->wqe->eseg.mss = htons(length);
 915         mpw->wqe->eseg.inline_hdr_sz = 0;
 916         mpw->wqe->eseg.rsvd0 = 0;
 917         mpw->wqe->eseg.rsvd1 = 0;
 918         mpw->wqe->eseg.rsvd2 = 0;
 919         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 920                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 921         mpw->wqe->ctrl[2] = 0;
 922         mpw->wqe->ctrl[3] = 0;
 923         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 924                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 925         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 926                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 927         mpw->data.dseg[2] = &(*dseg)[0];
 928         mpw->data.dseg[3] = &(*dseg)[1];
 929         mpw->data.dseg[4] = &(*dseg)[2];
 930 }
 931
 932 /**
 933  * Close a MPW session.
 934  *
 935  * @param txq
 936  *   Pointer to TX queue structure.
 937  * @param mpw
 938  *   Pointer to MPW session structure.
 939  */
 940 static inline void
 941 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 942 {
 943         unsigned int num = mpw->pkts_n;
 944
 945         /*
 946          * Store size in multiple of 16 bytes. Control and Ethernet segments
 947          * count as 2.
 948          */
 949         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 950         mpw->state = MLX5_MPW_STATE_CLOSED;
 951         if (num < 3)
 952                 ++txq->wqe_ci;
 953         else
 954                 txq->wqe_ci += 2;
 955         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 956         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 957 }
 958
 959 /**
 960  * DPDK callback for TX with MPW support.
 961  *
 962  * @param dpdk_txq
 963  *   Generic pointer to TX queue structure.
 964  * @param[in] pkts
 965  *   Packets to transmit.
 966  * @param pkts_n
 967  *   Number of packets in array.
 968  *
 969  * @return
 970  *   Number of packets successfully transmitted (<= pkts_n).
 971  */
 972 uint16_t
 973 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 974 {
 975         struct txq *txq = (struct txq *)dpdk_txq;
 976         uint16_t elts_head = txq->elts_head;
 977         const unsigned int elts_n = 1 << txq->elts_n;
 978         unsigned int i = 0;
 979         unsigned int j = 0;
 980         unsigned int max;
 981         uint16_t max_wqe;
 982         unsigned int comp;
 983         struct mlx5_mpw mpw = {
 984                 .state = MLX5_MPW_STATE_CLOSED,
 985         };
 986
 987         if (unlikely(!pkts_n))
 988                 return 0;
 989         /* Prefetch first packet cacheline. */
 990         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 991         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 992         /* Start processing. */
 993         txq_complete(txq);
 994         max = (elts_n - (elts_head - txq->elts_tail));
 995         if (max > elts_n)
 996                 max -= elts_n;
 997         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 998         if (unlikely(!max_wqe))
 999                 return 0;
1000         do {
1001                 struct rte_mbuf *buf = *(pkts++);
1002                 unsigned int elts_head_next;
1003                 uint32_t length;
1004                 unsigned int segs_n = buf->nb_segs;
1005                 uint32_t cs_flags = 0;
1006
1007                 /*
1008                  * Make sure there is enough room to store this packet and
1009                  * that one ring entry remains unused.
1010                  */
1011                 assert(segs_n);
1012                 if (max < segs_n + 1)
1013                         break;
1014                 /* Do not bother with large packets MPW cannot handle. */
1015                 if (segs_n > MLX5_MPW_DSEG_MAX)
1016                         break;
1017                 max -= segs_n;
1018                 --pkts_n;
1019                 /* Should we enable HW CKSUM offload */
1020                 if (buf->ol_flags &
1021                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1022                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1023                 /* Retrieve packet information. */
1024                 length = PKT_LEN(buf);
1025                 assert(length);
1026                 /* Start new session if packet differs. */
1027                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1028                     ((mpw.len != length) ||
1029                      (segs_n != 1) ||
1030                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1031                         mlx5_mpw_close(txq, &mpw);
1032                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1033                         /*
1034                          * Multi-Packet WQE consumes at most two WQE.
1035                          * mlx5_mpw_new() expects to be able to use such
1036                          * resources.
1037                          */
1038                         if (unlikely(max_wqe < 2))
1039                                 break;
1040                         max_wqe -= 2;
1041                         mlx5_mpw_new(txq, &mpw, length);
1042                         mpw.wqe->eseg.cs_flags = cs_flags;
1043                 }
1044                 /* Multi-segment packets must be alone in their MPW. */
1045                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1046 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1047                 length = 0;
1048 #endif
1049                 do {
1050                         volatile struct mlx5_wqe_data_seg *dseg;
1051                         uintptr_t addr;
1052
1053                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1054                         assert(buf);
1055                         (*txq->elts)[elts_head] = buf;
1056                         dseg = mpw.data.dseg[mpw.pkts_n];
1057                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1058                         *dseg = (struct mlx5_wqe_data_seg){
1059                                 .byte_count = htonl(DATA_LEN(buf)),
1060                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1061                                 .addr = htonll(addr),
1062                         };
1063                         elts_head = elts_head_next;
1064 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1065                         length += DATA_LEN(buf);
1066 #endif
1067                         buf = buf->next;
1068                         ++mpw.pkts_n;
1069                         ++j;
1070                 } while (--segs_n);
1071                 assert(length == mpw.len);
1072                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1073                         mlx5_mpw_close(txq, &mpw);
1074                 elts_head = elts_head_next;
1075 #ifdef MLX5_PMD_SOFT_COUNTERS
1076                 /* Increment sent bytes counter. */
1077                 txq->stats.obytes += length;
1078 #endif
1079                 ++i;
1080         } while (pkts_n);
1081         /* Take a shortcut if nothing must be sent. */
1082         if (unlikely(i == 0))
1083                 return 0;
1084         /* Check whether completion threshold has been reached. */
1085         /* "j" includes both packets and segments. */
1086         comp = txq->elts_comp + j;
1087         if (comp >= MLX5_TX_COMP_THRESH) {
1088                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1089
1090                 /* Request completion on last WQE. */
1091                 wqe->ctrl[2] = htonl(8);
1092                 /* Save elts_head in unused "immediate" field of WQE. */
1093                 wqe->ctrl[3] = elts_head;
1094                 txq->elts_comp = 0;
1095         } else {
1096                 txq->elts_comp = comp;
1097         }
1098 #ifdef MLX5_PMD_SOFT_COUNTERS
1099         /* Increment sent packets counter. */
1100         txq->stats.opackets += i;
1101 #endif
1102         /* Ring QP doorbell. */
1103         if (mpw.state == MLX5_MPW_STATE_OPENED)
1104                 mlx5_mpw_close(txq, &mpw);
1105         mlx5_tx_dbrec(txq, mpw.wqe);
1106         txq->elts_head = elts_head;
1107         return i;
1108 }
1109
1110 /**
1111  * Open a MPW inline session.
1112  *
1113  * @param txq
1114  *   Pointer to TX queue structure.
1115  * @param mpw
1116  *   Pointer to MPW session structure.
1117  * @param length
1118  *   Packet length.
1119  */
1120 static inline void
1121 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1122 {
1123         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1124         struct mlx5_wqe_inl_small *inl;
1125
1126         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1127         mpw->pkts_n = 0;
1128         mpw->len = length;
1129         mpw->total_len = 0;
1130         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1131         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1132                                   (txq->wqe_ci << 8) |
1133                                   MLX5_OPCODE_TSO);
1134         mpw->wqe->ctrl[2] = 0;
1135         mpw->wqe->ctrl[3] = 0;
1136         mpw->wqe->eseg.mss = htons(length);
1137         mpw->wqe->eseg.inline_hdr_sz = 0;
1138         mpw->wqe->eseg.cs_flags = 0;
1139         mpw->wqe->eseg.rsvd0 = 0;
1140         mpw->wqe->eseg.rsvd1 = 0;
1141         mpw->wqe->eseg.rsvd2 = 0;
1142         inl = (struct mlx5_wqe_inl_small *)
1143                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1144         mpw->data.raw = (uint8_t *)&inl->raw;
1145 }
1146
1147 /**
1148  * Close a MPW inline session.
1149  *
1150  * @param txq
1151  *   Pointer to TX queue structure.
1152  * @param mpw
1153  *   Pointer to MPW session structure.
1154  */
1155 static inline void
1156 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1157 {
1158         unsigned int size;
1159         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1160                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1161
1162         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1163         /*
1164          * Store size in multiple of 16 bytes. Control and Ethernet segments
1165          * count as 2.
1166          */
1167         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1168         mpw->state = MLX5_MPW_STATE_CLOSED;
1169         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1170         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1171 }
1172
1173 /**
1174  * DPDK callback for TX with MPW inline support.
1175  *
1176  * @param dpdk_txq
1177  *   Generic pointer to TX queue structure.
1178  * @param[in] pkts
1179  *   Packets to transmit.
1180  * @param pkts_n
1181  *   Number of packets in array.
1182  *
1183  * @return
1184  *   Number of packets successfully transmitted (<= pkts_n).
1185  */
1186 uint16_t
1187 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1188                          uint16_t pkts_n)
1189 {
1190         struct txq *txq = (struct txq *)dpdk_txq;
1191         uint16_t elts_head = txq->elts_head;
1192         const unsigned int elts_n = 1 << txq->elts_n;
1193         unsigned int i = 0;
1194         unsigned int j = 0;
1195         unsigned int max;
1196         uint16_t max_wqe;
1197         unsigned int comp;
1198         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1199         struct mlx5_mpw mpw = {
1200                 .state = MLX5_MPW_STATE_CLOSED,
1201         };
1202         /*
1203          * Compute the maximum number of WQE which can be consumed by inline
1204          * code.
1205          * - 2 DSEG for:
1206          *   - 1 control segment,
1207          *   - 1 Ethernet segment,
1208          * - N Dseg from the inline request.
1209          */
1210         const unsigned int wqe_inl_n =
1211                 ((2 * MLX5_WQE_DWORD_SIZE +
1212                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1213                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1214
1215         if (unlikely(!pkts_n))
1216                 return 0;
1217         /* Prefetch first packet cacheline. */
1218         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1219         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1220         /* Start processing. */
1221         txq_complete(txq);
1222         max = (elts_n - (elts_head - txq->elts_tail));
1223         if (max > elts_n)
1224                 max -= elts_n;
1225         do {
1226                 struct rte_mbuf *buf = *(pkts++);
1227                 unsigned int elts_head_next;
1228                 uintptr_t addr;
1229                 uint32_t length;
1230                 unsigned int segs_n = buf->nb_segs;
1231                 uint32_t cs_flags = 0;
1232
1233                 /*
1234                  * Make sure there is enough room to store this packet and
1235                  * that one ring entry remains unused.
1236                  */
1237                 assert(segs_n);
1238                 if (max < segs_n + 1)
1239                         break;
1240                 /* Do not bother with large packets MPW cannot handle. */
1241                 if (segs_n > MLX5_MPW_DSEG_MAX)
1242                         break;
1243                 max -= segs_n;
1244                 --pkts_n;
1245                 /*
1246                  * Compute max_wqe in case less WQE were consumed in previous
1247                  * iteration.
1248                  */
1249                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1250                 /* Should we enable HW CKSUM offload */
1251                 if (buf->ol_flags &
1252                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1253                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1254                 /* Retrieve packet information. */
1255                 length = PKT_LEN(buf);
1256                 /* Start new session if packet differs. */
1257                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1258                         if ((mpw.len != length) ||
1259                             (segs_n != 1) ||
1260                             (mpw.wqe->eseg.cs_flags != cs_flags))
1261                                 mlx5_mpw_close(txq, &mpw);
1262                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1263                         if ((mpw.len != length) ||
1264                             (segs_n != 1) ||
1265                             (length > inline_room) ||
1266                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1267                                 mlx5_mpw_inline_close(txq, &mpw);
1268                                 inline_room =
1269                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1270                         }
1271                 }
1272                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1273                         if ((segs_n != 1) ||
1274                             (length > inline_room)) {
1275                                 /*
1276                                  * Multi-Packet WQE consumes at most two WQE.
1277                                  * mlx5_mpw_new() expects to be able to use
1278                                  * such resources.
1279                                  */
1280                                 if (unlikely(max_wqe < 2))
1281                                         break;
1282                                 max_wqe -= 2;
1283                                 mlx5_mpw_new(txq, &mpw, length);
1284                                 mpw.wqe->eseg.cs_flags = cs_flags;
1285                         } else {
1286                                 if (unlikely(max_wqe < wqe_inl_n))
1287                                         break;
1288                                 max_wqe -= wqe_inl_n;
1289                                 mlx5_mpw_inline_new(txq, &mpw, length);
1290                                 mpw.wqe->eseg.cs_flags = cs_flags;
1291                         }
1292                 }
1293                 /* Multi-segment packets must be alone in their MPW. */
1294                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1295                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1296                         assert(inline_room ==
1297                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1298 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1299                         length = 0;
1300 #endif
1301                         do {
1302                                 volatile struct mlx5_wqe_data_seg *dseg;
1303
1304                                 elts_head_next =
1305                                         (elts_head + 1) & (elts_n - 1);
1306                                 assert(buf);
1307                                 (*txq->elts)[elts_head] = buf;
1308                                 dseg = mpw.data.dseg[mpw.pkts_n];
1309                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1310                                 *dseg = (struct mlx5_wqe_data_seg){
1311                                         .byte_count = htonl(DATA_LEN(buf)),
1312                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1313                                         .addr = htonll(addr),
1314                                 };
1315                                 elts_head = elts_head_next;
1316 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1317                                 length += DATA_LEN(buf);
1318 #endif
1319                                 buf = buf->next;
1320                                 ++mpw.pkts_n;
1321                                 ++j;
1322                         } while (--segs_n);
1323                         assert(length == mpw.len);
1324                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1325                                 mlx5_mpw_close(txq, &mpw);
1326                 } else {
1327                         unsigned int max;
1328
1329                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1330                         assert(length <= inline_room);
1331                         assert(length == DATA_LEN(buf));
1332                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1333                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1334                         (*txq->elts)[elts_head] = buf;
1335                         /* Maximum number of bytes before wrapping. */
1336                         max = ((((uintptr_t)(txq->wqes)) +
1337                                 (1 << txq->wqe_n) *
1338                                 MLX5_WQE_SIZE) -
1339                                (uintptr_t)mpw.data.raw);
1340                         if (length > max) {
1341                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1342                                            (void *)addr,
1343                                            max);
1344                                 mpw.data.raw = (volatile void *)txq->wqes;
1345                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1346                                            (void *)(addr + max),
1347                                            length - max);
1348                                 mpw.data.raw += length - max;
1349                         } else {
1350                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1351                                            (void *)addr,
1352                                            length);
1353
1354                                 if (length == max)
1355                                         mpw.data.raw =
1356                                                 (volatile void *)txq->wqes;
1357                                 else
1358                                         mpw.data.raw += length;
1359                         }
1360                         ++mpw.pkts_n;
1361                         mpw.total_len += length;
1362                         ++j;
1363                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1364                                 mlx5_mpw_inline_close(txq, &mpw);
1365                                 inline_room =
1366                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1367                         } else {
1368                                 inline_room -= length;
1369                         }
1370                 }
1371                 elts_head = elts_head_next;
1372 #ifdef MLX5_PMD_SOFT_COUNTERS
1373                 /* Increment sent bytes counter. */
1374                 txq->stats.obytes += length;
1375 #endif
1376                 ++i;
1377         } while (pkts_n);
1378         /* Take a shortcut if nothing must be sent. */
1379         if (unlikely(i == 0))
1380                 return 0;
1381         /* Check whether completion threshold has been reached. */
1382         /* "j" includes both packets and segments. */
1383         comp = txq->elts_comp + j;
1384         if (comp >= MLX5_TX_COMP_THRESH) {
1385                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1386
1387                 /* Request completion on last WQE. */
1388                 wqe->ctrl[2] = htonl(8);
1389                 /* Save elts_head in unused "immediate" field of WQE. */
1390                 wqe->ctrl[3] = elts_head;
1391                 txq->elts_comp = 0;
1392         } else {
1393                 txq->elts_comp = comp;
1394         }
1395 #ifdef MLX5_PMD_SOFT_COUNTERS
1396         /* Increment sent packets counter. */
1397         txq->stats.opackets += i;
1398 #endif
1399         /* Ring QP doorbell. */
1400         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1401                 mlx5_mpw_inline_close(txq, &mpw);
1402         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1403                 mlx5_mpw_close(txq, &mpw);
1404         mlx5_tx_dbrec(txq, mpw.wqe);
1405         txq->elts_head = elts_head;
1406         return i;
1407 }
1408
1409 /**
1410  * Open an Enhanced MPW session.
1411  *
1412  * @param txq
1413  *   Pointer to TX queue structure.
1414  * @param mpw
1415  *   Pointer to MPW session structure.
1416  * @param length
1417  *   Packet length.
1418  */
1419 static inline void
1420 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1421 {
1422         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1423
1424         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1425         mpw->pkts_n = 0;
1426         mpw->total_len = sizeof(struct mlx5_wqe);
1427         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1428         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1429                                   (txq->wqe_ci << 8) |
1430                                   MLX5_OPCODE_ENHANCED_MPSW);
1431         mpw->wqe->ctrl[2] = 0;
1432         mpw->wqe->ctrl[3] = 0;
1433         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1434         if (unlikely(padding)) {
1435                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1436
1437                 /* Pad the first 2 DWORDs with zero-length inline header. */
1438                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1439                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1440                         htonl(MLX5_INLINE_SEG);
1441                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1442                 /* Start from the next WQEBB. */
1443                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1444         } else {
1445                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1446         }
1447 }
1448
1449 /**
1450  * Close an Enhanced MPW session.
1451  *
1452  * @param txq
1453  *   Pointer to TX queue structure.
1454  * @param mpw
1455  *   Pointer to MPW session structure.
1456  *
1457  * @return
1458  *   Number of consumed WQEs.
1459  */
1460 static inline uint16_t
1461 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1462 {
1463         uint16_t ret;
1464
1465         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1466          * count as 2.
1467          */
1468         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1469         mpw->state = MLX5_MPW_STATE_CLOSED;
1470         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1471         txq->wqe_ci += ret;
1472         return ret;
1473 }
1474
1475 /**
1476  * DPDK callback for TX with Enhanced MPW support.
1477  *
1478  * @param dpdk_txq
1479  *   Generic pointer to TX queue structure.
1480  * @param[in] pkts
1481  *   Packets to transmit.
1482  * @param pkts_n
1483  *   Number of packets in array.
1484  *
1485  * @return
1486  *   Number of packets successfully transmitted (<= pkts_n).
1487  */
1488 uint16_t
1489 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1490 {
1491         struct txq *txq = (struct txq *)dpdk_txq;
1492         uint16_t elts_head = txq->elts_head;
1493         const unsigned int elts_n = 1 << txq->elts_n;
1494         unsigned int i = 0;
1495         unsigned int j = 0;
1496         unsigned int max_elts;
1497         uint16_t max_wqe;
1498         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1499         unsigned int mpw_room = 0;
1500         unsigned int inl_pad = 0;
1501         uint32_t inl_hdr;
1502         struct mlx5_mpw mpw = {
1503                 .state = MLX5_MPW_STATE_CLOSED,
1504         };
1505
1506         if (unlikely(!pkts_n))
1507                 return 0;
1508         /* Start processing. */
1509         txq_complete(txq);
1510         max_elts = (elts_n - (elts_head - txq->elts_tail));
1511         if (max_elts > elts_n)
1512                 max_elts -= elts_n;
1513         /* A CQE slot must always be available. */
1514         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1515         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1516         if (unlikely(!max_wqe))
1517                 return 0;
1518         do {
1519                 struct rte_mbuf *buf = *(pkts++);
1520                 unsigned int elts_head_next;
1521                 uintptr_t addr;
1522                 uint64_t naddr;
1523                 unsigned int n;
1524                 unsigned int do_inline = 0; /* Whether inline is possible. */
1525                 uint32_t length;
1526                 unsigned int segs_n = buf->nb_segs;
1527                 uint32_t cs_flags = 0;
1528
1529                 /*
1530                  * Make sure there is enough room to store this packet and
1531                  * that one ring entry remains unused.
1532                  */
1533                 assert(segs_n);
1534                 if (max_elts - j < segs_n + 1)
1535                         break;
1536                 /* Do not bother with large packets MPW cannot handle. */
1537                 if (segs_n > MLX5_MPW_DSEG_MAX)
1538                         break;
1539                 /* Should we enable HW CKSUM offload. */
1540                 if (buf->ol_flags &
1541                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1542                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1543                 /* Retrieve packet information. */
1544                 length = PKT_LEN(buf);
1545                 /* Start new session if:
1546                  * - multi-segment packet
1547                  * - no space left even for a dseg
1548                  * - next packet can be inlined with a new WQE
1549                  * - cs_flag differs
1550                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1551                  * segmented packet.
1552                  */
1553                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1554                         if ((segs_n != 1) ||
1555                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1556                               mpw_room) ||
1557                             (length <= txq->inline_max_packet_sz &&
1558                              inl_pad + sizeof(inl_hdr) + length >
1559                               mpw_room) ||
1560                             (mpw.wqe->eseg.cs_flags != cs_flags))
1561                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1562                 }
1563                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1564                         if (unlikely(segs_n != 1)) {
1565                                 /* Fall back to legacy MPW.
1566                                  * A MPW session consumes 2 WQEs at most to
1567                                  * include MLX5_MPW_DSEG_MAX pointers.
1568                                  */
1569                                 if (unlikely(max_wqe < 2))
1570                                         break;
1571                                 mlx5_mpw_new(txq, &mpw, length);
1572                         } else {
1573                                 /* In Enhanced MPW, inline as much as the budget
1574                                  * is allowed. The remaining space is to be
1575                                  * filled with dsegs. If the title WQEBB isn't
1576                                  * padded, it will have 2 dsegs there.
1577                                  */
1578                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1579                                             (max_inline ? max_inline :
1580                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1581                                             MLX5_WQE_SIZE);
1582                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1583                                               mpw_room))
1584                                         break;
1585                                 /* Don't pad the title WQEBB to not waste WQ. */
1586                                 mlx5_empw_new(txq, &mpw, 0);
1587                                 mpw_room -= mpw.total_len;
1588                                 inl_pad = 0;
1589                                 do_inline =
1590                                         length <= txq->inline_max_packet_sz &&
1591                                         sizeof(inl_hdr) + length <= mpw_room &&
1592                                         !txq->mpw_hdr_dseg;
1593                         }
1594                         mpw.wqe->eseg.cs_flags = cs_flags;
1595                 } else {
1596                         /* Evaluate whether the next packet can be inlined.
1597                          * Inlininig is possible when:
1598                          * - length is less than configured value
1599                          * - length fits for remaining space
1600                          * - not required to fill the title WQEBB with dsegs
1601                          */
1602                         do_inline =
1603                                 length <= txq->inline_max_packet_sz &&
1604                                 inl_pad + sizeof(inl_hdr) + length <=
1605                                  mpw_room &&
1606                                 (!txq->mpw_hdr_dseg ||
1607                                  mpw.total_len >= MLX5_WQE_SIZE);
1608                 }
1609                 /* Multi-segment packets must be alone in their MPW. */
1610                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1611                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1612 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1613                         length = 0;
1614 #endif
1615                         do {
1616                                 volatile struct mlx5_wqe_data_seg *dseg;
1617
1618                                 elts_head_next =
1619                                         (elts_head + 1) & (elts_n - 1);
1620                                 assert(buf);
1621                                 (*txq->elts)[elts_head] = buf;
1622                                 dseg = mpw.data.dseg[mpw.pkts_n];
1623                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1624                                 *dseg = (struct mlx5_wqe_data_seg){
1625                                         .byte_count = htonl(DATA_LEN(buf)),
1626                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1627                                         .addr = htonll(addr),
1628                                 };
1629                                 elts_head = elts_head_next;
1630 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1631                                 length += DATA_LEN(buf);
1632 #endif
1633                                 buf = buf->next;
1634                                 ++j;
1635                                 ++mpw.pkts_n;
1636                         } while (--segs_n);
1637                         /* A multi-segmented packet takes one MPW session.
1638                          * TODO: Pack more multi-segmented packets if possible.
1639                          */
1640                         mlx5_mpw_close(txq, &mpw);
1641                         if (mpw.pkts_n < 3)
1642                                 max_wqe--;
1643                         else
1644                                 max_wqe -= 2;
1645                 } else if (do_inline) {
1646                         /* Inline packet into WQE. */
1647                         unsigned int max;
1648
1649                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1650                         assert(length == DATA_LEN(buf));
1651                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1652                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1653                         mpw.data.raw = (volatile void *)
1654                                 ((uintptr_t)mpw.data.raw + inl_pad);
1655                         max = tx_mlx5_wq_tailroom(txq,
1656                                         (void *)(uintptr_t)mpw.data.raw);
1657                         /* Copy inline header. */
1658                         mpw.data.raw = (volatile void *)
1659                                 mlx5_copy_to_wq(
1660                                           (void *)(uintptr_t)mpw.data.raw,
1661                                           &inl_hdr,
1662                                           sizeof(inl_hdr),
1663                                           (void *)(uintptr_t)txq->wqes,
1664                                           max);
1665                         max = tx_mlx5_wq_tailroom(txq,
1666                                         (void *)(uintptr_t)mpw.data.raw);
1667                         /* Copy packet data. */
1668                         mpw.data.raw = (volatile void *)
1669                                 mlx5_copy_to_wq(
1670                                           (void *)(uintptr_t)mpw.data.raw,
1671                                           (void *)addr,
1672                                           length,
1673                                           (void *)(uintptr_t)txq->wqes,
1674                                           max);
1675                         ++mpw.pkts_n;
1676                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1677                         /* No need to get completion as the entire packet is
1678                          * copied to WQ. Free the buf right away.
1679                          */
1680                         elts_head_next = elts_head;
1681                         rte_pktmbuf_free_seg(buf);
1682                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1683                         /* Add pad in the next packet if any. */
1684                         inl_pad = (((uintptr_t)mpw.data.raw +
1685                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1686                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1687                                   (uintptr_t)mpw.data.raw;
1688                 } else {
1689                         /* No inline. Load a dseg of packet pointer. */
1690                         volatile rte_v128u32_t *dseg;
1691
1692                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1693                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1694                         assert(length == DATA_LEN(buf));
1695                         if (!tx_mlx5_wq_tailroom(txq,
1696                                         (void *)((uintptr_t)mpw.data.raw
1697                                                 + inl_pad)))
1698                                 dseg = (volatile void *)txq->wqes;
1699                         else
1700                                 dseg = (volatile void *)
1701                                         ((uintptr_t)mpw.data.raw +
1702                                          inl_pad);
1703                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1704                         (*txq->elts)[elts_head] = buf;
1705                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1706                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1707                                 rte_prefetch2((void *)(addr +
1708                                                 n * RTE_CACHE_LINE_SIZE));
1709                         naddr = htonll(addr);
1710                         *dseg = (rte_v128u32_t) {
1711                                 htonl(length),
1712                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1713                                 naddr,
1714                                 naddr >> 32,
1715                         };
1716                         mpw.data.raw = (volatile void *)(dseg + 1);
1717                         mpw.total_len += (inl_pad + sizeof(*dseg));
1718                         ++j;
1719                         ++mpw.pkts_n;
1720                         mpw_room -= (inl_pad + sizeof(*dseg));
1721                         inl_pad = 0;
1722                 }
1723                 elts_head = elts_head_next;
1724 #ifdef MLX5_PMD_SOFT_COUNTERS
1725                 /* Increment sent bytes counter. */
1726                 txq->stats.obytes += length;
1727 #endif
1728                 ++i;
1729         } while (i < pkts_n);
1730         /* Take a shortcut if nothing must be sent. */
1731         if (unlikely(i == 0))
1732                 return 0;
1733         /* Check whether completion threshold has been reached. */
1734         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1735                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1736                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1737                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1738
1739                 /* Request completion on last WQE. */
1740                 wqe->ctrl[2] = htonl(8);
1741                 /* Save elts_head in unused "immediate" field of WQE. */
1742                 wqe->ctrl[3] = elts_head;
1743                 txq->elts_comp = 0;
1744                 txq->mpw_comp = txq->wqe_ci;
1745                 txq->cq_pi++;
1746         } else {
1747                 txq->elts_comp += j;
1748         }
1749 #ifdef MLX5_PMD_SOFT_COUNTERS
1750         /* Increment sent packets counter. */
1751         txq->stats.opackets += i;
1752 #endif
1753         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1754                 mlx5_empw_close(txq, &mpw);
1755         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1756                 mlx5_mpw_close(txq, &mpw);
1757         /* Ring QP doorbell. */
1758         mlx5_tx_dbrec(txq, mpw.wqe);
1759         txq->elts_head = elts_head;
1760         return i;
1761 }
1762
1763 /**
1764  * Translate RX completion flags to packet type.
1765  *
1766  * @param[in] cqe
1767  *   Pointer to CQE.
1768  *
1769  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1770  *
1771  * @return
1772  *   Packet type for struct rte_mbuf.
1773  */
1774 static inline uint32_t
1775 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1776 {
1777         uint32_t pkt_type;
1778         uint16_t flags = ntohs(cqe->hdr_type_etc);
1779
1780         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1781                 pkt_type =
1782                         TRANSPOSE(flags,
1783                                   MLX5_CQE_RX_IPV4_PACKET,
1784                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1785                         TRANSPOSE(flags,
1786                                   MLX5_CQE_RX_IPV6_PACKET,
1787                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1788                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1789                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1790                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1791         } else {
1792                 pkt_type =
1793                         TRANSPOSE(flags,
1794                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1795                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1796                         TRANSPOSE(flags,
1797                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1798                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1799         }
1800         return pkt_type;
1801 }
1802
1803 /**
1804  * Get size of the next packet for a given CQE. For compressed CQEs, the
1805  * consumer index is updated only once all packets of the current one have
1806  * been processed.
1807  *
1808  * @param rxq
1809  *   Pointer to RX queue.
1810  * @param cqe
1811  *   CQE to process.
1812  * @param[out] rss_hash
1813  *   Packet RSS Hash result.
1814  *
1815  * @return
1816  *   Packet size in bytes (0 if there is none), -1 in case of completion
1817  *   with error.
1818  */
1819 static inline int
1820 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1821                  uint16_t cqe_cnt, uint32_t *rss_hash)
1822 {
1823         struct rxq_zip *zip = &rxq->zip;
1824         uint16_t cqe_n = cqe_cnt + 1;
1825         int len = 0;
1826         uint16_t idx, end;
1827
1828         /* Process compressed data in the CQE and mini arrays. */
1829         if (zip->ai) {
1830                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1831                         (volatile struct mlx5_mini_cqe8 (*)[8])
1832                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1833
1834                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1835                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1836                 if ((++zip->ai & 7) == 0) {
1837                         /* Invalidate consumed CQEs */
1838                         idx = zip->ca;
1839                         end = zip->na;
1840                         while (idx != end) {
1841                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1842                                         MLX5_CQE_INVALIDATE;
1843                                 ++idx;
1844                         }
1845                         /*
1846                          * Increment consumer index to skip the number of
1847                          * CQEs consumed. Hardware leaves holes in the CQ
1848                          * ring for software use.
1849                          */
1850                         zip->ca = zip->na;
1851                         zip->na += 8;
1852                 }
1853                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1854                         /* Invalidate the rest */
1855                         idx = zip->ca;
1856                         end = zip->cq_ci;
1857
1858                         while (idx != end) {
1859                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1860                                         MLX5_CQE_INVALIDATE;
1861                                 ++idx;
1862                         }
1863                         rxq->cq_ci = zip->cq_ci;
1864                         zip->ai = 0;
1865                 }
1866         /* No compressed data, get next CQE and verify if it is compressed. */
1867         } else {
1868                 int ret;
1869                 int8_t op_own;
1870
1871                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1872                 if (unlikely(ret == 1))
1873                         return 0;
1874                 ++rxq->cq_ci;
1875                 op_own = cqe->op_own;
1876                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1877                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1878                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1879                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1880                                                           cqe_cnt]);
1881
1882                         /* Fix endianness. */
1883                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1884                         /*
1885                          * Current mini array position is the one returned by
1886                          * check_cqe64().
1887                          *
1888                          * If completion comprises several mini arrays, as a
1889                          * special case the second one is located 7 CQEs after
1890                          * the initial CQE instead of 8 for subsequent ones.
1891                          */
1892                         zip->ca = rxq->cq_ci;
1893                         zip->na = zip->ca + 7;
1894                         /* Compute the next non compressed CQE. */
1895                         --rxq->cq_ci;
1896                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1897                         /* Get packet size to return. */
1898                         len = ntohl((*mc)[0].byte_cnt);
1899                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1900                         zip->ai = 1;
1901                         /* Prefetch all the entries to be invalidated */
1902                         idx = zip->ca;
1903                         end = zip->cq_ci;
1904                         while (idx != end) {
1905                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1906                                 ++idx;
1907                         }
1908                 } else {
1909                         len = ntohl(cqe->byte_cnt);
1910                         *rss_hash = ntohl(cqe->rx_hash_res);
1911                 }
1912                 /* Error while receiving packet. */
1913                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1914                         return -1;
1915         }
1916         return len;
1917 }
1918
1919 /**
1920  * Translate RX completion flags to offload flags.
1921  *
1922  * @param[in] rxq
1923  *   Pointer to RX queue structure.
1924  * @param[in] cqe
1925  *   Pointer to CQE.
1926  *
1927  * @return
1928  *   Offload flags (ol_flags) for struct rte_mbuf.
1929  */
1930 static inline uint32_t
1931 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1932 {
1933         uint32_t ol_flags = 0;
1934         uint16_t flags = ntohs(cqe->hdr_type_etc);
1935
1936         ol_flags =
1937                 TRANSPOSE(flags,
1938                           MLX5_CQE_RX_L3_HDR_VALID,
1939                           PKT_RX_IP_CKSUM_GOOD) |
1940                 TRANSPOSE(flags,
1941                           MLX5_CQE_RX_L4_HDR_VALID,
1942                           PKT_RX_L4_CKSUM_GOOD);
1943         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1944                 ol_flags |=
1945                         TRANSPOSE(flags,
1946                                   MLX5_CQE_RX_L3_HDR_VALID,
1947                                   PKT_RX_IP_CKSUM_GOOD) |
1948                         TRANSPOSE(flags,
1949                                   MLX5_CQE_RX_L4_HDR_VALID,
1950                                   PKT_RX_L4_CKSUM_GOOD);
1951         return ol_flags;
1952 }
1953
1954 /**
1955  * DPDK callback for RX.
1956  *
1957  * @param dpdk_rxq
1958  *   Generic pointer to RX queue structure.
1959  * @param[out] pkts
1960  *   Array to store received packets.
1961  * @param pkts_n
1962  *   Maximum number of packets in array.
1963  *
1964  * @return
1965  *   Number of packets successfully received (<= pkts_n).
1966  */
1967 uint16_t
1968 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1969 {
1970         struct rxq *rxq = dpdk_rxq;
1971         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1972         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1973         const unsigned int sges_n = rxq->sges_n;
1974         struct rte_mbuf *pkt = NULL;
1975         struct rte_mbuf *seg = NULL;
1976         volatile struct mlx5_cqe *cqe =
1977                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1978         unsigned int i = 0;
1979         unsigned int rq_ci = rxq->rq_ci << sges_n;
1980         int len = 0; /* keep its value across iterations. */
1981
1982         while (pkts_n) {
1983                 unsigned int idx = rq_ci & wqe_cnt;
1984                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1985                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1986                 uint32_t rss_hash_res = 0;
1987
1988                 if (pkt)
1989                         NEXT(seg) = rep;
1990                 seg = rep;
1991                 rte_prefetch0(seg);
1992                 rte_prefetch0(cqe);
1993                 rte_prefetch0(wqe);
1994                 rep = rte_mbuf_raw_alloc(rxq->mp);
1995                 if (unlikely(rep == NULL)) {
1996                         ++rxq->stats.rx_nombuf;
1997                         if (!pkt) {
1998                                 /*
1999                                  * no buffers before we even started,
2000                                  * bail out silently.
2001                                  */
2002                                 break;
2003                         }
2004                         while (pkt != seg) {
2005                                 assert(pkt != (*rxq->elts)[idx]);
2006                                 rep = NEXT(pkt);
2007                                 NEXT(pkt) = NULL;
2008                                 NB_SEGS(pkt) = 1;
2009                                 rte_mbuf_raw_free(pkt);
2010                                 pkt = rep;
2011                         }
2012                         break;
2013                 }
2014                 if (!pkt) {
2015                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2016                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2017                                                &rss_hash_res);
2018                         if (!len) {
2019                                 rte_mbuf_raw_free(rep);
2020                                 break;
2021                         }
2022                         if (unlikely(len == -1)) {
2023                                 /* RX error, packet is likely too large. */
2024                                 rte_mbuf_raw_free(rep);
2025                                 ++rxq->stats.idropped;
2026                                 goto skip;
2027                         }
2028                         pkt = seg;
2029                         assert(len >= (rxq->crc_present << 2));
2030                         /* Update packet information. */
2031                         pkt->packet_type = 0;
2032                         pkt->ol_flags = 0;
2033                         if (rss_hash_res && rxq->rss_hash) {
2034                                 pkt->hash.rss = rss_hash_res;
2035                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2036                         }
2037                         if (rxq->mark &&
2038                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2039                                 pkt->ol_flags |= PKT_RX_FDIR;
2040                                 if (cqe->sop_drop_qpn !=
2041                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2042                                         uint32_t mark = cqe->sop_drop_qpn;
2043
2044                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2045                                         pkt->hash.fdir.hi =
2046                                                 mlx5_flow_mark_get(mark);
2047                                 }
2048                         }
2049                         if (rxq->csum | rxq->csum_l2tun) {
2050                                 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2051                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2052                         }
2053                         if (rxq->vlan_strip &&
2054                             (cqe->hdr_type_etc &
2055                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2056                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2057                                         PKT_RX_VLAN_STRIPPED;
2058                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2059                         }
2060                         if (rxq->crc_present)
2061                                 len -= ETHER_CRC_LEN;
2062                         PKT_LEN(pkt) = len;
2063                 }
2064                 DATA_LEN(rep) = DATA_LEN(seg);
2065                 PKT_LEN(rep) = PKT_LEN(seg);
2066                 SET_DATA_OFF(rep, DATA_OFF(seg));
2067                 NB_SEGS(rep) = NB_SEGS(seg);
2068                 PORT(rep) = PORT(seg);
2069                 NEXT(rep) = NULL;
2070                 (*rxq->elts)[idx] = rep;
2071                 /*
2072                  * Fill NIC descriptor with the new buffer.  The lkey and size
2073                  * of the buffers are already known, only the buffer address
2074                  * changes.
2075                  */
2076                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2077                 if (len > DATA_LEN(seg)) {
2078                         len -= DATA_LEN(seg);
2079                         ++NB_SEGS(pkt);
2080                         ++rq_ci;
2081                         continue;
2082                 }
2083                 DATA_LEN(seg) = len;
2084 #ifdef MLX5_PMD_SOFT_COUNTERS
2085                 /* Increment bytes counter. */
2086                 rxq->stats.ibytes += PKT_LEN(pkt);
2087 #endif
2088                 /* Return packet. */
2089                 *(pkts++) = pkt;
2090                 pkt = NULL;
2091                 --pkts_n;
2092                 ++i;
2093 skip:
2094                 /* Align consumer index to the next stride. */
2095                 rq_ci >>= sges_n;
2096                 ++rq_ci;
2097                 rq_ci <<= sges_n;
2098         }
2099         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2100                 return 0;
2101         /* Update the consumer index. */
2102         rxq->rq_ci = rq_ci >> sges_n;
2103         rte_wmb();
2104         *rxq->cq_db = htonl(rxq->cq_ci);
2105         rte_wmb();
2106         *rxq->rq_db = htonl(rxq->rq_ci);
2107 #ifdef MLX5_PMD_SOFT_COUNTERS
2108         /* Increment packets counter. */
2109         rxq->stats.ipackets += i;
2110 #endif
2111         return i;
2112 }
2113
2114 /**
2115  * Dummy DPDK callback for TX.
2116  *
2117  * This function is used to temporarily replace the real callback during
2118  * unsafe control operations on the queue, or in case of error.
2119  *
2120  * @param dpdk_txq
2121  *   Generic pointer to TX queue structure.
2122  * @param[in] pkts
2123  *   Packets to transmit.
2124  * @param pkts_n
2125  *   Number of packets in array.
2126  *
2127  * @return
2128  *   Number of packets successfully transmitted (<= pkts_n).
2129  */
2130 uint16_t
2131 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2132 {
2133         (void)dpdk_txq;
2134         (void)pkts;
2135         (void)pkts_n;
2136         return 0;
2137 }
2138
2139 /**
2140  * Dummy DPDK callback for RX.
2141  *
2142  * This function is used to temporarily replace the real callback during
2143  * unsafe control operations on the queue, or in case of error.
2144  *
2145  * @param dpdk_rxq
2146  *   Generic pointer to RX queue structure.
2147  * @param[out] pkts
2148  *   Array to store received packets.
2149  * @param pkts_n
2150  *   Maximum number of packets in array.
2151  *
2152  * @return
2153  *   Number of packets successfully received (<= pkts_n).
2154  */
2155 uint16_t
2156 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2157 {
2158         (void)dpdk_rxq;
2159         (void)pkts;
2160         (void)pkts_n;
2161         return 0;
2162 }
2163
2164 /**
2165  * DPDK callback for rx queue interrupt enable.
2166  *
2167  * @param dev
2168  *   Pointer to Ethernet device structure.
2169  * @param rx_queue_id
2170  *   RX queue number
2171  *
2172  * @return
2173  *   0 on success, negative on failure.
2174  */
2175 int
2176 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2177 {
2178 #ifdef HAVE_UPDATE_CQ_CI
2179         struct priv *priv = mlx5_get_priv(dev);
2180         struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2181         struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2182         struct ibv_cq *cq = rxq_ctrl->cq;
2183         uint16_t ci = rxq->cq_ci;
2184         int ret = 0;
2185
2186         ibv_mlx5_exp_update_cq_ci(cq, ci);
2187         ret = ibv_req_notify_cq(cq, 0);
2188 #else
2189         int ret = -1;
2190         (void)dev;
2191         (void)rx_queue_id;
2192 #endif
2193         if (ret)
2194                 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2195         return ret;
2196 }
2197
2198 /**
2199  * DPDK callback for rx queue interrupt disable.
2200  *
2201  * @param dev
2202  *   Pointer to Ethernet device structure.
2203  * @param rx_queue_id
2204  *   RX queue number
2205  *
2206  * @return
2207  *   0 on success, negative on failure.
2208  */
2209 int
2210 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2211 {
2212 #ifdef HAVE_UPDATE_CQ_CI
2213         struct priv *priv = mlx5_get_priv(dev);
2214         struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2215         struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2216         struct ibv_cq *cq = rxq_ctrl->cq;
2217         struct ibv_cq *ev_cq;
2218         void *ev_ctx;
2219         int ret = 0;
2220
2221         ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2222         if (ret || ev_cq != cq)
2223                 ret = -1;
2224         else
2225                 ibv_ack_cq_events(cq, 1);
2226 #else
2227         int ret = -1;
2228         (void)dev;
2229         (void)rx_queue_id;
2230 #endif
2231         if (ret)
2232                 WARN("unable to disable interrupt on rx queue %d",
2233                      rx_queue_id);
2234         return ret;
2235 }