drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static __rte_always_inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci);
  75
  76 static __rte_always_inline void
  77 txq_complete(struct txq *txq);
  78
  79 static __rte_always_inline uint32_t
  80 txq_mb2mr(struct txq *txq, struct rte_mbuf *mb);
  81
  82 static __rte_always_inline void
  83 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe);
  84
  85 static __rte_always_inline uint32_t
  86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  87
  88 static __rte_always_inline int
  89 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  90                  uint16_t cqe_cnt, uint32_t *rss_hash);
  91
  92 static __rte_always_inline uint32_t
  93 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  94
  95 #ifndef NDEBUG
  96
  97 /**
  98  * Verify or set magic value in CQE.
  99  *
 100  * @param cqe
 101  *   Pointer to CQE.
 102  *
 103  * @return
 104  *   0 the first time.
 105  */
 106 static inline int
 107 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 108 {
 109         static const uint8_t magic[] = "seen";
 110         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 111         int ret = 1;
 112         unsigned int i;
 113
 114         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 115                 if (!ret || (*buf)[i] != magic[i]) {
 116                         ret = 0;
 117                         (*buf)[i] = magic[i];
 118                 }
 119         return ret;
 120 }
 121
 122 #endif /* NDEBUG */
 123
 124 /**
 125  * Check whether CQE is valid.
 126  *
 127  * @param cqe
 128  *   Pointer to CQE.
 129  * @param cqes_n
 130  *   Size of completion queue.
 131  * @param ci
 132  *   Consumer index.
 133  *
 134  * @return
 135  *   0 on success, 1 on failure.
 136  */
 137 static inline int
 138 check_cqe(volatile struct mlx5_cqe *cqe,
 139           unsigned int cqes_n, const uint16_t ci)
 140 {
 141         uint16_t idx = ci & cqes_n;
 142         uint8_t op_own = cqe->op_own;
 143         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 144         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 145
 146         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 147                 return 1; /* No CQE. */
 148 #ifndef NDEBUG
 149         if ((op_code == MLX5_CQE_RESP_ERR) ||
 150             (op_code == MLX5_CQE_REQ_ERR)) {
 151                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 152                 uint8_t syndrome = err_cqe->syndrome;
 153
 154                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 155                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 156                         return 0;
 157                 if (!check_cqe_seen(cqe))
 158                         ERROR("unexpected CQE error %u (0x%02x)"
 159                               " syndrome 0x%02x",
 160                               op_code, op_code, syndrome);
 161                 return 1;
 162         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 163                    (op_code != MLX5_CQE_REQ)) {
 164                 if (!check_cqe_seen(cqe))
 165                         ERROR("unexpected CQE opcode %u (0x%02x)",
 166                               op_code, op_code);
 167                 return 1;
 168         }
 169 #endif /* NDEBUG */
 170         return 0;
 171 }
 172
 173 /**
 174  * Return the address of the WQE.
 175  *
 176  * @param txq
 177  *   Pointer to TX queue structure.
 178  * @param  wqe_ci
 179  *   WQE consumer index.
 180  *
 181  * @return
 182  *   WQE address.
 183  */
 184 static inline uintptr_t *
 185 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 186 {
 187         ci &= ((1 << txq->wqe_n) - 1);
 188         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 189 }
 190
 191 /**
 192  * Return the size of tailroom of WQ.
 193  *
 194  * @param txq
 195  *   Pointer to TX queue structure.
 196  * @param addr
 197  *   Pointer to tail of WQ.
 198  *
 199  * @return
 200  *   Size of tailroom.
 201  */
 202 static inline size_t
 203 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 204 {
 205         size_t tailroom;
 206         tailroom = (uintptr_t)(txq->wqes) +
 207                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 208                    (uintptr_t)addr;
 209         return tailroom;
 210 }
 211
 212 /**
 213  * Copy data to tailroom of circular queue.
 214  *
 215  * @param dst
 216  *   Pointer to destination.
 217  * @param src
 218  *   Pointer to source.
 219  * @param n
 220  *   Number of bytes to copy.
 221  * @param base
 222  *   Pointer to head of queue.
 223  * @param tailroom
 224  *   Size of tailroom from dst.
 225  *
 226  * @return
 227  *   Pointer after copied data.
 228  */
 229 static inline void *
 230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 231                 void *base, size_t tailroom)
 232 {
 233         void *ret;
 234
 235         if (n > tailroom) {
 236                 rte_memcpy(dst, src, tailroom);
 237                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 238                            n - tailroom);
 239                 ret = (uint8_t *)base + n - tailroom;
 240         } else {
 241                 rte_memcpy(dst, src, n);
 242                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 243         }
 244         return ret;
 245 }
 246
 247 /**
 248  * Manage TX completions.
 249  *
 250  * When sending a burst, mlx5_tx_burst() posts several WRs.
 251  *
 252  * @param txq
 253  *   Pointer to TX queue structure.
 254  */
 255 static inline void
 256 txq_complete(struct txq *txq)
 257 {
 258         const uint16_t elts_n = 1 << txq->elts_n;
 259         const uint16_t elts_m = elts_n - 1;
 260         const unsigned int cqe_n = 1 << txq->cqe_n;
 261         const unsigned int cqe_cnt = cqe_n - 1;
 262         uint16_t elts_free = txq->elts_tail;
 263         uint16_t elts_tail;
 264         uint16_t cq_ci = txq->cq_ci;
 265         volatile struct mlx5_cqe *cqe = NULL;
 266         volatile struct mlx5_wqe_ctrl *ctrl;
 267         struct rte_mbuf *m, *free[elts_n];
 268         struct rte_mempool *pool = NULL;
 269         unsigned int blk_n = 0;
 270
 271         do {
 272                 volatile struct mlx5_cqe *tmp;
 273
 274                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 275                 if (check_cqe(tmp, cqe_n, cq_ci))
 276                         break;
 277                 cqe = tmp;
 278 #ifndef NDEBUG
 279                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 280                         if (!check_cqe_seen(cqe))
 281                                 ERROR("unexpected compressed CQE, TX stopped");
 282                         return;
 283                 }
 284                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 285                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 286                         if (!check_cqe_seen(cqe))
 287                                 ERROR("unexpected error CQE, TX stopped");
 288                         return;
 289                 }
 290 #endif /* NDEBUG */
 291                 ++cq_ci;
 292         } while (1);
 293         if (unlikely(cqe == NULL))
 294                 return;
 295         txq->wqe_pi = ntohs(cqe->wqe_counter);
 296         ctrl = (volatile struct mlx5_wqe_ctrl *)
 297                 tx_mlx5_wqe(txq, txq->wqe_pi);
 298         elts_tail = ctrl->ctrl3;
 299         assert((elts_tail & elts_m) < (1 << txq->wqe_n));
 300         /* Free buffers. */
 301         while (elts_free != elts_tail) {
 302                 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
 303                 if (likely(m != NULL)) {
 304                         if (likely(m->pool == pool)) {
 305                                 free[blk_n++] = m;
 306                         } else {
 307                                 if (likely(pool != NULL))
 308                                         rte_mempool_put_bulk(pool,
 309                                                              (void *)free,
 310                                                              blk_n);
 311                                 free[0] = m;
 312                                 pool = m->pool;
 313                                 blk_n = 1;
 314                         }
 315                 }
 316         }
 317         if (blk_n)
 318                 rte_mempool_put_bulk(pool, (void *)free, blk_n);
 319 #ifndef NDEBUG
 320         elts_free = txq->elts_tail;
 321         /* Poisoning. */
 322         while (elts_free != elts_tail) {
 323                 memset(&(*txq->elts)[elts_free & elts_m],
 324                        0x66,
 325                        sizeof((*txq->elts)[elts_free & elts_m]));
 326                 ++elts_free;
 327         }
 328 #endif
 329         txq->cq_ci = cq_ci;
 330         txq->elts_tail = elts_tail;
 331         /* Update the consumer index. */
 332         rte_wmb();
 333         *txq->cq_db = htonl(cq_ci);
 334 }
 335
 336 /**
 337  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 338  * the cloned mbuf is allocated is returned instead.
 339  *
 340  * @param buf
 341  *   Pointer to mbuf.
 342  *
 343  * @return
 344  *   Memory pool where data is located for given mbuf.
 345  */
 346 static struct rte_mempool *
 347 txq_mb2mp(struct rte_mbuf *buf)
 348 {
 349         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 350                 return rte_mbuf_from_indirect(buf)->pool;
 351         return buf->pool;
 352 }
 353
 354 /**
 355  * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
 356  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 357  * remove an entry first.
 358  *
 359  * @param txq
 360  *   Pointer to TX queue structure.
 361  * @param[in] mp
 362  *   Memory Pool for which a Memory Region lkey must be returned.
 363  *
 364  * @return
 365  *   mr->lkey on success, (uint32_t)-1 on failure.
 366  */
 367 static inline uint32_t
 368 txq_mb2mr(struct txq *txq, struct rte_mbuf *mb)
 369 {
 370         uint16_t i = txq->mr_cache_idx;
 371         uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
 372
 373         assert(i < RTE_DIM(txq->mp2mr));
 374         if (likely(txq->mp2mr[i].start <= addr && txq->mp2mr[i].end >= addr))
 375                 return txq->mp2mr[i].lkey;
 376         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 377                 if (unlikely(txq->mp2mr[i].mr == NULL)) {
 378                         /* Unknown MP, add a new MR for it. */
 379                         break;
 380                 }
 381                 if (txq->mp2mr[i].start <= addr &&
 382                     txq->mp2mr[i].end >= addr) {
 383                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 384                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 385                                txq->mp2mr[i].lkey);
 386                         txq->mr_cache_idx = i;
 387                         return txq->mp2mr[i].lkey;
 388                 }
 389         }
 390         txq->mr_cache_idx = 0;
 391         return txq_mp2mr_reg(txq, txq_mb2mp(mb), i);
 392 }
 393
 394 /**
 395  * Ring TX queue doorbell.
 396  *
 397  * @param txq
 398  *   Pointer to TX queue structure.
 399  * @param wqe
 400  *   Pointer to the last WQE posted in the NIC.
 401  */
 402 static inline void
 403 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 404 {
 405         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 406         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 407
 408         rte_wmb();
 409         *txq->qp_db = htonl(txq->wqe_ci);
 410         /* Ensure ordering between DB record and BF copy. */
 411         rte_wmb();
 412         *dst = *src;
 413 }
 414
 415 /**
 416  * DPDK callback to check the status of a tx descriptor.
 417  *
 418  * @param tx_queue
 419  *   The tx queue.
 420  * @param[in] offset
 421  *   The index of the descriptor in the ring.
 422  *
 423  * @return
 424  *   The status of the tx descriptor.
 425  */
 426 int
 427 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 428 {
 429         struct txq *txq = tx_queue;
 430         uint16_t used;
 431
 432         txq_complete(txq);
 433         used = txq->elts_head - txq->elts_tail;
 434         if (offset < used)
 435                 return RTE_ETH_TX_DESC_FULL;
 436         return RTE_ETH_TX_DESC_DONE;
 437 }
 438
 439 /**
 440  * DPDK callback to check the status of a rx descriptor.
 441  *
 442  * @param rx_queue
 443  *   The rx queue.
 444  * @param[in] offset
 445  *   The index of the descriptor in the ring.
 446  *
 447  * @return
 448  *   The status of the tx descriptor.
 449  */
 450 int
 451 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 452 {
 453         struct rxq *rxq = rx_queue;
 454         struct rxq_zip *zip = &rxq->zip;
 455         volatile struct mlx5_cqe *cqe;
 456         const unsigned int cqe_n = (1 << rxq->cqe_n);
 457         const unsigned int cqe_cnt = cqe_n - 1;
 458         unsigned int cq_ci;
 459         unsigned int used;
 460
 461         /* if we are processing a compressed cqe */
 462         if (zip->ai) {
 463                 used = zip->cqe_cnt - zip->ca;
 464                 cq_ci = zip->cq_ci;
 465         } else {
 466                 used = 0;
 467                 cq_ci = rxq->cq_ci;
 468         }
 469         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 470         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 471                 int8_t op_own;
 472                 unsigned int n;
 473
 474                 op_own = cqe->op_own;
 475                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 476                         n = ntohl(cqe->byte_cnt);
 477                 else
 478                         n = 1;
 479                 cq_ci += n;
 480                 used += n;
 481                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 482         }
 483         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 484         if (offset < used)
 485                 return RTE_ETH_RX_DESC_DONE;
 486         return RTE_ETH_RX_DESC_AVAIL;
 487 }
 488
 489 /**
 490  * DPDK callback for TX.
 491  *
 492  * @param dpdk_txq
 493  *   Generic pointer to TX queue structure.
 494  * @param[in] pkts
 495  *   Packets to transmit.
 496  * @param pkts_n
 497  *   Number of packets in array.
 498  *
 499  * @return
 500  *   Number of packets successfully transmitted (<= pkts_n).
 501  */
 502 uint16_t
 503 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 504 {
 505         struct txq *txq = (struct txq *)dpdk_txq;
 506         uint16_t elts_head = txq->elts_head;
 507         const uint16_t elts_n = 1 << txq->elts_n;
 508         const uint16_t elts_m = elts_n - 1;
 509         unsigned int i = 0;
 510         unsigned int j = 0;
 511         unsigned int k = 0;
 512         uint16_t max_elts;
 513         unsigned int max_inline = txq->max_inline;
 514         const unsigned int inline_en = !!max_inline && txq->inline_en;
 515         uint16_t max_wqe;
 516         unsigned int comp;
 517         volatile struct mlx5_wqe_v *wqe = NULL;
 518         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 519         unsigned int segs_n = 0;
 520         struct rte_mbuf *buf = NULL;
 521         uint8_t *raw;
 522
 523         if (unlikely(!pkts_n))
 524                 return 0;
 525         /* Prefetch first packet cacheline. */
 526         rte_prefetch0(*pkts);
 527         /* Start processing. */
 528         txq_complete(txq);
 529         max_elts = (elts_n - (elts_head - txq->elts_tail));
 530         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 531         if (unlikely(!max_wqe))
 532                 return 0;
 533         do {
 534                 volatile rte_v128u32_t *dseg = NULL;
 535                 uint32_t length;
 536                 unsigned int ds = 0;
 537                 unsigned int sg = 0; /* counter of additional segs attached. */
 538                 uintptr_t addr;
 539                 uint64_t naddr;
 540                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 541                 uint16_t tso_header_sz = 0;
 542                 uint16_t ehdr;
 543                 uint8_t cs_flags = 0;
 544                 uint64_t tso = 0;
 545                 uint16_t tso_segsz = 0;
 546 #ifdef MLX5_PMD_SOFT_COUNTERS
 547                 uint32_t total_length = 0;
 548 #endif
 549
 550                 /* first_seg */
 551                 buf = *pkts;
 552                 segs_n = buf->nb_segs;
 553                 /*
 554                  * Make sure there is enough room to store this packet and
 555                  * that one ring entry remains unused.
 556                  */
 557                 assert(segs_n);
 558                 if (max_elts < segs_n)
 559                         break;
 560                 max_elts -= segs_n;
 561                 --segs_n;
 562                 if (unlikely(--max_wqe == 0))
 563                         break;
 564                 wqe = (volatile struct mlx5_wqe_v *)
 565                         tx_mlx5_wqe(txq, txq->wqe_ci);
 566                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 567                 if (pkts_n - i > 1)
 568                         rte_prefetch0(*(pkts + 1));
 569                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 570                 length = DATA_LEN(buf);
 571                 ehdr = (((uint8_t *)addr)[1] << 8) |
 572                        ((uint8_t *)addr)[0];
 573 #ifdef MLX5_PMD_SOFT_COUNTERS
 574                 total_length = length;
 575 #endif
 576                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 577                         break;
 578                 /* Update element. */
 579                 (*txq->elts)[elts_head & elts_m] = buf;
 580                 /* Prefetch next buffer data. */
 581                 if (pkts_n - i > 1)
 582                         rte_prefetch0(
 583                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 584                 /* Should we enable HW CKSUM offload */
 585                 if (buf->ol_flags &
 586                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 587                         const uint64_t is_tunneled = buf->ol_flags &
 588                                                      (PKT_TX_TUNNEL_GRE |
 589                                                       PKT_TX_TUNNEL_VXLAN);
 590
 591                         if (is_tunneled && txq->tunnel_en) {
 592                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 593                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 594                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 595                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 596                         } else {
 597                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 598                                            MLX5_ETH_WQE_L4_CSUM;
 599                         }
 600                 }
 601                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 602                 /* Replace the Ethernet type by the VLAN if necessary. */
 603                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 604                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 605                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 606
 607                         addr += 2;
 608                         length -= 2;
 609                         /* Copy Destination and source mac address. */
 610                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 611                         /* Copy VLAN. */
 612                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 613                         /* Copy missing two bytes to end the DSeg. */
 614                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 615                                ((uint8_t *)addr) + len, 2);
 616                         addr += len + 2;
 617                         length -= (len + 2);
 618                 } else {
 619                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 620                                MLX5_WQE_DWORD_SIZE);
 621                         length -= pkt_inline_sz;
 622                         addr += pkt_inline_sz;
 623                 }
 624                 if (txq->tso_en) {
 625                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 626                         if (tso) {
 627                                 uintptr_t end = (uintptr_t)
 628                                                 (((uintptr_t)txq->wqes) +
 629                                                 (1 << txq->wqe_n) *
 630                                                 MLX5_WQE_SIZE);
 631                                 unsigned int copy_b;
 632                                 uint8_t vlan_sz = (buf->ol_flags &
 633                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 634                                 const uint64_t is_tunneled =
 635                                                         buf->ol_flags &
 636                                                         (PKT_TX_TUNNEL_GRE |
 637                                                          PKT_TX_TUNNEL_VXLAN);
 638
 639                                 tso_header_sz = buf->l2_len + vlan_sz +
 640                                                 buf->l3_len + buf->l4_len;
 641                                 tso_segsz = buf->tso_segsz;
 642
 643                                 if (is_tunneled && txq->tunnel_en) {
 644                                         tso_header_sz += buf->outer_l2_len +
 645                                                          buf->outer_l3_len;
 646                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 647                                 } else {
 648                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 649                                 }
 650                                 if (unlikely(tso_header_sz >
 651                                              MLX5_MAX_TSO_HEADER))
 652                                         break;
 653                                 copy_b = tso_header_sz - pkt_inline_sz;
 654                                 /* First seg must contain all headers. */
 655                                 assert(copy_b <= length);
 656                                 raw += MLX5_WQE_DWORD_SIZE;
 657                                 if (copy_b &&
 658                                    ((end - (uintptr_t)raw) > copy_b)) {
 659                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 660                                                       1 + 3) / 4;
 661
 662                                         if (unlikely(max_wqe < n))
 663                                                 break;
 664                                         max_wqe -= n;
 665                                         rte_memcpy((void *)raw,
 666                                                    (void *)addr, copy_b);
 667                                         addr += copy_b;
 668                                         length -= copy_b;
 669                                         pkt_inline_sz += copy_b;
 670                                         /*
 671                                          * Another DWORD will be added
 672                                          * in the inline part.
 673                                          */
 674                                         raw += MLX5_WQE_DS(copy_b) *
 675                                                MLX5_WQE_DWORD_SIZE -
 676                                                MLX5_WQE_DWORD_SIZE;
 677                                 } else {
 678                                         /* NOP WQE. */
 679                                         wqe->ctrl = (rte_v128u32_t){
 680                                                      htonl(txq->wqe_ci << 8),
 681                                                      htonl(txq->qp_num_8s | 1),
 682                                                      0,
 683                                                      0,
 684                                         };
 685                                         ds = 1;
 686                                         total_length = 0;
 687                                         k++;
 688                                         goto next_wqe;
 689                                 }
 690                         }
 691                 }
 692                 /* Inline if enough room. */
 693                 if (inline_en || tso) {
 694                         uintptr_t end = (uintptr_t)
 695                                 (((uintptr_t)txq->wqes) +
 696                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 697                         unsigned int inline_room = max_inline *
 698                                                    RTE_CACHE_LINE_SIZE -
 699                                                    (pkt_inline_sz - 2);
 700                         uintptr_t addr_end = (addr + inline_room) &
 701                                              ~(RTE_CACHE_LINE_SIZE - 1);
 702                         unsigned int copy_b = (addr_end > addr) ?
 703                                 RTE_MIN((addr_end - addr), length) :
 704                                 0;
 705
 706                         raw += MLX5_WQE_DWORD_SIZE;
 707                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 708                                 /*
 709                                  * One Dseg remains in the current WQE.  To
 710                                  * keep the computation positive, it is
 711                                  * removed after the bytes to Dseg conversion.
 712                                  */
 713                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 714
 715                                 if (unlikely(max_wqe < n))
 716                                         break;
 717                                 max_wqe -= n;
 718                                 if (tso) {
 719                                         uint32_t inl =
 720                                                 htonl(copy_b | MLX5_INLINE_SEG);
 721
 722                                         pkt_inline_sz =
 723                                                 MLX5_WQE_DS(tso_header_sz) *
 724                                                 MLX5_WQE_DWORD_SIZE;
 725                                         rte_memcpy((void *)raw,
 726                                                    (void *)&inl, sizeof(inl));
 727                                         raw += sizeof(inl);
 728                                         pkt_inline_sz += sizeof(inl);
 729                                 }
 730                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 731                                 addr += copy_b;
 732                                 length -= copy_b;
 733                                 pkt_inline_sz += copy_b;
 734                         }
 735                         /*
 736                          * 2 DWORDs consumed by the WQE header + ETH segment +
 737                          * the size of the inline part of the packet.
 738                          */
 739                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 740                         if (length > 0) {
 741                                 if (ds % (MLX5_WQE_SIZE /
 742                                           MLX5_WQE_DWORD_SIZE) == 0) {
 743                                         if (unlikely(--max_wqe == 0))
 744                                                 break;
 745                                         dseg = (volatile rte_v128u32_t *)
 746                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 747                                                            ds / 4);
 748                                 } else {
 749                                         dseg = (volatile rte_v128u32_t *)
 750                                                 ((uintptr_t)wqe +
 751                                                  (ds * MLX5_WQE_DWORD_SIZE));
 752                                 }
 753                                 goto use_dseg;
 754                         } else if (!segs_n) {
 755                                 goto next_pkt;
 756                         } else {
 757                                 /* dseg will be advance as part of next_seg */
 758                                 dseg = (volatile rte_v128u32_t *)
 759                                         ((uintptr_t)wqe +
 760                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 761                                 goto next_seg;
 762                         }
 763                 } else {
 764                         /*
 765                          * No inline has been done in the packet, only the
 766                          * Ethernet Header as been stored.
 767                          */
 768                         dseg = (volatile rte_v128u32_t *)
 769                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 770                         ds = 3;
 771 use_dseg:
 772                         /* Add the remaining packet as a simple ds. */
 773                         naddr = htonll(addr);
 774                         *dseg = (rte_v128u32_t){
 775                                 htonl(length),
 776                                 txq_mb2mr(txq, buf),
 777                                 naddr,
 778                                 naddr >> 32,
 779                         };
 780                         ++ds;
 781                         if (!segs_n)
 782                                 goto next_pkt;
 783                 }
 784 next_seg:
 785                 assert(buf);
 786                 assert(ds);
 787                 assert(wqe);
 788                 /*
 789                  * Spill on next WQE when the current one does not have
 790                  * enough room left. Size of WQE must a be a multiple
 791                  * of data segment size.
 792                  */
 793                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 794                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 795                         if (unlikely(--max_wqe == 0))
 796                                 break;
 797                         dseg = (volatile rte_v128u32_t *)
 798                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 799                         rte_prefetch0(tx_mlx5_wqe(txq,
 800                                                   txq->wqe_ci + ds / 4 + 1));
 801                 } else {
 802                         ++dseg;
 803                 }
 804                 ++ds;
 805                 buf = buf->next;
 806                 assert(buf);
 807                 length = DATA_LEN(buf);
 808 #ifdef MLX5_PMD_SOFT_COUNTERS
 809                 total_length += length;
 810 #endif
 811                 /* Store segment information. */
 812                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 813                 *dseg = (rte_v128u32_t){
 814                         htonl(length),
 815                         txq_mb2mr(txq, buf),
 816                         naddr,
 817                         naddr >> 32,
 818                 };
 819                 (*txq->elts)[++elts_head & elts_m] = buf;
 820                 ++sg;
 821                 /* Advance counter only if all segs are successfully posted. */
 822                 if (sg < segs_n)
 823                         goto next_seg;
 824                 else
 825                         j += sg;
 826 next_pkt:
 827                 ++elts_head;
 828                 ++pkts;
 829                 ++i;
 830                 /* Initialize known and common part of the WQE structure. */
 831                 if (tso) {
 832                         wqe->ctrl = (rte_v128u32_t){
 833                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 834                                 htonl(txq->qp_num_8s | ds),
 835                                 0,
 836                                 0,
 837                         };
 838                         wqe->eseg = (rte_v128u32_t){
 839                                 0,
 840                                 cs_flags | (htons(tso_segsz) << 16),
 841                                 0,
 842                                 (ehdr << 16) | htons(tso_header_sz),
 843                         };
 844                 } else {
 845                         wqe->ctrl = (rte_v128u32_t){
 846                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 847                                 htonl(txq->qp_num_8s | ds),
 848                                 0,
 849                                 0,
 850                         };
 851                         wqe->eseg = (rte_v128u32_t){
 852                                 0,
 853                                 cs_flags,
 854                                 0,
 855                                 (ehdr << 16) | htons(pkt_inline_sz),
 856                         };
 857                 }
 858 next_wqe:
 859                 txq->wqe_ci += (ds + 3) / 4;
 860                 /* Save the last successful WQE for completion request */
 861                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 862 #ifdef MLX5_PMD_SOFT_COUNTERS
 863                 /* Increment sent bytes counter. */
 864                 txq->stats.obytes += total_length;
 865 #endif
 866         } while (i < pkts_n);
 867         /* Take a shortcut if nothing must be sent. */
 868         if (unlikely((i + k) == 0))
 869                 return 0;
 870         txq->elts_head += (i + j);
 871         /* Check whether completion threshold has been reached. */
 872         comp = txq->elts_comp + i + j + k;
 873         if (comp >= MLX5_TX_COMP_THRESH) {
 874                 /* Request completion on last WQE. */
 875                 last_wqe->ctrl2 = htonl(8);
 876                 /* Save elts_head in unused "immediate" field of WQE. */
 877                 last_wqe->ctrl3 = txq->elts_head;
 878                 txq->elts_comp = 0;
 879         } else {
 880                 txq->elts_comp = comp;
 881         }
 882 #ifdef MLX5_PMD_SOFT_COUNTERS
 883         /* Increment sent packets counter. */
 884         txq->stats.opackets += i;
 885 #endif
 886         /* Ring QP doorbell. */
 887         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 888         return i;
 889 }
 890
 891 /**
 892  * Open a MPW session.
 893  *
 894  * @param txq
 895  *   Pointer to TX queue structure.
 896  * @param mpw
 897  *   Pointer to MPW session structure.
 898  * @param length
 899  *   Packet length.
 900  */
 901 static inline void
 902 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 903 {
 904         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 905         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 906                 (volatile struct mlx5_wqe_data_seg (*)[])
 907                 tx_mlx5_wqe(txq, idx + 1);
 908
 909         mpw->state = MLX5_MPW_STATE_OPENED;
 910         mpw->pkts_n = 0;
 911         mpw->len = length;
 912         mpw->total_len = 0;
 913         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 914         mpw->wqe->eseg.mss = htons(length);
 915         mpw->wqe->eseg.inline_hdr_sz = 0;
 916         mpw->wqe->eseg.rsvd0 = 0;
 917         mpw->wqe->eseg.rsvd1 = 0;
 918         mpw->wqe->eseg.rsvd2 = 0;
 919         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 920                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 921         mpw->wqe->ctrl[2] = 0;
 922         mpw->wqe->ctrl[3] = 0;
 923         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 924                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 925         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 926                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 927         mpw->data.dseg[2] = &(*dseg)[0];
 928         mpw->data.dseg[3] = &(*dseg)[1];
 929         mpw->data.dseg[4] = &(*dseg)[2];
 930 }
 931
 932 /**
 933  * Close a MPW session.
 934  *
 935  * @param txq
 936  *   Pointer to TX queue structure.
 937  * @param mpw
 938  *   Pointer to MPW session structure.
 939  */
 940 static inline void
 941 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 942 {
 943         unsigned int num = mpw->pkts_n;
 944
 945         /*
 946          * Store size in multiple of 16 bytes. Control and Ethernet segments
 947          * count as 2.
 948          */
 949         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 950         mpw->state = MLX5_MPW_STATE_CLOSED;
 951         if (num < 3)
 952                 ++txq->wqe_ci;
 953         else
 954                 txq->wqe_ci += 2;
 955         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 956         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 957 }
 958
 959 /**
 960  * DPDK callback for TX with MPW support.
 961  *
 962  * @param dpdk_txq
 963  *   Generic pointer to TX queue structure.
 964  * @param[in] pkts
 965  *   Packets to transmit.
 966  * @param pkts_n
 967  *   Number of packets in array.
 968  *
 969  * @return
 970  *   Number of packets successfully transmitted (<= pkts_n).
 971  */
 972 uint16_t
 973 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 974 {
 975         struct txq *txq = (struct txq *)dpdk_txq;
 976         uint16_t elts_head = txq->elts_head;
 977         const uint16_t elts_n = 1 << txq->elts_n;
 978         const uint16_t elts_m = elts_n - 1;
 979         unsigned int i = 0;
 980         unsigned int j = 0;
 981         uint16_t max_elts;
 982         uint16_t max_wqe;
 983         unsigned int comp;
 984         struct mlx5_mpw mpw = {
 985                 .state = MLX5_MPW_STATE_CLOSED,
 986         };
 987
 988         if (unlikely(!pkts_n))
 989                 return 0;
 990         /* Prefetch first packet cacheline. */
 991         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 992         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 993         /* Start processing. */
 994         txq_complete(txq);
 995         max_elts = (elts_n - (elts_head - txq->elts_tail));
 996         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 997         if (unlikely(!max_wqe))
 998                 return 0;
 999         do {
1000                 struct rte_mbuf *buf = *(pkts++);
1001                 uint32_t length;
1002                 unsigned int segs_n = buf->nb_segs;
1003                 uint32_t cs_flags = 0;
1004
1005                 /*
1006                  * Make sure there is enough room to store this packet and
1007                  * that one ring entry remains unused.
1008                  */
1009                 assert(segs_n);
1010                 if (max_elts < segs_n)
1011                         break;
1012                 /* Do not bother with large packets MPW cannot handle. */
1013                 if (segs_n > MLX5_MPW_DSEG_MAX)
1014                         break;
1015                 max_elts -= segs_n;
1016                 --pkts_n;
1017                 /* Should we enable HW CKSUM offload */
1018                 if (buf->ol_flags &
1019                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1020                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1021                 /* Retrieve packet information. */
1022                 length = PKT_LEN(buf);
1023                 assert(length);
1024                 /* Start new session if packet differs. */
1025                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1026                     ((mpw.len != length) ||
1027                      (segs_n != 1) ||
1028                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1029                         mlx5_mpw_close(txq, &mpw);
1030                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1031                         /*
1032                          * Multi-Packet WQE consumes at most two WQE.
1033                          * mlx5_mpw_new() expects to be able to use such
1034                          * resources.
1035                          */
1036                         if (unlikely(max_wqe < 2))
1037                                 break;
1038                         max_wqe -= 2;
1039                         mlx5_mpw_new(txq, &mpw, length);
1040                         mpw.wqe->eseg.cs_flags = cs_flags;
1041                 }
1042                 /* Multi-segment packets must be alone in their MPW. */
1043                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1044 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1045                 length = 0;
1046 #endif
1047                 do {
1048                         volatile struct mlx5_wqe_data_seg *dseg;
1049                         uintptr_t addr;
1050
1051                         assert(buf);
1052                         (*txq->elts)[elts_head++ & elts_m] = buf;
1053                         dseg = mpw.data.dseg[mpw.pkts_n];
1054                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1055                         *dseg = (struct mlx5_wqe_data_seg){
1056                                 .byte_count = htonl(DATA_LEN(buf)),
1057                                 .lkey = txq_mb2mr(txq, buf),
1058                                 .addr = htonll(addr),
1059                         };
1060 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1061                         length += DATA_LEN(buf);
1062 #endif
1063                         buf = buf->next;
1064                         ++mpw.pkts_n;
1065                         ++j;
1066                 } while (--segs_n);
1067                 assert(length == mpw.len);
1068                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1069                         mlx5_mpw_close(txq, &mpw);
1070 #ifdef MLX5_PMD_SOFT_COUNTERS
1071                 /* Increment sent bytes counter. */
1072                 txq->stats.obytes += length;
1073 #endif
1074                 ++i;
1075         } while (pkts_n);
1076         /* Take a shortcut if nothing must be sent. */
1077         if (unlikely(i == 0))
1078                 return 0;
1079         /* Check whether completion threshold has been reached. */
1080         /* "j" includes both packets and segments. */
1081         comp = txq->elts_comp + j;
1082         if (comp >= MLX5_TX_COMP_THRESH) {
1083                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1084
1085                 /* Request completion on last WQE. */
1086                 wqe->ctrl[2] = htonl(8);
1087                 /* Save elts_head in unused "immediate" field of WQE. */
1088                 wqe->ctrl[3] = elts_head;
1089                 txq->elts_comp = 0;
1090         } else {
1091                 txq->elts_comp = comp;
1092         }
1093 #ifdef MLX5_PMD_SOFT_COUNTERS
1094         /* Increment sent packets counter. */
1095         txq->stats.opackets += i;
1096 #endif
1097         /* Ring QP doorbell. */
1098         if (mpw.state == MLX5_MPW_STATE_OPENED)
1099                 mlx5_mpw_close(txq, &mpw);
1100         mlx5_tx_dbrec(txq, mpw.wqe);
1101         txq->elts_head = elts_head;
1102         return i;
1103 }
1104
1105 /**
1106  * Open a MPW inline session.
1107  *
1108  * @param txq
1109  *   Pointer to TX queue structure.
1110  * @param mpw
1111  *   Pointer to MPW session structure.
1112  * @param length
1113  *   Packet length.
1114  */
1115 static inline void
1116 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1117 {
1118         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1119         struct mlx5_wqe_inl_small *inl;
1120
1121         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1122         mpw->pkts_n = 0;
1123         mpw->len = length;
1124         mpw->total_len = 0;
1125         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1126         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1127                                   (txq->wqe_ci << 8) |
1128                                   MLX5_OPCODE_TSO);
1129         mpw->wqe->ctrl[2] = 0;
1130         mpw->wqe->ctrl[3] = 0;
1131         mpw->wqe->eseg.mss = htons(length);
1132         mpw->wqe->eseg.inline_hdr_sz = 0;
1133         mpw->wqe->eseg.cs_flags = 0;
1134         mpw->wqe->eseg.rsvd0 = 0;
1135         mpw->wqe->eseg.rsvd1 = 0;
1136         mpw->wqe->eseg.rsvd2 = 0;
1137         inl = (struct mlx5_wqe_inl_small *)
1138                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1139         mpw->data.raw = (uint8_t *)&inl->raw;
1140 }
1141
1142 /**
1143  * Close a MPW inline session.
1144  *
1145  * @param txq
1146  *   Pointer to TX queue structure.
1147  * @param mpw
1148  *   Pointer to MPW session structure.
1149  */
1150 static inline void
1151 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1152 {
1153         unsigned int size;
1154         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1155                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1156
1157         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1158         /*
1159          * Store size in multiple of 16 bytes. Control and Ethernet segments
1160          * count as 2.
1161          */
1162         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1163         mpw->state = MLX5_MPW_STATE_CLOSED;
1164         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1165         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1166 }
1167
1168 /**
1169  * DPDK callback for TX with MPW inline support.
1170  *
1171  * @param dpdk_txq
1172  *   Generic pointer to TX queue structure.
1173  * @param[in] pkts
1174  *   Packets to transmit.
1175  * @param pkts_n
1176  *   Number of packets in array.
1177  *
1178  * @return
1179  *   Number of packets successfully transmitted (<= pkts_n).
1180  */
1181 uint16_t
1182 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1183                          uint16_t pkts_n)
1184 {
1185         struct txq *txq = (struct txq *)dpdk_txq;
1186         uint16_t elts_head = txq->elts_head;
1187         const uint16_t elts_n = 1 << txq->elts_n;
1188         const uint16_t elts_m = elts_n - 1;
1189         unsigned int i = 0;
1190         unsigned int j = 0;
1191         uint16_t max_elts;
1192         uint16_t max_wqe;
1193         unsigned int comp;
1194         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1195         struct mlx5_mpw mpw = {
1196                 .state = MLX5_MPW_STATE_CLOSED,
1197         };
1198         /*
1199          * Compute the maximum number of WQE which can be consumed by inline
1200          * code.
1201          * - 2 DSEG for:
1202          *   - 1 control segment,
1203          *   - 1 Ethernet segment,
1204          * - N Dseg from the inline request.
1205          */
1206         const unsigned int wqe_inl_n =
1207                 ((2 * MLX5_WQE_DWORD_SIZE +
1208                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1209                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1210
1211         if (unlikely(!pkts_n))
1212                 return 0;
1213         /* Prefetch first packet cacheline. */
1214         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1215         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1216         /* Start processing. */
1217         txq_complete(txq);
1218         max_elts = (elts_n - (elts_head - txq->elts_tail));
1219         do {
1220                 struct rte_mbuf *buf = *(pkts++);
1221                 uintptr_t addr;
1222                 uint32_t length;
1223                 unsigned int segs_n = buf->nb_segs;
1224                 uint32_t cs_flags = 0;
1225
1226                 /*
1227                  * Make sure there is enough room to store this packet and
1228                  * that one ring entry remains unused.
1229                  */
1230                 assert(segs_n);
1231                 if (max_elts < segs_n)
1232                         break;
1233                 /* Do not bother with large packets MPW cannot handle. */
1234                 if (segs_n > MLX5_MPW_DSEG_MAX)
1235                         break;
1236                 max_elts -= segs_n;
1237                 --pkts_n;
1238                 /*
1239                  * Compute max_wqe in case less WQE were consumed in previous
1240                  * iteration.
1241                  */
1242                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1243                 /* Should we enable HW CKSUM offload */
1244                 if (buf->ol_flags &
1245                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1246                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1247                 /* Retrieve packet information. */
1248                 length = PKT_LEN(buf);
1249                 /* Start new session if packet differs. */
1250                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1251                         if ((mpw.len != length) ||
1252                             (segs_n != 1) ||
1253                             (mpw.wqe->eseg.cs_flags != cs_flags))
1254                                 mlx5_mpw_close(txq, &mpw);
1255                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1256                         if ((mpw.len != length) ||
1257                             (segs_n != 1) ||
1258                             (length > inline_room) ||
1259                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1260                                 mlx5_mpw_inline_close(txq, &mpw);
1261                                 inline_room =
1262                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1263                         }
1264                 }
1265                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1266                         if ((segs_n != 1) ||
1267                             (length > inline_room)) {
1268                                 /*
1269                                  * Multi-Packet WQE consumes at most two WQE.
1270                                  * mlx5_mpw_new() expects to be able to use
1271                                  * such resources.
1272                                  */
1273                                 if (unlikely(max_wqe < 2))
1274                                         break;
1275                                 max_wqe -= 2;
1276                                 mlx5_mpw_new(txq, &mpw, length);
1277                                 mpw.wqe->eseg.cs_flags = cs_flags;
1278                         } else {
1279                                 if (unlikely(max_wqe < wqe_inl_n))
1280                                         break;
1281                                 max_wqe -= wqe_inl_n;
1282                                 mlx5_mpw_inline_new(txq, &mpw, length);
1283                                 mpw.wqe->eseg.cs_flags = cs_flags;
1284                         }
1285                 }
1286                 /* Multi-segment packets must be alone in their MPW. */
1287                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1288                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1289                         assert(inline_room ==
1290                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1291 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1292                         length = 0;
1293 #endif
1294                         do {
1295                                 volatile struct mlx5_wqe_data_seg *dseg;
1296
1297                                 assert(buf);
1298                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1299                                 dseg = mpw.data.dseg[mpw.pkts_n];
1300                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1301                                 *dseg = (struct mlx5_wqe_data_seg){
1302                                         .byte_count = htonl(DATA_LEN(buf)),
1303                                         .lkey = txq_mb2mr(txq, buf),
1304                                         .addr = htonll(addr),
1305                                 };
1306 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1307                                 length += DATA_LEN(buf);
1308 #endif
1309                                 buf = buf->next;
1310                                 ++mpw.pkts_n;
1311                                 ++j;
1312                         } while (--segs_n);
1313                         assert(length == mpw.len);
1314                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1315                                 mlx5_mpw_close(txq, &mpw);
1316                 } else {
1317                         unsigned int max;
1318
1319                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1320                         assert(length <= inline_room);
1321                         assert(length == DATA_LEN(buf));
1322                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1323                         (*txq->elts)[elts_head++ & elts_m] = buf;
1324                         /* Maximum number of bytes before wrapping. */
1325                         max = ((((uintptr_t)(txq->wqes)) +
1326                                 (1 << txq->wqe_n) *
1327                                 MLX5_WQE_SIZE) -
1328                                (uintptr_t)mpw.data.raw);
1329                         if (length > max) {
1330                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1331                                            (void *)addr,
1332                                            max);
1333                                 mpw.data.raw = (volatile void *)txq->wqes;
1334                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1335                                            (void *)(addr + max),
1336                                            length - max);
1337                                 mpw.data.raw += length - max;
1338                         } else {
1339                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1340                                            (void *)addr,
1341                                            length);
1342
1343                                 if (length == max)
1344                                         mpw.data.raw =
1345                                                 (volatile void *)txq->wqes;
1346                                 else
1347                                         mpw.data.raw += length;
1348                         }
1349                         ++mpw.pkts_n;
1350                         mpw.total_len += length;
1351                         ++j;
1352                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1353                                 mlx5_mpw_inline_close(txq, &mpw);
1354                                 inline_room =
1355                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1356                         } else {
1357                                 inline_room -= length;
1358                         }
1359                 }
1360 #ifdef MLX5_PMD_SOFT_COUNTERS
1361                 /* Increment sent bytes counter. */
1362                 txq->stats.obytes += length;
1363 #endif
1364                 ++i;
1365         } while (pkts_n);
1366         /* Take a shortcut if nothing must be sent. */
1367         if (unlikely(i == 0))
1368                 return 0;
1369         /* Check whether completion threshold has been reached. */
1370         /* "j" includes both packets and segments. */
1371         comp = txq->elts_comp + j;
1372         if (comp >= MLX5_TX_COMP_THRESH) {
1373                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1374
1375                 /* Request completion on last WQE. */
1376                 wqe->ctrl[2] = htonl(8);
1377                 /* Save elts_head in unused "immediate" field of WQE. */
1378                 wqe->ctrl[3] = elts_head;
1379                 txq->elts_comp = 0;
1380         } else {
1381                 txq->elts_comp = comp;
1382         }
1383 #ifdef MLX5_PMD_SOFT_COUNTERS
1384         /* Increment sent packets counter. */
1385         txq->stats.opackets += i;
1386 #endif
1387         /* Ring QP doorbell. */
1388         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1389                 mlx5_mpw_inline_close(txq, &mpw);
1390         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1391                 mlx5_mpw_close(txq, &mpw);
1392         mlx5_tx_dbrec(txq, mpw.wqe);
1393         txq->elts_head = elts_head;
1394         return i;
1395 }
1396
1397 /**
1398  * Open an Enhanced MPW session.
1399  *
1400  * @param txq
1401  *   Pointer to TX queue structure.
1402  * @param mpw
1403  *   Pointer to MPW session structure.
1404  * @param length
1405  *   Packet length.
1406  */
1407 static inline void
1408 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1409 {
1410         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1411
1412         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1413         mpw->pkts_n = 0;
1414         mpw->total_len = sizeof(struct mlx5_wqe);
1415         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1416         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1417                                   (txq->wqe_ci << 8) |
1418                                   MLX5_OPCODE_ENHANCED_MPSW);
1419         mpw->wqe->ctrl[2] = 0;
1420         mpw->wqe->ctrl[3] = 0;
1421         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1422         if (unlikely(padding)) {
1423                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1424
1425                 /* Pad the first 2 DWORDs with zero-length inline header. */
1426                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1427                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1428                         htonl(MLX5_INLINE_SEG);
1429                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1430                 /* Start from the next WQEBB. */
1431                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1432         } else {
1433                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1434         }
1435 }
1436
1437 /**
1438  * Close an Enhanced MPW session.
1439  *
1440  * @param txq
1441  *   Pointer to TX queue structure.
1442  * @param mpw
1443  *   Pointer to MPW session structure.
1444  *
1445  * @return
1446  *   Number of consumed WQEs.
1447  */
1448 static inline uint16_t
1449 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1450 {
1451         uint16_t ret;
1452
1453         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1454          * count as 2.
1455          */
1456         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1457         mpw->state = MLX5_MPW_STATE_CLOSED;
1458         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1459         txq->wqe_ci += ret;
1460         return ret;
1461 }
1462
1463 /**
1464  * DPDK callback for TX with Enhanced MPW support.
1465  *
1466  * @param dpdk_txq
1467  *   Generic pointer to TX queue structure.
1468  * @param[in] pkts
1469  *   Packets to transmit.
1470  * @param pkts_n
1471  *   Number of packets in array.
1472  *
1473  * @return
1474  *   Number of packets successfully transmitted (<= pkts_n).
1475  */
1476 uint16_t
1477 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1478 {
1479         struct txq *txq = (struct txq *)dpdk_txq;
1480         uint16_t elts_head = txq->elts_head;
1481         const uint16_t elts_n = 1 << txq->elts_n;
1482         const uint16_t elts_m = elts_n - 1;
1483         unsigned int i = 0;
1484         unsigned int j = 0;
1485         uint16_t max_elts;
1486         uint16_t max_wqe;
1487         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1488         unsigned int mpw_room = 0;
1489         unsigned int inl_pad = 0;
1490         uint32_t inl_hdr;
1491         struct mlx5_mpw mpw = {
1492                 .state = MLX5_MPW_STATE_CLOSED,
1493         };
1494
1495         if (unlikely(!pkts_n))
1496                 return 0;
1497         /* Start processing. */
1498         txq_complete(txq);
1499         max_elts = (elts_n - (elts_head - txq->elts_tail));
1500         /* A CQE slot must always be available. */
1501         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1502         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1503         if (unlikely(!max_wqe))
1504                 return 0;
1505         do {
1506                 struct rte_mbuf *buf = *(pkts++);
1507                 uintptr_t addr;
1508                 uint64_t naddr;
1509                 unsigned int n;
1510                 unsigned int do_inline = 0; /* Whether inline is possible. */
1511                 uint32_t length;
1512                 unsigned int segs_n = buf->nb_segs;
1513                 uint32_t cs_flags = 0;
1514
1515                 /*
1516                  * Make sure there is enough room to store this packet and
1517                  * that one ring entry remains unused.
1518                  */
1519                 assert(segs_n);
1520                 if (max_elts - j < segs_n)
1521                         break;
1522                 /* Do not bother with large packets MPW cannot handle. */
1523                 if (segs_n > MLX5_MPW_DSEG_MAX)
1524                         break;
1525                 /* Should we enable HW CKSUM offload. */
1526                 if (buf->ol_flags &
1527                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1528                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1529                 /* Retrieve packet information. */
1530                 length = PKT_LEN(buf);
1531                 /* Start new session if:
1532                  * - multi-segment packet
1533                  * - no space left even for a dseg
1534                  * - next packet can be inlined with a new WQE
1535                  * - cs_flag differs
1536                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1537                  * segmented packet.
1538                  */
1539                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1540                         if ((segs_n != 1) ||
1541                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1542                               mpw_room) ||
1543                             (length <= txq->inline_max_packet_sz &&
1544                              inl_pad + sizeof(inl_hdr) + length >
1545                               mpw_room) ||
1546                             (mpw.wqe->eseg.cs_flags != cs_flags))
1547                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1548                 }
1549                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1550                         if (unlikely(segs_n != 1)) {
1551                                 /* Fall back to legacy MPW.
1552                                  * A MPW session consumes 2 WQEs at most to
1553                                  * include MLX5_MPW_DSEG_MAX pointers.
1554                                  */
1555                                 if (unlikely(max_wqe < 2))
1556                                         break;
1557                                 mlx5_mpw_new(txq, &mpw, length);
1558                         } else {
1559                                 /* In Enhanced MPW, inline as much as the budget
1560                                  * is allowed. The remaining space is to be
1561                                  * filled with dsegs. If the title WQEBB isn't
1562                                  * padded, it will have 2 dsegs there.
1563                                  */
1564                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1565                                             (max_inline ? max_inline :
1566                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1567                                             MLX5_WQE_SIZE);
1568                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1569                                               mpw_room))
1570                                         break;
1571                                 /* Don't pad the title WQEBB to not waste WQ. */
1572                                 mlx5_empw_new(txq, &mpw, 0);
1573                                 mpw_room -= mpw.total_len;
1574                                 inl_pad = 0;
1575                                 do_inline =
1576                                         length <= txq->inline_max_packet_sz &&
1577                                         sizeof(inl_hdr) + length <= mpw_room &&
1578                                         !txq->mpw_hdr_dseg;
1579                         }
1580                         mpw.wqe->eseg.cs_flags = cs_flags;
1581                 } else {
1582                         /* Evaluate whether the next packet can be inlined.
1583                          * Inlininig is possible when:
1584                          * - length is less than configured value
1585                          * - length fits for remaining space
1586                          * - not required to fill the title WQEBB with dsegs
1587                          */
1588                         do_inline =
1589                                 length <= txq->inline_max_packet_sz &&
1590                                 inl_pad + sizeof(inl_hdr) + length <=
1591                                  mpw_room &&
1592                                 (!txq->mpw_hdr_dseg ||
1593                                  mpw.total_len >= MLX5_WQE_SIZE);
1594                 }
1595                 /* Multi-segment packets must be alone in their MPW. */
1596                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1597                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1598 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1599                         length = 0;
1600 #endif
1601                         do {
1602                                 volatile struct mlx5_wqe_data_seg *dseg;
1603
1604                                 assert(buf);
1605                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1606                                 dseg = mpw.data.dseg[mpw.pkts_n];
1607                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1608                                 *dseg = (struct mlx5_wqe_data_seg){
1609                                         .byte_count = htonl(DATA_LEN(buf)),
1610                                         .lkey = txq_mb2mr(txq, buf),
1611                                         .addr = htonll(addr),
1612                                 };
1613 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1614                                 length += DATA_LEN(buf);
1615 #endif
1616                                 buf = buf->next;
1617                                 ++j;
1618                                 ++mpw.pkts_n;
1619                         } while (--segs_n);
1620                         /* A multi-segmented packet takes one MPW session.
1621                          * TODO: Pack more multi-segmented packets if possible.
1622                          */
1623                         mlx5_mpw_close(txq, &mpw);
1624                         if (mpw.pkts_n < 3)
1625                                 max_wqe--;
1626                         else
1627                                 max_wqe -= 2;
1628                 } else if (do_inline) {
1629                         /* Inline packet into WQE. */
1630                         unsigned int max;
1631
1632                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1633                         assert(length == DATA_LEN(buf));
1634                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1635                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1636                         mpw.data.raw = (volatile void *)
1637                                 ((uintptr_t)mpw.data.raw + inl_pad);
1638                         max = tx_mlx5_wq_tailroom(txq,
1639                                         (void *)(uintptr_t)mpw.data.raw);
1640                         /* Copy inline header. */
1641                         mpw.data.raw = (volatile void *)
1642                                 mlx5_copy_to_wq(
1643                                           (void *)(uintptr_t)mpw.data.raw,
1644                                           &inl_hdr,
1645                                           sizeof(inl_hdr),
1646                                           (void *)(uintptr_t)txq->wqes,
1647                                           max);
1648                         max = tx_mlx5_wq_tailroom(txq,
1649                                         (void *)(uintptr_t)mpw.data.raw);
1650                         /* Copy packet data. */
1651                         mpw.data.raw = (volatile void *)
1652                                 mlx5_copy_to_wq(
1653                                           (void *)(uintptr_t)mpw.data.raw,
1654                                           (void *)addr,
1655                                           length,
1656                                           (void *)(uintptr_t)txq->wqes,
1657                                           max);
1658                         ++mpw.pkts_n;
1659                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1660                         /* No need to get completion as the entire packet is
1661                          * copied to WQ. Free the buf right away.
1662                          */
1663                         rte_pktmbuf_free_seg(buf);
1664                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1665                         /* Add pad in the next packet if any. */
1666                         inl_pad = (((uintptr_t)mpw.data.raw +
1667                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1668                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1669                                   (uintptr_t)mpw.data.raw;
1670                 } else {
1671                         /* No inline. Load a dseg of packet pointer. */
1672                         volatile rte_v128u32_t *dseg;
1673
1674                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1675                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1676                         assert(length == DATA_LEN(buf));
1677                         if (!tx_mlx5_wq_tailroom(txq,
1678                                         (void *)((uintptr_t)mpw.data.raw
1679                                                 + inl_pad)))
1680                                 dseg = (volatile void *)txq->wqes;
1681                         else
1682                                 dseg = (volatile void *)
1683                                         ((uintptr_t)mpw.data.raw +
1684                                          inl_pad);
1685                         (*txq->elts)[elts_head++ & elts_m] = buf;
1686                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1687                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1688                                 rte_prefetch2((void *)(addr +
1689                                                 n * RTE_CACHE_LINE_SIZE));
1690                         naddr = htonll(addr);
1691                         *dseg = (rte_v128u32_t) {
1692                                 htonl(length),
1693                                 txq_mb2mr(txq, buf),
1694                                 naddr,
1695                                 naddr >> 32,
1696                         };
1697                         mpw.data.raw = (volatile void *)(dseg + 1);
1698                         mpw.total_len += (inl_pad + sizeof(*dseg));
1699                         ++j;
1700                         ++mpw.pkts_n;
1701                         mpw_room -= (inl_pad + sizeof(*dseg));
1702                         inl_pad = 0;
1703                 }
1704 #ifdef MLX5_PMD_SOFT_COUNTERS
1705                 /* Increment sent bytes counter. */
1706                 txq->stats.obytes += length;
1707 #endif
1708                 ++i;
1709         } while (i < pkts_n);
1710         /* Take a shortcut if nothing must be sent. */
1711         if (unlikely(i == 0))
1712                 return 0;
1713         /* Check whether completion threshold has been reached. */
1714         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1715                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1716                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1717                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1718
1719                 /* Request completion on last WQE. */
1720                 wqe->ctrl[2] = htonl(8);
1721                 /* Save elts_head in unused "immediate" field of WQE. */
1722                 wqe->ctrl[3] = elts_head;
1723                 txq->elts_comp = 0;
1724                 txq->mpw_comp = txq->wqe_ci;
1725                 txq->cq_pi++;
1726         } else {
1727                 txq->elts_comp += j;
1728         }
1729 #ifdef MLX5_PMD_SOFT_COUNTERS
1730         /* Increment sent packets counter. */
1731         txq->stats.opackets += i;
1732 #endif
1733         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1734                 mlx5_empw_close(txq, &mpw);
1735         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1736                 mlx5_mpw_close(txq, &mpw);
1737         /* Ring QP doorbell. */
1738         mlx5_tx_dbrec(txq, mpw.wqe);
1739         txq->elts_head = elts_head;
1740         return i;
1741 }
1742
1743 /**
1744  * Translate RX completion flags to packet type.
1745  *
1746  * @param[in] cqe
1747  *   Pointer to CQE.
1748  *
1749  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1750  *
1751  * @return
1752  *   Packet type for struct rte_mbuf.
1753  */
1754 static inline uint32_t
1755 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1756 {
1757         uint32_t pkt_type;
1758         uint16_t flags = ntohs(cqe->hdr_type_etc);
1759
1760         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1761                 pkt_type =
1762                         TRANSPOSE(flags,
1763                                   MLX5_CQE_RX_IPV4_PACKET,
1764                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1765                         TRANSPOSE(flags,
1766                                   MLX5_CQE_RX_IPV6_PACKET,
1767                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1768                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1769                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1770                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1771         } else {
1772                 pkt_type =
1773                         TRANSPOSE(flags,
1774                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1775                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1776                         TRANSPOSE(flags,
1777                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1778                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1779         }
1780         return pkt_type;
1781 }
1782
1783 /**
1784  * Get size of the next packet for a given CQE. For compressed CQEs, the
1785  * consumer index is updated only once all packets of the current one have
1786  * been processed.
1787  *
1788  * @param rxq
1789  *   Pointer to RX queue.
1790  * @param cqe
1791  *   CQE to process.
1792  * @param[out] rss_hash
1793  *   Packet RSS Hash result.
1794  *
1795  * @return
1796  *   Packet size in bytes (0 if there is none), -1 in case of completion
1797  *   with error.
1798  */
1799 static inline int
1800 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1801                  uint16_t cqe_cnt, uint32_t *rss_hash)
1802 {
1803         struct rxq_zip *zip = &rxq->zip;
1804         uint16_t cqe_n = cqe_cnt + 1;
1805         int len = 0;
1806         uint16_t idx, end;
1807
1808         /* Process compressed data in the CQE and mini arrays. */
1809         if (zip->ai) {
1810                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1811                         (volatile struct mlx5_mini_cqe8 (*)[8])
1812                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1813
1814                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1815                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1816                 if ((++zip->ai & 7) == 0) {
1817                         /* Invalidate consumed CQEs */
1818                         idx = zip->ca;
1819                         end = zip->na;
1820                         while (idx != end) {
1821                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1822                                         MLX5_CQE_INVALIDATE;
1823                                 ++idx;
1824                         }
1825                         /*
1826                          * Increment consumer index to skip the number of
1827                          * CQEs consumed. Hardware leaves holes in the CQ
1828                          * ring for software use.
1829                          */
1830                         zip->ca = zip->na;
1831                         zip->na += 8;
1832                 }
1833                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1834                         /* Invalidate the rest */
1835                         idx = zip->ca;
1836                         end = zip->cq_ci;
1837
1838                         while (idx != end) {
1839                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1840                                         MLX5_CQE_INVALIDATE;
1841                                 ++idx;
1842                         }
1843                         rxq->cq_ci = zip->cq_ci;
1844                         zip->ai = 0;
1845                 }
1846         /* No compressed data, get next CQE and verify if it is compressed. */
1847         } else {
1848                 int ret;
1849                 int8_t op_own;
1850
1851                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1852                 if (unlikely(ret == 1))
1853                         return 0;
1854                 ++rxq->cq_ci;
1855                 op_own = cqe->op_own;
1856                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1857                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1858                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1859                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1860                                                           cqe_cnt]);
1861
1862                         /* Fix endianness. */
1863                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1864                         /*
1865                          * Current mini array position is the one returned by
1866                          * check_cqe64().
1867                          *
1868                          * If completion comprises several mini arrays, as a
1869                          * special case the second one is located 7 CQEs after
1870                          * the initial CQE instead of 8 for subsequent ones.
1871                          */
1872                         zip->ca = rxq->cq_ci;
1873                         zip->na = zip->ca + 7;
1874                         /* Compute the next non compressed CQE. */
1875                         --rxq->cq_ci;
1876                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1877                         /* Get packet size to return. */
1878                         len = ntohl((*mc)[0].byte_cnt);
1879                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1880                         zip->ai = 1;
1881                         /* Prefetch all the entries to be invalidated */
1882                         idx = zip->ca;
1883                         end = zip->cq_ci;
1884                         while (idx != end) {
1885                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1886                                 ++idx;
1887                         }
1888                 } else {
1889                         len = ntohl(cqe->byte_cnt);
1890                         *rss_hash = ntohl(cqe->rx_hash_res);
1891                 }
1892                 /* Error while receiving packet. */
1893                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1894                         return -1;
1895         }
1896         return len;
1897 }
1898
1899 /**
1900  * Translate RX completion flags to offload flags.
1901  *
1902  * @param[in] rxq
1903  *   Pointer to RX queue structure.
1904  * @param[in] cqe
1905  *   Pointer to CQE.
1906  *
1907  * @return
1908  *   Offload flags (ol_flags) for struct rte_mbuf.
1909  */
1910 static inline uint32_t
1911 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1912 {
1913         uint32_t ol_flags = 0;
1914         uint16_t flags = ntohs(cqe->hdr_type_etc);
1915
1916         ol_flags =
1917                 TRANSPOSE(flags,
1918                           MLX5_CQE_RX_L3_HDR_VALID,
1919                           PKT_RX_IP_CKSUM_GOOD) |
1920                 TRANSPOSE(flags,
1921                           MLX5_CQE_RX_L4_HDR_VALID,
1922                           PKT_RX_L4_CKSUM_GOOD);
1923         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1924                 ol_flags |=
1925                         TRANSPOSE(flags,
1926                                   MLX5_CQE_RX_L3_HDR_VALID,
1927                                   PKT_RX_IP_CKSUM_GOOD) |
1928                         TRANSPOSE(flags,
1929                                   MLX5_CQE_RX_L4_HDR_VALID,
1930                                   PKT_RX_L4_CKSUM_GOOD);
1931         return ol_flags;
1932 }
1933
1934 /**
1935  * DPDK callback for RX.
1936  *
1937  * @param dpdk_rxq
1938  *   Generic pointer to RX queue structure.
1939  * @param[out] pkts
1940  *   Array to store received packets.
1941  * @param pkts_n
1942  *   Maximum number of packets in array.
1943  *
1944  * @return
1945  *   Number of packets successfully received (<= pkts_n).
1946  */
1947 uint16_t
1948 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1949 {
1950         struct rxq *rxq = dpdk_rxq;
1951         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1952         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1953         const unsigned int sges_n = rxq->sges_n;
1954         struct rte_mbuf *pkt = NULL;
1955         struct rte_mbuf *seg = NULL;
1956         volatile struct mlx5_cqe *cqe =
1957                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1958         unsigned int i = 0;
1959         unsigned int rq_ci = rxq->rq_ci << sges_n;
1960         int len = 0; /* keep its value across iterations. */
1961
1962         while (pkts_n) {
1963                 unsigned int idx = rq_ci & wqe_cnt;
1964                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1965                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1966                 uint32_t rss_hash_res = 0;
1967
1968                 if (pkt)
1969                         NEXT(seg) = rep;
1970                 seg = rep;
1971                 rte_prefetch0(seg);
1972                 rte_prefetch0(cqe);
1973                 rte_prefetch0(wqe);
1974                 rep = rte_mbuf_raw_alloc(rxq->mp);
1975                 if (unlikely(rep == NULL)) {
1976                         ++rxq->stats.rx_nombuf;
1977                         if (!pkt) {
1978                                 /*
1979                                  * no buffers before we even started,
1980                                  * bail out silently.
1981                                  */
1982                                 break;
1983                         }
1984                         while (pkt != seg) {
1985                                 assert(pkt != (*rxq->elts)[idx]);
1986                                 rep = NEXT(pkt);
1987                                 NEXT(pkt) = NULL;
1988                                 NB_SEGS(pkt) = 1;
1989                                 rte_mbuf_raw_free(pkt);
1990                                 pkt = rep;
1991                         }
1992                         break;
1993                 }
1994                 if (!pkt) {
1995                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1996                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1997                                                &rss_hash_res);
1998                         if (!len) {
1999                                 rte_mbuf_raw_free(rep);
2000                                 break;
2001                         }
2002                         if (unlikely(len == -1)) {
2003                                 /* RX error, packet is likely too large. */
2004                                 rte_mbuf_raw_free(rep);
2005                                 ++rxq->stats.idropped;
2006                                 goto skip;
2007                         }
2008                         pkt = seg;
2009                         assert(len >= (rxq->crc_present << 2));
2010                         /* Update packet information. */
2011                         pkt->packet_type = 0;
2012                         pkt->ol_flags = 0;
2013                         if (rss_hash_res && rxq->rss_hash) {
2014                                 pkt->hash.rss = rss_hash_res;
2015                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2016                         }
2017                         if (rxq->mark &&
2018                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2019                                 pkt->ol_flags |= PKT_RX_FDIR;
2020                                 if (cqe->sop_drop_qpn !=
2021                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2022                                         uint32_t mark = cqe->sop_drop_qpn;
2023
2024                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2025                                         pkt->hash.fdir.hi =
2026                                                 mlx5_flow_mark_get(mark);
2027                                 }
2028                         }
2029                         if (rxq->csum | rxq->csum_l2tun) {
2030                                 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2031                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2032                         }
2033                         if (rxq->vlan_strip &&
2034                             (cqe->hdr_type_etc &
2035                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2036                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2037                                         PKT_RX_VLAN_STRIPPED;
2038                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2039                         }
2040                         if (rxq->crc_present)
2041                                 len -= ETHER_CRC_LEN;
2042                         PKT_LEN(pkt) = len;
2043                 }
2044                 DATA_LEN(rep) = DATA_LEN(seg);
2045                 PKT_LEN(rep) = PKT_LEN(seg);
2046                 SET_DATA_OFF(rep, DATA_OFF(seg));
2047                 PORT(rep) = PORT(seg);
2048                 (*rxq->elts)[idx] = rep;
2049                 /*
2050                  * Fill NIC descriptor with the new buffer.  The lkey and size
2051                  * of the buffers are already known, only the buffer address
2052                  * changes.
2053                  */
2054                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2055                 if (len > DATA_LEN(seg)) {
2056                         len -= DATA_LEN(seg);
2057                         ++NB_SEGS(pkt);
2058                         ++rq_ci;
2059                         continue;
2060                 }
2061                 DATA_LEN(seg) = len;
2062 #ifdef MLX5_PMD_SOFT_COUNTERS
2063                 /* Increment bytes counter. */
2064                 rxq->stats.ibytes += PKT_LEN(pkt);
2065 #endif
2066                 /* Return packet. */
2067                 *(pkts++) = pkt;
2068                 pkt = NULL;
2069                 --pkts_n;
2070                 ++i;
2071 skip:
2072                 /* Align consumer index to the next stride. */
2073                 rq_ci >>= sges_n;
2074                 ++rq_ci;
2075                 rq_ci <<= sges_n;
2076         }
2077         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2078                 return 0;
2079         /* Update the consumer index. */
2080         rxq->rq_ci = rq_ci >> sges_n;
2081         rte_wmb();
2082         *rxq->cq_db = htonl(rxq->cq_ci);
2083         rte_wmb();
2084         *rxq->rq_db = htonl(rxq->rq_ci);
2085 #ifdef MLX5_PMD_SOFT_COUNTERS
2086         /* Increment packets counter. */
2087         rxq->stats.ipackets += i;
2088 #endif
2089         return i;
2090 }
2091
2092 /**
2093  * Dummy DPDK callback for TX.
2094  *
2095  * This function is used to temporarily replace the real callback during
2096  * unsafe control operations on the queue, or in case of error.
2097  *
2098  * @param dpdk_txq
2099  *   Generic pointer to TX queue structure.
2100  * @param[in] pkts
2101  *   Packets to transmit.
2102  * @param pkts_n
2103  *   Number of packets in array.
2104  *
2105  * @return
2106  *   Number of packets successfully transmitted (<= pkts_n).
2107  */
2108 uint16_t
2109 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2110 {
2111         (void)dpdk_txq;
2112         (void)pkts;
2113         (void)pkts_n;
2114         return 0;
2115 }
2116
2117 /**
2118  * Dummy DPDK callback for RX.
2119  *
2120  * This function is used to temporarily replace the real callback during
2121  * unsafe control operations on the queue, or in case of error.
2122  *
2123  * @param dpdk_rxq
2124  *   Generic pointer to RX queue structure.
2125  * @param[out] pkts
2126  *   Array to store received packets.
2127  * @param pkts_n
2128  *   Maximum number of packets in array.
2129  *
2130  * @return
2131  *   Number of packets successfully received (<= pkts_n).
2132  */
2133 uint16_t
2134 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2135 {
2136         (void)dpdk_rxq;
2137         (void)pkts;
2138         (void)pkts_n;
2139         return 0;
2140 }