drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static __rte_always_inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci);
  75
  76 static __rte_always_inline void
  77 txq_complete(struct txq *txq);
  78
  79 static __rte_always_inline uint32_t
  80 txq_mp2mr(struct txq *txq, struct rte_mempool *mp);
  81
  82 static __rte_always_inline void
  83 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe);
  84
  85 static __rte_always_inline uint32_t
  86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  87
  88 static __rte_always_inline int
  89 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  90                  uint16_t cqe_cnt, uint32_t *rss_hash);
  91
  92 static __rte_always_inline uint32_t
  93 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  94
  95 #ifndef NDEBUG
  96
  97 /**
  98  * Verify or set magic value in CQE.
  99  *
 100  * @param cqe
 101  *   Pointer to CQE.
 102  *
 103  * @return
 104  *   0 the first time.
 105  */
 106 static inline int
 107 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 108 {
 109         static const uint8_t magic[] = "seen";
 110         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 111         int ret = 1;
 112         unsigned int i;
 113
 114         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 115                 if (!ret || (*buf)[i] != magic[i]) {
 116                         ret = 0;
 117                         (*buf)[i] = magic[i];
 118                 }
 119         return ret;
 120 }
 121
 122 #endif /* NDEBUG */
 123
 124 /**
 125  * Check whether CQE is valid.
 126  *
 127  * @param cqe
 128  *   Pointer to CQE.
 129  * @param cqes_n
 130  *   Size of completion queue.
 131  * @param ci
 132  *   Consumer index.
 133  *
 134  * @return
 135  *   0 on success, 1 on failure.
 136  */
 137 static inline int
 138 check_cqe(volatile struct mlx5_cqe *cqe,
 139           unsigned int cqes_n, const uint16_t ci)
 140 {
 141         uint16_t idx = ci & cqes_n;
 142         uint8_t op_own = cqe->op_own;
 143         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 144         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 145
 146         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 147                 return 1; /* No CQE. */
 148 #ifndef NDEBUG
 149         if ((op_code == MLX5_CQE_RESP_ERR) ||
 150             (op_code == MLX5_CQE_REQ_ERR)) {
 151                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 152                 uint8_t syndrome = err_cqe->syndrome;
 153
 154                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 155                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 156                         return 0;
 157                 if (!check_cqe_seen(cqe))
 158                         ERROR("unexpected CQE error %u (0x%02x)"
 159                               " syndrome 0x%02x",
 160                               op_code, op_code, syndrome);
 161                 return 1;
 162         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 163                    (op_code != MLX5_CQE_REQ)) {
 164                 if (!check_cqe_seen(cqe))
 165                         ERROR("unexpected CQE opcode %u (0x%02x)",
 166                               op_code, op_code);
 167                 return 1;
 168         }
 169 #endif /* NDEBUG */
 170         return 0;
 171 }
 172
 173 /**
 174  * Return the address of the WQE.
 175  *
 176  * @param txq
 177  *   Pointer to TX queue structure.
 178  * @param  wqe_ci
 179  *   WQE consumer index.
 180  *
 181  * @return
 182  *   WQE address.
 183  */
 184 static inline uintptr_t *
 185 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 186 {
 187         ci &= ((1 << txq->wqe_n) - 1);
 188         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 189 }
 190
 191 /**
 192  * Return the size of tailroom of WQ.
 193  *
 194  * @param txq
 195  *   Pointer to TX queue structure.
 196  * @param addr
 197  *   Pointer to tail of WQ.
 198  *
 199  * @return
 200  *   Size of tailroom.
 201  */
 202 static inline size_t
 203 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 204 {
 205         size_t tailroom;
 206         tailroom = (uintptr_t)(txq->wqes) +
 207                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 208                    (uintptr_t)addr;
 209         return tailroom;
 210 }
 211
 212 /**
 213  * Copy data to tailroom of circular queue.
 214  *
 215  * @param dst
 216  *   Pointer to destination.
 217  * @param src
 218  *   Pointer to source.
 219  * @param n
 220  *   Number of bytes to copy.
 221  * @param base
 222  *   Pointer to head of queue.
 223  * @param tailroom
 224  *   Size of tailroom from dst.
 225  *
 226  * @return
 227  *   Pointer after copied data.
 228  */
 229 static inline void *
 230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 231                 void *base, size_t tailroom)
 232 {
 233         void *ret;
 234
 235         if (n > tailroom) {
 236                 rte_memcpy(dst, src, tailroom);
 237                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 238                            n - tailroom);
 239                 ret = (uint8_t *)base + n - tailroom;
 240         } else {
 241                 rte_memcpy(dst, src, n);
 242                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 243         }
 244         return ret;
 245 }
 246
 247 /**
 248  * Manage TX completions.
 249  *
 250  * When sending a burst, mlx5_tx_burst() posts several WRs.
 251  *
 252  * @param txq
 253  *   Pointer to TX queue structure.
 254  */
 255 static inline void
 256 txq_complete(struct txq *txq)
 257 {
 258         const unsigned int elts_n = 1 << txq->elts_n;
 259         const unsigned int cqe_n = 1 << txq->cqe_n;
 260         const unsigned int cqe_cnt = cqe_n - 1;
 261         uint16_t elts_free = txq->elts_tail;
 262         uint16_t elts_tail;
 263         uint16_t cq_ci = txq->cq_ci;
 264         volatile struct mlx5_cqe *cqe = NULL;
 265         volatile struct mlx5_wqe_ctrl *ctrl;
 266
 267         do {
 268                 volatile struct mlx5_cqe *tmp;
 269
 270                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 271                 if (check_cqe(tmp, cqe_n, cq_ci))
 272                         break;
 273                 cqe = tmp;
 274 #ifndef NDEBUG
 275                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 276                         if (!check_cqe_seen(cqe))
 277                                 ERROR("unexpected compressed CQE, TX stopped");
 278                         return;
 279                 }
 280                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 281                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 282                         if (!check_cqe_seen(cqe))
 283                                 ERROR("unexpected error CQE, TX stopped");
 284                         return;
 285                 }
 286 #endif /* NDEBUG */
 287                 ++cq_ci;
 288         } while (1);
 289         if (unlikely(cqe == NULL))
 290                 return;
 291         txq->wqe_pi = ntohs(cqe->wqe_counter);
 292         ctrl = (volatile struct mlx5_wqe_ctrl *)
 293                 tx_mlx5_wqe(txq, txq->wqe_pi);
 294         elts_tail = ctrl->ctrl3;
 295         assert(elts_tail < (1 << txq->wqe_n));
 296         /* Free buffers. */
 297         while (elts_free != elts_tail) {
 298                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 299                 unsigned int elts_free_next =
 300                         (elts_free + 1) & (elts_n - 1);
 301                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 302
 303 #ifndef NDEBUG
 304                 /* Poisoning. */
 305                 memset(&(*txq->elts)[elts_free],
 306                        0x66,
 307                        sizeof((*txq->elts)[elts_free]));
 308 #endif
 309                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 310                 /* Only one segment needs to be freed. */
 311                 rte_pktmbuf_free_seg(elt);
 312                 elts_free = elts_free_next;
 313         }
 314         txq->cq_ci = cq_ci;
 315         txq->elts_tail = elts_tail;
 316         /* Update the consumer index. */
 317         rte_wmb();
 318         *txq->cq_db = htonl(cq_ci);
 319 }
 320
 321 /**
 322  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 323  * the cloned mbuf is allocated is returned instead.
 324  *
 325  * @param buf
 326  *   Pointer to mbuf.
 327  *
 328  * @return
 329  *   Memory pool where data is located for given mbuf.
 330  */
 331 static struct rte_mempool *
 332 txq_mb2mp(struct rte_mbuf *buf)
 333 {
 334         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 335                 return rte_mbuf_from_indirect(buf)->pool;
 336         return buf->pool;
 337 }
 338
 339 /**
 340  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 341  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 342  * remove an entry first.
 343  *
 344  * @param txq
 345  *   Pointer to TX queue structure.
 346  * @param[in] mp
 347  *   Memory Pool for which a Memory Region lkey must be returned.
 348  *
 349  * @return
 350  *   mr->lkey on success, (uint32_t)-1 on failure.
 351  */
 352 static inline uint32_t
 353 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 354 {
 355         unsigned int i;
 356         uint32_t lkey = (uint32_t)-1;
 357
 358         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 359                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 360                         /* Unknown MP, add a new MR for it. */
 361                         break;
 362                 }
 363                 if (txq->mp2mr[i].mp == mp) {
 364                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 365                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 366                                txq->mp2mr[i].lkey);
 367                         lkey = txq->mp2mr[i].lkey;
 368                         break;
 369                 }
 370         }
 371         if (unlikely(lkey == (uint32_t)-1))
 372                 lkey = txq_mp2mr_reg(txq, mp, i);
 373         return lkey;
 374 }
 375
 376 /**
 377  * Ring TX queue doorbell.
 378  *
 379  * @param txq
 380  *   Pointer to TX queue structure.
 381  * @param wqe
 382  *   Pointer to the last WQE posted in the NIC.
 383  */
 384 static inline void
 385 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 386 {
 387         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 388         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 389
 390         rte_wmb();
 391         *txq->qp_db = htonl(txq->wqe_ci);
 392         /* Ensure ordering between DB record and BF copy. */
 393         rte_wmb();
 394         *dst = *src;
 395 }
 396
 397 /**
 398  * DPDK callback to check the status of a tx descriptor.
 399  *
 400  * @param tx_queue
 401  *   The tx queue.
 402  * @param[in] offset
 403  *   The index of the descriptor in the ring.
 404  *
 405  * @return
 406  *   The status of the tx descriptor.
 407  */
 408 int
 409 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 410 {
 411         struct txq *txq = tx_queue;
 412         const unsigned int elts_n = 1 << txq->elts_n;
 413         const unsigned int elts_cnt = elts_n - 1;
 414         unsigned int used;
 415
 416         txq_complete(txq);
 417         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 418         if (offset < used)
 419                 return RTE_ETH_TX_DESC_FULL;
 420         return RTE_ETH_TX_DESC_DONE;
 421 }
 422
 423 /**
 424  * DPDK callback to check the status of a rx descriptor.
 425  *
 426  * @param rx_queue
 427  *   The rx queue.
 428  * @param[in] offset
 429  *   The index of the descriptor in the ring.
 430  *
 431  * @return
 432  *   The status of the tx descriptor.
 433  */
 434 int
 435 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 436 {
 437         struct rxq *rxq = rx_queue;
 438         struct rxq_zip *zip = &rxq->zip;
 439         volatile struct mlx5_cqe *cqe;
 440         const unsigned int cqe_n = (1 << rxq->cqe_n);
 441         const unsigned int cqe_cnt = cqe_n - 1;
 442         unsigned int cq_ci;
 443         unsigned int used;
 444
 445         /* if we are processing a compressed cqe */
 446         if (zip->ai) {
 447                 used = zip->cqe_cnt - zip->ca;
 448                 cq_ci = zip->cq_ci;
 449         } else {
 450                 used = 0;
 451                 cq_ci = rxq->cq_ci;
 452         }
 453         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 454         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 455                 int8_t op_own;
 456                 unsigned int n;
 457
 458                 op_own = cqe->op_own;
 459                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 460                         n = ntohl(cqe->byte_cnt);
 461                 else
 462                         n = 1;
 463                 cq_ci += n;
 464                 used += n;
 465                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 466         }
 467         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 468         if (offset < used)
 469                 return RTE_ETH_RX_DESC_DONE;
 470         return RTE_ETH_RX_DESC_AVAIL;
 471 }
 472
 473 /**
 474  * DPDK callback for TX.
 475  *
 476  * @param dpdk_txq
 477  *   Generic pointer to TX queue structure.
 478  * @param[in] pkts
 479  *   Packets to transmit.
 480  * @param pkts_n
 481  *   Number of packets in array.
 482  *
 483  * @return
 484  *   Number of packets successfully transmitted (<= pkts_n).
 485  */
 486 uint16_t
 487 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 488 {
 489         struct txq *txq = (struct txq *)dpdk_txq;
 490         uint16_t elts_head = txq->elts_head;
 491         const unsigned int elts_n = 1 << txq->elts_n;
 492         unsigned int i = 0;
 493         unsigned int j = 0;
 494         unsigned int k = 0;
 495         unsigned int max;
 496         unsigned int max_inline = txq->max_inline;
 497         const unsigned int inline_en = !!max_inline && txq->inline_en;
 498         uint16_t max_wqe;
 499         unsigned int comp;
 500         volatile struct mlx5_wqe_v *wqe = NULL;
 501         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 502         unsigned int segs_n = 0;
 503         struct rte_mbuf *buf = NULL;
 504         uint8_t *raw;
 505
 506         if (unlikely(!pkts_n))
 507                 return 0;
 508         /* Prefetch first packet cacheline. */
 509         rte_prefetch0(*pkts);
 510         /* Start processing. */
 511         txq_complete(txq);
 512         max = (elts_n - (elts_head - txq->elts_tail));
 513         if (max > elts_n)
 514                 max -= elts_n;
 515         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 516         if (unlikely(!max_wqe))
 517                 return 0;
 518         do {
 519                 volatile rte_v128u32_t *dseg = NULL;
 520                 uint32_t length;
 521                 unsigned int ds = 0;
 522                 unsigned int sg = 0; /* counter of additional segs attached. */
 523                 uintptr_t addr;
 524                 uint64_t naddr;
 525                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 526                 uint16_t tso_header_sz = 0;
 527                 uint16_t ehdr;
 528                 uint8_t cs_flags = 0;
 529                 uint64_t tso = 0;
 530 #ifdef MLX5_PMD_SOFT_COUNTERS
 531                 uint32_t total_length = 0;
 532 #endif
 533
 534                 /* first_seg */
 535                 buf = *pkts;
 536                 segs_n = buf->nb_segs;
 537                 /*
 538                  * Make sure there is enough room to store this packet and
 539                  * that one ring entry remains unused.
 540                  */
 541                 assert(segs_n);
 542                 if (max < segs_n + 1)
 543                         break;
 544                 max -= segs_n;
 545                 --segs_n;
 546                 if (unlikely(--max_wqe == 0))
 547                         break;
 548                 wqe = (volatile struct mlx5_wqe_v *)
 549                         tx_mlx5_wqe(txq, txq->wqe_ci);
 550                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 551                 if (pkts_n - i > 1)
 552                         rte_prefetch0(*(pkts + 1));
 553                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 554                 length = DATA_LEN(buf);
 555                 ehdr = (((uint8_t *)addr)[1] << 8) |
 556                        ((uint8_t *)addr)[0];
 557 #ifdef MLX5_PMD_SOFT_COUNTERS
 558                 total_length = length;
 559 #endif
 560                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 561                         break;
 562                 /* Update element. */
 563                 (*txq->elts)[elts_head] = buf;
 564                 /* Prefetch next buffer data. */
 565                 if (pkts_n - i > 1)
 566                         rte_prefetch0(
 567                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 568                 /* Should we enable HW CKSUM offload */
 569                 if (buf->ol_flags &
 570                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 571                         const uint64_t is_tunneled = buf->ol_flags &
 572                                                      (PKT_TX_TUNNEL_GRE |
 573                                                       PKT_TX_TUNNEL_VXLAN);
 574
 575                         if (is_tunneled && txq->tunnel_en) {
 576                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 577                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 578                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 579                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 580                         } else {
 581                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 582                                            MLX5_ETH_WQE_L4_CSUM;
 583                         }
 584                 }
 585                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 586                 /* Replace the Ethernet type by the VLAN if necessary. */
 587                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 588                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 589                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 590
 591                         addr += 2;
 592                         length -= 2;
 593                         /* Copy Destination and source mac address. */
 594                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 595                         /* Copy VLAN. */
 596                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 597                         /* Copy missing two bytes to end the DSeg. */
 598                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 599                                ((uint8_t *)addr) + len, 2);
 600                         addr += len + 2;
 601                         length -= (len + 2);
 602                 } else {
 603                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 604                                MLX5_WQE_DWORD_SIZE);
 605                         length -= pkt_inline_sz;
 606                         addr += pkt_inline_sz;
 607                 }
 608                 if (txq->tso_en) {
 609                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 610                         if (tso) {
 611                                 uintptr_t end = (uintptr_t)
 612                                                 (((uintptr_t)txq->wqes) +
 613                                                 (1 << txq->wqe_n) *
 614                                                 MLX5_WQE_SIZE);
 615                                 unsigned int copy_b;
 616                                 uint8_t vlan_sz = (buf->ol_flags &
 617                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 618                                 const uint64_t is_tunneled =
 619                                                         buf->ol_flags &
 620                                                         (PKT_TX_TUNNEL_GRE |
 621                                                          PKT_TX_TUNNEL_VXLAN);
 622
 623                                 tso_header_sz = buf->l2_len + vlan_sz +
 624                                                 buf->l3_len + buf->l4_len;
 625
 626                                 if (is_tunneled && txq->tunnel_en) {
 627                                         tso_header_sz += buf->outer_l2_len +
 628                                                          buf->outer_l3_len;
 629                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 630                                 } else {
 631                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 632                                 }
 633                                 if (unlikely(tso_header_sz >
 634                                              MLX5_MAX_TSO_HEADER))
 635                                         break;
 636                                 copy_b = tso_header_sz - pkt_inline_sz;
 637                                 /* First seg must contain all headers. */
 638                                 assert(copy_b <= length);
 639                                 raw += MLX5_WQE_DWORD_SIZE;
 640                                 if (copy_b &&
 641                                    ((end - (uintptr_t)raw) > copy_b)) {
 642                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 643                                                       1 + 3) / 4;
 644
 645                                         if (unlikely(max_wqe < n))
 646                                                 break;
 647                                         max_wqe -= n;
 648                                         rte_memcpy((void *)raw,
 649                                                    (void *)addr, copy_b);
 650                                         addr += copy_b;
 651                                         length -= copy_b;
 652                                         pkt_inline_sz += copy_b;
 653                                         /*
 654                                          * Another DWORD will be added
 655                                          * in the inline part.
 656                                          */
 657                                         raw += MLX5_WQE_DS(copy_b) *
 658                                                MLX5_WQE_DWORD_SIZE -
 659                                                MLX5_WQE_DWORD_SIZE;
 660                                 } else {
 661                                         /* NOP WQE. */
 662                                         wqe->ctrl = (rte_v128u32_t){
 663                                                      htonl(txq->wqe_ci << 8),
 664                                                      htonl(txq->qp_num_8s | 1),
 665                                                      0,
 666                                                      0,
 667                                         };
 668                                         ds = 1;
 669                                         total_length = 0;
 670                                         k++;
 671                                         goto next_wqe;
 672                                 }
 673                         }
 674                 }
 675                 /* Inline if enough room. */
 676                 if (inline_en || tso) {
 677                         uintptr_t end = (uintptr_t)
 678                                 (((uintptr_t)txq->wqes) +
 679                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 680                         unsigned int inline_room = max_inline *
 681                                                    RTE_CACHE_LINE_SIZE -
 682                                                    (pkt_inline_sz - 2);
 683                         uintptr_t addr_end = (addr + inline_room) &
 684                                              ~(RTE_CACHE_LINE_SIZE - 1);
 685                         unsigned int copy_b = (addr_end > addr) ?
 686                                 RTE_MIN((addr_end - addr), length) :
 687                                 0;
 688
 689                         raw += MLX5_WQE_DWORD_SIZE;
 690                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 691                                 /*
 692                                  * One Dseg remains in the current WQE.  To
 693                                  * keep the computation positive, it is
 694                                  * removed after the bytes to Dseg conversion.
 695                                  */
 696                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 697
 698                                 if (unlikely(max_wqe < n))
 699                                         break;
 700                                 max_wqe -= n;
 701                                 if (tso) {
 702                                         uint32_t inl =
 703                                                 htonl(copy_b | MLX5_INLINE_SEG);
 704
 705                                         pkt_inline_sz =
 706                                                 MLX5_WQE_DS(tso_header_sz) *
 707                                                 MLX5_WQE_DWORD_SIZE;
 708                                         rte_memcpy((void *)raw,
 709                                                    (void *)&inl, sizeof(inl));
 710                                         raw += sizeof(inl);
 711                                         pkt_inline_sz += sizeof(inl);
 712                                 }
 713                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 714                                 addr += copy_b;
 715                                 length -= copy_b;
 716                                 pkt_inline_sz += copy_b;
 717                         }
 718                         /*
 719                          * 2 DWORDs consumed by the WQE header + ETH segment +
 720                          * the size of the inline part of the packet.
 721                          */
 722                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 723                         if (length > 0) {
 724                                 if (ds % (MLX5_WQE_SIZE /
 725                                           MLX5_WQE_DWORD_SIZE) == 0) {
 726                                         if (unlikely(--max_wqe == 0))
 727                                                 break;
 728                                         dseg = (volatile rte_v128u32_t *)
 729                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 730                                                            ds / 4);
 731                                 } else {
 732                                         dseg = (volatile rte_v128u32_t *)
 733                                                 ((uintptr_t)wqe +
 734                                                  (ds * MLX5_WQE_DWORD_SIZE));
 735                                 }
 736                                 goto use_dseg;
 737                         } else if (!segs_n) {
 738                                 goto next_pkt;
 739                         } else {
 740                                 /* dseg will be advance as part of next_seg */
 741                                 dseg = (volatile rte_v128u32_t *)
 742                                         ((uintptr_t)wqe +
 743                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 744                                 goto next_seg;
 745                         }
 746                 } else {
 747                         /*
 748                          * No inline has been done in the packet, only the
 749                          * Ethernet Header as been stored.
 750                          */
 751                         dseg = (volatile rte_v128u32_t *)
 752                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 753                         ds = 3;
 754 use_dseg:
 755                         /* Add the remaining packet as a simple ds. */
 756                         naddr = htonll(addr);
 757                         *dseg = (rte_v128u32_t){
 758                                 htonl(length),
 759                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 760                                 naddr,
 761                                 naddr >> 32,
 762                         };
 763                         ++ds;
 764                         if (!segs_n)
 765                                 goto next_pkt;
 766                 }
 767 next_seg:
 768                 assert(buf);
 769                 assert(ds);
 770                 assert(wqe);
 771                 /*
 772                  * Spill on next WQE when the current one does not have
 773                  * enough room left. Size of WQE must a be a multiple
 774                  * of data segment size.
 775                  */
 776                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 777                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 778                         if (unlikely(--max_wqe == 0))
 779                                 break;
 780                         dseg = (volatile rte_v128u32_t *)
 781                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 782                         rte_prefetch0(tx_mlx5_wqe(txq,
 783                                                   txq->wqe_ci + ds / 4 + 1));
 784                 } else {
 785                         ++dseg;
 786                 }
 787                 ++ds;
 788                 buf = buf->next;
 789                 assert(buf);
 790                 length = DATA_LEN(buf);
 791 #ifdef MLX5_PMD_SOFT_COUNTERS
 792                 total_length += length;
 793 #endif
 794                 /* Store segment information. */
 795                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 796                 *dseg = (rte_v128u32_t){
 797                         htonl(length),
 798                         txq_mp2mr(txq, txq_mb2mp(buf)),
 799                         naddr,
 800                         naddr >> 32,
 801                 };
 802                 elts_head = (elts_head + 1) & (elts_n - 1);
 803                 (*txq->elts)[elts_head] = buf;
 804                 ++sg;
 805                 /* Advance counter only if all segs are successfully posted. */
 806                 if (sg < segs_n)
 807                         goto next_seg;
 808                 else
 809                         j += sg;
 810 next_pkt:
 811                 elts_head = (elts_head + 1) & (elts_n - 1);
 812                 ++pkts;
 813                 ++i;
 814                 /* Initialize known and common part of the WQE structure. */
 815                 if (tso) {
 816                         wqe->ctrl = (rte_v128u32_t){
 817                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 818                                 htonl(txq->qp_num_8s | ds),
 819                                 0,
 820                                 0,
 821                         };
 822                         wqe->eseg = (rte_v128u32_t){
 823                                 0,
 824                                 cs_flags | (htons(buf->tso_segsz) << 16),
 825                                 0,
 826                                 (ehdr << 16) | htons(tso_header_sz),
 827                         };
 828                 } else {
 829                         wqe->ctrl = (rte_v128u32_t){
 830                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 831                                 htonl(txq->qp_num_8s | ds),
 832                                 0,
 833                                 0,
 834                         };
 835                         wqe->eseg = (rte_v128u32_t){
 836                                 0,
 837                                 cs_flags,
 838                                 0,
 839                                 (ehdr << 16) | htons(pkt_inline_sz),
 840                         };
 841                 }
 842 next_wqe:
 843                 txq->wqe_ci += (ds + 3) / 4;
 844                 /* Save the last successful WQE for completion request */
 845                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 846 #ifdef MLX5_PMD_SOFT_COUNTERS
 847                 /* Increment sent bytes counter. */
 848                 txq->stats.obytes += total_length;
 849 #endif
 850         } while (i < pkts_n);
 851         /* Take a shortcut if nothing must be sent. */
 852         if (unlikely((i + k) == 0))
 853                 return 0;
 854         txq->elts_head = (txq->elts_head + i + j) & (elts_n - 1);
 855         /* Check whether completion threshold has been reached. */
 856         comp = txq->elts_comp + i + j + k;
 857         if (comp >= MLX5_TX_COMP_THRESH) {
 858                 /* Request completion on last WQE. */
 859                 last_wqe->ctrl2 = htonl(8);
 860                 /* Save elts_head in unused "immediate" field of WQE. */
 861                 last_wqe->ctrl3 = txq->elts_head;
 862                 txq->elts_comp = 0;
 863         } else {
 864                 txq->elts_comp = comp;
 865         }
 866 #ifdef MLX5_PMD_SOFT_COUNTERS
 867         /* Increment sent packets counter. */
 868         txq->stats.opackets += i;
 869 #endif
 870         /* Ring QP doorbell. */
 871         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 872         return i;
 873 }
 874
 875 /**
 876  * Open a MPW session.
 877  *
 878  * @param txq
 879  *   Pointer to TX queue structure.
 880  * @param mpw
 881  *   Pointer to MPW session structure.
 882  * @param length
 883  *   Packet length.
 884  */
 885 static inline void
 886 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 887 {
 888         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 889         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 890                 (volatile struct mlx5_wqe_data_seg (*)[])
 891                 tx_mlx5_wqe(txq, idx + 1);
 892
 893         mpw->state = MLX5_MPW_STATE_OPENED;
 894         mpw->pkts_n = 0;
 895         mpw->len = length;
 896         mpw->total_len = 0;
 897         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 898         mpw->wqe->eseg.mss = htons(length);
 899         mpw->wqe->eseg.inline_hdr_sz = 0;
 900         mpw->wqe->eseg.rsvd0 = 0;
 901         mpw->wqe->eseg.rsvd1 = 0;
 902         mpw->wqe->eseg.rsvd2 = 0;
 903         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 904                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 905         mpw->wqe->ctrl[2] = 0;
 906         mpw->wqe->ctrl[3] = 0;
 907         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 908                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 909         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 910                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 911         mpw->data.dseg[2] = &(*dseg)[0];
 912         mpw->data.dseg[3] = &(*dseg)[1];
 913         mpw->data.dseg[4] = &(*dseg)[2];
 914 }
 915
 916 /**
 917  * Close a MPW session.
 918  *
 919  * @param txq
 920  *   Pointer to TX queue structure.
 921  * @param mpw
 922  *   Pointer to MPW session structure.
 923  */
 924 static inline void
 925 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 926 {
 927         unsigned int num = mpw->pkts_n;
 928
 929         /*
 930          * Store size in multiple of 16 bytes. Control and Ethernet segments
 931          * count as 2.
 932          */
 933         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 934         mpw->state = MLX5_MPW_STATE_CLOSED;
 935         if (num < 3)
 936                 ++txq->wqe_ci;
 937         else
 938                 txq->wqe_ci += 2;
 939         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 940         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 941 }
 942
 943 /**
 944  * DPDK callback for TX with MPW support.
 945  *
 946  * @param dpdk_txq
 947  *   Generic pointer to TX queue structure.
 948  * @param[in] pkts
 949  *   Packets to transmit.
 950  * @param pkts_n
 951  *   Number of packets in array.
 952  *
 953  * @return
 954  *   Number of packets successfully transmitted (<= pkts_n).
 955  */
 956 uint16_t
 957 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 958 {
 959         struct txq *txq = (struct txq *)dpdk_txq;
 960         uint16_t elts_head = txq->elts_head;
 961         const unsigned int elts_n = 1 << txq->elts_n;
 962         unsigned int i = 0;
 963         unsigned int j = 0;
 964         unsigned int max;
 965         uint16_t max_wqe;
 966         unsigned int comp;
 967         struct mlx5_mpw mpw = {
 968                 .state = MLX5_MPW_STATE_CLOSED,
 969         };
 970
 971         if (unlikely(!pkts_n))
 972                 return 0;
 973         /* Prefetch first packet cacheline. */
 974         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 975         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 976         /* Start processing. */
 977         txq_complete(txq);
 978         max = (elts_n - (elts_head - txq->elts_tail));
 979         if (max > elts_n)
 980                 max -= elts_n;
 981         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 982         if (unlikely(!max_wqe))
 983                 return 0;
 984         do {
 985                 struct rte_mbuf *buf = *(pkts++);
 986                 unsigned int elts_head_next;
 987                 uint32_t length;
 988                 unsigned int segs_n = buf->nb_segs;
 989                 uint32_t cs_flags = 0;
 990
 991                 /*
 992                  * Make sure there is enough room to store this packet and
 993                  * that one ring entry remains unused.
 994                  */
 995                 assert(segs_n);
 996                 if (max < segs_n + 1)
 997                         break;
 998                 /* Do not bother with large packets MPW cannot handle. */
 999                 if (segs_n > MLX5_MPW_DSEG_MAX)
1000                         break;
1001                 max -= segs_n;
1002                 --pkts_n;
1003                 /* Should we enable HW CKSUM offload */
1004                 if (buf->ol_flags &
1005                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1006                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1007                 /* Retrieve packet information. */
1008                 length = PKT_LEN(buf);
1009                 assert(length);
1010                 /* Start new session if packet differs. */
1011                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1012                     ((mpw.len != length) ||
1013                      (segs_n != 1) ||
1014                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1015                         mlx5_mpw_close(txq, &mpw);
1016                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1017                         /*
1018                          * Multi-Packet WQE consumes at most two WQE.
1019                          * mlx5_mpw_new() expects to be able to use such
1020                          * resources.
1021                          */
1022                         if (unlikely(max_wqe < 2))
1023                                 break;
1024                         max_wqe -= 2;
1025                         mlx5_mpw_new(txq, &mpw, length);
1026                         mpw.wqe->eseg.cs_flags = cs_flags;
1027                 }
1028                 /* Multi-segment packets must be alone in their MPW. */
1029                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1030 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1031                 length = 0;
1032 #endif
1033                 do {
1034                         volatile struct mlx5_wqe_data_seg *dseg;
1035                         uintptr_t addr;
1036
1037                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1038                         assert(buf);
1039                         (*txq->elts)[elts_head] = buf;
1040                         dseg = mpw.data.dseg[mpw.pkts_n];
1041                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1042                         *dseg = (struct mlx5_wqe_data_seg){
1043                                 .byte_count = htonl(DATA_LEN(buf)),
1044                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1045                                 .addr = htonll(addr),
1046                         };
1047                         elts_head = elts_head_next;
1048 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1049                         length += DATA_LEN(buf);
1050 #endif
1051                         buf = buf->next;
1052                         ++mpw.pkts_n;
1053                         ++j;
1054                 } while (--segs_n);
1055                 assert(length == mpw.len);
1056                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1057                         mlx5_mpw_close(txq, &mpw);
1058                 elts_head = elts_head_next;
1059 #ifdef MLX5_PMD_SOFT_COUNTERS
1060                 /* Increment sent bytes counter. */
1061                 txq->stats.obytes += length;
1062 #endif
1063                 ++i;
1064         } while (pkts_n);
1065         /* Take a shortcut if nothing must be sent. */
1066         if (unlikely(i == 0))
1067                 return 0;
1068         /* Check whether completion threshold has been reached. */
1069         /* "j" includes both packets and segments. */
1070         comp = txq->elts_comp + j;
1071         if (comp >= MLX5_TX_COMP_THRESH) {
1072                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1073
1074                 /* Request completion on last WQE. */
1075                 wqe->ctrl[2] = htonl(8);
1076                 /* Save elts_head in unused "immediate" field of WQE. */
1077                 wqe->ctrl[3] = elts_head;
1078                 txq->elts_comp = 0;
1079         } else {
1080                 txq->elts_comp = comp;
1081         }
1082 #ifdef MLX5_PMD_SOFT_COUNTERS
1083         /* Increment sent packets counter. */
1084         txq->stats.opackets += i;
1085 #endif
1086         /* Ring QP doorbell. */
1087         if (mpw.state == MLX5_MPW_STATE_OPENED)
1088                 mlx5_mpw_close(txq, &mpw);
1089         mlx5_tx_dbrec(txq, mpw.wqe);
1090         txq->elts_head = elts_head;
1091         return i;
1092 }
1093
1094 /**
1095  * Open a MPW inline session.
1096  *
1097  * @param txq
1098  *   Pointer to TX queue structure.
1099  * @param mpw
1100  *   Pointer to MPW session structure.
1101  * @param length
1102  *   Packet length.
1103  */
1104 static inline void
1105 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1106 {
1107         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1108         struct mlx5_wqe_inl_small *inl;
1109
1110         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1111         mpw->pkts_n = 0;
1112         mpw->len = length;
1113         mpw->total_len = 0;
1114         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1115         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1116                                   (txq->wqe_ci << 8) |
1117                                   MLX5_OPCODE_TSO);
1118         mpw->wqe->ctrl[2] = 0;
1119         mpw->wqe->ctrl[3] = 0;
1120         mpw->wqe->eseg.mss = htons(length);
1121         mpw->wqe->eseg.inline_hdr_sz = 0;
1122         mpw->wqe->eseg.cs_flags = 0;
1123         mpw->wqe->eseg.rsvd0 = 0;
1124         mpw->wqe->eseg.rsvd1 = 0;
1125         mpw->wqe->eseg.rsvd2 = 0;
1126         inl = (struct mlx5_wqe_inl_small *)
1127                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1128         mpw->data.raw = (uint8_t *)&inl->raw;
1129 }
1130
1131 /**
1132  * Close a MPW inline session.
1133  *
1134  * @param txq
1135  *   Pointer to TX queue structure.
1136  * @param mpw
1137  *   Pointer to MPW session structure.
1138  */
1139 static inline void
1140 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1141 {
1142         unsigned int size;
1143         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1144                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1145
1146         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1147         /*
1148          * Store size in multiple of 16 bytes. Control and Ethernet segments
1149          * count as 2.
1150          */
1151         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1152         mpw->state = MLX5_MPW_STATE_CLOSED;
1153         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1154         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1155 }
1156
1157 /**
1158  * DPDK callback for TX with MPW inline support.
1159  *
1160  * @param dpdk_txq
1161  *   Generic pointer to TX queue structure.
1162  * @param[in] pkts
1163  *   Packets to transmit.
1164  * @param pkts_n
1165  *   Number of packets in array.
1166  *
1167  * @return
1168  *   Number of packets successfully transmitted (<= pkts_n).
1169  */
1170 uint16_t
1171 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1172                          uint16_t pkts_n)
1173 {
1174         struct txq *txq = (struct txq *)dpdk_txq;
1175         uint16_t elts_head = txq->elts_head;
1176         const unsigned int elts_n = 1 << txq->elts_n;
1177         unsigned int i = 0;
1178         unsigned int j = 0;
1179         unsigned int max;
1180         uint16_t max_wqe;
1181         unsigned int comp;
1182         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1183         struct mlx5_mpw mpw = {
1184                 .state = MLX5_MPW_STATE_CLOSED,
1185         };
1186         /*
1187          * Compute the maximum number of WQE which can be consumed by inline
1188          * code.
1189          * - 2 DSEG for:
1190          *   - 1 control segment,
1191          *   - 1 Ethernet segment,
1192          * - N Dseg from the inline request.
1193          */
1194         const unsigned int wqe_inl_n =
1195                 ((2 * MLX5_WQE_DWORD_SIZE +
1196                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1197                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1198
1199         if (unlikely(!pkts_n))
1200                 return 0;
1201         /* Prefetch first packet cacheline. */
1202         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1203         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1204         /* Start processing. */
1205         txq_complete(txq);
1206         max = (elts_n - (elts_head - txq->elts_tail));
1207         if (max > elts_n)
1208                 max -= elts_n;
1209         do {
1210                 struct rte_mbuf *buf = *(pkts++);
1211                 unsigned int elts_head_next;
1212                 uintptr_t addr;
1213                 uint32_t length;
1214                 unsigned int segs_n = buf->nb_segs;
1215                 uint32_t cs_flags = 0;
1216
1217                 /*
1218                  * Make sure there is enough room to store this packet and
1219                  * that one ring entry remains unused.
1220                  */
1221                 assert(segs_n);
1222                 if (max < segs_n + 1)
1223                         break;
1224                 /* Do not bother with large packets MPW cannot handle. */
1225                 if (segs_n > MLX5_MPW_DSEG_MAX)
1226                         break;
1227                 max -= segs_n;
1228                 --pkts_n;
1229                 /*
1230                  * Compute max_wqe in case less WQE were consumed in previous
1231                  * iteration.
1232                  */
1233                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1234                 /* Should we enable HW CKSUM offload */
1235                 if (buf->ol_flags &
1236                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1237                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1238                 /* Retrieve packet information. */
1239                 length = PKT_LEN(buf);
1240                 /* Start new session if packet differs. */
1241                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1242                         if ((mpw.len != length) ||
1243                             (segs_n != 1) ||
1244                             (mpw.wqe->eseg.cs_flags != cs_flags))
1245                                 mlx5_mpw_close(txq, &mpw);
1246                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1247                         if ((mpw.len != length) ||
1248                             (segs_n != 1) ||
1249                             (length > inline_room) ||
1250                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1251                                 mlx5_mpw_inline_close(txq, &mpw);
1252                                 inline_room =
1253                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1254                         }
1255                 }
1256                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1257                         if ((segs_n != 1) ||
1258                             (length > inline_room)) {
1259                                 /*
1260                                  * Multi-Packet WQE consumes at most two WQE.
1261                                  * mlx5_mpw_new() expects to be able to use
1262                                  * such resources.
1263                                  */
1264                                 if (unlikely(max_wqe < 2))
1265                                         break;
1266                                 max_wqe -= 2;
1267                                 mlx5_mpw_new(txq, &mpw, length);
1268                                 mpw.wqe->eseg.cs_flags = cs_flags;
1269                         } else {
1270                                 if (unlikely(max_wqe < wqe_inl_n))
1271                                         break;
1272                                 max_wqe -= wqe_inl_n;
1273                                 mlx5_mpw_inline_new(txq, &mpw, length);
1274                                 mpw.wqe->eseg.cs_flags = cs_flags;
1275                         }
1276                 }
1277                 /* Multi-segment packets must be alone in their MPW. */
1278                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1279                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1280                         assert(inline_room ==
1281                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1282 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1283                         length = 0;
1284 #endif
1285                         do {
1286                                 volatile struct mlx5_wqe_data_seg *dseg;
1287
1288                                 elts_head_next =
1289                                         (elts_head + 1) & (elts_n - 1);
1290                                 assert(buf);
1291                                 (*txq->elts)[elts_head] = buf;
1292                                 dseg = mpw.data.dseg[mpw.pkts_n];
1293                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1294                                 *dseg = (struct mlx5_wqe_data_seg){
1295                                         .byte_count = htonl(DATA_LEN(buf)),
1296                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1297                                         .addr = htonll(addr),
1298                                 };
1299                                 elts_head = elts_head_next;
1300 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1301                                 length += DATA_LEN(buf);
1302 #endif
1303                                 buf = buf->next;
1304                                 ++mpw.pkts_n;
1305                                 ++j;
1306                         } while (--segs_n);
1307                         assert(length == mpw.len);
1308                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1309                                 mlx5_mpw_close(txq, &mpw);
1310                 } else {
1311                         unsigned int max;
1312
1313                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1314                         assert(length <= inline_room);
1315                         assert(length == DATA_LEN(buf));
1316                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1317                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1318                         (*txq->elts)[elts_head] = buf;
1319                         /* Maximum number of bytes before wrapping. */
1320                         max = ((((uintptr_t)(txq->wqes)) +
1321                                 (1 << txq->wqe_n) *
1322                                 MLX5_WQE_SIZE) -
1323                                (uintptr_t)mpw.data.raw);
1324                         if (length > max) {
1325                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1326                                            (void *)addr,
1327                                            max);
1328                                 mpw.data.raw = (volatile void *)txq->wqes;
1329                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1330                                            (void *)(addr + max),
1331                                            length - max);
1332                                 mpw.data.raw += length - max;
1333                         } else {
1334                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1335                                            (void *)addr,
1336                                            length);
1337
1338                                 if (length == max)
1339                                         mpw.data.raw =
1340                                                 (volatile void *)txq->wqes;
1341                                 else
1342                                         mpw.data.raw += length;
1343                         }
1344                         ++mpw.pkts_n;
1345                         mpw.total_len += length;
1346                         ++j;
1347                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1348                                 mlx5_mpw_inline_close(txq, &mpw);
1349                                 inline_room =
1350                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1351                         } else {
1352                                 inline_room -= length;
1353                         }
1354                 }
1355                 elts_head = elts_head_next;
1356 #ifdef MLX5_PMD_SOFT_COUNTERS
1357                 /* Increment sent bytes counter. */
1358                 txq->stats.obytes += length;
1359 #endif
1360                 ++i;
1361         } while (pkts_n);
1362         /* Take a shortcut if nothing must be sent. */
1363         if (unlikely(i == 0))
1364                 return 0;
1365         /* Check whether completion threshold has been reached. */
1366         /* "j" includes both packets and segments. */
1367         comp = txq->elts_comp + j;
1368         if (comp >= MLX5_TX_COMP_THRESH) {
1369                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1370
1371                 /* Request completion on last WQE. */
1372                 wqe->ctrl[2] = htonl(8);
1373                 /* Save elts_head in unused "immediate" field of WQE. */
1374                 wqe->ctrl[3] = elts_head;
1375                 txq->elts_comp = 0;
1376         } else {
1377                 txq->elts_comp = comp;
1378         }
1379 #ifdef MLX5_PMD_SOFT_COUNTERS
1380         /* Increment sent packets counter. */
1381         txq->stats.opackets += i;
1382 #endif
1383         /* Ring QP doorbell. */
1384         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1385                 mlx5_mpw_inline_close(txq, &mpw);
1386         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1387                 mlx5_mpw_close(txq, &mpw);
1388         mlx5_tx_dbrec(txq, mpw.wqe);
1389         txq->elts_head = elts_head;
1390         return i;
1391 }
1392
1393 /**
1394  * Open an Enhanced MPW session.
1395  *
1396  * @param txq
1397  *   Pointer to TX queue structure.
1398  * @param mpw
1399  *   Pointer to MPW session structure.
1400  * @param length
1401  *   Packet length.
1402  */
1403 static inline void
1404 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1405 {
1406         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1407
1408         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1409         mpw->pkts_n = 0;
1410         mpw->total_len = sizeof(struct mlx5_wqe);
1411         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1412         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1413                                   (txq->wqe_ci << 8) |
1414                                   MLX5_OPCODE_ENHANCED_MPSW);
1415         mpw->wqe->ctrl[2] = 0;
1416         mpw->wqe->ctrl[3] = 0;
1417         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1418         if (unlikely(padding)) {
1419                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1420
1421                 /* Pad the first 2 DWORDs with zero-length inline header. */
1422                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1423                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1424                         htonl(MLX5_INLINE_SEG);
1425                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1426                 /* Start from the next WQEBB. */
1427                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1428         } else {
1429                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1430         }
1431 }
1432
1433 /**
1434  * Close an Enhanced MPW session.
1435  *
1436  * @param txq
1437  *   Pointer to TX queue structure.
1438  * @param mpw
1439  *   Pointer to MPW session structure.
1440  *
1441  * @return
1442  *   Number of consumed WQEs.
1443  */
1444 static inline uint16_t
1445 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1446 {
1447         uint16_t ret;
1448
1449         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1450          * count as 2.
1451          */
1452         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1453         mpw->state = MLX5_MPW_STATE_CLOSED;
1454         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1455         txq->wqe_ci += ret;
1456         return ret;
1457 }
1458
1459 /**
1460  * DPDK callback for TX with Enhanced MPW support.
1461  *
1462  * @param dpdk_txq
1463  *   Generic pointer to TX queue structure.
1464  * @param[in] pkts
1465  *   Packets to transmit.
1466  * @param pkts_n
1467  *   Number of packets in array.
1468  *
1469  * @return
1470  *   Number of packets successfully transmitted (<= pkts_n).
1471  */
1472 uint16_t
1473 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1474 {
1475         struct txq *txq = (struct txq *)dpdk_txq;
1476         uint16_t elts_head = txq->elts_head;
1477         const unsigned int elts_n = 1 << txq->elts_n;
1478         unsigned int i = 0;
1479         unsigned int j = 0;
1480         unsigned int max_elts;
1481         uint16_t max_wqe;
1482         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1483         unsigned int mpw_room = 0;
1484         unsigned int inl_pad = 0;
1485         uint32_t inl_hdr;
1486         struct mlx5_mpw mpw = {
1487                 .state = MLX5_MPW_STATE_CLOSED,
1488         };
1489
1490         if (unlikely(!pkts_n))
1491                 return 0;
1492         /* Start processing. */
1493         txq_complete(txq);
1494         max_elts = (elts_n - (elts_head - txq->elts_tail));
1495         if (max_elts > elts_n)
1496                 max_elts -= elts_n;
1497         /* A CQE slot must always be available. */
1498         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1499         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1500         if (unlikely(!max_wqe))
1501                 return 0;
1502         do {
1503                 struct rte_mbuf *buf = *(pkts++);
1504                 unsigned int elts_head_next;
1505                 uintptr_t addr;
1506                 uint64_t naddr;
1507                 unsigned int n;
1508                 unsigned int do_inline = 0; /* Whether inline is possible. */
1509                 uint32_t length;
1510                 unsigned int segs_n = buf->nb_segs;
1511                 uint32_t cs_flags = 0;
1512
1513                 /*
1514                  * Make sure there is enough room to store this packet and
1515                  * that one ring entry remains unused.
1516                  */
1517                 assert(segs_n);
1518                 if (max_elts - j < segs_n + 1)
1519                         break;
1520                 /* Do not bother with large packets MPW cannot handle. */
1521                 if (segs_n > MLX5_MPW_DSEG_MAX)
1522                         break;
1523                 /* Should we enable HW CKSUM offload. */
1524                 if (buf->ol_flags &
1525                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1526                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1527                 /* Retrieve packet information. */
1528                 length = PKT_LEN(buf);
1529                 /* Start new session if:
1530                  * - multi-segment packet
1531                  * - no space left even for a dseg
1532                  * - next packet can be inlined with a new WQE
1533                  * - cs_flag differs
1534                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1535                  * segmented packet.
1536                  */
1537                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1538                         if ((segs_n != 1) ||
1539                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1540                               mpw_room) ||
1541                             (length <= txq->inline_max_packet_sz &&
1542                              inl_pad + sizeof(inl_hdr) + length >
1543                               mpw_room) ||
1544                             (mpw.wqe->eseg.cs_flags != cs_flags))
1545                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1546                 }
1547                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1548                         if (unlikely(segs_n != 1)) {
1549                                 /* Fall back to legacy MPW.
1550                                  * A MPW session consumes 2 WQEs at most to
1551                                  * include MLX5_MPW_DSEG_MAX pointers.
1552                                  */
1553                                 if (unlikely(max_wqe < 2))
1554                                         break;
1555                                 mlx5_mpw_new(txq, &mpw, length);
1556                         } else {
1557                                 /* In Enhanced MPW, inline as much as the budget
1558                                  * is allowed. The remaining space is to be
1559                                  * filled with dsegs. If the title WQEBB isn't
1560                                  * padded, it will have 2 dsegs there.
1561                                  */
1562                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1563                                             (max_inline ? max_inline :
1564                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1565                                             MLX5_WQE_SIZE);
1566                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1567                                               mpw_room))
1568                                         break;
1569                                 /* Don't pad the title WQEBB to not waste WQ. */
1570                                 mlx5_empw_new(txq, &mpw, 0);
1571                                 mpw_room -= mpw.total_len;
1572                                 inl_pad = 0;
1573                                 do_inline =
1574                                         length <= txq->inline_max_packet_sz &&
1575                                         sizeof(inl_hdr) + length <= mpw_room &&
1576                                         !txq->mpw_hdr_dseg;
1577                         }
1578                         mpw.wqe->eseg.cs_flags = cs_flags;
1579                 } else {
1580                         /* Evaluate whether the next packet can be inlined.
1581                          * Inlininig is possible when:
1582                          * - length is less than configured value
1583                          * - length fits for remaining space
1584                          * - not required to fill the title WQEBB with dsegs
1585                          */
1586                         do_inline =
1587                                 length <= txq->inline_max_packet_sz &&
1588                                 inl_pad + sizeof(inl_hdr) + length <=
1589                                  mpw_room &&
1590                                 (!txq->mpw_hdr_dseg ||
1591                                  mpw.total_len >= MLX5_WQE_SIZE);
1592                 }
1593                 /* Multi-segment packets must be alone in their MPW. */
1594                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1595                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1596 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1597                         length = 0;
1598 #endif
1599                         do {
1600                                 volatile struct mlx5_wqe_data_seg *dseg;
1601
1602                                 elts_head_next =
1603                                         (elts_head + 1) & (elts_n - 1);
1604                                 assert(buf);
1605                                 (*txq->elts)[elts_head] = buf;
1606                                 dseg = mpw.data.dseg[mpw.pkts_n];
1607                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1608                                 *dseg = (struct mlx5_wqe_data_seg){
1609                                         .byte_count = htonl(DATA_LEN(buf)),
1610                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1611                                         .addr = htonll(addr),
1612                                 };
1613                                 elts_head = elts_head_next;
1614 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1615                                 length += DATA_LEN(buf);
1616 #endif
1617                                 buf = buf->next;
1618                                 ++j;
1619                                 ++mpw.pkts_n;
1620                         } while (--segs_n);
1621                         /* A multi-segmented packet takes one MPW session.
1622                          * TODO: Pack more multi-segmented packets if possible.
1623                          */
1624                         mlx5_mpw_close(txq, &mpw);
1625                         if (mpw.pkts_n < 3)
1626                                 max_wqe--;
1627                         else
1628                                 max_wqe -= 2;
1629                 } else if (do_inline) {
1630                         /* Inline packet into WQE. */
1631                         unsigned int max;
1632
1633                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1634                         assert(length == DATA_LEN(buf));
1635                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1636                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1637                         mpw.data.raw = (volatile void *)
1638                                 ((uintptr_t)mpw.data.raw + inl_pad);
1639                         max = tx_mlx5_wq_tailroom(txq,
1640                                         (void *)(uintptr_t)mpw.data.raw);
1641                         /* Copy inline header. */
1642                         mpw.data.raw = (volatile void *)
1643                                 mlx5_copy_to_wq(
1644                                           (void *)(uintptr_t)mpw.data.raw,
1645                                           &inl_hdr,
1646                                           sizeof(inl_hdr),
1647                                           (void *)(uintptr_t)txq->wqes,
1648                                           max);
1649                         max = tx_mlx5_wq_tailroom(txq,
1650                                         (void *)(uintptr_t)mpw.data.raw);
1651                         /* Copy packet data. */
1652                         mpw.data.raw = (volatile void *)
1653                                 mlx5_copy_to_wq(
1654                                           (void *)(uintptr_t)mpw.data.raw,
1655                                           (void *)addr,
1656                                           length,
1657                                           (void *)(uintptr_t)txq->wqes,
1658                                           max);
1659                         ++mpw.pkts_n;
1660                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1661                         /* No need to get completion as the entire packet is
1662                          * copied to WQ. Free the buf right away.
1663                          */
1664                         elts_head_next = elts_head;
1665                         rte_pktmbuf_free_seg(buf);
1666                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1667                         /* Add pad in the next packet if any. */
1668                         inl_pad = (((uintptr_t)mpw.data.raw +
1669                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1670                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1671                                   (uintptr_t)mpw.data.raw;
1672                 } else {
1673                         /* No inline. Load a dseg of packet pointer. */
1674                         volatile rte_v128u32_t *dseg;
1675
1676                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1677                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1678                         assert(length == DATA_LEN(buf));
1679                         if (!tx_mlx5_wq_tailroom(txq,
1680                                         (void *)((uintptr_t)mpw.data.raw
1681                                                 + inl_pad)))
1682                                 dseg = (volatile void *)txq->wqes;
1683                         else
1684                                 dseg = (volatile void *)
1685                                         ((uintptr_t)mpw.data.raw +
1686                                          inl_pad);
1687                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1688                         (*txq->elts)[elts_head] = buf;
1689                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1690                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1691                                 rte_prefetch2((void *)(addr +
1692                                                 n * RTE_CACHE_LINE_SIZE));
1693                         naddr = htonll(addr);
1694                         *dseg = (rte_v128u32_t) {
1695                                 htonl(length),
1696                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1697                                 naddr,
1698                                 naddr >> 32,
1699                         };
1700                         mpw.data.raw = (volatile void *)(dseg + 1);
1701                         mpw.total_len += (inl_pad + sizeof(*dseg));
1702                         ++j;
1703                         ++mpw.pkts_n;
1704                         mpw_room -= (inl_pad + sizeof(*dseg));
1705                         inl_pad = 0;
1706                 }
1707                 elts_head = elts_head_next;
1708 #ifdef MLX5_PMD_SOFT_COUNTERS
1709                 /* Increment sent bytes counter. */
1710                 txq->stats.obytes += length;
1711 #endif
1712                 ++i;
1713         } while (i < pkts_n);
1714         /* Take a shortcut if nothing must be sent. */
1715         if (unlikely(i == 0))
1716                 return 0;
1717         /* Check whether completion threshold has been reached. */
1718         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1719                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1720                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1721                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1722
1723                 /* Request completion on last WQE. */
1724                 wqe->ctrl[2] = htonl(8);
1725                 /* Save elts_head in unused "immediate" field of WQE. */
1726                 wqe->ctrl[3] = elts_head;
1727                 txq->elts_comp = 0;
1728                 txq->mpw_comp = txq->wqe_ci;
1729                 txq->cq_pi++;
1730         } else {
1731                 txq->elts_comp += j;
1732         }
1733 #ifdef MLX5_PMD_SOFT_COUNTERS
1734         /* Increment sent packets counter. */
1735         txq->stats.opackets += i;
1736 #endif
1737         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1738                 mlx5_empw_close(txq, &mpw);
1739         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1740                 mlx5_mpw_close(txq, &mpw);
1741         /* Ring QP doorbell. */
1742         mlx5_tx_dbrec(txq, mpw.wqe);
1743         txq->elts_head = elts_head;
1744         return i;
1745 }
1746
1747 /**
1748  * Translate RX completion flags to packet type.
1749  *
1750  * @param[in] cqe
1751  *   Pointer to CQE.
1752  *
1753  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1754  *
1755  * @return
1756  *   Packet type for struct rte_mbuf.
1757  */
1758 static inline uint32_t
1759 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1760 {
1761         uint32_t pkt_type;
1762         uint16_t flags = ntohs(cqe->hdr_type_etc);
1763
1764         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1765                 pkt_type =
1766                         TRANSPOSE(flags,
1767                                   MLX5_CQE_RX_IPV4_PACKET,
1768                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1769                         TRANSPOSE(flags,
1770                                   MLX5_CQE_RX_IPV6_PACKET,
1771                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1772                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1773                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1774                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1775         } else {
1776                 pkt_type =
1777                         TRANSPOSE(flags,
1778                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1779                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1780                         TRANSPOSE(flags,
1781                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1782                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1783         }
1784         return pkt_type;
1785 }
1786
1787 /**
1788  * Get size of the next packet for a given CQE. For compressed CQEs, the
1789  * consumer index is updated only once all packets of the current one have
1790  * been processed.
1791  *
1792  * @param rxq
1793  *   Pointer to RX queue.
1794  * @param cqe
1795  *   CQE to process.
1796  * @param[out] rss_hash
1797  *   Packet RSS Hash result.
1798  *
1799  * @return
1800  *   Packet size in bytes (0 if there is none), -1 in case of completion
1801  *   with error.
1802  */
1803 static inline int
1804 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1805                  uint16_t cqe_cnt, uint32_t *rss_hash)
1806 {
1807         struct rxq_zip *zip = &rxq->zip;
1808         uint16_t cqe_n = cqe_cnt + 1;
1809         int len = 0;
1810         uint16_t idx, end;
1811
1812         /* Process compressed data in the CQE and mini arrays. */
1813         if (zip->ai) {
1814                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1815                         (volatile struct mlx5_mini_cqe8 (*)[8])
1816                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1817
1818                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1819                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1820                 if ((++zip->ai & 7) == 0) {
1821                         /* Invalidate consumed CQEs */
1822                         idx = zip->ca;
1823                         end = zip->na;
1824                         while (idx != end) {
1825                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1826                                         MLX5_CQE_INVALIDATE;
1827                                 ++idx;
1828                         }
1829                         /*
1830                          * Increment consumer index to skip the number of
1831                          * CQEs consumed. Hardware leaves holes in the CQ
1832                          * ring for software use.
1833                          */
1834                         zip->ca = zip->na;
1835                         zip->na += 8;
1836                 }
1837                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1838                         /* Invalidate the rest */
1839                         idx = zip->ca;
1840                         end = zip->cq_ci;
1841
1842                         while (idx != end) {
1843                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1844                                         MLX5_CQE_INVALIDATE;
1845                                 ++idx;
1846                         }
1847                         rxq->cq_ci = zip->cq_ci;
1848                         zip->ai = 0;
1849                 }
1850         /* No compressed data, get next CQE and verify if it is compressed. */
1851         } else {
1852                 int ret;
1853                 int8_t op_own;
1854
1855                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1856                 if (unlikely(ret == 1))
1857                         return 0;
1858                 ++rxq->cq_ci;
1859                 op_own = cqe->op_own;
1860                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1861                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1862                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1863                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1864                                                           cqe_cnt]);
1865
1866                         /* Fix endianness. */
1867                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1868                         /*
1869                          * Current mini array position is the one returned by
1870                          * check_cqe64().
1871                          *
1872                          * If completion comprises several mini arrays, as a
1873                          * special case the second one is located 7 CQEs after
1874                          * the initial CQE instead of 8 for subsequent ones.
1875                          */
1876                         zip->ca = rxq->cq_ci;
1877                         zip->na = zip->ca + 7;
1878                         /* Compute the next non compressed CQE. */
1879                         --rxq->cq_ci;
1880                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1881                         /* Get packet size to return. */
1882                         len = ntohl((*mc)[0].byte_cnt);
1883                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1884                         zip->ai = 1;
1885                         /* Prefetch all the entries to be invalidated */
1886                         idx = zip->ca;
1887                         end = zip->cq_ci;
1888                         while (idx != end) {
1889                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1890                                 ++idx;
1891                         }
1892                 } else {
1893                         len = ntohl(cqe->byte_cnt);
1894                         *rss_hash = ntohl(cqe->rx_hash_res);
1895                 }
1896                 /* Error while receiving packet. */
1897                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1898                         return -1;
1899         }
1900         return len;
1901 }
1902
1903 /**
1904  * Translate RX completion flags to offload flags.
1905  *
1906  * @param[in] rxq
1907  *   Pointer to RX queue structure.
1908  * @param[in] cqe
1909  *   Pointer to CQE.
1910  *
1911  * @return
1912  *   Offload flags (ol_flags) for struct rte_mbuf.
1913  */
1914 static inline uint32_t
1915 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1916 {
1917         uint32_t ol_flags = 0;
1918         uint16_t flags = ntohs(cqe->hdr_type_etc);
1919
1920         ol_flags =
1921                 TRANSPOSE(flags,
1922                           MLX5_CQE_RX_L3_HDR_VALID,
1923                           PKT_RX_IP_CKSUM_GOOD) |
1924                 TRANSPOSE(flags,
1925                           MLX5_CQE_RX_L4_HDR_VALID,
1926                           PKT_RX_L4_CKSUM_GOOD);
1927         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1928                 ol_flags |=
1929                         TRANSPOSE(flags,
1930                                   MLX5_CQE_RX_L3_HDR_VALID,
1931                                   PKT_RX_IP_CKSUM_GOOD) |
1932                         TRANSPOSE(flags,
1933                                   MLX5_CQE_RX_L4_HDR_VALID,
1934                                   PKT_RX_L4_CKSUM_GOOD);
1935         return ol_flags;
1936 }
1937
1938 /**
1939  * DPDK callback for RX.
1940  *
1941  * @param dpdk_rxq
1942  *   Generic pointer to RX queue structure.
1943  * @param[out] pkts
1944  *   Array to store received packets.
1945  * @param pkts_n
1946  *   Maximum number of packets in array.
1947  *
1948  * @return
1949  *   Number of packets successfully received (<= pkts_n).
1950  */
1951 uint16_t
1952 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1953 {
1954         struct rxq *rxq = dpdk_rxq;
1955         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1956         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1957         const unsigned int sges_n = rxq->sges_n;
1958         struct rte_mbuf *pkt = NULL;
1959         struct rte_mbuf *seg = NULL;
1960         volatile struct mlx5_cqe *cqe =
1961                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1962         unsigned int i = 0;
1963         unsigned int rq_ci = rxq->rq_ci << sges_n;
1964         int len = 0; /* keep its value across iterations. */
1965
1966         while (pkts_n) {
1967                 unsigned int idx = rq_ci & wqe_cnt;
1968                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1969                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1970                 uint32_t rss_hash_res = 0;
1971
1972                 if (pkt)
1973                         NEXT(seg) = rep;
1974                 seg = rep;
1975                 rte_prefetch0(seg);
1976                 rte_prefetch0(cqe);
1977                 rte_prefetch0(wqe);
1978                 rep = rte_mbuf_raw_alloc(rxq->mp);
1979                 if (unlikely(rep == NULL)) {
1980                         ++rxq->stats.rx_nombuf;
1981                         if (!pkt) {
1982                                 /*
1983                                  * no buffers before we even started,
1984                                  * bail out silently.
1985                                  */
1986                                 break;
1987                         }
1988                         while (pkt != seg) {
1989                                 assert(pkt != (*rxq->elts)[idx]);
1990                                 rep = NEXT(pkt);
1991                                 NEXT(pkt) = NULL;
1992                                 NB_SEGS(pkt) = 1;
1993                                 rte_mbuf_raw_free(pkt);
1994                                 pkt = rep;
1995                         }
1996                         break;
1997                 }
1998                 if (!pkt) {
1999                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2000                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2001                                                &rss_hash_res);
2002                         if (!len) {
2003                                 rte_mbuf_raw_free(rep);
2004                                 break;
2005                         }
2006                         if (unlikely(len == -1)) {
2007                                 /* RX error, packet is likely too large. */
2008                                 rte_mbuf_raw_free(rep);
2009                                 ++rxq->stats.idropped;
2010                                 goto skip;
2011                         }
2012                         pkt = seg;
2013                         assert(len >= (rxq->crc_present << 2));
2014                         /* Update packet information. */
2015                         pkt->packet_type = 0;
2016                         pkt->ol_flags = 0;
2017                         if (rss_hash_res && rxq->rss_hash) {
2018                                 pkt->hash.rss = rss_hash_res;
2019                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2020                         }
2021                         if (rxq->mark &&
2022                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2023                                 pkt->ol_flags |= PKT_RX_FDIR;
2024                                 if (cqe->sop_drop_qpn !=
2025                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2026                                         uint32_t mark = cqe->sop_drop_qpn;
2027
2028                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2029                                         pkt->hash.fdir.hi =
2030                                                 mlx5_flow_mark_get(mark);
2031                                 }
2032                         }
2033                         if (rxq->csum | rxq->csum_l2tun) {
2034                                 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2035                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2036                         }
2037                         if (rxq->vlan_strip &&
2038                             (cqe->hdr_type_etc &
2039                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2040                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2041                                         PKT_RX_VLAN_STRIPPED;
2042                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2043                         }
2044                         if (rxq->crc_present)
2045                                 len -= ETHER_CRC_LEN;
2046                         PKT_LEN(pkt) = len;
2047                 }
2048                 DATA_LEN(rep) = DATA_LEN(seg);
2049                 PKT_LEN(rep) = PKT_LEN(seg);
2050                 SET_DATA_OFF(rep, DATA_OFF(seg));
2051                 PORT(rep) = PORT(seg);
2052                 (*rxq->elts)[idx] = rep;
2053                 /*
2054                  * Fill NIC descriptor with the new buffer.  The lkey and size
2055                  * of the buffers are already known, only the buffer address
2056                  * changes.
2057                  */
2058                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2059                 if (len > DATA_LEN(seg)) {
2060                         len -= DATA_LEN(seg);
2061                         ++NB_SEGS(pkt);
2062                         ++rq_ci;
2063                         continue;
2064                 }
2065                 DATA_LEN(seg) = len;
2066 #ifdef MLX5_PMD_SOFT_COUNTERS
2067                 /* Increment bytes counter. */
2068                 rxq->stats.ibytes += PKT_LEN(pkt);
2069 #endif
2070                 /* Return packet. */
2071                 *(pkts++) = pkt;
2072                 pkt = NULL;
2073                 --pkts_n;
2074                 ++i;
2075 skip:
2076                 /* Align consumer index to the next stride. */
2077                 rq_ci >>= sges_n;
2078                 ++rq_ci;
2079                 rq_ci <<= sges_n;
2080         }
2081         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2082                 return 0;
2083         /* Update the consumer index. */
2084         rxq->rq_ci = rq_ci >> sges_n;
2085         rte_wmb();
2086         *rxq->cq_db = htonl(rxq->cq_ci);
2087         rte_wmb();
2088         *rxq->rq_db = htonl(rxq->rq_ci);
2089 #ifdef MLX5_PMD_SOFT_COUNTERS
2090         /* Increment packets counter. */
2091         rxq->stats.ipackets += i;
2092 #endif
2093         return i;
2094 }
2095
2096 /**
2097  * Dummy DPDK callback for TX.
2098  *
2099  * This function is used to temporarily replace the real callback during
2100  * unsafe control operations on the queue, or in case of error.
2101  *
2102  * @param dpdk_txq
2103  *   Generic pointer to TX queue structure.
2104  * @param[in] pkts
2105  *   Packets to transmit.
2106  * @param pkts_n
2107  *   Number of packets in array.
2108  *
2109  * @return
2110  *   Number of packets successfully transmitted (<= pkts_n).
2111  */
2112 uint16_t
2113 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2114 {
2115         (void)dpdk_txq;
2116         (void)pkts;
2117         (void)pkts_n;
2118         return 0;
2119 }
2120
2121 /**
2122  * Dummy DPDK callback for RX.
2123  *
2124  * This function is used to temporarily replace the real callback during
2125  * unsafe control operations on the queue, or in case of error.
2126  *
2127  * @param dpdk_rxq
2128  *   Generic pointer to RX queue structure.
2129  * @param[out] pkts
2130  *   Array to store received packets.
2131  * @param pkts_n
2132  *   Maximum number of packets in array.
2133  *
2134  * @return
2135  *   Number of packets successfully received (<= pkts_n).
2136  */
2137 uint16_t
2138 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2139 {
2140         (void)dpdk_rxq;
2141         (void)pkts;
2142         (void)pkts_n;
2143         return 0;
2144 }