drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Manage TX completions.
 199  *
 200  * When sending a burst, mlx5_tx_burst() posts several WRs.
 201  *
 202  * @param txq
 203  *   Pointer to TX queue structure.
 204  */
 205 static inline void
 206 txq_complete(struct txq *txq)
 207 {
 208         const unsigned int elts_n = 1 << txq->elts_n;
 209         const unsigned int cqe_n = 1 << txq->cqe_n;
 210         const unsigned int cqe_cnt = cqe_n - 1;
 211         uint16_t elts_free = txq->elts_tail;
 212         uint16_t elts_tail;
 213         uint16_t cq_ci = txq->cq_ci;
 214         volatile struct mlx5_cqe *cqe = NULL;
 215         volatile struct mlx5_wqe_ctrl *ctrl;
 216
 217         do {
 218                 volatile struct mlx5_cqe *tmp;
 219
 220                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 221                 if (check_cqe(tmp, cqe_n, cq_ci))
 222                         break;
 223                 cqe = tmp;
 224 #ifndef NDEBUG
 225                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 226                         if (!check_cqe_seen(cqe))
 227                                 ERROR("unexpected compressed CQE, TX stopped");
 228                         return;
 229                 }
 230                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 231                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 232                         if (!check_cqe_seen(cqe))
 233                                 ERROR("unexpected error CQE, TX stopped");
 234                         return;
 235                 }
 236 #endif /* NDEBUG */
 237                 ++cq_ci;
 238         } while (1);
 239         if (unlikely(cqe == NULL))
 240                 return;
 241         txq->wqe_pi = ntohs(cqe->wqe_counter);
 242         ctrl = (volatile struct mlx5_wqe_ctrl *)
 243                 tx_mlx5_wqe(txq, txq->wqe_pi);
 244         elts_tail = ctrl->ctrl3;
 245         assert(elts_tail < (1 << txq->wqe_n));
 246         /* Free buffers. */
 247         while (elts_free != elts_tail) {
 248                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 249                 unsigned int elts_free_next =
 250                         (elts_free + 1) & (elts_n - 1);
 251                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 252
 253 #ifndef NDEBUG
 254                 /* Poisoning. */
 255                 memset(&(*txq->elts)[elts_free],
 256                        0x66,
 257                        sizeof((*txq->elts)[elts_free]));
 258 #endif
 259                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 260                 /* Only one segment needs to be freed. */
 261                 rte_pktmbuf_free_seg(elt);
 262                 elts_free = elts_free_next;
 263         }
 264         txq->cq_ci = cq_ci;
 265         txq->elts_tail = elts_tail;
 266         /* Update the consumer index. */
 267         rte_wmb();
 268         *txq->cq_db = htonl(cq_ci);
 269 }
 270
 271 /**
 272  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 273  * the cloned mbuf is allocated is returned instead.
 274  *
 275  * @param buf
 276  *   Pointer to mbuf.
 277  *
 278  * @return
 279  *   Memory pool where data is located for given mbuf.
 280  */
 281 static struct rte_mempool *
 282 txq_mb2mp(struct rte_mbuf *buf)
 283 {
 284         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 285                 return rte_mbuf_from_indirect(buf)->pool;
 286         return buf->pool;
 287 }
 288
 289 /**
 290  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 291  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 292  * remove an entry first.
 293  *
 294  * @param txq
 295  *   Pointer to TX queue structure.
 296  * @param[in] mp
 297  *   Memory Pool for which a Memory Region lkey must be returned.
 298  *
 299  * @return
 300  *   mr->lkey on success, (uint32_t)-1 on failure.
 301  */
 302 static inline uint32_t
 303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 304 {
 305         unsigned int i;
 306         uint32_t lkey = (uint32_t)-1;
 307
 308         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 309                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 310                         /* Unknown MP, add a new MR for it. */
 311                         break;
 312                 }
 313                 if (txq->mp2mr[i].mp == mp) {
 314                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 315                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 316                                txq->mp2mr[i].lkey);
 317                         lkey = txq->mp2mr[i].lkey;
 318                         break;
 319                 }
 320         }
 321         if (unlikely(lkey == (uint32_t)-1))
 322                 lkey = txq_mp2mr_reg(txq, mp, i);
 323         return lkey;
 324 }
 325
 326 /**
 327  * Ring TX queue doorbell.
 328  *
 329  * @param txq
 330  *   Pointer to TX queue structure.
 331  * @param wqe
 332  *   Pointer to the last WQE posted in the NIC.
 333  */
 334 static inline void
 335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 336 {
 337         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 338         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 339
 340         rte_wmb();
 341         *txq->qp_db = htonl(txq->wqe_ci);
 342         /* Ensure ordering between DB record and BF copy. */
 343         rte_wmb();
 344         *dst = *src;
 345 }
 346
 347 /**
 348  * DPDK callback to check the status of a tx descriptor.
 349  *
 350  * @param tx_queue
 351  *   The tx queue.
 352  * @param[in] offset
 353  *   The index of the descriptor in the ring.
 354  *
 355  * @return
 356  *   The status of the tx descriptor.
 357  */
 358 int
 359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 360 {
 361         struct txq *txq = tx_queue;
 362         const unsigned int elts_n = 1 << txq->elts_n;
 363         const unsigned int elts_cnt = elts_n - 1;
 364         unsigned int used;
 365
 366         txq_complete(txq);
 367         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 368         if (offset < used)
 369                 return RTE_ETH_TX_DESC_FULL;
 370         return RTE_ETH_TX_DESC_DONE;
 371 }
 372
 373 /**
 374  * DPDK callback to check the status of a rx descriptor.
 375  *
 376  * @param rx_queue
 377  *   The rx queue.
 378  * @param[in] offset
 379  *   The index of the descriptor in the ring.
 380  *
 381  * @return
 382  *   The status of the tx descriptor.
 383  */
 384 int
 385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 386 {
 387         struct rxq *rxq = rx_queue;
 388         struct rxq_zip *zip = &rxq->zip;
 389         volatile struct mlx5_cqe *cqe;
 390         const unsigned int cqe_n = (1 << rxq->cqe_n);
 391         const unsigned int cqe_cnt = cqe_n - 1;
 392         unsigned int cq_ci;
 393         unsigned int used;
 394
 395         /* if we are processing a compressed cqe */
 396         if (zip->ai) {
 397                 used = zip->cqe_cnt - zip->ca;
 398                 cq_ci = zip->cq_ci;
 399         } else {
 400                 used = 0;
 401                 cq_ci = rxq->cq_ci;
 402         }
 403         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 404         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 405                 int8_t op_own;
 406                 unsigned int n;
 407
 408                 op_own = cqe->op_own;
 409                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 410                         n = ntohl(cqe->byte_cnt);
 411                 else
 412                         n = 1;
 413                 cq_ci += n;
 414                 used += n;
 415                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 416         }
 417         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 418         if (offset < used)
 419                 return RTE_ETH_RX_DESC_DONE;
 420         return RTE_ETH_RX_DESC_AVAIL;
 421 }
 422
 423 /**
 424  * DPDK callback for TX.
 425  *
 426  * @param dpdk_txq
 427  *   Generic pointer to TX queue structure.
 428  * @param[in] pkts
 429  *   Packets to transmit.
 430  * @param pkts_n
 431  *   Number of packets in array.
 432  *
 433  * @return
 434  *   Number of packets successfully transmitted (<= pkts_n).
 435  */
 436 uint16_t
 437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 438 {
 439         struct txq *txq = (struct txq *)dpdk_txq;
 440         uint16_t elts_head = txq->elts_head;
 441         const unsigned int elts_n = 1 << txq->elts_n;
 442         unsigned int i = 0;
 443         unsigned int j = 0;
 444         unsigned int k = 0;
 445         unsigned int max;
 446         uint16_t max_wqe;
 447         unsigned int comp;
 448         volatile struct mlx5_wqe_v *wqe = NULL;
 449         unsigned int segs_n = 0;
 450         struct rte_mbuf *buf = NULL;
 451         uint8_t *raw;
 452
 453         if (unlikely(!pkts_n))
 454                 return 0;
 455         /* Prefetch first packet cacheline. */
 456         rte_prefetch0(*pkts);
 457         /* Start processing. */
 458         txq_complete(txq);
 459         max = (elts_n - (elts_head - txq->elts_tail));
 460         if (max > elts_n)
 461                 max -= elts_n;
 462         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 463         if (unlikely(!max_wqe))
 464                 return 0;
 465         do {
 466                 volatile rte_v128u32_t *dseg = NULL;
 467                 uint32_t length;
 468                 unsigned int ds = 0;
 469                 uintptr_t addr;
 470                 uint64_t naddr;
 471                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 472                 uint16_t tso_header_sz = 0;
 473                 uint16_t ehdr;
 474                 uint8_t cs_flags = 0;
 475                 uint64_t tso = 0;
 476 #ifdef MLX5_PMD_SOFT_COUNTERS
 477                 uint32_t total_length = 0;
 478 #endif
 479
 480                 /* first_seg */
 481                 buf = *(pkts++);
 482                 segs_n = buf->nb_segs;
 483                 /*
 484                  * Make sure there is enough room to store this packet and
 485                  * that one ring entry remains unused.
 486                  */
 487                 assert(segs_n);
 488                 if (max < segs_n + 1)
 489                         break;
 490                 max -= segs_n;
 491                 --segs_n;
 492                 if (!segs_n)
 493                         --pkts_n;
 494                 if (unlikely(--max_wqe == 0))
 495                         break;
 496                 wqe = (volatile struct mlx5_wqe_v *)
 497                         tx_mlx5_wqe(txq, txq->wqe_ci);
 498                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 499                 if (pkts_n > 1)
 500                         rte_prefetch0(*pkts);
 501                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 502                 length = DATA_LEN(buf);
 503                 ehdr = (((uint8_t *)addr)[1] << 8) |
 504                        ((uint8_t *)addr)[0];
 505 #ifdef MLX5_PMD_SOFT_COUNTERS
 506                 total_length = length;
 507 #endif
 508                 assert(length >= MLX5_WQE_DWORD_SIZE);
 509                 /* Update element. */
 510                 (*txq->elts)[elts_head] = buf;
 511                 elts_head = (elts_head + 1) & (elts_n - 1);
 512                 /* Prefetch next buffer data. */
 513                 if (pkts_n > 1) {
 514                         volatile void *pkt_addr;
 515
 516                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 517                         rte_prefetch0(pkt_addr);
 518                 }
 519                 /* Should we enable HW CKSUM offload */
 520                 if (buf->ol_flags &
 521                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 522                         const uint64_t is_tunneled = buf->ol_flags &
 523                                                      (PKT_TX_TUNNEL_GRE |
 524                                                       PKT_TX_TUNNEL_VXLAN);
 525
 526                         if (is_tunneled && txq->tunnel_en) {
 527                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 528                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 529                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 530                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 531                         } else {
 532                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 533                                            MLX5_ETH_WQE_L4_CSUM;
 534                         }
 535                 }
 536                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 537                 /* Replace the Ethernet type by the VLAN if necessary. */
 538                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 539                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 540                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 541
 542                         addr += 2;
 543                         length -= 2;
 544                         /* Copy Destination and source mac address. */
 545                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 546                         /* Copy VLAN. */
 547                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 548                         /* Copy missing two bytes to end the DSeg. */
 549                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 550                                ((uint8_t *)addr) + len, 2);
 551                         addr += len + 2;
 552                         length -= (len + 2);
 553                 } else {
 554                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 555                                MLX5_WQE_DWORD_SIZE);
 556                         length -= pkt_inline_sz;
 557                         addr += pkt_inline_sz;
 558                 }
 559                 if (txq->tso_en) {
 560                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 561                         if (tso) {
 562                                 uintptr_t end = (uintptr_t)
 563                                                 (((uintptr_t)txq->wqes) +
 564                                                 (1 << txq->wqe_n) *
 565                                                 MLX5_WQE_SIZE);
 566                                 unsigned int copy_b;
 567                                 uint8_t vlan_sz = (buf->ol_flags &
 568                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 569                                 const uint64_t is_tunneled =
 570                                                         buf->ol_flags &
 571                                                         (PKT_TX_TUNNEL_GRE |
 572                                                          PKT_TX_TUNNEL_VXLAN);
 573
 574                                 tso_header_sz = buf->l2_len + vlan_sz +
 575                                                 buf->l3_len + buf->l4_len;
 576
 577                                 if (is_tunneled && txq->tunnel_en) {
 578                                         tso_header_sz += buf->outer_l2_len +
 579                                                          buf->outer_l3_len;
 580                                 }
 581                                 if (unlikely(tso_header_sz >
 582                                              MLX5_MAX_TSO_HEADER))
 583                                         break;
 584                                 copy_b = tso_header_sz - pkt_inline_sz;
 585                                 /* First seg must contain all headers. */
 586                                 assert(copy_b <= length);
 587                                 raw += MLX5_WQE_DWORD_SIZE;
 588                                 if (copy_b &&
 589                                    ((end - (uintptr_t)raw) > copy_b)) {
 590                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 591                                                       1 + 3) / 4;
 592
 593                                         if (unlikely(max_wqe < n))
 594                                                 break;
 595                                         max_wqe -= n;
 596                                         rte_memcpy((void *)raw,
 597                                                    (void *)addr, copy_b);
 598                                         addr += copy_b;
 599                                         length -= copy_b;
 600                                         pkt_inline_sz += copy_b;
 601                                         /*
 602                                          * Another DWORD will be added
 603                                          * in the inline part.
 604                                          */
 605                                         raw += MLX5_WQE_DS(copy_b) *
 606                                                MLX5_WQE_DWORD_SIZE -
 607                                                MLX5_WQE_DWORD_SIZE;
 608                                 } else {
 609                                         /* NOP WQE. */
 610                                         wqe->ctrl = (rte_v128u32_t){
 611                                                      htonl(txq->wqe_ci << 8),
 612                                                      htonl(txq->qp_num_8s | 1),
 613                                                      0,
 614                                                      0,
 615                                         };
 616                                         ds = 1;
 617                                         total_length = 0;
 618                                         pkts--;
 619                                         pkts_n++;
 620                                         elts_head = (elts_head - 1) &
 621                                                     (elts_n - 1);
 622                                         k++;
 623                                         goto next_wqe;
 624                                 }
 625                         }
 626                 }
 627                 /* Inline if enough room. */
 628                 if (txq->inline_en || tso) {
 629                         uintptr_t end = (uintptr_t)
 630                                 (((uintptr_t)txq->wqes) +
 631                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 632                         unsigned int max_inline = txq->max_inline *
 633                                                   RTE_CACHE_LINE_SIZE -
 634                                                   (pkt_inline_sz - 2);
 635                         uintptr_t addr_end = (addr + max_inline) &
 636                                              ~(RTE_CACHE_LINE_SIZE - 1);
 637                         unsigned int copy_b = (addr_end > addr) ?
 638                                 RTE_MIN((addr_end - addr), length) :
 639                                 0;
 640
 641                         raw += MLX5_WQE_DWORD_SIZE;
 642                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 643                                 /*
 644                                  * One Dseg remains in the current WQE.  To
 645                                  * keep the computation positive, it is
 646                                  * removed after the bytes to Dseg conversion.
 647                                  */
 648                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 649
 650                                 if (unlikely(max_wqe < n))
 651                                         break;
 652                                 max_wqe -= n;
 653                                 if (tso) {
 654                                         uint32_t inl =
 655                                                 htonl(copy_b | MLX5_INLINE_SEG);
 656
 657                                         pkt_inline_sz =
 658                                                 MLX5_WQE_DS(tso_header_sz) *
 659                                                 MLX5_WQE_DWORD_SIZE;
 660                                         rte_memcpy((void *)raw,
 661                                                    (void *)&inl, sizeof(inl));
 662                                         raw += sizeof(inl);
 663                                         pkt_inline_sz += sizeof(inl);
 664                                 }
 665                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 666                                 addr += copy_b;
 667                                 length -= copy_b;
 668                                 pkt_inline_sz += copy_b;
 669                         }
 670                         /*
 671                          * 2 DWORDs consumed by the WQE header + ETH segment +
 672                          * the size of the inline part of the packet.
 673                          */
 674                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 675                         if (length > 0) {
 676                                 if (ds % (MLX5_WQE_SIZE /
 677                                           MLX5_WQE_DWORD_SIZE) == 0) {
 678                                         if (unlikely(--max_wqe == 0))
 679                                                 break;
 680                                         dseg = (volatile rte_v128u32_t *)
 681                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 682                                                            ds / 4);
 683                                 } else {
 684                                         dseg = (volatile rte_v128u32_t *)
 685                                                 ((uintptr_t)wqe +
 686                                                  (ds * MLX5_WQE_DWORD_SIZE));
 687                                 }
 688                                 goto use_dseg;
 689                         } else if (!segs_n) {
 690                                 goto next_pkt;
 691                         } else {
 692                                 /* dseg will be advance as part of next_seg */
 693                                 dseg = (volatile rte_v128u32_t *)
 694                                         ((uintptr_t)wqe +
 695                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 696                                 goto next_seg;
 697                         }
 698                 } else {
 699                         /*
 700                          * No inline has been done in the packet, only the
 701                          * Ethernet Header as been stored.
 702                          */
 703                         dseg = (volatile rte_v128u32_t *)
 704                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 705                         ds = 3;
 706 use_dseg:
 707                         /* Add the remaining packet as a simple ds. */
 708                         naddr = htonll(addr);
 709                         *dseg = (rte_v128u32_t){
 710                                 htonl(length),
 711                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 712                                 naddr,
 713                                 naddr >> 32,
 714                         };
 715                         ++ds;
 716                         if (!segs_n)
 717                                 goto next_pkt;
 718                 }
 719 next_seg:
 720                 assert(buf);
 721                 assert(ds);
 722                 assert(wqe);
 723                 /*
 724                  * Spill on next WQE when the current one does not have
 725                  * enough room left. Size of WQE must a be a multiple
 726                  * of data segment size.
 727                  */
 728                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 729                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 730                         if (unlikely(--max_wqe == 0))
 731                                 break;
 732                         dseg = (volatile rte_v128u32_t *)
 733                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 734                         rte_prefetch0(tx_mlx5_wqe(txq,
 735                                                   txq->wqe_ci + ds / 4 + 1));
 736                 } else {
 737                         ++dseg;
 738                 }
 739                 ++ds;
 740                 buf = buf->next;
 741                 assert(buf);
 742                 length = DATA_LEN(buf);
 743 #ifdef MLX5_PMD_SOFT_COUNTERS
 744                 total_length += length;
 745 #endif
 746                 /* Store segment information. */
 747                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 748                 *dseg = (rte_v128u32_t){
 749                         htonl(length),
 750                         txq_mp2mr(txq, txq_mb2mp(buf)),
 751                         naddr,
 752                         naddr >> 32,
 753                 };
 754                 (*txq->elts)[elts_head] = buf;
 755                 elts_head = (elts_head + 1) & (elts_n - 1);
 756                 ++j;
 757                 --segs_n;
 758                 if (segs_n)
 759                         goto next_seg;
 760                 else
 761                         --pkts_n;
 762 next_pkt:
 763                 ++i;
 764                 /* Initialize known and common part of the WQE structure. */
 765                 if (tso) {
 766                         wqe->ctrl = (rte_v128u32_t){
 767                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 768                                 htonl(txq->qp_num_8s | ds),
 769                                 0,
 770                                 0,
 771                         };
 772                         wqe->eseg = (rte_v128u32_t){
 773                                 0,
 774                                 cs_flags | (htons(buf->tso_segsz) << 16),
 775                                 0,
 776                                 (ehdr << 16) | htons(tso_header_sz),
 777                         };
 778                 } else {
 779                         wqe->ctrl = (rte_v128u32_t){
 780                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 781                                 htonl(txq->qp_num_8s | ds),
 782                                 0,
 783                                 0,
 784                         };
 785                         wqe->eseg = (rte_v128u32_t){
 786                                 0,
 787                                 cs_flags,
 788                                 0,
 789                                 (ehdr << 16) | htons(pkt_inline_sz),
 790                         };
 791                 }
 792 next_wqe:
 793                 txq->wqe_ci += (ds + 3) / 4;
 794 #ifdef MLX5_PMD_SOFT_COUNTERS
 795                 /* Increment sent bytes counter. */
 796                 txq->stats.obytes += total_length;
 797 #endif
 798         } while (pkts_n);
 799         /* Take a shortcut if nothing must be sent. */
 800         if (unlikely((i + k) == 0))
 801                 return 0;
 802         /* Check whether completion threshold has been reached. */
 803         comp = txq->elts_comp + i + j + k;
 804         if (comp >= MLX5_TX_COMP_THRESH) {
 805                 volatile struct mlx5_wqe_ctrl *w =
 806                         (volatile struct mlx5_wqe_ctrl *)wqe;
 807
 808                 /* Request completion on last WQE. */
 809                 w->ctrl2 = htonl(8);
 810                 /* Save elts_head in unused "immediate" field of WQE. */
 811                 w->ctrl3 = elts_head;
 812                 txq->elts_comp = 0;
 813         } else {
 814                 txq->elts_comp = comp;
 815         }
 816 #ifdef MLX5_PMD_SOFT_COUNTERS
 817         /* Increment sent packets counter. */
 818         txq->stats.opackets += i;
 819 #endif
 820         /* Ring QP doorbell. */
 821         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
 822         txq->elts_head = elts_head;
 823         return i;
 824 }
 825
 826 /**
 827  * Open a MPW session.
 828  *
 829  * @param txq
 830  *   Pointer to TX queue structure.
 831  * @param mpw
 832  *   Pointer to MPW session structure.
 833  * @param length
 834  *   Packet length.
 835  */
 836 static inline void
 837 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 838 {
 839         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 840         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 841                 (volatile struct mlx5_wqe_data_seg (*)[])
 842                 tx_mlx5_wqe(txq, idx + 1);
 843
 844         mpw->state = MLX5_MPW_STATE_OPENED;
 845         mpw->pkts_n = 0;
 846         mpw->len = length;
 847         mpw->total_len = 0;
 848         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 849         mpw->wqe->eseg.mss = htons(length);
 850         mpw->wqe->eseg.inline_hdr_sz = 0;
 851         mpw->wqe->eseg.rsvd0 = 0;
 852         mpw->wqe->eseg.rsvd1 = 0;
 853         mpw->wqe->eseg.rsvd2 = 0;
 854         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 855                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 856         mpw->wqe->ctrl[2] = 0;
 857         mpw->wqe->ctrl[3] = 0;
 858         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 859                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 860         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 861                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 862         mpw->data.dseg[2] = &(*dseg)[0];
 863         mpw->data.dseg[3] = &(*dseg)[1];
 864         mpw->data.dseg[4] = &(*dseg)[2];
 865 }
 866
 867 /**
 868  * Close a MPW session.
 869  *
 870  * @param txq
 871  *   Pointer to TX queue structure.
 872  * @param mpw
 873  *   Pointer to MPW session structure.
 874  */
 875 static inline void
 876 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 877 {
 878         unsigned int num = mpw->pkts_n;
 879
 880         /*
 881          * Store size in multiple of 16 bytes. Control and Ethernet segments
 882          * count as 2.
 883          */
 884         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 885         mpw->state = MLX5_MPW_STATE_CLOSED;
 886         if (num < 3)
 887                 ++txq->wqe_ci;
 888         else
 889                 txq->wqe_ci += 2;
 890         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 891         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 892 }
 893
 894 /**
 895  * DPDK callback for TX with MPW support.
 896  *
 897  * @param dpdk_txq
 898  *   Generic pointer to TX queue structure.
 899  * @param[in] pkts
 900  *   Packets to transmit.
 901  * @param pkts_n
 902  *   Number of packets in array.
 903  *
 904  * @return
 905  *   Number of packets successfully transmitted (<= pkts_n).
 906  */
 907 uint16_t
 908 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 909 {
 910         struct txq *txq = (struct txq *)dpdk_txq;
 911         uint16_t elts_head = txq->elts_head;
 912         const unsigned int elts_n = 1 << txq->elts_n;
 913         unsigned int i = 0;
 914         unsigned int j = 0;
 915         unsigned int max;
 916         uint16_t max_wqe;
 917         unsigned int comp;
 918         struct mlx5_mpw mpw = {
 919                 .state = MLX5_MPW_STATE_CLOSED,
 920         };
 921
 922         if (unlikely(!pkts_n))
 923                 return 0;
 924         /* Prefetch first packet cacheline. */
 925         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 926         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 927         /* Start processing. */
 928         txq_complete(txq);
 929         max = (elts_n - (elts_head - txq->elts_tail));
 930         if (max > elts_n)
 931                 max -= elts_n;
 932         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 933         if (unlikely(!max_wqe))
 934                 return 0;
 935         do {
 936                 struct rte_mbuf *buf = *(pkts++);
 937                 unsigned int elts_head_next;
 938                 uint32_t length;
 939                 unsigned int segs_n = buf->nb_segs;
 940                 uint32_t cs_flags = 0;
 941
 942                 /*
 943                  * Make sure there is enough room to store this packet and
 944                  * that one ring entry remains unused.
 945                  */
 946                 assert(segs_n);
 947                 if (max < segs_n + 1)
 948                         break;
 949                 /* Do not bother with large packets MPW cannot handle. */
 950                 if (segs_n > MLX5_MPW_DSEG_MAX)
 951                         break;
 952                 max -= segs_n;
 953                 --pkts_n;
 954                 /* Should we enable HW CKSUM offload */
 955                 if (buf->ol_flags &
 956                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 957                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 958                 /* Retrieve packet information. */
 959                 length = PKT_LEN(buf);
 960                 assert(length);
 961                 /* Start new session if packet differs. */
 962                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 963                     ((mpw.len != length) ||
 964                      (segs_n != 1) ||
 965                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 966                         mlx5_mpw_close(txq, &mpw);
 967                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 968                         /*
 969                          * Multi-Packet WQE consumes at most two WQE.
 970                          * mlx5_mpw_new() expects to be able to use such
 971                          * resources.
 972                          */
 973                         if (unlikely(max_wqe < 2))
 974                                 break;
 975                         max_wqe -= 2;
 976                         mlx5_mpw_new(txq, &mpw, length);
 977                         mpw.wqe->eseg.cs_flags = cs_flags;
 978                 }
 979                 /* Multi-segment packets must be alone in their MPW. */
 980                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 981 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 982                 length = 0;
 983 #endif
 984                 do {
 985                         volatile struct mlx5_wqe_data_seg *dseg;
 986                         uintptr_t addr;
 987
 988                         elts_head_next = (elts_head + 1) & (elts_n - 1);
 989                         assert(buf);
 990                         (*txq->elts)[elts_head] = buf;
 991                         dseg = mpw.data.dseg[mpw.pkts_n];
 992                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 993                         *dseg = (struct mlx5_wqe_data_seg){
 994                                 .byte_count = htonl(DATA_LEN(buf)),
 995                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
 996                                 .addr = htonll(addr),
 997                         };
 998                         elts_head = elts_head_next;
 999 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1000                         length += DATA_LEN(buf);
1001 #endif
1002                         buf = buf->next;
1003                         ++mpw.pkts_n;
1004                         ++j;
1005                 } while (--segs_n);
1006                 assert(length == mpw.len);
1007                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1008                         mlx5_mpw_close(txq, &mpw);
1009                 elts_head = elts_head_next;
1010 #ifdef MLX5_PMD_SOFT_COUNTERS
1011                 /* Increment sent bytes counter. */
1012                 txq->stats.obytes += length;
1013 #endif
1014                 ++i;
1015         } while (pkts_n);
1016         /* Take a shortcut if nothing must be sent. */
1017         if (unlikely(i == 0))
1018                 return 0;
1019         /* Check whether completion threshold has been reached. */
1020         /* "j" includes both packets and segments. */
1021         comp = txq->elts_comp + j;
1022         if (comp >= MLX5_TX_COMP_THRESH) {
1023                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1024
1025                 /* Request completion on last WQE. */
1026                 wqe->ctrl[2] = htonl(8);
1027                 /* Save elts_head in unused "immediate" field of WQE. */
1028                 wqe->ctrl[3] = elts_head;
1029                 txq->elts_comp = 0;
1030         } else {
1031                 txq->elts_comp = comp;
1032         }
1033 #ifdef MLX5_PMD_SOFT_COUNTERS
1034         /* Increment sent packets counter. */
1035         txq->stats.opackets += i;
1036 #endif
1037         /* Ring QP doorbell. */
1038         if (mpw.state == MLX5_MPW_STATE_OPENED)
1039                 mlx5_mpw_close(txq, &mpw);
1040         mlx5_tx_dbrec(txq, mpw.wqe);
1041         txq->elts_head = elts_head;
1042         return i;
1043 }
1044
1045 /**
1046  * Open a MPW inline session.
1047  *
1048  * @param txq
1049  *   Pointer to TX queue structure.
1050  * @param mpw
1051  *   Pointer to MPW session structure.
1052  * @param length
1053  *   Packet length.
1054  */
1055 static inline void
1056 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1057 {
1058         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1059         struct mlx5_wqe_inl_small *inl;
1060
1061         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1062         mpw->pkts_n = 0;
1063         mpw->len = length;
1064         mpw->total_len = 0;
1065         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1066         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1067                                   (txq->wqe_ci << 8) |
1068                                   MLX5_OPCODE_TSO);
1069         mpw->wqe->ctrl[2] = 0;
1070         mpw->wqe->ctrl[3] = 0;
1071         mpw->wqe->eseg.mss = htons(length);
1072         mpw->wqe->eseg.inline_hdr_sz = 0;
1073         mpw->wqe->eseg.cs_flags = 0;
1074         mpw->wqe->eseg.rsvd0 = 0;
1075         mpw->wqe->eseg.rsvd1 = 0;
1076         mpw->wqe->eseg.rsvd2 = 0;
1077         inl = (struct mlx5_wqe_inl_small *)
1078                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1079         mpw->data.raw = (uint8_t *)&inl->raw;
1080 }
1081
1082 /**
1083  * Close a MPW inline session.
1084  *
1085  * @param txq
1086  *   Pointer to TX queue structure.
1087  * @param mpw
1088  *   Pointer to MPW session structure.
1089  */
1090 static inline void
1091 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1092 {
1093         unsigned int size;
1094         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1095                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1096
1097         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1098         /*
1099          * Store size in multiple of 16 bytes. Control and Ethernet segments
1100          * count as 2.
1101          */
1102         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1103         mpw->state = MLX5_MPW_STATE_CLOSED;
1104         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1105         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1106 }
1107
1108 /**
1109  * DPDK callback for TX with MPW inline support.
1110  *
1111  * @param dpdk_txq
1112  *   Generic pointer to TX queue structure.
1113  * @param[in] pkts
1114  *   Packets to transmit.
1115  * @param pkts_n
1116  *   Number of packets in array.
1117  *
1118  * @return
1119  *   Number of packets successfully transmitted (<= pkts_n).
1120  */
1121 uint16_t
1122 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1123                          uint16_t pkts_n)
1124 {
1125         struct txq *txq = (struct txq *)dpdk_txq;
1126         uint16_t elts_head = txq->elts_head;
1127         const unsigned int elts_n = 1 << txq->elts_n;
1128         unsigned int i = 0;
1129         unsigned int j = 0;
1130         unsigned int max;
1131         uint16_t max_wqe;
1132         unsigned int comp;
1133         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1134         struct mlx5_mpw mpw = {
1135                 .state = MLX5_MPW_STATE_CLOSED,
1136         };
1137         /*
1138          * Compute the maximum number of WQE which can be consumed by inline
1139          * code.
1140          * - 2 DSEG for:
1141          *   - 1 control segment,
1142          *   - 1 Ethernet segment,
1143          * - N Dseg from the inline request.
1144          */
1145         const unsigned int wqe_inl_n =
1146                 ((2 * MLX5_WQE_DWORD_SIZE +
1147                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1148                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1149
1150         if (unlikely(!pkts_n))
1151                 return 0;
1152         /* Prefetch first packet cacheline. */
1153         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1154         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1155         /* Start processing. */
1156         txq_complete(txq);
1157         max = (elts_n - (elts_head - txq->elts_tail));
1158         if (max > elts_n)
1159                 max -= elts_n;
1160         do {
1161                 struct rte_mbuf *buf = *(pkts++);
1162                 unsigned int elts_head_next;
1163                 uintptr_t addr;
1164                 uint32_t length;
1165                 unsigned int segs_n = buf->nb_segs;
1166                 uint32_t cs_flags = 0;
1167
1168                 /*
1169                  * Make sure there is enough room to store this packet and
1170                  * that one ring entry remains unused.
1171                  */
1172                 assert(segs_n);
1173                 if (max < segs_n + 1)
1174                         break;
1175                 /* Do not bother with large packets MPW cannot handle. */
1176                 if (segs_n > MLX5_MPW_DSEG_MAX)
1177                         break;
1178                 max -= segs_n;
1179                 --pkts_n;
1180                 /*
1181                  * Compute max_wqe in case less WQE were consumed in previous
1182                  * iteration.
1183                  */
1184                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1185                 /* Should we enable HW CKSUM offload */
1186                 if (buf->ol_flags &
1187                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1188                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1189                 /* Retrieve packet information. */
1190                 length = PKT_LEN(buf);
1191                 /* Start new session if packet differs. */
1192                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1193                         if ((mpw.len != length) ||
1194                             (segs_n != 1) ||
1195                             (mpw.wqe->eseg.cs_flags != cs_flags))
1196                                 mlx5_mpw_close(txq, &mpw);
1197                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1198                         if ((mpw.len != length) ||
1199                             (segs_n != 1) ||
1200                             (length > inline_room) ||
1201                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1202                                 mlx5_mpw_inline_close(txq, &mpw);
1203                                 inline_room =
1204                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1205                         }
1206                 }
1207                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1208                         if ((segs_n != 1) ||
1209                             (length > inline_room)) {
1210                                 /*
1211                                  * Multi-Packet WQE consumes at most two WQE.
1212                                  * mlx5_mpw_new() expects to be able to use
1213                                  * such resources.
1214                                  */
1215                                 if (unlikely(max_wqe < 2))
1216                                         break;
1217                                 max_wqe -= 2;
1218                                 mlx5_mpw_new(txq, &mpw, length);
1219                                 mpw.wqe->eseg.cs_flags = cs_flags;
1220                         } else {
1221                                 if (unlikely(max_wqe < wqe_inl_n))
1222                                         break;
1223                                 max_wqe -= wqe_inl_n;
1224                                 mlx5_mpw_inline_new(txq, &mpw, length);
1225                                 mpw.wqe->eseg.cs_flags = cs_flags;
1226                         }
1227                 }
1228                 /* Multi-segment packets must be alone in their MPW. */
1229                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1230                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1231                         assert(inline_room ==
1232                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1233 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1234                         length = 0;
1235 #endif
1236                         do {
1237                                 volatile struct mlx5_wqe_data_seg *dseg;
1238
1239                                 elts_head_next =
1240                                         (elts_head + 1) & (elts_n - 1);
1241                                 assert(buf);
1242                                 (*txq->elts)[elts_head] = buf;
1243                                 dseg = mpw.data.dseg[mpw.pkts_n];
1244                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1245                                 *dseg = (struct mlx5_wqe_data_seg){
1246                                         .byte_count = htonl(DATA_LEN(buf)),
1247                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1248                                         .addr = htonll(addr),
1249                                 };
1250                                 elts_head = elts_head_next;
1251 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1252                                 length += DATA_LEN(buf);
1253 #endif
1254                                 buf = buf->next;
1255                                 ++mpw.pkts_n;
1256                                 ++j;
1257                         } while (--segs_n);
1258                         assert(length == mpw.len);
1259                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1260                                 mlx5_mpw_close(txq, &mpw);
1261                 } else {
1262                         unsigned int max;
1263
1264                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1265                         assert(length <= inline_room);
1266                         assert(length == DATA_LEN(buf));
1267                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1268                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1269                         (*txq->elts)[elts_head] = buf;
1270                         /* Maximum number of bytes before wrapping. */
1271                         max = ((((uintptr_t)(txq->wqes)) +
1272                                 (1 << txq->wqe_n) *
1273                                 MLX5_WQE_SIZE) -
1274                                (uintptr_t)mpw.data.raw);
1275                         if (length > max) {
1276                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1277                                            (void *)addr,
1278                                            max);
1279                                 mpw.data.raw = (volatile void *)txq->wqes;
1280                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1281                                            (void *)(addr + max),
1282                                            length - max);
1283                                 mpw.data.raw += length - max;
1284                         } else {
1285                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1286                                            (void *)addr,
1287                                            length);
1288
1289                                 if (length == max)
1290                                         mpw.data.raw =
1291                                                 (volatile void *)txq->wqes;
1292                                 else
1293                                         mpw.data.raw += length;
1294                         }
1295                         ++mpw.pkts_n;
1296                         mpw.total_len += length;
1297                         ++j;
1298                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1299                                 mlx5_mpw_inline_close(txq, &mpw);
1300                                 inline_room =
1301                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1302                         } else {
1303                                 inline_room -= length;
1304                         }
1305                 }
1306                 elts_head = elts_head_next;
1307 #ifdef MLX5_PMD_SOFT_COUNTERS
1308                 /* Increment sent bytes counter. */
1309                 txq->stats.obytes += length;
1310 #endif
1311                 ++i;
1312         } while (pkts_n);
1313         /* Take a shortcut if nothing must be sent. */
1314         if (unlikely(i == 0))
1315                 return 0;
1316         /* Check whether completion threshold has been reached. */
1317         /* "j" includes both packets and segments. */
1318         comp = txq->elts_comp + j;
1319         if (comp >= MLX5_TX_COMP_THRESH) {
1320                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1321
1322                 /* Request completion on last WQE. */
1323                 wqe->ctrl[2] = htonl(8);
1324                 /* Save elts_head in unused "immediate" field of WQE. */
1325                 wqe->ctrl[3] = elts_head;
1326                 txq->elts_comp = 0;
1327         } else {
1328                 txq->elts_comp = comp;
1329         }
1330 #ifdef MLX5_PMD_SOFT_COUNTERS
1331         /* Increment sent packets counter. */
1332         txq->stats.opackets += i;
1333 #endif
1334         /* Ring QP doorbell. */
1335         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1336                 mlx5_mpw_inline_close(txq, &mpw);
1337         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1338                 mlx5_mpw_close(txq, &mpw);
1339         mlx5_tx_dbrec(txq, mpw.wqe);
1340         txq->elts_head = elts_head;
1341         return i;
1342 }
1343
1344 /**
1345  * Translate RX completion flags to packet type.
1346  *
1347  * @param[in] cqe
1348  *   Pointer to CQE.
1349  *
1350  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1351  *
1352  * @return
1353  *   Packet type for struct rte_mbuf.
1354  */
1355 static inline uint32_t
1356 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1357 {
1358         uint32_t pkt_type;
1359         uint16_t flags = ntohs(cqe->hdr_type_etc);
1360
1361         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1362                 pkt_type =
1363                         TRANSPOSE(flags,
1364                                   MLX5_CQE_RX_IPV4_PACKET,
1365                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1366                         TRANSPOSE(flags,
1367                                   MLX5_CQE_RX_IPV6_PACKET,
1368                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1369                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1370                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1371                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1372         } else {
1373                 pkt_type =
1374                         TRANSPOSE(flags,
1375                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1376                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1377                         TRANSPOSE(flags,
1378                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1379                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1380         }
1381         return pkt_type;
1382 }
1383
1384 /**
1385  * Get size of the next packet for a given CQE. For compressed CQEs, the
1386  * consumer index is updated only once all packets of the current one have
1387  * been processed.
1388  *
1389  * @param rxq
1390  *   Pointer to RX queue.
1391  * @param cqe
1392  *   CQE to process.
1393  * @param[out] rss_hash
1394  *   Packet RSS Hash result.
1395  *
1396  * @return
1397  *   Packet size in bytes (0 if there is none), -1 in case of completion
1398  *   with error.
1399  */
1400 static inline int
1401 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1402                  uint16_t cqe_cnt, uint32_t *rss_hash)
1403 {
1404         struct rxq_zip *zip = &rxq->zip;
1405         uint16_t cqe_n = cqe_cnt + 1;
1406         int len = 0;
1407         uint16_t idx, end;
1408
1409         /* Process compressed data in the CQE and mini arrays. */
1410         if (zip->ai) {
1411                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1412                         (volatile struct mlx5_mini_cqe8 (*)[8])
1413                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1414
1415                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1416                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1417                 if ((++zip->ai & 7) == 0) {
1418                         /* Invalidate consumed CQEs */
1419                         idx = zip->ca;
1420                         end = zip->na;
1421                         while (idx != end) {
1422                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1423                                         MLX5_CQE_INVALIDATE;
1424                                 ++idx;
1425                         }
1426                         /*
1427                          * Increment consumer index to skip the number of
1428                          * CQEs consumed. Hardware leaves holes in the CQ
1429                          * ring for software use.
1430                          */
1431                         zip->ca = zip->na;
1432                         zip->na += 8;
1433                 }
1434                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1435                         /* Invalidate the rest */
1436                         idx = zip->ca;
1437                         end = zip->cq_ci;
1438
1439                         while (idx != end) {
1440                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1441                                         MLX5_CQE_INVALIDATE;
1442                                 ++idx;
1443                         }
1444                         rxq->cq_ci = zip->cq_ci;
1445                         zip->ai = 0;
1446                 }
1447         /* No compressed data, get next CQE and verify if it is compressed. */
1448         } else {
1449                 int ret;
1450                 int8_t op_own;
1451
1452                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1453                 if (unlikely(ret == 1))
1454                         return 0;
1455                 ++rxq->cq_ci;
1456                 op_own = cqe->op_own;
1457                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1458                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1459                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1460                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1461                                                           cqe_cnt]);
1462
1463                         /* Fix endianness. */
1464                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1465                         /*
1466                          * Current mini array position is the one returned by
1467                          * check_cqe64().
1468                          *
1469                          * If completion comprises several mini arrays, as a
1470                          * special case the second one is located 7 CQEs after
1471                          * the initial CQE instead of 8 for subsequent ones.
1472                          */
1473                         zip->ca = rxq->cq_ci;
1474                         zip->na = zip->ca + 7;
1475                         /* Compute the next non compressed CQE. */
1476                         --rxq->cq_ci;
1477                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1478                         /* Get packet size to return. */
1479                         len = ntohl((*mc)[0].byte_cnt);
1480                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1481                         zip->ai = 1;
1482                         /* Prefetch all the entries to be invalidated */
1483                         idx = zip->ca;
1484                         end = zip->cq_ci;
1485                         while (idx != end) {
1486                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1487                                 ++idx;
1488                         }
1489                 } else {
1490                         len = ntohl(cqe->byte_cnt);
1491                         *rss_hash = ntohl(cqe->rx_hash_res);
1492                 }
1493                 /* Error while receiving packet. */
1494                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1495                         return -1;
1496         }
1497         return len;
1498 }
1499
1500 /**
1501  * Translate RX completion flags to offload flags.
1502  *
1503  * @param[in] rxq
1504  *   Pointer to RX queue structure.
1505  * @param[in] cqe
1506  *   Pointer to CQE.
1507  *
1508  * @return
1509  *   Offload flags (ol_flags) for struct rte_mbuf.
1510  */
1511 static inline uint32_t
1512 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1513 {
1514         uint32_t ol_flags = 0;
1515         uint16_t flags = ntohs(cqe->hdr_type_etc);
1516
1517         ol_flags =
1518                 TRANSPOSE(flags,
1519                           MLX5_CQE_RX_L3_HDR_VALID,
1520                           PKT_RX_IP_CKSUM_GOOD) |
1521                 TRANSPOSE(flags,
1522                           MLX5_CQE_RX_L4_HDR_VALID,
1523                           PKT_RX_L4_CKSUM_GOOD);
1524         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1525                 ol_flags |=
1526                         TRANSPOSE(flags,
1527                                   MLX5_CQE_RX_L3_HDR_VALID,
1528                                   PKT_RX_IP_CKSUM_GOOD) |
1529                         TRANSPOSE(flags,
1530                                   MLX5_CQE_RX_L4_HDR_VALID,
1531                                   PKT_RX_L4_CKSUM_GOOD);
1532         return ol_flags;
1533 }
1534
1535 /**
1536  * DPDK callback for RX.
1537  *
1538  * @param dpdk_rxq
1539  *   Generic pointer to RX queue structure.
1540  * @param[out] pkts
1541  *   Array to store received packets.
1542  * @param pkts_n
1543  *   Maximum number of packets in array.
1544  *
1545  * @return
1546  *   Number of packets successfully received (<= pkts_n).
1547  */
1548 uint16_t
1549 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1550 {
1551         struct rxq *rxq = dpdk_rxq;
1552         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1553         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1554         const unsigned int sges_n = rxq->sges_n;
1555         struct rte_mbuf *pkt = NULL;
1556         struct rte_mbuf *seg = NULL;
1557         volatile struct mlx5_cqe *cqe =
1558                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1559         unsigned int i = 0;
1560         unsigned int rq_ci = rxq->rq_ci << sges_n;
1561         int len; /* keep its value across iterations. */
1562
1563         while (pkts_n) {
1564                 unsigned int idx = rq_ci & wqe_cnt;
1565                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1566                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1567                 uint32_t rss_hash_res = 0;
1568
1569                 if (pkt)
1570                         NEXT(seg) = rep;
1571                 seg = rep;
1572                 rte_prefetch0(seg);
1573                 rte_prefetch0(cqe);
1574                 rte_prefetch0(wqe);
1575                 rep = rte_mbuf_raw_alloc(rxq->mp);
1576                 if (unlikely(rep == NULL)) {
1577                         ++rxq->stats.rx_nombuf;
1578                         if (!pkt) {
1579                                 /*
1580                                  * no buffers before we even started,
1581                                  * bail out silently.
1582                                  */
1583                                 break;
1584                         }
1585                         while (pkt != seg) {
1586                                 assert(pkt != (*rxq->elts)[idx]);
1587                                 rep = NEXT(pkt);
1588                                 rte_mbuf_refcnt_set(pkt, 0);
1589                                 __rte_mbuf_raw_free(pkt);
1590                                 pkt = rep;
1591                         }
1592                         break;
1593                 }
1594                 if (!pkt) {
1595                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1596                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1597                                                &rss_hash_res);
1598                         if (!len) {
1599                                 rte_mbuf_refcnt_set(rep, 0);
1600                                 __rte_mbuf_raw_free(rep);
1601                                 break;
1602                         }
1603                         if (unlikely(len == -1)) {
1604                                 /* RX error, packet is likely too large. */
1605                                 rte_mbuf_refcnt_set(rep, 0);
1606                                 __rte_mbuf_raw_free(rep);
1607                                 ++rxq->stats.idropped;
1608                                 goto skip;
1609                         }
1610                         pkt = seg;
1611                         assert(len >= (rxq->crc_present << 2));
1612                         /* Update packet information. */
1613                         pkt->packet_type = 0;
1614                         pkt->ol_flags = 0;
1615                         if (rss_hash_res && rxq->rss_hash) {
1616                                 pkt->hash.rss = rss_hash_res;
1617                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1618                         }
1619                         if (rxq->mark && (cqe->sop_drop_qpn !=
1620                                           htonl(MLX5_FLOW_MARK_INVALID))) {
1621                                 pkt->ol_flags |= PKT_RX_FDIR;
1622                                 if (cqe->sop_drop_qpn !=
1623                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1624                                         uint32_t mark = cqe->sop_drop_qpn;
1625
1626                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1627                                         pkt->hash.fdir.hi =
1628                                                 mlx5_flow_mark_get(mark);
1629                                 }
1630                         }
1631                         if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1632                             rxq->crc_present) {
1633                                 if (rxq->csum) {
1634                                         pkt->packet_type =
1635                                                 rxq_cq_to_pkt_type(cqe);
1636                                         pkt->ol_flags |=
1637                                                 rxq_cq_to_ol_flags(rxq, cqe);
1638                                 }
1639                                 if (ntohs(cqe->hdr_type_etc) &
1640                                     MLX5_CQE_VLAN_STRIPPED) {
1641                                         pkt->ol_flags |= PKT_RX_VLAN_PKT |
1642                                                 PKT_RX_VLAN_STRIPPED;
1643                                         pkt->vlan_tci = ntohs(cqe->vlan_info);
1644                                 }
1645                                 if (rxq->crc_present)
1646                                         len -= ETHER_CRC_LEN;
1647                         }
1648                         PKT_LEN(pkt) = len;
1649                 }
1650                 DATA_LEN(rep) = DATA_LEN(seg);
1651                 PKT_LEN(rep) = PKT_LEN(seg);
1652                 SET_DATA_OFF(rep, DATA_OFF(seg));
1653                 NB_SEGS(rep) = NB_SEGS(seg);
1654                 PORT(rep) = PORT(seg);
1655                 NEXT(rep) = NULL;
1656                 (*rxq->elts)[idx] = rep;
1657                 /*
1658                  * Fill NIC descriptor with the new buffer.  The lkey and size
1659                  * of the buffers are already known, only the buffer address
1660                  * changes.
1661                  */
1662                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1663                 if (len > DATA_LEN(seg)) {
1664                         len -= DATA_LEN(seg);
1665                         ++NB_SEGS(pkt);
1666                         ++rq_ci;
1667                         continue;
1668                 }
1669                 DATA_LEN(seg) = len;
1670 #ifdef MLX5_PMD_SOFT_COUNTERS
1671                 /* Increment bytes counter. */
1672                 rxq->stats.ibytes += PKT_LEN(pkt);
1673 #endif
1674                 /* Return packet. */
1675                 *(pkts++) = pkt;
1676                 pkt = NULL;
1677                 --pkts_n;
1678                 ++i;
1679 skip:
1680                 /* Align consumer index to the next stride. */
1681                 rq_ci >>= sges_n;
1682                 ++rq_ci;
1683                 rq_ci <<= sges_n;
1684         }
1685         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1686                 return 0;
1687         /* Update the consumer index. */
1688         rxq->rq_ci = rq_ci >> sges_n;
1689         rte_wmb();
1690         *rxq->cq_db = htonl(rxq->cq_ci);
1691         rte_wmb();
1692         *rxq->rq_db = htonl(rxq->rq_ci);
1693 #ifdef MLX5_PMD_SOFT_COUNTERS
1694         /* Increment packets counter. */
1695         rxq->stats.ipackets += i;
1696 #endif
1697         return i;
1698 }
1699
1700 /**
1701  * Dummy DPDK callback for TX.
1702  *
1703  * This function is used to temporarily replace the real callback during
1704  * unsafe control operations on the queue, or in case of error.
1705  *
1706  * @param dpdk_txq
1707  *   Generic pointer to TX queue structure.
1708  * @param[in] pkts
1709  *   Packets to transmit.
1710  * @param pkts_n
1711  *   Number of packets in array.
1712  *
1713  * @return
1714  *   Number of packets successfully transmitted (<= pkts_n).
1715  */
1716 uint16_t
1717 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1718 {
1719         (void)dpdk_txq;
1720         (void)pkts;
1721         (void)pkts_n;
1722         return 0;
1723 }
1724
1725 /**
1726  * Dummy DPDK callback for RX.
1727  *
1728  * This function is used to temporarily replace the real callback during
1729  * unsafe control operations on the queue, or in case of error.
1730  *
1731  * @param dpdk_rxq
1732  *   Generic pointer to RX queue structure.
1733  * @param[out] pkts
1734  *   Array to store received packets.
1735  * @param pkts_n
1736  *   Maximum number of packets in array.
1737  *
1738  * @return
1739  *   Number of packets successfully received (<= pkts_n).
1740  */
1741 uint16_t
1742 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1743 {
1744         (void)dpdk_rxq;
1745         (void)pkts;
1746         (void)pkts_n;
1747         return 0;
1748 }