drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 #include <rte_mbuf.h>
  52 #include <rte_mempool.h>
  53 #include <rte_prefetch.h>
  54 #include <rte_common.h>
  55 #include <rte_branch_prediction.h>
  56 #include <rte_ether.h>
  57
  58 #include "mlx5.h"
  59 #include "mlx5_utils.h"
  60 #include "mlx5_rxtx.h"
  61 #include "mlx5_autoconf.h"
  62 #include "mlx5_defs.h"
  63 #include "mlx5_prm.h"
  64
  65 static __rte_always_inline uint32_t
  66 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  67
  68 static __rte_always_inline int
  69 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  70                  uint16_t cqe_cnt, uint32_t *rss_hash);
  71
  72 static __rte_always_inline uint32_t
  73 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  74
  75 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  76         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  77 };
  78
  79 /**
  80  * Build a table to translate Rx completion flags to packet type.
  81  *
  82  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  83  */
  84 void
  85 mlx5_set_ptype_table(void)
  86 {
  87         unsigned int i;
  88         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  89
  90         /* Last entry must not be overwritten, reserved for errored packet. */
  91         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  92                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  93         /*
  94          * The index to the array should have:
  95          * bit[1:0] = l3_hdr_type
  96          * bit[4:2] = l4_hdr_type
  97          * bit[5] = ip_frag
  98          * bit[6] = tunneled
  99          * bit[7] = outer_l3_type
 100          */
 101         /* L3 */
 102         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_NONFRAG;
 104         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_NONFRAG;
 106         /* Fragmented */
 107         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 108                      RTE_PTYPE_L4_FRAG;
 109         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_FRAG;
 111         /* TCP */
 112         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_TCP;
 114         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_TCP;
 116         /* UDP */
 117         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_UDP;
 119         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_UDP;
 121         /* Repeat with outer_l3_type being set. Just in case. */
 122         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_NONFRAG;
 124         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_NONFRAG;
 126         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_FRAG;
 128         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_FRAG;
 130         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_TCP;
 132         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_TCP;
 134         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_UDP;
 136         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_UDP;
 138         /* Tunneled - L3 */
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L4_NONFRAG;
 148         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L4_NONFRAG;
 151         /* Tunneled - Fragmented */
 152         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L4_FRAG;
 155         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L4_FRAG;
 158         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L4_FRAG;
 161         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L4_FRAG;
 164         /* Tunneled - TCP */
 165         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 167                      RTE_PTYPE_L4_TCP;
 168         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_L4_TCP;
 171         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_L4_TCP;
 174         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_L4_TCP;
 177         /* Tunneled - UDP */
 178         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_L4_UDP;
 181         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_L4_UDP;
 184         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_L4_UDP;
 187         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_L4_UDP;
 190 }
 191
 192 /**
 193  * Return the size of tailroom of WQ.
 194  *
 195  * @param txq
 196  *   Pointer to TX queue structure.
 197  * @param addr
 198  *   Pointer to tail of WQ.
 199  *
 200  * @return
 201  *   Size of tailroom.
 202  */
 203 static inline size_t
 204 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 205 {
 206         size_t tailroom;
 207         tailroom = (uintptr_t)(txq->wqes) +
 208                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 209                    (uintptr_t)addr;
 210         return tailroom;
 211 }
 212
 213 /**
 214  * Copy data to tailroom of circular queue.
 215  *
 216  * @param dst
 217  *   Pointer to destination.
 218  * @param src
 219  *   Pointer to source.
 220  * @param n
 221  *   Number of bytes to copy.
 222  * @param base
 223  *   Pointer to head of queue.
 224  * @param tailroom
 225  *   Size of tailroom from dst.
 226  *
 227  * @return
 228  *   Pointer after copied data.
 229  */
 230 static inline void *
 231 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 232                 void *base, size_t tailroom)
 233 {
 234         void *ret;
 235
 236         if (n > tailroom) {
 237                 rte_memcpy(dst, src, tailroom);
 238                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 239                            n - tailroom);
 240                 ret = (uint8_t *)base + n - tailroom;
 241         } else {
 242                 rte_memcpy(dst, src, n);
 243                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 244         }
 245         return ret;
 246 }
 247
 248 /**
 249  * DPDK callback to check the status of a tx descriptor.
 250  *
 251  * @param tx_queue
 252  *   The tx queue.
 253  * @param[in] offset
 254  *   The index of the descriptor in the ring.
 255  *
 256  * @return
 257  *   The status of the tx descriptor.
 258  */
 259 int
 260 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 261 {
 262         struct txq *txq = tx_queue;
 263         uint16_t used;
 264
 265         mlx5_tx_complete(txq);
 266         used = txq->elts_head - txq->elts_tail;
 267         if (offset < used)
 268                 return RTE_ETH_TX_DESC_FULL;
 269         return RTE_ETH_TX_DESC_DONE;
 270 }
 271
 272 /**
 273  * DPDK callback to check the status of a rx descriptor.
 274  *
 275  * @param rx_queue
 276  *   The rx queue.
 277  * @param[in] offset
 278  *   The index of the descriptor in the ring.
 279  *
 280  * @return
 281  *   The status of the tx descriptor.
 282  */
 283 int
 284 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 285 {
 286         struct rxq *rxq = rx_queue;
 287         struct rxq_zip *zip = &rxq->zip;
 288         volatile struct mlx5_cqe *cqe;
 289         const unsigned int cqe_n = (1 << rxq->cqe_n);
 290         const unsigned int cqe_cnt = cqe_n - 1;
 291         unsigned int cq_ci;
 292         unsigned int used;
 293
 294         /* if we are processing a compressed cqe */
 295         if (zip->ai) {
 296                 used = zip->cqe_cnt - zip->ca;
 297                 cq_ci = zip->cq_ci;
 298         } else {
 299                 used = 0;
 300                 cq_ci = rxq->cq_ci;
 301         }
 302         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 303         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 304                 int8_t op_own;
 305                 unsigned int n;
 306
 307                 op_own = cqe->op_own;
 308                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 309                         n = ntohl(cqe->byte_cnt);
 310                 else
 311                         n = 1;
 312                 cq_ci += n;
 313                 used += n;
 314                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 315         }
 316         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 317         if (offset < used)
 318                 return RTE_ETH_RX_DESC_DONE;
 319         return RTE_ETH_RX_DESC_AVAIL;
 320 }
 321
 322 /**
 323  * DPDK callback for TX.
 324  *
 325  * @param dpdk_txq
 326  *   Generic pointer to TX queue structure.
 327  * @param[in] pkts
 328  *   Packets to transmit.
 329  * @param pkts_n
 330  *   Number of packets in array.
 331  *
 332  * @return
 333  *   Number of packets successfully transmitted (<= pkts_n).
 334  */
 335 uint16_t
 336 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 337 {
 338         struct txq *txq = (struct txq *)dpdk_txq;
 339         uint16_t elts_head = txq->elts_head;
 340         const uint16_t elts_n = 1 << txq->elts_n;
 341         const uint16_t elts_m = elts_n - 1;
 342         unsigned int i = 0;
 343         unsigned int j = 0;
 344         unsigned int k = 0;
 345         uint16_t max_elts;
 346         unsigned int max_inline = txq->max_inline;
 347         const unsigned int inline_en = !!max_inline && txq->inline_en;
 348         uint16_t max_wqe;
 349         unsigned int comp;
 350         volatile struct mlx5_wqe_v *wqe = NULL;
 351         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 352         unsigned int segs_n = 0;
 353         struct rte_mbuf *buf = NULL;
 354         uint8_t *raw;
 355
 356         if (unlikely(!pkts_n))
 357                 return 0;
 358         /* Prefetch first packet cacheline. */
 359         rte_prefetch0(*pkts);
 360         /* Start processing. */
 361         mlx5_tx_complete(txq);
 362         max_elts = (elts_n - (elts_head - txq->elts_tail));
 363         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 364         if (unlikely(!max_wqe))
 365                 return 0;
 366         do {
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint64_t naddr;
 373                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 374                 uint16_t tso_header_sz = 0;
 375                 uint16_t ehdr;
 376                 uint8_t cs_flags = 0;
 377                 uint64_t tso = 0;
 378                 uint16_t tso_segsz = 0;
 379 #ifdef MLX5_PMD_SOFT_COUNTERS
 380                 uint32_t total_length = 0;
 381 #endif
 382
 383                 /* first_seg */
 384                 buf = *pkts;
 385                 segs_n = buf->nb_segs;
 386                 /*
 387                  * Make sure there is enough room to store this packet and
 388                  * that one ring entry remains unused.
 389                  */
 390                 assert(segs_n);
 391                 if (max_elts < segs_n)
 392                         break;
 393                 max_elts -= segs_n;
 394                 --segs_n;
 395                 if (unlikely(--max_wqe == 0))
 396                         break;
 397                 wqe = (volatile struct mlx5_wqe_v *)
 398                         tx_mlx5_wqe(txq, txq->wqe_ci);
 399                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 400                 if (pkts_n - i > 1)
 401                         rte_prefetch0(*(pkts + 1));
 402                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 403                 length = DATA_LEN(buf);
 404                 ehdr = (((uint8_t *)addr)[1] << 8) |
 405                        ((uint8_t *)addr)[0];
 406 #ifdef MLX5_PMD_SOFT_COUNTERS
 407                 total_length = length;
 408 #endif
 409                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 410                         break;
 411                 /* Update element. */
 412                 (*txq->elts)[elts_head & elts_m] = buf;
 413                 /* Prefetch next buffer data. */
 414                 if (pkts_n - i > 1)
 415                         rte_prefetch0(
 416                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 417                 /* Should we enable HW CKSUM offload */
 418                 if (buf->ol_flags &
 419                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 420                         const uint64_t is_tunneled = buf->ol_flags &
 421                                                      (PKT_TX_TUNNEL_GRE |
 422                                                       PKT_TX_TUNNEL_VXLAN);
 423
 424                         if (is_tunneled && txq->tunnel_en) {
 425                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 426                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 427                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 428                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 429                         } else {
 430                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 431                                            MLX5_ETH_WQE_L4_CSUM;
 432                         }
 433                 }
 434                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 435                 /* Replace the Ethernet type by the VLAN if necessary. */
 436                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 437                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 438                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 439
 440                         addr += 2;
 441                         length -= 2;
 442                         /* Copy Destination and source mac address. */
 443                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 444                         /* Copy VLAN. */
 445                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 446                         /* Copy missing two bytes to end the DSeg. */
 447                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 448                                ((uint8_t *)addr) + len, 2);
 449                         addr += len + 2;
 450                         length -= (len + 2);
 451                 } else {
 452                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 453                                MLX5_WQE_DWORD_SIZE);
 454                         length -= pkt_inline_sz;
 455                         addr += pkt_inline_sz;
 456                 }
 457                 if (txq->tso_en) {
 458                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 459                         if (tso) {
 460                                 uintptr_t end = (uintptr_t)
 461                                                 (((uintptr_t)txq->wqes) +
 462                                                 (1 << txq->wqe_n) *
 463                                                 MLX5_WQE_SIZE);
 464                                 unsigned int copy_b;
 465                                 uint8_t vlan_sz = (buf->ol_flags &
 466                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 467                                 const uint64_t is_tunneled =
 468                                                         buf->ol_flags &
 469                                                         (PKT_TX_TUNNEL_GRE |
 470                                                          PKT_TX_TUNNEL_VXLAN);
 471
 472                                 tso_header_sz = buf->l2_len + vlan_sz +
 473                                                 buf->l3_len + buf->l4_len;
 474                                 tso_segsz = buf->tso_segsz;
 475
 476                                 if (is_tunneled && txq->tunnel_en) {
 477                                         tso_header_sz += buf->outer_l2_len +
 478                                                          buf->outer_l3_len;
 479                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 480                                 } else {
 481                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 482                                 }
 483                                 if (unlikely(tso_header_sz >
 484                                              MLX5_MAX_TSO_HEADER))
 485                                         break;
 486                                 copy_b = tso_header_sz - pkt_inline_sz;
 487                                 /* First seg must contain all headers. */
 488                                 assert(copy_b <= length);
 489                                 raw += MLX5_WQE_DWORD_SIZE;
 490                                 if (copy_b &&
 491                                    ((end - (uintptr_t)raw) > copy_b)) {
 492                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 493                                                       1 + 3) / 4;
 494
 495                                         if (unlikely(max_wqe < n))
 496                                                 break;
 497                                         max_wqe -= n;
 498                                         rte_memcpy((void *)raw,
 499                                                    (void *)addr, copy_b);
 500                                         addr += copy_b;
 501                                         length -= copy_b;
 502                                         pkt_inline_sz += copy_b;
 503                                         /*
 504                                          * Another DWORD will be added
 505                                          * in the inline part.
 506                                          */
 507                                         raw += MLX5_WQE_DS(copy_b) *
 508                                                MLX5_WQE_DWORD_SIZE -
 509                                                MLX5_WQE_DWORD_SIZE;
 510                                 } else {
 511                                         /* NOP WQE. */
 512                                         wqe->ctrl = (rte_v128u32_t){
 513                                                      htonl(txq->wqe_ci << 8),
 514                                                      htonl(txq->qp_num_8s | 1),
 515                                                      0,
 516                                                      0,
 517                                         };
 518                                         ds = 1;
 519                                         total_length = 0;
 520                                         k++;
 521                                         goto next_wqe;
 522                                 }
 523                         }
 524                 }
 525                 /* Inline if enough room. */
 526                 if (inline_en || tso) {
 527                         uintptr_t end = (uintptr_t)
 528                                 (((uintptr_t)txq->wqes) +
 529                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 530                         unsigned int inline_room = max_inline *
 531                                                    RTE_CACHE_LINE_SIZE -
 532                                                    (pkt_inline_sz - 2);
 533                         uintptr_t addr_end = (addr + inline_room) &
 534                                              ~(RTE_CACHE_LINE_SIZE - 1);
 535                         unsigned int copy_b = (addr_end > addr) ?
 536                                 RTE_MIN((addr_end - addr), length) :
 537                                 0;
 538
 539                         raw += MLX5_WQE_DWORD_SIZE;
 540                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 541                                 /*
 542                                  * One Dseg remains in the current WQE.  To
 543                                  * keep the computation positive, it is
 544                                  * removed after the bytes to Dseg conversion.
 545                                  */
 546                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 547
 548                                 if (unlikely(max_wqe < n))
 549                                         break;
 550                                 max_wqe -= n;
 551                                 if (tso) {
 552                                         uint32_t inl =
 553                                                 htonl(copy_b | MLX5_INLINE_SEG);
 554
 555                                         pkt_inline_sz =
 556                                                 MLX5_WQE_DS(tso_header_sz) *
 557                                                 MLX5_WQE_DWORD_SIZE;
 558                                         rte_memcpy((void *)raw,
 559                                                    (void *)&inl, sizeof(inl));
 560                                         raw += sizeof(inl);
 561                                         pkt_inline_sz += sizeof(inl);
 562                                 }
 563                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 564                                 addr += copy_b;
 565                                 length -= copy_b;
 566                                 pkt_inline_sz += copy_b;
 567                         }
 568                         /*
 569                          * 2 DWORDs consumed by the WQE header + ETH segment +
 570                          * the size of the inline part of the packet.
 571                          */
 572                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 573                         if (length > 0) {
 574                                 if (ds % (MLX5_WQE_SIZE /
 575                                           MLX5_WQE_DWORD_SIZE) == 0) {
 576                                         if (unlikely(--max_wqe == 0))
 577                                                 break;
 578                                         dseg = (volatile rte_v128u32_t *)
 579                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 580                                                            ds / 4);
 581                                 } else {
 582                                         dseg = (volatile rte_v128u32_t *)
 583                                                 ((uintptr_t)wqe +
 584                                                  (ds * MLX5_WQE_DWORD_SIZE));
 585                                 }
 586                                 goto use_dseg;
 587                         } else if (!segs_n) {
 588                                 goto next_pkt;
 589                         } else {
 590                                 /* dseg will be advance as part of next_seg */
 591                                 dseg = (volatile rte_v128u32_t *)
 592                                         ((uintptr_t)wqe +
 593                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 594                                 goto next_seg;
 595                         }
 596                 } else {
 597                         /*
 598                          * No inline has been done in the packet, only the
 599                          * Ethernet Header as been stored.
 600                          */
 601                         dseg = (volatile rte_v128u32_t *)
 602                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 603                         ds = 3;
 604 use_dseg:
 605                         /* Add the remaining packet as a simple ds. */
 606                         naddr = htonll(addr);
 607                         *dseg = (rte_v128u32_t){
 608                                 htonl(length),
 609                                 mlx5_tx_mb2mr(txq, buf),
 610                                 naddr,
 611                                 naddr >> 32,
 612                         };
 613                         ++ds;
 614                         if (!segs_n)
 615                                 goto next_pkt;
 616                 }
 617 next_seg:
 618                 assert(buf);
 619                 assert(ds);
 620                 assert(wqe);
 621                 /*
 622                  * Spill on next WQE when the current one does not have
 623                  * enough room left. Size of WQE must a be a multiple
 624                  * of data segment size.
 625                  */
 626                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 627                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 628                         if (unlikely(--max_wqe == 0))
 629                                 break;
 630                         dseg = (volatile rte_v128u32_t *)
 631                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 632                         rte_prefetch0(tx_mlx5_wqe(txq,
 633                                                   txq->wqe_ci + ds / 4 + 1));
 634                 } else {
 635                         ++dseg;
 636                 }
 637                 ++ds;
 638                 buf = buf->next;
 639                 assert(buf);
 640                 length = DATA_LEN(buf);
 641 #ifdef MLX5_PMD_SOFT_COUNTERS
 642                 total_length += length;
 643 #endif
 644                 /* Store segment information. */
 645                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 646                 *dseg = (rte_v128u32_t){
 647                         htonl(length),
 648                         mlx5_tx_mb2mr(txq, buf),
 649                         naddr,
 650                         naddr >> 32,
 651                 };
 652                 (*txq->elts)[++elts_head & elts_m] = buf;
 653                 ++sg;
 654                 /* Advance counter only if all segs are successfully posted. */
 655                 if (sg < segs_n)
 656                         goto next_seg;
 657                 else
 658                         j += sg;
 659 next_pkt:
 660                 ++elts_head;
 661                 ++pkts;
 662                 ++i;
 663                 /* Initialize known and common part of the WQE structure. */
 664                 if (tso) {
 665                         wqe->ctrl = (rte_v128u32_t){
 666                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 667                                 htonl(txq->qp_num_8s | ds),
 668                                 0,
 669                                 0,
 670                         };
 671                         wqe->eseg = (rte_v128u32_t){
 672                                 0,
 673                                 cs_flags | (htons(tso_segsz) << 16),
 674                                 0,
 675                                 (ehdr << 16) | htons(tso_header_sz),
 676                         };
 677                 } else {
 678                         wqe->ctrl = (rte_v128u32_t){
 679                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 680                                 htonl(txq->qp_num_8s | ds),
 681                                 0,
 682                                 0,
 683                         };
 684                         wqe->eseg = (rte_v128u32_t){
 685                                 0,
 686                                 cs_flags,
 687                                 0,
 688                                 (ehdr << 16) | htons(pkt_inline_sz),
 689                         };
 690                 }
 691 next_wqe:
 692                 txq->wqe_ci += (ds + 3) / 4;
 693                 /* Save the last successful WQE for completion request */
 694                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 695 #ifdef MLX5_PMD_SOFT_COUNTERS
 696                 /* Increment sent bytes counter. */
 697                 txq->stats.obytes += total_length;
 698 #endif
 699         } while (i < pkts_n);
 700         /* Take a shortcut if nothing must be sent. */
 701         if (unlikely((i + k) == 0))
 702                 return 0;
 703         txq->elts_head += (i + j);
 704         /* Check whether completion threshold has been reached. */
 705         comp = txq->elts_comp + i + j + k;
 706         if (comp >= MLX5_TX_COMP_THRESH) {
 707                 /* Request completion on last WQE. */
 708                 last_wqe->ctrl2 = htonl(8);
 709                 /* Save elts_head in unused "immediate" field of WQE. */
 710                 last_wqe->ctrl3 = txq->elts_head;
 711                 txq->elts_comp = 0;
 712         } else {
 713                 txq->elts_comp = comp;
 714         }
 715 #ifdef MLX5_PMD_SOFT_COUNTERS
 716         /* Increment sent packets counter. */
 717         txq->stats.opackets += i;
 718 #endif
 719         /* Ring QP doorbell. */
 720         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 721         return i;
 722 }
 723
 724 /**
 725  * Open a MPW session.
 726  *
 727  * @param txq
 728  *   Pointer to TX queue structure.
 729  * @param mpw
 730  *   Pointer to MPW session structure.
 731  * @param length
 732  *   Packet length.
 733  */
 734 static inline void
 735 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 736 {
 737         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 738         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 739                 (volatile struct mlx5_wqe_data_seg (*)[])
 740                 tx_mlx5_wqe(txq, idx + 1);
 741
 742         mpw->state = MLX5_MPW_STATE_OPENED;
 743         mpw->pkts_n = 0;
 744         mpw->len = length;
 745         mpw->total_len = 0;
 746         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 747         mpw->wqe->eseg.mss = htons(length);
 748         mpw->wqe->eseg.inline_hdr_sz = 0;
 749         mpw->wqe->eseg.rsvd0 = 0;
 750         mpw->wqe->eseg.rsvd1 = 0;
 751         mpw->wqe->eseg.rsvd2 = 0;
 752         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 753                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 754         mpw->wqe->ctrl[2] = 0;
 755         mpw->wqe->ctrl[3] = 0;
 756         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 757                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 758         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 759                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 760         mpw->data.dseg[2] = &(*dseg)[0];
 761         mpw->data.dseg[3] = &(*dseg)[1];
 762         mpw->data.dseg[4] = &(*dseg)[2];
 763 }
 764
 765 /**
 766  * Close a MPW session.
 767  *
 768  * @param txq
 769  *   Pointer to TX queue structure.
 770  * @param mpw
 771  *   Pointer to MPW session structure.
 772  */
 773 static inline void
 774 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 775 {
 776         unsigned int num = mpw->pkts_n;
 777
 778         /*
 779          * Store size in multiple of 16 bytes. Control and Ethernet segments
 780          * count as 2.
 781          */
 782         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 783         mpw->state = MLX5_MPW_STATE_CLOSED;
 784         if (num < 3)
 785                 ++txq->wqe_ci;
 786         else
 787                 txq->wqe_ci += 2;
 788         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 789         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 790 }
 791
 792 /**
 793  * DPDK callback for TX with MPW support.
 794  *
 795  * @param dpdk_txq
 796  *   Generic pointer to TX queue structure.
 797  * @param[in] pkts
 798  *   Packets to transmit.
 799  * @param pkts_n
 800  *   Number of packets in array.
 801  *
 802  * @return
 803  *   Number of packets successfully transmitted (<= pkts_n).
 804  */
 805 uint16_t
 806 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 807 {
 808         struct txq *txq = (struct txq *)dpdk_txq;
 809         uint16_t elts_head = txq->elts_head;
 810         const uint16_t elts_n = 1 << txq->elts_n;
 811         const uint16_t elts_m = elts_n - 1;
 812         unsigned int i = 0;
 813         unsigned int j = 0;
 814         uint16_t max_elts;
 815         uint16_t max_wqe;
 816         unsigned int comp;
 817         struct mlx5_mpw mpw = {
 818                 .state = MLX5_MPW_STATE_CLOSED,
 819         };
 820
 821         if (unlikely(!pkts_n))
 822                 return 0;
 823         /* Prefetch first packet cacheline. */
 824         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 825         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 826         /* Start processing. */
 827         mlx5_tx_complete(txq);
 828         max_elts = (elts_n - (elts_head - txq->elts_tail));
 829         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 830         if (unlikely(!max_wqe))
 831                 return 0;
 832         do {
 833                 struct rte_mbuf *buf = *(pkts++);
 834                 uint32_t length;
 835                 unsigned int segs_n = buf->nb_segs;
 836                 uint32_t cs_flags = 0;
 837
 838                 /*
 839                  * Make sure there is enough room to store this packet and
 840                  * that one ring entry remains unused.
 841                  */
 842                 assert(segs_n);
 843                 if (max_elts < segs_n)
 844                         break;
 845                 /* Do not bother with large packets MPW cannot handle. */
 846                 if (segs_n > MLX5_MPW_DSEG_MAX)
 847                         break;
 848                 max_elts -= segs_n;
 849                 --pkts_n;
 850                 /* Should we enable HW CKSUM offload */
 851                 if (buf->ol_flags &
 852                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 853                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 854                 /* Retrieve packet information. */
 855                 length = PKT_LEN(buf);
 856                 assert(length);
 857                 /* Start new session if packet differs. */
 858                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 859                     ((mpw.len != length) ||
 860                      (segs_n != 1) ||
 861                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 862                         mlx5_mpw_close(txq, &mpw);
 863                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 864                         /*
 865                          * Multi-Packet WQE consumes at most two WQE.
 866                          * mlx5_mpw_new() expects to be able to use such
 867                          * resources.
 868                          */
 869                         if (unlikely(max_wqe < 2))
 870                                 break;
 871                         max_wqe -= 2;
 872                         mlx5_mpw_new(txq, &mpw, length);
 873                         mpw.wqe->eseg.cs_flags = cs_flags;
 874                 }
 875                 /* Multi-segment packets must be alone in their MPW. */
 876                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 877 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 878                 length = 0;
 879 #endif
 880                 do {
 881                         volatile struct mlx5_wqe_data_seg *dseg;
 882                         uintptr_t addr;
 883
 884                         assert(buf);
 885                         (*txq->elts)[elts_head++ & elts_m] = buf;
 886                         dseg = mpw.data.dseg[mpw.pkts_n];
 887                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 888                         *dseg = (struct mlx5_wqe_data_seg){
 889                                 .byte_count = htonl(DATA_LEN(buf)),
 890                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 891                                 .addr = htonll(addr),
 892                         };
 893 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 894                         length += DATA_LEN(buf);
 895 #endif
 896                         buf = buf->next;
 897                         ++mpw.pkts_n;
 898                         ++j;
 899                 } while (--segs_n);
 900                 assert(length == mpw.len);
 901                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 902                         mlx5_mpw_close(txq, &mpw);
 903 #ifdef MLX5_PMD_SOFT_COUNTERS
 904                 /* Increment sent bytes counter. */
 905                 txq->stats.obytes += length;
 906 #endif
 907                 ++i;
 908         } while (pkts_n);
 909         /* Take a shortcut if nothing must be sent. */
 910         if (unlikely(i == 0))
 911                 return 0;
 912         /* Check whether completion threshold has been reached. */
 913         /* "j" includes both packets and segments. */
 914         comp = txq->elts_comp + j;
 915         if (comp >= MLX5_TX_COMP_THRESH) {
 916                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 917
 918                 /* Request completion on last WQE. */
 919                 wqe->ctrl[2] = htonl(8);
 920                 /* Save elts_head in unused "immediate" field of WQE. */
 921                 wqe->ctrl[3] = elts_head;
 922                 txq->elts_comp = 0;
 923         } else {
 924                 txq->elts_comp = comp;
 925         }
 926 #ifdef MLX5_PMD_SOFT_COUNTERS
 927         /* Increment sent packets counter. */
 928         txq->stats.opackets += i;
 929 #endif
 930         /* Ring QP doorbell. */
 931         if (mpw.state == MLX5_MPW_STATE_OPENED)
 932                 mlx5_mpw_close(txq, &mpw);
 933         mlx5_tx_dbrec(txq, mpw.wqe);
 934         txq->elts_head = elts_head;
 935         return i;
 936 }
 937
 938 /**
 939  * Open a MPW inline session.
 940  *
 941  * @param txq
 942  *   Pointer to TX queue structure.
 943  * @param mpw
 944  *   Pointer to MPW session structure.
 945  * @param length
 946  *   Packet length.
 947  */
 948 static inline void
 949 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 950 {
 951         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 952         struct mlx5_wqe_inl_small *inl;
 953
 954         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 955         mpw->pkts_n = 0;
 956         mpw->len = length;
 957         mpw->total_len = 0;
 958         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 959         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 960                                   (txq->wqe_ci << 8) |
 961                                   MLX5_OPCODE_TSO);
 962         mpw->wqe->ctrl[2] = 0;
 963         mpw->wqe->ctrl[3] = 0;
 964         mpw->wqe->eseg.mss = htons(length);
 965         mpw->wqe->eseg.inline_hdr_sz = 0;
 966         mpw->wqe->eseg.cs_flags = 0;
 967         mpw->wqe->eseg.rsvd0 = 0;
 968         mpw->wqe->eseg.rsvd1 = 0;
 969         mpw->wqe->eseg.rsvd2 = 0;
 970         inl = (struct mlx5_wqe_inl_small *)
 971                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 972         mpw->data.raw = (uint8_t *)&inl->raw;
 973 }
 974
 975 /**
 976  * Close a MPW inline session.
 977  *
 978  * @param txq
 979  *   Pointer to TX queue structure.
 980  * @param mpw
 981  *   Pointer to MPW session structure.
 982  */
 983 static inline void
 984 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
 985 {
 986         unsigned int size;
 987         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 988                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 989
 990         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 991         /*
 992          * Store size in multiple of 16 bytes. Control and Ethernet segments
 993          * count as 2.
 994          */
 995         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
 996         mpw->state = MLX5_MPW_STATE_CLOSED;
 997         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
 998         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 999 }
1000
1001 /**
1002  * DPDK callback for TX with MPW inline support.
1003  *
1004  * @param dpdk_txq
1005  *   Generic pointer to TX queue structure.
1006  * @param[in] pkts
1007  *   Packets to transmit.
1008  * @param pkts_n
1009  *   Number of packets in array.
1010  *
1011  * @return
1012  *   Number of packets successfully transmitted (<= pkts_n).
1013  */
1014 uint16_t
1015 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1016                          uint16_t pkts_n)
1017 {
1018         struct txq *txq = (struct txq *)dpdk_txq;
1019         uint16_t elts_head = txq->elts_head;
1020         const uint16_t elts_n = 1 << txq->elts_n;
1021         const uint16_t elts_m = elts_n - 1;
1022         unsigned int i = 0;
1023         unsigned int j = 0;
1024         uint16_t max_elts;
1025         uint16_t max_wqe;
1026         unsigned int comp;
1027         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1028         struct mlx5_mpw mpw = {
1029                 .state = MLX5_MPW_STATE_CLOSED,
1030         };
1031         /*
1032          * Compute the maximum number of WQE which can be consumed by inline
1033          * code.
1034          * - 2 DSEG for:
1035          *   - 1 control segment,
1036          *   - 1 Ethernet segment,
1037          * - N Dseg from the inline request.
1038          */
1039         const unsigned int wqe_inl_n =
1040                 ((2 * MLX5_WQE_DWORD_SIZE +
1041                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1042                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1043
1044         if (unlikely(!pkts_n))
1045                 return 0;
1046         /* Prefetch first packet cacheline. */
1047         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1048         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1049         /* Start processing. */
1050         mlx5_tx_complete(txq);
1051         max_elts = (elts_n - (elts_head - txq->elts_tail));
1052         do {
1053                 struct rte_mbuf *buf = *(pkts++);
1054                 uintptr_t addr;
1055                 uint32_t length;
1056                 unsigned int segs_n = buf->nb_segs;
1057                 uint32_t cs_flags = 0;
1058
1059                 /*
1060                  * Make sure there is enough room to store this packet and
1061                  * that one ring entry remains unused.
1062                  */
1063                 assert(segs_n);
1064                 if (max_elts < segs_n)
1065                         break;
1066                 /* Do not bother with large packets MPW cannot handle. */
1067                 if (segs_n > MLX5_MPW_DSEG_MAX)
1068                         break;
1069                 max_elts -= segs_n;
1070                 --pkts_n;
1071                 /*
1072                  * Compute max_wqe in case less WQE were consumed in previous
1073                  * iteration.
1074                  */
1075                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1076                 /* Should we enable HW CKSUM offload */
1077                 if (buf->ol_flags &
1078                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1079                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1080                 /* Retrieve packet information. */
1081                 length = PKT_LEN(buf);
1082                 /* Start new session if packet differs. */
1083                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1084                         if ((mpw.len != length) ||
1085                             (segs_n != 1) ||
1086                             (mpw.wqe->eseg.cs_flags != cs_flags))
1087                                 mlx5_mpw_close(txq, &mpw);
1088                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1089                         if ((mpw.len != length) ||
1090                             (segs_n != 1) ||
1091                             (length > inline_room) ||
1092                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1093                                 mlx5_mpw_inline_close(txq, &mpw);
1094                                 inline_room =
1095                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1096                         }
1097                 }
1098                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1099                         if ((segs_n != 1) ||
1100                             (length > inline_room)) {
1101                                 /*
1102                                  * Multi-Packet WQE consumes at most two WQE.
1103                                  * mlx5_mpw_new() expects to be able to use
1104                                  * such resources.
1105                                  */
1106                                 if (unlikely(max_wqe < 2))
1107                                         break;
1108                                 max_wqe -= 2;
1109                                 mlx5_mpw_new(txq, &mpw, length);
1110                                 mpw.wqe->eseg.cs_flags = cs_flags;
1111                         } else {
1112                                 if (unlikely(max_wqe < wqe_inl_n))
1113                                         break;
1114                                 max_wqe -= wqe_inl_n;
1115                                 mlx5_mpw_inline_new(txq, &mpw, length);
1116                                 mpw.wqe->eseg.cs_flags = cs_flags;
1117                         }
1118                 }
1119                 /* Multi-segment packets must be alone in their MPW. */
1120                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1121                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1122                         assert(inline_room ==
1123                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1124 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1125                         length = 0;
1126 #endif
1127                         do {
1128                                 volatile struct mlx5_wqe_data_seg *dseg;
1129
1130                                 assert(buf);
1131                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1132                                 dseg = mpw.data.dseg[mpw.pkts_n];
1133                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1134                                 *dseg = (struct mlx5_wqe_data_seg){
1135                                         .byte_count = htonl(DATA_LEN(buf)),
1136                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1137                                         .addr = htonll(addr),
1138                                 };
1139 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1140                                 length += DATA_LEN(buf);
1141 #endif
1142                                 buf = buf->next;
1143                                 ++mpw.pkts_n;
1144                                 ++j;
1145                         } while (--segs_n);
1146                         assert(length == mpw.len);
1147                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1148                                 mlx5_mpw_close(txq, &mpw);
1149                 } else {
1150                         unsigned int max;
1151
1152                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1153                         assert(length <= inline_room);
1154                         assert(length == DATA_LEN(buf));
1155                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1156                         (*txq->elts)[elts_head++ & elts_m] = buf;
1157                         /* Maximum number of bytes before wrapping. */
1158                         max = ((((uintptr_t)(txq->wqes)) +
1159                                 (1 << txq->wqe_n) *
1160                                 MLX5_WQE_SIZE) -
1161                                (uintptr_t)mpw.data.raw);
1162                         if (length > max) {
1163                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1164                                            (void *)addr,
1165                                            max);
1166                                 mpw.data.raw = (volatile void *)txq->wqes;
1167                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1168                                            (void *)(addr + max),
1169                                            length - max);
1170                                 mpw.data.raw += length - max;
1171                         } else {
1172                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1173                                            (void *)addr,
1174                                            length);
1175
1176                                 if (length == max)
1177                                         mpw.data.raw =
1178                                                 (volatile void *)txq->wqes;
1179                                 else
1180                                         mpw.data.raw += length;
1181                         }
1182                         ++mpw.pkts_n;
1183                         mpw.total_len += length;
1184                         ++j;
1185                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1186                                 mlx5_mpw_inline_close(txq, &mpw);
1187                                 inline_room =
1188                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1189                         } else {
1190                                 inline_room -= length;
1191                         }
1192                 }
1193 #ifdef MLX5_PMD_SOFT_COUNTERS
1194                 /* Increment sent bytes counter. */
1195                 txq->stats.obytes += length;
1196 #endif
1197                 ++i;
1198         } while (pkts_n);
1199         /* Take a shortcut if nothing must be sent. */
1200         if (unlikely(i == 0))
1201                 return 0;
1202         /* Check whether completion threshold has been reached. */
1203         /* "j" includes both packets and segments. */
1204         comp = txq->elts_comp + j;
1205         if (comp >= MLX5_TX_COMP_THRESH) {
1206                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1207
1208                 /* Request completion on last WQE. */
1209                 wqe->ctrl[2] = htonl(8);
1210                 /* Save elts_head in unused "immediate" field of WQE. */
1211                 wqe->ctrl[3] = elts_head;
1212                 txq->elts_comp = 0;
1213         } else {
1214                 txq->elts_comp = comp;
1215         }
1216 #ifdef MLX5_PMD_SOFT_COUNTERS
1217         /* Increment sent packets counter. */
1218         txq->stats.opackets += i;
1219 #endif
1220         /* Ring QP doorbell. */
1221         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1222                 mlx5_mpw_inline_close(txq, &mpw);
1223         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1224                 mlx5_mpw_close(txq, &mpw);
1225         mlx5_tx_dbrec(txq, mpw.wqe);
1226         txq->elts_head = elts_head;
1227         return i;
1228 }
1229
1230 /**
1231  * Open an Enhanced MPW session.
1232  *
1233  * @param txq
1234  *   Pointer to TX queue structure.
1235  * @param mpw
1236  *   Pointer to MPW session structure.
1237  * @param length
1238  *   Packet length.
1239  */
1240 static inline void
1241 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1242 {
1243         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1244
1245         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1246         mpw->pkts_n = 0;
1247         mpw->total_len = sizeof(struct mlx5_wqe);
1248         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1249         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1250                                   (txq->wqe_ci << 8) |
1251                                   MLX5_OPCODE_ENHANCED_MPSW);
1252         mpw->wqe->ctrl[2] = 0;
1253         mpw->wqe->ctrl[3] = 0;
1254         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1255         if (unlikely(padding)) {
1256                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1257
1258                 /* Pad the first 2 DWORDs with zero-length inline header. */
1259                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1260                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1261                         htonl(MLX5_INLINE_SEG);
1262                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1263                 /* Start from the next WQEBB. */
1264                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1265         } else {
1266                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1267         }
1268 }
1269
1270 /**
1271  * Close an Enhanced MPW session.
1272  *
1273  * @param txq
1274  *   Pointer to TX queue structure.
1275  * @param mpw
1276  *   Pointer to MPW session structure.
1277  *
1278  * @return
1279  *   Number of consumed WQEs.
1280  */
1281 static inline uint16_t
1282 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1283 {
1284         uint16_t ret;
1285
1286         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1287          * count as 2.
1288          */
1289         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1290         mpw->state = MLX5_MPW_STATE_CLOSED;
1291         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1292         txq->wqe_ci += ret;
1293         return ret;
1294 }
1295
1296 /**
1297  * DPDK callback for TX with Enhanced MPW support.
1298  *
1299  * @param dpdk_txq
1300  *   Generic pointer to TX queue structure.
1301  * @param[in] pkts
1302  *   Packets to transmit.
1303  * @param pkts_n
1304  *   Number of packets in array.
1305  *
1306  * @return
1307  *   Number of packets successfully transmitted (<= pkts_n).
1308  */
1309 uint16_t
1310 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1311 {
1312         struct txq *txq = (struct txq *)dpdk_txq;
1313         uint16_t elts_head = txq->elts_head;
1314         const uint16_t elts_n = 1 << txq->elts_n;
1315         const uint16_t elts_m = elts_n - 1;
1316         unsigned int i = 0;
1317         unsigned int j = 0;
1318         uint16_t max_elts;
1319         uint16_t max_wqe;
1320         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1321         unsigned int mpw_room = 0;
1322         unsigned int inl_pad = 0;
1323         uint32_t inl_hdr;
1324         struct mlx5_mpw mpw = {
1325                 .state = MLX5_MPW_STATE_CLOSED,
1326         };
1327
1328         if (unlikely(!pkts_n))
1329                 return 0;
1330         /* Start processing. */
1331         mlx5_tx_complete(txq);
1332         max_elts = (elts_n - (elts_head - txq->elts_tail));
1333         /* A CQE slot must always be available. */
1334         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1335         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1336         if (unlikely(!max_wqe))
1337                 return 0;
1338         do {
1339                 struct rte_mbuf *buf = *(pkts++);
1340                 uintptr_t addr;
1341                 uint64_t naddr;
1342                 unsigned int n;
1343                 unsigned int do_inline = 0; /* Whether inline is possible. */
1344                 uint32_t length;
1345                 unsigned int segs_n = buf->nb_segs;
1346                 uint32_t cs_flags = 0;
1347
1348                 /*
1349                  * Make sure there is enough room to store this packet and
1350                  * that one ring entry remains unused.
1351                  */
1352                 assert(segs_n);
1353                 if (max_elts - j < segs_n)
1354                         break;
1355                 /* Do not bother with large packets MPW cannot handle. */
1356                 if (segs_n > MLX5_MPW_DSEG_MAX)
1357                         break;
1358                 /* Should we enable HW CKSUM offload. */
1359                 if (buf->ol_flags &
1360                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1361                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1362                 /* Retrieve packet information. */
1363                 length = PKT_LEN(buf);
1364                 /* Start new session if:
1365                  * - multi-segment packet
1366                  * - no space left even for a dseg
1367                  * - next packet can be inlined with a new WQE
1368                  * - cs_flag differs
1369                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1370                  * segmented packet.
1371                  */
1372                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1373                         if ((segs_n != 1) ||
1374                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1375                               mpw_room) ||
1376                             (length <= txq->inline_max_packet_sz &&
1377                              inl_pad + sizeof(inl_hdr) + length >
1378                               mpw_room) ||
1379                             (mpw.wqe->eseg.cs_flags != cs_flags))
1380                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1381                 }
1382                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1383                         if (unlikely(segs_n != 1)) {
1384                                 /* Fall back to legacy MPW.
1385                                  * A MPW session consumes 2 WQEs at most to
1386                                  * include MLX5_MPW_DSEG_MAX pointers.
1387                                  */
1388                                 if (unlikely(max_wqe < 2))
1389                                         break;
1390                                 mlx5_mpw_new(txq, &mpw, length);
1391                         } else {
1392                                 /* In Enhanced MPW, inline as much as the budget
1393                                  * is allowed. The remaining space is to be
1394                                  * filled with dsegs. If the title WQEBB isn't
1395                                  * padded, it will have 2 dsegs there.
1396                                  */
1397                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1398                                             (max_inline ? max_inline :
1399                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1400                                             MLX5_WQE_SIZE);
1401                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1402                                               mpw_room))
1403                                         break;
1404                                 /* Don't pad the title WQEBB to not waste WQ. */
1405                                 mlx5_empw_new(txq, &mpw, 0);
1406                                 mpw_room -= mpw.total_len;
1407                                 inl_pad = 0;
1408                                 do_inline =
1409                                         length <= txq->inline_max_packet_sz &&
1410                                         sizeof(inl_hdr) + length <= mpw_room &&
1411                                         !txq->mpw_hdr_dseg;
1412                         }
1413                         mpw.wqe->eseg.cs_flags = cs_flags;
1414                 } else {
1415                         /* Evaluate whether the next packet can be inlined.
1416                          * Inlininig is possible when:
1417                          * - length is less than configured value
1418                          * - length fits for remaining space
1419                          * - not required to fill the title WQEBB with dsegs
1420                          */
1421                         do_inline =
1422                                 length <= txq->inline_max_packet_sz &&
1423                                 inl_pad + sizeof(inl_hdr) + length <=
1424                                  mpw_room &&
1425                                 (!txq->mpw_hdr_dseg ||
1426                                  mpw.total_len >= MLX5_WQE_SIZE);
1427                 }
1428                 /* Multi-segment packets must be alone in their MPW. */
1429                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1430                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1431 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1432                         length = 0;
1433 #endif
1434                         do {
1435                                 volatile struct mlx5_wqe_data_seg *dseg;
1436
1437                                 assert(buf);
1438                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1439                                 dseg = mpw.data.dseg[mpw.pkts_n];
1440                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1441                                 *dseg = (struct mlx5_wqe_data_seg){
1442                                         .byte_count = htonl(DATA_LEN(buf)),
1443                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1444                                         .addr = htonll(addr),
1445                                 };
1446 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1447                                 length += DATA_LEN(buf);
1448 #endif
1449                                 buf = buf->next;
1450                                 ++j;
1451                                 ++mpw.pkts_n;
1452                         } while (--segs_n);
1453                         /* A multi-segmented packet takes one MPW session.
1454                          * TODO: Pack more multi-segmented packets if possible.
1455                          */
1456                         mlx5_mpw_close(txq, &mpw);
1457                         if (mpw.pkts_n < 3)
1458                                 max_wqe--;
1459                         else
1460                                 max_wqe -= 2;
1461                 } else if (do_inline) {
1462                         /* Inline packet into WQE. */
1463                         unsigned int max;
1464
1465                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1466                         assert(length == DATA_LEN(buf));
1467                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1468                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1469                         mpw.data.raw = (volatile void *)
1470                                 ((uintptr_t)mpw.data.raw + inl_pad);
1471                         max = tx_mlx5_wq_tailroom(txq,
1472                                         (void *)(uintptr_t)mpw.data.raw);
1473                         /* Copy inline header. */
1474                         mpw.data.raw = (volatile void *)
1475                                 mlx5_copy_to_wq(
1476                                           (void *)(uintptr_t)mpw.data.raw,
1477                                           &inl_hdr,
1478                                           sizeof(inl_hdr),
1479                                           (void *)(uintptr_t)txq->wqes,
1480                                           max);
1481                         max = tx_mlx5_wq_tailroom(txq,
1482                                         (void *)(uintptr_t)mpw.data.raw);
1483                         /* Copy packet data. */
1484                         mpw.data.raw = (volatile void *)
1485                                 mlx5_copy_to_wq(
1486                                           (void *)(uintptr_t)mpw.data.raw,
1487                                           (void *)addr,
1488                                           length,
1489                                           (void *)(uintptr_t)txq->wqes,
1490                                           max);
1491                         ++mpw.pkts_n;
1492                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1493                         /* No need to get completion as the entire packet is
1494                          * copied to WQ. Free the buf right away.
1495                          */
1496                         rte_pktmbuf_free_seg(buf);
1497                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1498                         /* Add pad in the next packet if any. */
1499                         inl_pad = (((uintptr_t)mpw.data.raw +
1500                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1501                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1502                                   (uintptr_t)mpw.data.raw;
1503                 } else {
1504                         /* No inline. Load a dseg of packet pointer. */
1505                         volatile rte_v128u32_t *dseg;
1506
1507                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1508                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1509                         assert(length == DATA_LEN(buf));
1510                         if (!tx_mlx5_wq_tailroom(txq,
1511                                         (void *)((uintptr_t)mpw.data.raw
1512                                                 + inl_pad)))
1513                                 dseg = (volatile void *)txq->wqes;
1514                         else
1515                                 dseg = (volatile void *)
1516                                         ((uintptr_t)mpw.data.raw +
1517                                          inl_pad);
1518                         (*txq->elts)[elts_head++ & elts_m] = buf;
1519                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1520                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1521                                 rte_prefetch2((void *)(addr +
1522                                                 n * RTE_CACHE_LINE_SIZE));
1523                         naddr = htonll(addr);
1524                         *dseg = (rte_v128u32_t) {
1525                                 htonl(length),
1526                                 mlx5_tx_mb2mr(txq, buf),
1527                                 naddr,
1528                                 naddr >> 32,
1529                         };
1530                         mpw.data.raw = (volatile void *)(dseg + 1);
1531                         mpw.total_len += (inl_pad + sizeof(*dseg));
1532                         ++j;
1533                         ++mpw.pkts_n;
1534                         mpw_room -= (inl_pad + sizeof(*dseg));
1535                         inl_pad = 0;
1536                 }
1537 #ifdef MLX5_PMD_SOFT_COUNTERS
1538                 /* Increment sent bytes counter. */
1539                 txq->stats.obytes += length;
1540 #endif
1541                 ++i;
1542         } while (i < pkts_n);
1543         /* Take a shortcut if nothing must be sent. */
1544         if (unlikely(i == 0))
1545                 return 0;
1546         /* Check whether completion threshold has been reached. */
1547         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1548                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1549                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1550                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1551
1552                 /* Request completion on last WQE. */
1553                 wqe->ctrl[2] = htonl(8);
1554                 /* Save elts_head in unused "immediate" field of WQE. */
1555                 wqe->ctrl[3] = elts_head;
1556                 txq->elts_comp = 0;
1557                 txq->mpw_comp = txq->wqe_ci;
1558                 txq->cq_pi++;
1559         } else {
1560                 txq->elts_comp += j;
1561         }
1562 #ifdef MLX5_PMD_SOFT_COUNTERS
1563         /* Increment sent packets counter. */
1564         txq->stats.opackets += i;
1565 #endif
1566         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1567                 mlx5_empw_close(txq, &mpw);
1568         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1569                 mlx5_mpw_close(txq, &mpw);
1570         /* Ring QP doorbell. */
1571         mlx5_tx_dbrec(txq, mpw.wqe);
1572         txq->elts_head = elts_head;
1573         return i;
1574 }
1575
1576 /**
1577  * Translate RX completion flags to packet type.
1578  *
1579  * @param[in] cqe
1580  *   Pointer to CQE.
1581  *
1582  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1583  *
1584  * @return
1585  *   Packet type for struct rte_mbuf.
1586  */
1587 static inline uint32_t
1588 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1589 {
1590         uint8_t idx;
1591         uint8_t pinfo = cqe->pkt_info;
1592         uint16_t ptype = cqe->hdr_type_etc;
1593
1594         /*
1595          * The index to the array should have:
1596          * bit[1:0] = l3_hdr_type
1597          * bit[4:2] = l4_hdr_type
1598          * bit[5] = ip_frag
1599          * bit[6] = tunneled
1600          * bit[7] = outer_l3_type
1601          */
1602         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1603         return mlx5_ptype_table[idx];
1604 }
1605
1606 /**
1607  * Get size of the next packet for a given CQE. For compressed CQEs, the
1608  * consumer index is updated only once all packets of the current one have
1609  * been processed.
1610  *
1611  * @param rxq
1612  *   Pointer to RX queue.
1613  * @param cqe
1614  *   CQE to process.
1615  * @param[out] rss_hash
1616  *   Packet RSS Hash result.
1617  *
1618  * @return
1619  *   Packet size in bytes (0 if there is none), -1 in case of completion
1620  *   with error.
1621  */
1622 static inline int
1623 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1624                  uint16_t cqe_cnt, uint32_t *rss_hash)
1625 {
1626         struct rxq_zip *zip = &rxq->zip;
1627         uint16_t cqe_n = cqe_cnt + 1;
1628         int len = 0;
1629         uint16_t idx, end;
1630
1631         /* Process compressed data in the CQE and mini arrays. */
1632         if (zip->ai) {
1633                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1634                         (volatile struct mlx5_mini_cqe8 (*)[8])
1635                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1636
1637                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1638                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1639                 if ((++zip->ai & 7) == 0) {
1640                         /* Invalidate consumed CQEs */
1641                         idx = zip->ca;
1642                         end = zip->na;
1643                         while (idx != end) {
1644                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1645                                         MLX5_CQE_INVALIDATE;
1646                                 ++idx;
1647                         }
1648                         /*
1649                          * Increment consumer index to skip the number of
1650                          * CQEs consumed. Hardware leaves holes in the CQ
1651                          * ring for software use.
1652                          */
1653                         zip->ca = zip->na;
1654                         zip->na += 8;
1655                 }
1656                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1657                         /* Invalidate the rest */
1658                         idx = zip->ca;
1659                         end = zip->cq_ci;
1660
1661                         while (idx != end) {
1662                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1663                                         MLX5_CQE_INVALIDATE;
1664                                 ++idx;
1665                         }
1666                         rxq->cq_ci = zip->cq_ci;
1667                         zip->ai = 0;
1668                 }
1669         /* No compressed data, get next CQE and verify if it is compressed. */
1670         } else {
1671                 int ret;
1672                 int8_t op_own;
1673
1674                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1675                 if (unlikely(ret == 1))
1676                         return 0;
1677                 ++rxq->cq_ci;
1678                 op_own = cqe->op_own;
1679                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1680                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1681                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1682                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1683                                                           cqe_cnt].pkt_info);
1684
1685                         /* Fix endianness. */
1686                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1687                         /*
1688                          * Current mini array position is the one returned by
1689                          * check_cqe64().
1690                          *
1691                          * If completion comprises several mini arrays, as a
1692                          * special case the second one is located 7 CQEs after
1693                          * the initial CQE instead of 8 for subsequent ones.
1694                          */
1695                         zip->ca = rxq->cq_ci;
1696                         zip->na = zip->ca + 7;
1697                         /* Compute the next non compressed CQE. */
1698                         --rxq->cq_ci;
1699                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1700                         /* Get packet size to return. */
1701                         len = ntohl((*mc)[0].byte_cnt);
1702                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1703                         zip->ai = 1;
1704                         /* Prefetch all the entries to be invalidated */
1705                         idx = zip->ca;
1706                         end = zip->cq_ci;
1707                         while (idx != end) {
1708                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1709                                 ++idx;
1710                         }
1711                 } else {
1712                         len = ntohl(cqe->byte_cnt);
1713                         *rss_hash = ntohl(cqe->rx_hash_res);
1714                 }
1715                 /* Error while receiving packet. */
1716                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1717                         return -1;
1718         }
1719         return len;
1720 }
1721
1722 /**
1723  * Translate RX completion flags to offload flags.
1724  *
1725  * @param[in] rxq
1726  *   Pointer to RX queue structure.
1727  * @param[in] cqe
1728  *   Pointer to CQE.
1729  *
1730  * @return
1731  *   Offload flags (ol_flags) for struct rte_mbuf.
1732  */
1733 static inline uint32_t
1734 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1735 {
1736         uint32_t ol_flags = 0;
1737         uint16_t flags = ntohs(cqe->hdr_type_etc);
1738
1739         ol_flags =
1740                 TRANSPOSE(flags,
1741                           MLX5_CQE_RX_L3_HDR_VALID,
1742                           PKT_RX_IP_CKSUM_GOOD) |
1743                 TRANSPOSE(flags,
1744                           MLX5_CQE_RX_L4_HDR_VALID,
1745                           PKT_RX_L4_CKSUM_GOOD);
1746         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1747                 ol_flags |=
1748                         TRANSPOSE(flags,
1749                                   MLX5_CQE_RX_L3_HDR_VALID,
1750                                   PKT_RX_IP_CKSUM_GOOD) |
1751                         TRANSPOSE(flags,
1752                                   MLX5_CQE_RX_L4_HDR_VALID,
1753                                   PKT_RX_L4_CKSUM_GOOD);
1754         return ol_flags;
1755 }
1756
1757 /**
1758  * DPDK callback for RX.
1759  *
1760  * @param dpdk_rxq
1761  *   Generic pointer to RX queue structure.
1762  * @param[out] pkts
1763  *   Array to store received packets.
1764  * @param pkts_n
1765  *   Maximum number of packets in array.
1766  *
1767  * @return
1768  *   Number of packets successfully received (<= pkts_n).
1769  */
1770 uint16_t
1771 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1772 {
1773         struct rxq *rxq = dpdk_rxq;
1774         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1775         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1776         const unsigned int sges_n = rxq->sges_n;
1777         struct rte_mbuf *pkt = NULL;
1778         struct rte_mbuf *seg = NULL;
1779         volatile struct mlx5_cqe *cqe =
1780                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1781         unsigned int i = 0;
1782         unsigned int rq_ci = rxq->rq_ci << sges_n;
1783         int len = 0; /* keep its value across iterations. */
1784
1785         while (pkts_n) {
1786                 unsigned int idx = rq_ci & wqe_cnt;
1787                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1788                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1789                 uint32_t rss_hash_res = 0;
1790
1791                 if (pkt)
1792                         NEXT(seg) = rep;
1793                 seg = rep;
1794                 rte_prefetch0(seg);
1795                 rte_prefetch0(cqe);
1796                 rte_prefetch0(wqe);
1797                 rep = rte_mbuf_raw_alloc(rxq->mp);
1798                 if (unlikely(rep == NULL)) {
1799                         ++rxq->stats.rx_nombuf;
1800                         if (!pkt) {
1801                                 /*
1802                                  * no buffers before we even started,
1803                                  * bail out silently.
1804                                  */
1805                                 break;
1806                         }
1807                         while (pkt != seg) {
1808                                 assert(pkt != (*rxq->elts)[idx]);
1809                                 rep = NEXT(pkt);
1810                                 NEXT(pkt) = NULL;
1811                                 NB_SEGS(pkt) = 1;
1812                                 rte_mbuf_raw_free(pkt);
1813                                 pkt = rep;
1814                         }
1815                         break;
1816                 }
1817                 if (!pkt) {
1818                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1819                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1820                                                &rss_hash_res);
1821                         if (!len) {
1822                                 rte_mbuf_raw_free(rep);
1823                                 break;
1824                         }
1825                         if (unlikely(len == -1)) {
1826                                 /* RX error, packet is likely too large. */
1827                                 rte_mbuf_raw_free(rep);
1828                                 ++rxq->stats.idropped;
1829                                 goto skip;
1830                         }
1831                         pkt = seg;
1832                         assert(len >= (rxq->crc_present << 2));
1833                         /* Update packet information. */
1834                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1835                         pkt->ol_flags = 0;
1836                         if (rss_hash_res && rxq->rss_hash) {
1837                                 pkt->hash.rss = rss_hash_res;
1838                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1839                         }
1840                         if (rxq->mark &&
1841                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1842                                 pkt->ol_flags |= PKT_RX_FDIR;
1843                                 if (cqe->sop_drop_qpn !=
1844                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1845                                         uint32_t mark = cqe->sop_drop_qpn;
1846
1847                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1848                                         pkt->hash.fdir.hi =
1849                                                 mlx5_flow_mark_get(mark);
1850                                 }
1851                         }
1852                         if (rxq->csum | rxq->csum_l2tun)
1853                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1854                         if (rxq->vlan_strip &&
1855                             (cqe->hdr_type_etc &
1856                              htons(MLX5_CQE_VLAN_STRIPPED))) {
1857                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1858                                         PKT_RX_VLAN_STRIPPED;
1859                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
1860                         }
1861                         if (rxq->crc_present)
1862                                 len -= ETHER_CRC_LEN;
1863                         PKT_LEN(pkt) = len;
1864                 }
1865                 DATA_LEN(rep) = DATA_LEN(seg);
1866                 PKT_LEN(rep) = PKT_LEN(seg);
1867                 SET_DATA_OFF(rep, DATA_OFF(seg));
1868                 PORT(rep) = PORT(seg);
1869                 (*rxq->elts)[idx] = rep;
1870                 /*
1871                  * Fill NIC descriptor with the new buffer.  The lkey and size
1872                  * of the buffers are already known, only the buffer address
1873                  * changes.
1874                  */
1875                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1876                 if (len > DATA_LEN(seg)) {
1877                         len -= DATA_LEN(seg);
1878                         ++NB_SEGS(pkt);
1879                         ++rq_ci;
1880                         continue;
1881                 }
1882                 DATA_LEN(seg) = len;
1883 #ifdef MLX5_PMD_SOFT_COUNTERS
1884                 /* Increment bytes counter. */
1885                 rxq->stats.ibytes += PKT_LEN(pkt);
1886 #endif
1887                 /* Return packet. */
1888                 *(pkts++) = pkt;
1889                 pkt = NULL;
1890                 --pkts_n;
1891                 ++i;
1892 skip:
1893                 /* Align consumer index to the next stride. */
1894                 rq_ci >>= sges_n;
1895                 ++rq_ci;
1896                 rq_ci <<= sges_n;
1897         }
1898         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1899                 return 0;
1900         /* Update the consumer index. */
1901         rxq->rq_ci = rq_ci >> sges_n;
1902         rte_wmb();
1903         *rxq->cq_db = htonl(rxq->cq_ci);
1904         rte_wmb();
1905         *rxq->rq_db = htonl(rxq->rq_ci);
1906 #ifdef MLX5_PMD_SOFT_COUNTERS
1907         /* Increment packets counter. */
1908         rxq->stats.ipackets += i;
1909 #endif
1910         return i;
1911 }
1912
1913 /**
1914  * Dummy DPDK callback for TX.
1915  *
1916  * This function is used to temporarily replace the real callback during
1917  * unsafe control operations on the queue, or in case of error.
1918  *
1919  * @param dpdk_txq
1920  *   Generic pointer to TX queue structure.
1921  * @param[in] pkts
1922  *   Packets to transmit.
1923  * @param pkts_n
1924  *   Number of packets in array.
1925  *
1926  * @return
1927  *   Number of packets successfully transmitted (<= pkts_n).
1928  */
1929 uint16_t
1930 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1931 {
1932         (void)dpdk_txq;
1933         (void)pkts;
1934         (void)pkts_n;
1935         return 0;
1936 }
1937
1938 /**
1939  * Dummy DPDK callback for RX.
1940  *
1941  * This function is used to temporarily replace the real callback during
1942  * unsafe control operations on the queue, or in case of error.
1943  *
1944  * @param dpdk_rxq
1945  *   Generic pointer to RX queue structure.
1946  * @param[out] pkts
1947  *   Array to store received packets.
1948  * @param pkts_n
1949  *   Maximum number of packets in array.
1950  *
1951  * @return
1952  *   Number of packets successfully received (<= pkts_n).
1953  */
1954 uint16_t
1955 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1956 {
1957         (void)dpdk_rxq;
1958         (void)pkts;
1959         (void)pkts_n;
1960         return 0;
1961 }
1962
1963 /*
1964  * Vectorized Rx/Tx routines are not compiled in when required vector
1965  * instructions are not supported on a target architecture. The following null
1966  * stubs are needed for linkage when those are not included outside of this file
1967  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1968  */
1969
1970 uint16_t __attribute__((weak))
1971 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1972 {
1973         (void)dpdk_txq;
1974         (void)pkts;
1975         (void)pkts_n;
1976         return 0;
1977 }
1978
1979 uint16_t __attribute__((weak))
1980 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1981 {
1982         (void)dpdk_txq;
1983         (void)pkts;
1984         (void)pkts_n;
1985         return 0;
1986 }
1987
1988 uint16_t __attribute__((weak))
1989 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1990 {
1991         (void)dpdk_rxq;
1992         (void)pkts;
1993         (void)pkts_n;
1994         return 0;
1995 }
1996
1997 int __attribute__((weak))
1998 priv_check_raw_vec_tx_support(struct priv *priv)
1999 {
2000         (void)priv;
2001         return -ENOTSUP;
2002 }
2003
2004 int __attribute__((weak))
2005 priv_check_vec_tx_support(struct priv *priv)
2006 {
2007         (void)priv;
2008         return -ENOTSUP;
2009 }
2010
2011 int __attribute__((weak))
2012 rxq_check_vec_support(struct rxq *rxq)
2013 {
2014         (void)rxq;
2015         return -ENOTSUP;
2016 }
2017
2018 int __attribute__((weak))
2019 priv_check_vec_rx_support(struct priv *priv)
2020 {
2021         (void)priv;
2022         return -ENOTSUP;
2023 }