4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 txq_complete(struct txq *txq) __attribute__((always_inline));
159 * Manage TX completions.
161 * When sending a burst, mlx5_tx_burst() posts several WRs.
164 * Pointer to TX queue structure.
167 txq_complete(struct txq *txq)
169 const unsigned int elts_n = txq->elts_n;
170 const unsigned int cqe_n = txq->cqe_n;
171 const unsigned int cqe_cnt = cqe_n - 1;
172 uint16_t elts_free = txq->elts_tail;
174 uint16_t cq_ci = txq->cq_ci;
175 volatile struct mlx5_cqe64 *cqe = NULL;
176 volatile union mlx5_wqe *wqe;
179 volatile struct mlx5_cqe64 *tmp;
181 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
182 if (check_cqe64(tmp, cqe_n, cq_ci))
186 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
187 if (!check_cqe64_seen(cqe))
188 ERROR("unexpected compressed CQE, TX stopped");
191 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
192 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
193 if (!check_cqe64_seen(cqe))
194 ERROR("unexpected error CQE, TX stopped");
200 if (unlikely(cqe == NULL))
202 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)];
203 elts_tail = wqe->wqe.ctrl.data[3];
204 assert(elts_tail < txq->wqe_n);
206 while (elts_free != elts_tail) {
207 struct rte_mbuf *elt = (*txq->elts)[elts_free];
208 unsigned int elts_free_next =
209 (elts_free + 1) & (elts_n - 1);
210 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
214 memset(&(*txq->elts)[elts_free],
216 sizeof((*txq->elts)[elts_free]));
218 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
219 /* Only one segment needs to be freed. */
220 rte_pktmbuf_free_seg(elt);
221 elts_free = elts_free_next;
224 txq->elts_tail = elts_tail;
225 /* Update the consumer index. */
227 *txq->cq_db = htonl(cq_ci);
231 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
232 * the cloned mbuf is allocated is returned instead.
238 * Memory pool where data is located for given mbuf.
240 static struct rte_mempool *
241 txq_mb2mp(struct rte_mbuf *buf)
243 if (unlikely(RTE_MBUF_INDIRECT(buf)))
244 return rte_mbuf_from_indirect(buf)->pool;
248 static inline uint32_t
249 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
250 __attribute__((always_inline));
253 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
254 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
255 * remove an entry first.
258 * Pointer to TX queue structure.
260 * Memory Pool for which a Memory Region lkey must be returned.
263 * mr->lkey on success, (uint32_t)-1 on failure.
265 static inline uint32_t
266 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
269 uint32_t lkey = (uint32_t)-1;
271 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
272 if (unlikely(txq->mp2mr[i].mp == NULL)) {
273 /* Unknown MP, add a new MR for it. */
276 if (txq->mp2mr[i].mp == mp) {
277 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
278 assert(htonl(txq->mp2mr[i].mr->lkey) ==
280 lkey = txq->mp2mr[i].lkey;
284 if (unlikely(lkey == (uint32_t)-1))
285 lkey = txq_mp2mr_reg(txq, mp, i);
290 * Write a regular WQE.
293 * Pointer to TX queue structure.
295 * Pointer to the WQE to fill.
301 * Memory region lkey.
304 mlx5_wqe_write(struct txq *txq, volatile union mlx5_wqe *wqe,
305 struct rte_mbuf *buf, uint32_t length, uint32_t lkey)
307 uintptr_t addr = rte_pktmbuf_mtod(buf, uintptr_t);
309 rte_mov16((uint8_t *)&wqe->wqe.eseg.inline_hdr_start,
313 /* Need to insert VLAN ? */
314 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
315 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
317 memcpy((uint8_t *)&wqe->wqe.eseg.inline_hdr_start + 12,
318 &vlan, sizeof(vlan));
319 addr -= sizeof(vlan);
320 length += sizeof(vlan);
323 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
324 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
325 wqe->wqe.ctrl.data[2] = 0;
326 wqe->wqe.ctrl.data[3] = 0;
327 wqe->inl.eseg.rsvd0 = 0;
328 wqe->inl.eseg.rsvd1 = 0;
329 wqe->inl.eseg.mss = 0;
330 wqe->inl.eseg.rsvd2 = 0;
331 wqe->wqe.eseg.inline_hdr_sz = htons(16);
332 /* Store remaining data in data segment. */
333 wqe->wqe.dseg.byte_count = htonl(length);
334 wqe->wqe.dseg.lkey = lkey;
335 wqe->wqe.dseg.addr = htonll(addr);
336 /* Increment consumer index. */
341 * Write a inline WQE.
344 * Pointer to TX queue structure.
346 * Pointer to the WQE to fill.
348 * Buffer data address.
352 * Memory region lkey.
355 mlx5_wqe_write_inline(struct txq *txq, volatile union mlx5_wqe *wqe,
356 uintptr_t addr, uint32_t length)
359 uint16_t wqe_cnt = txq->wqe_n - 1;
360 uint16_t wqe_ci = txq->wqe_ci + 1;
362 /* Copy the first 16 bytes into inline header. */
363 rte_memcpy((void *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
364 (void *)(uintptr_t)addr,
365 MLX5_ETH_INLINE_HEADER_SIZE);
366 addr += MLX5_ETH_INLINE_HEADER_SIZE;
367 length -= MLX5_ETH_INLINE_HEADER_SIZE;
368 size = 3 + ((4 + length + 15) / 16);
369 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
370 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
371 (void *)addr, MLX5_WQE64_INL_DATA);
372 addr += MLX5_WQE64_INL_DATA;
373 length -= MLX5_WQE64_INL_DATA;
375 volatile union mlx5_wqe *wqe_next =
376 &(*txq->wqes)[wqe_ci & wqe_cnt];
377 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
381 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
384 length -= copy_bytes;
388 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
389 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
390 wqe->inl.ctrl.data[2] = 0;
391 wqe->inl.ctrl.data[3] = 0;
392 wqe->inl.eseg.rsvd0 = 0;
393 wqe->inl.eseg.rsvd1 = 0;
394 wqe->inl.eseg.mss = 0;
395 wqe->inl.eseg.rsvd2 = 0;
396 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
397 /* Increment consumer index. */
398 txq->wqe_ci = wqe_ci;
402 * Write a inline WQE with VLAN.
405 * Pointer to TX queue structure.
407 * Pointer to the WQE to fill.
409 * Buffer data address.
413 * Memory region lkey.
415 * VLAN field to insert in packet.
418 mlx5_wqe_write_inline_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
419 uintptr_t addr, uint32_t length, uint16_t vlan_tci)
422 uint32_t wqe_cnt = txq->wqe_n - 1;
423 uint16_t wqe_ci = txq->wqe_ci + 1;
424 uint32_t vlan = htonl(0x81000000 | vlan_tci);
427 * Copy 12 bytes of source & destination MAC address.
428 * Copy 4 bytes of VLAN.
429 * Copy 2 bytes of Ether type.
431 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
432 (uint8_t *)addr, 12);
433 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 12,
434 &vlan, sizeof(vlan));
435 rte_memcpy((uint8_t *)((uintptr_t)wqe->inl.eseg.inline_hdr_start + 16),
436 (uint8_t *)(addr + 12), 2);
437 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
438 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
439 size = (sizeof(wqe->inl.ctrl.ctrl) +
440 sizeof(wqe->inl.eseg) +
441 sizeof(wqe->inl.byte_cnt) +
443 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
444 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
445 (void *)addr, MLX5_WQE64_INL_DATA);
446 addr += MLX5_WQE64_INL_DATA;
447 length -= MLX5_WQE64_INL_DATA;
449 volatile union mlx5_wqe *wqe_next =
450 &(*txq->wqes)[wqe_ci & wqe_cnt];
451 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
455 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
458 length -= copy_bytes;
462 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
463 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
464 wqe->inl.ctrl.data[2] = 0;
465 wqe->inl.ctrl.data[3] = 0;
466 wqe->inl.eseg.rsvd0 = 0;
467 wqe->inl.eseg.rsvd1 = 0;
468 wqe->inl.eseg.mss = 0;
469 wqe->inl.eseg.rsvd2 = 0;
470 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
471 /* Increment consumer index. */
472 txq->wqe_ci = wqe_ci;
476 * Ring TX queue doorbell.
479 * Pointer to TX queue structure.
482 mlx5_tx_dbrec(struct txq *txq)
484 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
486 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
487 htonl(txq->qp_num_8s),
492 *txq->qp_db = htonl(txq->wqe_ci);
493 /* Ensure ordering between DB record and BF copy. */
495 rte_mov16(dst, (uint8_t *)data);
496 txq->bf_offset ^= txq->bf_buf_size;
503 * Pointer to TX queue structure.
505 * CQE consumer index.
508 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
510 volatile struct mlx5_cqe64 *cqe;
512 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
520 * Pointer to TX queue structure.
522 * WQE consumer index.
525 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
527 volatile union mlx5_wqe *wqe;
529 wqe = &(*txq->wqes)[ci & (txq->wqe_n - 1)];
534 * DPDK callback for TX.
537 * Generic pointer to TX queue structure.
539 * Packets to transmit.
541 * Number of packets in array.
544 * Number of packets successfully transmitted (<= pkts_n).
547 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
549 struct txq *txq = (struct txq *)dpdk_txq;
550 uint16_t elts_head = txq->elts_head;
551 const unsigned int elts_n = txq->elts_n;
556 volatile union mlx5_wqe *wqe = NULL;
558 if (unlikely(!pkts_n))
560 /* Prefetch first packet cacheline. */
561 tx_prefetch_cqe(txq, txq->cq_ci);
562 tx_prefetch_cqe(txq, txq->cq_ci + 1);
563 rte_prefetch0(*pkts);
564 /* Start processing. */
566 max = (elts_n - (elts_head - txq->elts_tail));
570 struct rte_mbuf *buf = *(pkts++);
571 unsigned int elts_head_next;
574 unsigned int segs_n = buf->nb_segs;
575 volatile struct mlx5_wqe_data_seg *dseg;
576 unsigned int ds = sizeof(*wqe) / 16;
579 * Make sure there is enough room to store this packet and
580 * that one ring entry remains unused.
583 if (max < segs_n + 1)
587 elts_head_next = (elts_head + 1) & (elts_n - 1);
588 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
589 dseg = &wqe->wqe.dseg;
592 rte_prefetch0(*pkts);
593 length = DATA_LEN(buf);
594 /* Update element. */
595 (*txq->elts)[elts_head] = buf;
596 /* Prefetch next buffer data. */
598 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
600 /* Retrieve Memory Region key for this memory pool. */
601 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
602 mlx5_wqe_write(txq, wqe, buf, length, lkey);
603 /* Should we enable HW CKSUM offload */
605 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
606 wqe->wqe.eseg.cs_flags =
607 MLX5_ETH_WQE_L3_CSUM |
608 MLX5_ETH_WQE_L4_CSUM;
610 wqe->wqe.eseg.cs_flags = 0;
614 * Spill on next WQE when the current one does not have
615 * enough room left. Size of WQE must a be a multiple
616 * of data segment size.
618 assert(!(sizeof(*wqe) % sizeof(*dseg)));
619 if (!(ds % (sizeof(*wqe) / 16)))
620 dseg = (volatile void *)
621 &(*txq->wqes)[txq->wqe_ci++ &
628 /* Store segment information. */
629 dseg->byte_count = htonl(DATA_LEN(buf));
630 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
631 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
632 (*txq->elts)[elts_head_next] = buf;
633 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
634 #ifdef MLX5_PMD_SOFT_COUNTERS
635 length += DATA_LEN(buf);
639 /* Update DS field in WQE. */
640 wqe->wqe.ctrl.data[1] &= htonl(0xffffffc0);
641 wqe->wqe.ctrl.data[1] |= htonl(ds & 0x3f);
642 elts_head = elts_head_next;
643 #ifdef MLX5_PMD_SOFT_COUNTERS
644 /* Increment sent bytes counter. */
645 txq->stats.obytes += length;
647 elts_head = elts_head_next;
650 /* Take a shortcut if nothing must be sent. */
651 if (unlikely(i == 0))
653 /* Check whether completion threshold has been reached. */
654 comp = txq->elts_comp + i + j;
655 if (comp >= MLX5_TX_COMP_THRESH) {
656 /* Request completion on last WQE. */
657 wqe->wqe.ctrl.data[2] = htonl(8);
658 /* Save elts_head in unused "immediate" field of WQE. */
659 wqe->wqe.ctrl.data[3] = elts_head;
662 txq->elts_comp = comp;
664 #ifdef MLX5_PMD_SOFT_COUNTERS
665 /* Increment sent packets counter. */
666 txq->stats.opackets += i;
668 /* Ring QP doorbell. */
670 txq->elts_head = elts_head;
675 * DPDK callback for TX with inline support.
678 * Generic pointer to TX queue structure.
680 * Packets to transmit.
682 * Number of packets in array.
685 * Number of packets successfully transmitted (<= pkts_n).
688 mlx5_tx_burst_inline(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
690 struct txq *txq = (struct txq *)dpdk_txq;
691 uint16_t elts_head = txq->elts_head;
692 const unsigned int elts_n = txq->elts_n;
697 volatile union mlx5_wqe *wqe = NULL;
698 unsigned int max_inline = txq->max_inline;
700 if (unlikely(!pkts_n))
702 /* Prefetch first packet cacheline. */
703 tx_prefetch_cqe(txq, txq->cq_ci);
704 tx_prefetch_cqe(txq, txq->cq_ci + 1);
705 rte_prefetch0(*pkts);
706 /* Start processing. */
708 max = (elts_n - (elts_head - txq->elts_tail));
712 struct rte_mbuf *buf = *(pkts++);
713 unsigned int elts_head_next;
717 unsigned int segs_n = buf->nb_segs;
718 volatile struct mlx5_wqe_data_seg *dseg;
719 unsigned int ds = sizeof(*wqe) / 16;
722 * Make sure there is enough room to store this packet and
723 * that one ring entry remains unused.
726 if (max < segs_n + 1)
730 elts_head_next = (elts_head + 1) & (elts_n - 1);
731 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
732 dseg = &wqe->wqe.dseg;
733 tx_prefetch_wqe(txq, txq->wqe_ci);
734 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
736 rte_prefetch0(*pkts);
737 /* Should we enable HW CKSUM offload */
739 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
740 wqe->inl.eseg.cs_flags =
741 MLX5_ETH_WQE_L3_CSUM |
742 MLX5_ETH_WQE_L4_CSUM;
744 wqe->inl.eseg.cs_flags = 0;
746 /* Retrieve buffer information. */
747 addr = rte_pktmbuf_mtod(buf, uintptr_t);
748 length = DATA_LEN(buf);
749 /* Update element. */
750 (*txq->elts)[elts_head] = buf;
751 /* Prefetch next buffer data. */
753 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
755 if ((length <= max_inline) && (segs_n == 1)) {
756 if (buf->ol_flags & PKT_TX_VLAN_PKT)
757 mlx5_wqe_write_inline_vlan(txq, wqe,
761 mlx5_wqe_write_inline(txq, wqe, addr, length);
764 /* Retrieve Memory Region key for this memory pool. */
765 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
766 mlx5_wqe_write(txq, wqe, buf, length, lkey);
770 * Spill on next WQE when the current one does not have
771 * enough room left. Size of WQE must a be a multiple
772 * of data segment size.
774 assert(!(sizeof(*wqe) % sizeof(*dseg)));
775 if (!(ds % (sizeof(*wqe) / 16)))
776 dseg = (volatile void *)
777 &(*txq->wqes)[txq->wqe_ci++ &
784 /* Store segment information. */
785 dseg->byte_count = htonl(DATA_LEN(buf));
786 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
787 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
788 (*txq->elts)[elts_head_next] = buf;
789 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
790 #ifdef MLX5_PMD_SOFT_COUNTERS
791 length += DATA_LEN(buf);
795 /* Update DS field in WQE. */
796 wqe->inl.ctrl.data[1] &= htonl(0xffffffc0);
797 wqe->inl.ctrl.data[1] |= htonl(ds & 0x3f);
799 elts_head = elts_head_next;
800 #ifdef MLX5_PMD_SOFT_COUNTERS
801 /* Increment sent bytes counter. */
802 txq->stats.obytes += length;
806 /* Take a shortcut if nothing must be sent. */
807 if (unlikely(i == 0))
809 /* Check whether completion threshold has been reached. */
810 comp = txq->elts_comp + i + j;
811 if (comp >= MLX5_TX_COMP_THRESH) {
812 /* Request completion on last WQE. */
813 wqe->inl.ctrl.data[2] = htonl(8);
814 /* Save elts_head in unused "immediate" field of WQE. */
815 wqe->inl.ctrl.data[3] = elts_head;
818 txq->elts_comp = comp;
820 #ifdef MLX5_PMD_SOFT_COUNTERS
821 /* Increment sent packets counter. */
822 txq->stats.opackets += i;
824 /* Ring QP doorbell. */
826 txq->elts_head = elts_head;
831 * Open a MPW session.
834 * Pointer to TX queue structure.
836 * Pointer to MPW session structure.
841 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
843 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
844 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
845 (volatile struct mlx5_wqe_data_seg (*)[])
846 (uintptr_t)&(*txq->wqes)[(idx + 1) & (txq->wqe_n - 1)];
848 mpw->state = MLX5_MPW_STATE_OPENED;
852 mpw->wqe = &(*txq->wqes)[idx];
853 mpw->wqe->mpw.eseg.mss = htons(length);
854 mpw->wqe->mpw.eseg.inline_hdr_sz = 0;
855 mpw->wqe->mpw.eseg.rsvd0 = 0;
856 mpw->wqe->mpw.eseg.rsvd1 = 0;
857 mpw->wqe->mpw.eseg.rsvd2 = 0;
858 mpw->wqe->mpw.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
860 MLX5_OPCODE_LSO_MPW);
861 mpw->wqe->mpw.ctrl.data[2] = 0;
862 mpw->wqe->mpw.ctrl.data[3] = 0;
863 mpw->data.dseg[0] = &mpw->wqe->mpw.dseg[0];
864 mpw->data.dseg[1] = &mpw->wqe->mpw.dseg[1];
865 mpw->data.dseg[2] = &(*dseg)[0];
866 mpw->data.dseg[3] = &(*dseg)[1];
867 mpw->data.dseg[4] = &(*dseg)[2];
871 * Close a MPW session.
874 * Pointer to TX queue structure.
876 * Pointer to MPW session structure.
879 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
881 unsigned int num = mpw->pkts_n;
884 * Store size in multiple of 16 bytes. Control and Ethernet segments
887 mpw->wqe->mpw.ctrl.data[1] = htonl(txq->qp_num_8s | (2 + num));
888 mpw->state = MLX5_MPW_STATE_CLOSED;
893 tx_prefetch_wqe(txq, txq->wqe_ci);
894 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
898 * DPDK callback for TX with MPW support.
901 * Generic pointer to TX queue structure.
903 * Packets to transmit.
905 * Number of packets in array.
908 * Number of packets successfully transmitted (<= pkts_n).
911 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
913 struct txq *txq = (struct txq *)dpdk_txq;
914 uint16_t elts_head = txq->elts_head;
915 const unsigned int elts_n = txq->elts_n;
920 struct mlx5_mpw mpw = {
921 .state = MLX5_MPW_STATE_CLOSED,
924 if (unlikely(!pkts_n))
926 /* Prefetch first packet cacheline. */
927 tx_prefetch_cqe(txq, txq->cq_ci);
928 tx_prefetch_wqe(txq, txq->wqe_ci);
929 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
930 /* Start processing. */
932 max = (elts_n - (elts_head - txq->elts_tail));
936 struct rte_mbuf *buf = *(pkts++);
937 unsigned int elts_head_next;
939 unsigned int segs_n = buf->nb_segs;
940 uint32_t cs_flags = 0;
943 * Make sure there is enough room to store this packet and
944 * that one ring entry remains unused.
947 if (max < segs_n + 1)
949 /* Do not bother with large packets MPW cannot handle. */
950 if (segs_n > MLX5_MPW_DSEG_MAX)
954 /* Should we enable HW CKSUM offload */
956 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
957 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
958 /* Retrieve packet information. */
959 length = PKT_LEN(buf);
961 /* Start new session if packet differs. */
962 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
963 ((mpw.len != length) ||
965 (mpw.wqe->mpw.eseg.cs_flags != cs_flags)))
966 mlx5_mpw_close(txq, &mpw);
967 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
968 mlx5_mpw_new(txq, &mpw, length);
969 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
971 /* Multi-segment packets must be alone in their MPW. */
972 assert((segs_n == 1) || (mpw.pkts_n == 0));
973 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
977 volatile struct mlx5_wqe_data_seg *dseg;
980 elts_head_next = (elts_head + 1) & (elts_n - 1);
982 (*txq->elts)[elts_head] = buf;
983 dseg = mpw.data.dseg[mpw.pkts_n];
984 addr = rte_pktmbuf_mtod(buf, uintptr_t);
985 *dseg = (struct mlx5_wqe_data_seg){
986 .byte_count = htonl(DATA_LEN(buf)),
987 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
988 .addr = htonll(addr),
990 elts_head = elts_head_next;
991 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
992 length += DATA_LEN(buf);
998 assert(length == mpw.len);
999 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1000 mlx5_mpw_close(txq, &mpw);
1001 elts_head = elts_head_next;
1002 #ifdef MLX5_PMD_SOFT_COUNTERS
1003 /* Increment sent bytes counter. */
1004 txq->stats.obytes += length;
1008 /* Take a shortcut if nothing must be sent. */
1009 if (unlikely(i == 0))
1011 /* Check whether completion threshold has been reached. */
1012 /* "j" includes both packets and segments. */
1013 comp = txq->elts_comp + j;
1014 if (comp >= MLX5_TX_COMP_THRESH) {
1015 volatile union mlx5_wqe *wqe = mpw.wqe;
1017 /* Request completion on last WQE. */
1018 wqe->mpw.ctrl.data[2] = htonl(8);
1019 /* Save elts_head in unused "immediate" field of WQE. */
1020 wqe->mpw.ctrl.data[3] = elts_head;
1023 txq->elts_comp = comp;
1025 #ifdef MLX5_PMD_SOFT_COUNTERS
1026 /* Increment sent packets counter. */
1027 txq->stats.opackets += i;
1029 /* Ring QP doorbell. */
1030 if (mpw.state == MLX5_MPW_STATE_OPENED)
1031 mlx5_mpw_close(txq, &mpw);
1033 txq->elts_head = elts_head;
1038 * Open a MPW inline session.
1041 * Pointer to TX queue structure.
1043 * Pointer to MPW session structure.
1048 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1050 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
1052 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1056 mpw->wqe = &(*txq->wqes)[idx];
1057 mpw->wqe->mpw_inl.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1058 (txq->wqe_ci << 8) |
1059 MLX5_OPCODE_LSO_MPW);
1060 mpw->wqe->mpw_inl.ctrl.data[2] = 0;
1061 mpw->wqe->mpw_inl.ctrl.data[3] = 0;
1062 mpw->wqe->mpw_inl.eseg.mss = htons(length);
1063 mpw->wqe->mpw_inl.eseg.inline_hdr_sz = 0;
1064 mpw->wqe->mpw_inl.eseg.cs_flags = 0;
1065 mpw->wqe->mpw_inl.eseg.rsvd0 = 0;
1066 mpw->wqe->mpw_inl.eseg.rsvd1 = 0;
1067 mpw->wqe->mpw_inl.eseg.rsvd2 = 0;
1068 mpw->data.raw = &mpw->wqe->mpw_inl.data[0];
1072 * Close a MPW inline session.
1075 * Pointer to TX queue structure.
1077 * Pointer to MPW session structure.
1080 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1084 size = sizeof(*mpw->wqe) - MLX5_MWQE64_INL_DATA + mpw->total_len;
1086 * Store size in multiple of 16 bytes. Control and Ethernet segments
1089 mpw->wqe->mpw_inl.ctrl.data[1] =
1090 htonl(txq->qp_num_8s | ((size + 15) / 16));
1091 mpw->state = MLX5_MPW_STATE_CLOSED;
1092 mpw->wqe->mpw_inl.byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1093 txq->wqe_ci += (size + (sizeof(*mpw->wqe) - 1)) / sizeof(*mpw->wqe);
1097 * DPDK callback for TX with MPW inline support.
1100 * Generic pointer to TX queue structure.
1102 * Packets to transmit.
1104 * Number of packets in array.
1107 * Number of packets successfully transmitted (<= pkts_n).
1110 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1113 struct txq *txq = (struct txq *)dpdk_txq;
1114 uint16_t elts_head = txq->elts_head;
1115 const unsigned int elts_n = txq->elts_n;
1120 unsigned int inline_room = txq->max_inline;
1121 struct mlx5_mpw mpw = {
1122 .state = MLX5_MPW_STATE_CLOSED,
1125 if (unlikely(!pkts_n))
1127 /* Prefetch first packet cacheline. */
1128 tx_prefetch_cqe(txq, txq->cq_ci);
1129 tx_prefetch_wqe(txq, txq->wqe_ci);
1130 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
1131 /* Start processing. */
1133 max = (elts_n - (elts_head - txq->elts_tail));
1137 struct rte_mbuf *buf = *(pkts++);
1138 unsigned int elts_head_next;
1141 unsigned int segs_n = buf->nb_segs;
1142 uint32_t cs_flags = 0;
1145 * Make sure there is enough room to store this packet and
1146 * that one ring entry remains unused.
1149 if (max < segs_n + 1)
1151 /* Do not bother with large packets MPW cannot handle. */
1152 if (segs_n > MLX5_MPW_DSEG_MAX)
1156 /* Should we enable HW CKSUM offload */
1158 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1159 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1160 /* Retrieve packet information. */
1161 length = PKT_LEN(buf);
1162 /* Start new session if packet differs. */
1163 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1164 if ((mpw.len != length) ||
1166 (mpw.wqe->mpw.eseg.cs_flags != cs_flags))
1167 mlx5_mpw_close(txq, &mpw);
1168 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1169 if ((mpw.len != length) ||
1171 (length > inline_room) ||
1172 (mpw.wqe->mpw_inl.eseg.cs_flags != cs_flags)) {
1173 mlx5_mpw_inline_close(txq, &mpw);
1174 inline_room = txq->max_inline;
1177 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1178 if ((segs_n != 1) ||
1179 (length > inline_room)) {
1180 mlx5_mpw_new(txq, &mpw, length);
1181 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
1183 mlx5_mpw_inline_new(txq, &mpw, length);
1184 mpw.wqe->mpw_inl.eseg.cs_flags = cs_flags;
1187 /* Multi-segment packets must be alone in their MPW. */
1188 assert((segs_n == 1) || (mpw.pkts_n == 0));
1189 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1190 assert(inline_room == txq->max_inline);
1191 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1195 volatile struct mlx5_wqe_data_seg *dseg;
1198 (elts_head + 1) & (elts_n - 1);
1200 (*txq->elts)[elts_head] = buf;
1201 dseg = mpw.data.dseg[mpw.pkts_n];
1202 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1203 *dseg = (struct mlx5_wqe_data_seg){
1204 .byte_count = htonl(DATA_LEN(buf)),
1205 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1206 .addr = htonll(addr),
1208 elts_head = elts_head_next;
1209 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1210 length += DATA_LEN(buf);
1216 assert(length == mpw.len);
1217 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1218 mlx5_mpw_close(txq, &mpw);
1222 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1223 assert(length <= inline_room);
1224 assert(length == DATA_LEN(buf));
1225 elts_head_next = (elts_head + 1) & (elts_n - 1);
1226 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1227 (*txq->elts)[elts_head] = buf;
1228 /* Maximum number of bytes before wrapping. */
1229 max = ((uintptr_t)&(*txq->wqes)[txq->wqe_n] -
1230 (uintptr_t)mpw.data.raw);
1232 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1236 (volatile void *)&(*txq->wqes)[0];
1237 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1238 (void *)(addr + max),
1240 mpw.data.raw += length - max;
1242 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1245 mpw.data.raw += length;
1247 if ((uintptr_t)mpw.data.raw ==
1248 (uintptr_t)&(*txq->wqes)[txq->wqe_n])
1250 (volatile void *)&(*txq->wqes)[0];
1253 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1254 mlx5_mpw_inline_close(txq, &mpw);
1255 inline_room = txq->max_inline;
1257 inline_room -= length;
1260 mpw.total_len += length;
1261 elts_head = elts_head_next;
1262 #ifdef MLX5_PMD_SOFT_COUNTERS
1263 /* Increment sent bytes counter. */
1264 txq->stats.obytes += length;
1268 /* Take a shortcut if nothing must be sent. */
1269 if (unlikely(i == 0))
1271 /* Check whether completion threshold has been reached. */
1272 /* "j" includes both packets and segments. */
1273 comp = txq->elts_comp + j;
1274 if (comp >= MLX5_TX_COMP_THRESH) {
1275 volatile union mlx5_wqe *wqe = mpw.wqe;
1277 /* Request completion on last WQE. */
1278 wqe->mpw_inl.ctrl.data[2] = htonl(8);
1279 /* Save elts_head in unused "immediate" field of WQE. */
1280 wqe->mpw_inl.ctrl.data[3] = elts_head;
1283 txq->elts_comp = comp;
1285 #ifdef MLX5_PMD_SOFT_COUNTERS
1286 /* Increment sent packets counter. */
1287 txq->stats.opackets += i;
1289 /* Ring QP doorbell. */
1290 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1291 mlx5_mpw_inline_close(txq, &mpw);
1292 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1293 mlx5_mpw_close(txq, &mpw);
1295 txq->elts_head = elts_head;
1300 * Translate RX completion flags to packet type.
1305 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1308 * Packet type for struct rte_mbuf.
1310 static inline uint32_t
1311 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
1314 uint8_t flags = cqe->l4_hdr_type_etc;
1315 uint8_t info = cqe->rsvd0[0];
1317 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
1320 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
1321 RTE_PTYPE_L3_IPV4) |
1323 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
1324 RTE_PTYPE_L3_IPV6) |
1326 IBV_EXP_CQ_RX_IPV4_PACKET,
1327 RTE_PTYPE_INNER_L3_IPV4) |
1329 IBV_EXP_CQ_RX_IPV6_PACKET,
1330 RTE_PTYPE_INNER_L3_IPV6);
1334 MLX5_CQE_L3_HDR_TYPE_IPV6,
1335 RTE_PTYPE_L3_IPV6) |
1337 MLX5_CQE_L3_HDR_TYPE_IPV4,
1343 * Get size of the next packet for a given CQE. For compressed CQEs, the
1344 * consumer index is updated only once all packets of the current one have
1348 * Pointer to RX queue.
1353 * Packet size in bytes (0 if there is none), -1 in case of completion
1357 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
1360 struct rxq_zip *zip = &rxq->zip;
1361 uint16_t cqe_n = cqe_cnt + 1;
1364 /* Process compressed data in the CQE and mini arrays. */
1366 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1367 (volatile struct mlx5_mini_cqe8 (*)[8])
1368 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
1370 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1371 if ((++zip->ai & 7) == 0) {
1373 * Increment consumer index to skip the number of
1374 * CQEs consumed. Hardware leaves holes in the CQ
1375 * ring for software use.
1380 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1381 uint16_t idx = rxq->cq_ci;
1382 uint16_t end = zip->cq_ci;
1384 while (idx != end) {
1385 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
1386 MLX5_CQE_INVALIDATE;
1389 rxq->cq_ci = zip->cq_ci;
1392 /* No compressed data, get next CQE and verify if it is compressed. */
1397 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
1398 if (unlikely(ret == 1))
1401 op_own = cqe->op_own;
1402 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1403 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1404 (volatile struct mlx5_mini_cqe8 (*)[8])
1405 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1408 /* Fix endianness. */
1409 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1411 * Current mini array position is the one returned by
1414 * If completion comprises several mini arrays, as a
1415 * special case the second one is located 7 CQEs after
1416 * the initial CQE instead of 8 for subsequent ones.
1418 zip->ca = rxq->cq_ci & cqe_cnt;
1419 zip->na = zip->ca + 7;
1420 /* Compute the next non compressed CQE. */
1422 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1423 /* Get packet size to return. */
1424 len = ntohl((*mc)[0].byte_cnt);
1427 len = ntohl(cqe->byte_cnt);
1429 /* Error while receiving packet. */
1430 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1437 * Translate RX completion flags to offload flags.
1440 * Pointer to RX queue structure.
1445 * Offload flags (ol_flags) for struct rte_mbuf.
1447 static inline uint32_t
1448 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
1450 uint32_t ol_flags = 0;
1451 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1452 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1453 uint8_t info = cqe->rsvd0[0];
1455 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1456 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1458 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
1459 PKT_RX_IP_CKSUM_BAD);
1460 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1461 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1462 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1463 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1465 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
1466 PKT_RX_L4_CKSUM_BAD);
1468 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
1469 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
1472 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1474 TRANSPOSE(~cqe->l4_hdr_type_etc,
1475 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
1476 PKT_RX_IP_CKSUM_BAD) |
1477 TRANSPOSE(~cqe->l4_hdr_type_etc,
1478 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
1479 PKT_RX_L4_CKSUM_BAD);
1484 * DPDK callback for RX.
1487 * Generic pointer to RX queue structure.
1489 * Array to store received packets.
1491 * Maximum number of packets in array.
1494 * Number of packets successfully received (<= pkts_n).
1497 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1499 struct rxq *rxq = dpdk_rxq;
1500 const unsigned int wqe_cnt = rxq->elts_n - 1;
1501 const unsigned int cqe_cnt = rxq->cqe_n - 1;
1502 const unsigned int sges_n = rxq->sges_n;
1503 struct rte_mbuf *pkt = NULL;
1504 struct rte_mbuf *seg = NULL;
1505 volatile struct mlx5_cqe64 *cqe =
1506 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1508 unsigned int rq_ci = rxq->rq_ci << sges_n;
1512 unsigned int idx = rq_ci & wqe_cnt;
1513 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1514 struct rte_mbuf *rep = (*rxq->elts)[idx];
1522 rep = rte_mbuf_raw_alloc(rxq->mp);
1523 if (unlikely(rep == NULL)) {
1524 ++rxq->stats.rx_nombuf;
1527 * no buffers before we even started,
1528 * bail out silently.
1532 while (pkt != seg) {
1533 assert(pkt != (*rxq->elts)[idx]);
1535 rte_mbuf_refcnt_set(pkt, 0);
1536 __rte_mbuf_raw_free(pkt);
1542 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1543 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1545 rte_mbuf_refcnt_set(rep, 0);
1546 __rte_mbuf_raw_free(rep);
1549 if (unlikely(len == -1)) {
1550 /* RX error, packet is likely too large. */
1551 rte_mbuf_refcnt_set(rep, 0);
1552 __rte_mbuf_raw_free(rep);
1553 ++rxq->stats.idropped;
1557 assert(len >= (rxq->crc_present << 2));
1558 /* Update packet information. */
1559 pkt->packet_type = 0;
1561 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1565 rxq_cq_to_pkt_type(cqe);
1567 rxq_cq_to_ol_flags(rxq, cqe);
1569 if (cqe->l4_hdr_type_etc &
1570 MLX5_CQE_VLAN_STRIPPED) {
1571 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1572 PKT_RX_VLAN_STRIPPED;
1573 pkt->vlan_tci = ntohs(cqe->vlan_info);
1575 if (rxq->crc_present)
1576 len -= ETHER_CRC_LEN;
1580 DATA_LEN(rep) = DATA_LEN(seg);
1581 PKT_LEN(rep) = PKT_LEN(seg);
1582 SET_DATA_OFF(rep, DATA_OFF(seg));
1583 NB_SEGS(rep) = NB_SEGS(seg);
1584 PORT(rep) = PORT(seg);
1586 (*rxq->elts)[idx] = rep;
1588 * Fill NIC descriptor with the new buffer. The lkey and size
1589 * of the buffers are already known, only the buffer address
1592 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1593 if (len > DATA_LEN(seg)) {
1594 len -= DATA_LEN(seg);
1599 DATA_LEN(seg) = len;
1600 #ifdef MLX5_PMD_SOFT_COUNTERS
1601 /* Increment bytes counter. */
1602 rxq->stats.ibytes += PKT_LEN(pkt);
1604 /* Return packet. */
1610 /* Align consumer index to the next stride. */
1615 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1617 /* Update the consumer index. */
1618 rxq->rq_ci = rq_ci >> sges_n;
1620 *rxq->cq_db = htonl(rxq->cq_ci);
1622 *rxq->rq_db = htonl(rxq->rq_ci);
1623 #ifdef MLX5_PMD_SOFT_COUNTERS
1624 /* Increment packets counter. */
1625 rxq->stats.ipackets += i;
1631 * Dummy DPDK callback for TX.
1633 * This function is used to temporarily replace the real callback during
1634 * unsafe control operations on the queue, or in case of error.
1637 * Generic pointer to TX queue structure.
1639 * Packets to transmit.
1641 * Number of packets in array.
1644 * Number of packets successfully transmitted (<= pkts_n).
1647 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1656 * Dummy DPDK callback for RX.
1658 * This function is used to temporarily replace the real callback during
1659 * unsafe control operations on the queue, or in case of error.
1662 * Generic pointer to RX queue structure.
1664 * Array to store received packets.
1666 * Maximum number of packets in array.
1669 * Number of packets successfully received (<= pkts_n).
1672 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)