drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 #include <rte_mbuf.h>
  52 #include <rte_mempool.h>
  53 #include <rte_prefetch.h>
  54 #include <rte_common.h>
  55 #include <rte_branch_prediction.h>
  56 #include <rte_ether.h>
  57
  58 #include "mlx5.h"
  59 #include "mlx5_utils.h"
  60 #include "mlx5_rxtx.h"
  61 #include "mlx5_autoconf.h"
  62 #include "mlx5_defs.h"
  63 #include "mlx5_prm.h"
  64
  65 static __rte_always_inline uint32_t
  66 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  67
  68 static __rte_always_inline int
  69 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  70                  uint16_t cqe_cnt, uint32_t *rss_hash);
  71
  72 static __rte_always_inline uint32_t
  73 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  74
  75 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  76         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  77 };
  78
  79 /**
  80  * Build a table to translate Rx completion flags to packet type.
  81  *
  82  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  83  */
  84 void
  85 mlx5_set_ptype_table(void)
  86 {
  87         unsigned int i;
  88         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  89
  90         /* Last entry must not be overwritten, reserved for errored packet. */
  91         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  92                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  93         /*
  94          * The index to the array should have:
  95          * bit[1:0] = l3_hdr_type
  96          * bit[4:2] = l4_hdr_type
  97          * bit[5] = ip_frag
  98          * bit[6] = tunneled
  99          * bit[7] = outer_l3_type
 100          */
 101         /* L3 */
 102         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_NONFRAG;
 104         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_NONFRAG;
 106         /* Fragmented */
 107         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 108                      RTE_PTYPE_L4_FRAG;
 109         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_FRAG;
 111         /* TCP */
 112         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_TCP;
 114         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_TCP;
 116         /* UDP */
 117         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_UDP;
 119         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_UDP;
 121         /* Repeat with outer_l3_type being set. Just in case. */
 122         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_NONFRAG;
 124         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_NONFRAG;
 126         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_FRAG;
 128         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_FRAG;
 130         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_TCP;
 132         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_TCP;
 134         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_UDP;
 136         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_UDP;
 138         /* Tunneled - L3 */
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L4_NONFRAG;
 148         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L4_NONFRAG;
 151         /* Tunneled - Fragmented */
 152         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L4_FRAG;
 155         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L4_FRAG;
 158         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L4_FRAG;
 161         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L4_FRAG;
 164         /* Tunneled - TCP */
 165         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 167                      RTE_PTYPE_L4_TCP;
 168         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_L4_TCP;
 171         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_L4_TCP;
 174         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_L4_TCP;
 177         /* Tunneled - UDP */
 178         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_L4_UDP;
 181         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_L4_UDP;
 184         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_L4_UDP;
 187         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_L4_UDP;
 190 }
 191
 192 /**
 193  * Return the size of tailroom of WQ.
 194  *
 195  * @param txq
 196  *   Pointer to TX queue structure.
 197  * @param addr
 198  *   Pointer to tail of WQ.
 199  *
 200  * @return
 201  *   Size of tailroom.
 202  */
 203 static inline size_t
 204 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 205 {
 206         size_t tailroom;
 207         tailroom = (uintptr_t)(txq->wqes) +
 208                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 209                    (uintptr_t)addr;
 210         return tailroom;
 211 }
 212
 213 /**
 214  * Copy data to tailroom of circular queue.
 215  *
 216  * @param dst
 217  *   Pointer to destination.
 218  * @param src
 219  *   Pointer to source.
 220  * @param n
 221  *   Number of bytes to copy.
 222  * @param base
 223  *   Pointer to head of queue.
 224  * @param tailroom
 225  *   Size of tailroom from dst.
 226  *
 227  * @return
 228  *   Pointer after copied data.
 229  */
 230 static inline void *
 231 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 232                 void *base, size_t tailroom)
 233 {
 234         void *ret;
 235
 236         if (n > tailroom) {
 237                 rte_memcpy(dst, src, tailroom);
 238                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 239                            n - tailroom);
 240                 ret = (uint8_t *)base + n - tailroom;
 241         } else {
 242                 rte_memcpy(dst, src, n);
 243                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 244         }
 245         return ret;
 246 }
 247
 248 /**
 249  * DPDK callback to check the status of a tx descriptor.
 250  *
 251  * @param tx_queue
 252  *   The tx queue.
 253  * @param[in] offset
 254  *   The index of the descriptor in the ring.
 255  *
 256  * @return
 257  *   The status of the tx descriptor.
 258  */
 259 int
 260 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 261 {
 262         struct txq *txq = tx_queue;
 263         uint16_t used;
 264
 265         mlx5_tx_complete(txq);
 266         used = txq->elts_head - txq->elts_tail;
 267         if (offset < used)
 268                 return RTE_ETH_TX_DESC_FULL;
 269         return RTE_ETH_TX_DESC_DONE;
 270 }
 271
 272 /**
 273  * DPDK callback to check the status of a rx descriptor.
 274  *
 275  * @param rx_queue
 276  *   The rx queue.
 277  * @param[in] offset
 278  *   The index of the descriptor in the ring.
 279  *
 280  * @return
 281  *   The status of the tx descriptor.
 282  */
 283 int
 284 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 285 {
 286         struct rxq *rxq = rx_queue;
 287         struct rxq_zip *zip = &rxq->zip;
 288         volatile struct mlx5_cqe *cqe;
 289         const unsigned int cqe_n = (1 << rxq->cqe_n);
 290         const unsigned int cqe_cnt = cqe_n - 1;
 291         unsigned int cq_ci;
 292         unsigned int used;
 293
 294         /* if we are processing a compressed cqe */
 295         if (zip->ai) {
 296                 used = zip->cqe_cnt - zip->ca;
 297                 cq_ci = zip->cq_ci;
 298         } else {
 299                 used = 0;
 300                 cq_ci = rxq->cq_ci;
 301         }
 302         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 303         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 304                 int8_t op_own;
 305                 unsigned int n;
 306
 307                 op_own = cqe->op_own;
 308                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 309                         n = ntohl(cqe->byte_cnt);
 310                 else
 311                         n = 1;
 312                 cq_ci += n;
 313                 used += n;
 314                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 315         }
 316         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 317         if (offset < used)
 318                 return RTE_ETH_RX_DESC_DONE;
 319         return RTE_ETH_RX_DESC_AVAIL;
 320 }
 321
 322 /**
 323  * DPDK callback for TX.
 324  *
 325  * @param dpdk_txq
 326  *   Generic pointer to TX queue structure.
 327  * @param[in] pkts
 328  *   Packets to transmit.
 329  * @param pkts_n
 330  *   Number of packets in array.
 331  *
 332  * @return
 333  *   Number of packets successfully transmitted (<= pkts_n).
 334  */
 335 uint16_t
 336 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 337 {
 338         struct txq *txq = (struct txq *)dpdk_txq;
 339         uint16_t elts_head = txq->elts_head;
 340         const uint16_t elts_n = 1 << txq->elts_n;
 341         const uint16_t elts_m = elts_n - 1;
 342         unsigned int i = 0;
 343         unsigned int j = 0;
 344         unsigned int k = 0;
 345         uint16_t max_elts;
 346         unsigned int max_inline = txq->max_inline;
 347         const unsigned int inline_en = !!max_inline && txq->inline_en;
 348         uint16_t max_wqe;
 349         unsigned int comp;
 350         volatile struct mlx5_wqe_v *wqe = NULL;
 351         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 352         unsigned int segs_n = 0;
 353         struct rte_mbuf *buf = NULL;
 354         uint8_t *raw;
 355
 356         if (unlikely(!pkts_n))
 357                 return 0;
 358         /* Prefetch first packet cacheline. */
 359         rte_prefetch0(*pkts);
 360         /* Start processing. */
 361         mlx5_tx_complete(txq);
 362         max_elts = (elts_n - (elts_head - txq->elts_tail));
 363         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 364         if (unlikely(!max_wqe))
 365                 return 0;
 366         do {
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint64_t naddr;
 373                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 374                 uint16_t tso_header_sz = 0;
 375                 uint16_t ehdr;
 376                 uint8_t cs_flags = 0;
 377                 uint64_t tso = 0;
 378                 uint16_t tso_segsz = 0;
 379 #ifdef MLX5_PMD_SOFT_COUNTERS
 380                 uint32_t total_length = 0;
 381 #endif
 382
 383                 /* first_seg */
 384                 buf = *pkts;
 385                 segs_n = buf->nb_segs;
 386                 /*
 387                  * Make sure there is enough room to store this packet and
 388                  * that one ring entry remains unused.
 389                  */
 390                 assert(segs_n);
 391                 if (max_elts < segs_n)
 392                         break;
 393                 max_elts -= segs_n;
 394                 --segs_n;
 395                 if (unlikely(--max_wqe == 0))
 396                         break;
 397                 wqe = (volatile struct mlx5_wqe_v *)
 398                         tx_mlx5_wqe(txq, txq->wqe_ci);
 399                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 400                 if (pkts_n - i > 1)
 401                         rte_prefetch0(*(pkts + 1));
 402                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 403                 length = DATA_LEN(buf);
 404                 ehdr = (((uint8_t *)addr)[1] << 8) |
 405                        ((uint8_t *)addr)[0];
 406 #ifdef MLX5_PMD_SOFT_COUNTERS
 407                 total_length = length;
 408 #endif
 409                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 410                         break;
 411                 /* Update element. */
 412                 (*txq->elts)[elts_head & elts_m] = buf;
 413                 /* Prefetch next buffer data. */
 414                 if (pkts_n - i > 1)
 415                         rte_prefetch0(
 416                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 417                 /* Should we enable HW CKSUM offload */
 418                 if (buf->ol_flags &
 419                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 420                         const uint64_t is_tunneled = buf->ol_flags &
 421                                                      (PKT_TX_TUNNEL_GRE |
 422                                                       PKT_TX_TUNNEL_VXLAN);
 423
 424                         if (is_tunneled && txq->tunnel_en) {
 425                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 426                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 427                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 428                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 429                         } else {
 430                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 431                                            MLX5_ETH_WQE_L4_CSUM;
 432                         }
 433                 }
 434                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 435                 /* Replace the Ethernet type by the VLAN if necessary. */
 436                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 437                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 438                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 439
 440                         addr += 2;
 441                         length -= 2;
 442                         /* Copy Destination and source mac address. */
 443                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 444                         /* Copy VLAN. */
 445                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 446                         /* Copy missing two bytes to end the DSeg. */
 447                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 448                                ((uint8_t *)addr) + len, 2);
 449                         addr += len + 2;
 450                         length -= (len + 2);
 451                 } else {
 452                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 453                                MLX5_WQE_DWORD_SIZE);
 454                         length -= pkt_inline_sz;
 455                         addr += pkt_inline_sz;
 456                 }
 457                 raw += MLX5_WQE_DWORD_SIZE;
 458                 if (txq->tso_en) {
 459                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 460                         if (tso) {
 461                                 uintptr_t end = (uintptr_t)
 462                                                 (((uintptr_t)txq->wqes) +
 463                                                 (1 << txq->wqe_n) *
 464                                                 MLX5_WQE_SIZE);
 465                                 unsigned int copy_b;
 466                                 uint8_t vlan_sz = (buf->ol_flags &
 467                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 468                                 const uint64_t is_tunneled =
 469                                                         buf->ol_flags &
 470                                                         (PKT_TX_TUNNEL_GRE |
 471                                                          PKT_TX_TUNNEL_VXLAN);
 472
 473                                 tso_header_sz = buf->l2_len + vlan_sz +
 474                                                 buf->l3_len + buf->l4_len;
 475                                 tso_segsz = buf->tso_segsz;
 476
 477                                 if (is_tunneled && txq->tunnel_en) {
 478                                         tso_header_sz += buf->outer_l2_len +
 479                                                          buf->outer_l3_len;
 480                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 481                                 } else {
 482                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 483                                 }
 484                                 if (unlikely(tso_header_sz >
 485                                              MLX5_MAX_TSO_HEADER))
 486                                         break;
 487                                 copy_b = tso_header_sz - pkt_inline_sz;
 488                                 /* First seg must contain all headers. */
 489                                 assert(copy_b <= length);
 490                                 if (copy_b &&
 491                                    ((end - (uintptr_t)raw) > copy_b)) {
 492                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 493                                                       1 + 3) / 4;
 494
 495                                         if (unlikely(max_wqe < n))
 496                                                 break;
 497                                         max_wqe -= n;
 498                                         rte_memcpy((void *)raw,
 499                                                    (void *)addr, copy_b);
 500                                         addr += copy_b;
 501                                         length -= copy_b;
 502                                         /* Include padding for TSO header. */
 503                                         copy_b = MLX5_WQE_DS(copy_b) *
 504                                                  MLX5_WQE_DWORD_SIZE;
 505                                         pkt_inline_sz += copy_b;
 506                                         raw += copy_b;
 507                                 } else {
 508                                         /* NOP WQE. */
 509                                         wqe->ctrl = (rte_v128u32_t){
 510                                                      htonl(txq->wqe_ci << 8),
 511                                                      htonl(txq->qp_num_8s | 1),
 512                                                      0,
 513                                                      0,
 514                                         };
 515                                         ds = 1;
 516                                         total_length = 0;
 517                                         k++;
 518                                         goto next_wqe;
 519                                 }
 520                         }
 521                 }
 522                 /* Inline if enough room. */
 523                 if (inline_en || tso) {
 524                         uint32_t inl;
 525                         uintptr_t end = (uintptr_t)
 526                                 (((uintptr_t)txq->wqes) +
 527                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 528                         unsigned int inline_room = max_inline *
 529                                                    RTE_CACHE_LINE_SIZE -
 530                                                    (pkt_inline_sz - 2) -
 531                                                    !!tso * sizeof(inl);
 532                         uintptr_t addr_end = (addr + inline_room) &
 533                                              ~(RTE_CACHE_LINE_SIZE - 1);
 534                         unsigned int copy_b = (addr_end > addr) ?
 535                                 RTE_MIN((addr_end - addr), length) :
 536                                 0;
 537
 538                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 539                                 /*
 540                                  * One Dseg remains in the current WQE.  To
 541                                  * keep the computation positive, it is
 542                                  * removed after the bytes to Dseg conversion.
 543                                  */
 544                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 545
 546                                 if (unlikely(max_wqe < n))
 547                                         break;
 548                                 max_wqe -= n;
 549                                 if (tso) {
 550                                         inl = htonl(copy_b | MLX5_INLINE_SEG);
 551                                         rte_memcpy((void *)raw,
 552                                                    (void *)&inl, sizeof(inl));
 553                                         raw += sizeof(inl);
 554                                         pkt_inline_sz += sizeof(inl);
 555                                 }
 556                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 557                                 addr += copy_b;
 558                                 length -= copy_b;
 559                                 pkt_inline_sz += copy_b;
 560                         }
 561                         /*
 562                          * 2 DWORDs consumed by the WQE header + ETH segment +
 563                          * the size of the inline part of the packet.
 564                          */
 565                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 566                         if (length > 0) {
 567                                 if (ds % (MLX5_WQE_SIZE /
 568                                           MLX5_WQE_DWORD_SIZE) == 0) {
 569                                         if (unlikely(--max_wqe == 0))
 570                                                 break;
 571                                         dseg = (volatile rte_v128u32_t *)
 572                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 573                                                            ds / 4);
 574                                 } else {
 575                                         dseg = (volatile rte_v128u32_t *)
 576                                                 ((uintptr_t)wqe +
 577                                                  (ds * MLX5_WQE_DWORD_SIZE));
 578                                 }
 579                                 goto use_dseg;
 580                         } else if (!segs_n) {
 581                                 goto next_pkt;
 582                         } else {
 583                                 /* dseg will be advance as part of next_seg */
 584                                 dseg = (volatile rte_v128u32_t *)
 585                                         ((uintptr_t)wqe +
 586                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 587                                 goto next_seg;
 588                         }
 589                 } else {
 590                         /*
 591                          * No inline has been done in the packet, only the
 592                          * Ethernet Header as been stored.
 593                          */
 594                         dseg = (volatile rte_v128u32_t *)
 595                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 596                         ds = 3;
 597 use_dseg:
 598                         /* Add the remaining packet as a simple ds. */
 599                         naddr = htonll(addr);
 600                         *dseg = (rte_v128u32_t){
 601                                 htonl(length),
 602                                 mlx5_tx_mb2mr(txq, buf),
 603                                 naddr,
 604                                 naddr >> 32,
 605                         };
 606                         ++ds;
 607                         if (!segs_n)
 608                                 goto next_pkt;
 609                 }
 610 next_seg:
 611                 assert(buf);
 612                 assert(ds);
 613                 assert(wqe);
 614                 /*
 615                  * Spill on next WQE when the current one does not have
 616                  * enough room left. Size of WQE must a be a multiple
 617                  * of data segment size.
 618                  */
 619                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 620                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 621                         if (unlikely(--max_wqe == 0))
 622                                 break;
 623                         dseg = (volatile rte_v128u32_t *)
 624                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 625                         rte_prefetch0(tx_mlx5_wqe(txq,
 626                                                   txq->wqe_ci + ds / 4 + 1));
 627                 } else {
 628                         ++dseg;
 629                 }
 630                 ++ds;
 631                 buf = buf->next;
 632                 assert(buf);
 633                 length = DATA_LEN(buf);
 634 #ifdef MLX5_PMD_SOFT_COUNTERS
 635                 total_length += length;
 636 #endif
 637                 /* Store segment information. */
 638                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 639                 *dseg = (rte_v128u32_t){
 640                         htonl(length),
 641                         mlx5_tx_mb2mr(txq, buf),
 642                         naddr,
 643                         naddr >> 32,
 644                 };
 645                 (*txq->elts)[++elts_head & elts_m] = buf;
 646                 ++sg;
 647                 /* Advance counter only if all segs are successfully posted. */
 648                 if (sg < segs_n)
 649                         goto next_seg;
 650                 else
 651                         j += sg;
 652 next_pkt:
 653                 ++elts_head;
 654                 ++pkts;
 655                 ++i;
 656                 /* Initialize known and common part of the WQE structure. */
 657                 if (tso) {
 658                         wqe->ctrl = (rte_v128u32_t){
 659                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 660                                 htonl(txq->qp_num_8s | ds),
 661                                 0,
 662                                 0,
 663                         };
 664                         wqe->eseg = (rte_v128u32_t){
 665                                 0,
 666                                 cs_flags | (htons(tso_segsz) << 16),
 667                                 0,
 668                                 (ehdr << 16) | htons(tso_header_sz),
 669                         };
 670                 } else {
 671                         wqe->ctrl = (rte_v128u32_t){
 672                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 673                                 htonl(txq->qp_num_8s | ds),
 674                                 0,
 675                                 0,
 676                         };
 677                         wqe->eseg = (rte_v128u32_t){
 678                                 0,
 679                                 cs_flags,
 680                                 0,
 681                                 (ehdr << 16) | htons(pkt_inline_sz),
 682                         };
 683                 }
 684 next_wqe:
 685                 txq->wqe_ci += (ds + 3) / 4;
 686                 /* Save the last successful WQE for completion request */
 687                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 688 #ifdef MLX5_PMD_SOFT_COUNTERS
 689                 /* Increment sent bytes counter. */
 690                 txq->stats.obytes += total_length;
 691 #endif
 692         } while (i < pkts_n);
 693         /* Take a shortcut if nothing must be sent. */
 694         if (unlikely((i + k) == 0))
 695                 return 0;
 696         txq->elts_head += (i + j);
 697         /* Check whether completion threshold has been reached. */
 698         comp = txq->elts_comp + i + j + k;
 699         if (comp >= MLX5_TX_COMP_THRESH) {
 700                 /* Request completion on last WQE. */
 701                 last_wqe->ctrl2 = htonl(8);
 702                 /* Save elts_head in unused "immediate" field of WQE. */
 703                 last_wqe->ctrl3 = txq->elts_head;
 704                 txq->elts_comp = 0;
 705         } else {
 706                 txq->elts_comp = comp;
 707         }
 708 #ifdef MLX5_PMD_SOFT_COUNTERS
 709         /* Increment sent packets counter. */
 710         txq->stats.opackets += i;
 711 #endif
 712         /* Ring QP doorbell. */
 713         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 714         return i;
 715 }
 716
 717 /**
 718  * Open a MPW session.
 719  *
 720  * @param txq
 721  *   Pointer to TX queue structure.
 722  * @param mpw
 723  *   Pointer to MPW session structure.
 724  * @param length
 725  *   Packet length.
 726  */
 727 static inline void
 728 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 729 {
 730         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 731         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 732                 (volatile struct mlx5_wqe_data_seg (*)[])
 733                 tx_mlx5_wqe(txq, idx + 1);
 734
 735         mpw->state = MLX5_MPW_STATE_OPENED;
 736         mpw->pkts_n = 0;
 737         mpw->len = length;
 738         mpw->total_len = 0;
 739         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 740         mpw->wqe->eseg.mss = htons(length);
 741         mpw->wqe->eseg.inline_hdr_sz = 0;
 742         mpw->wqe->eseg.rsvd0 = 0;
 743         mpw->wqe->eseg.rsvd1 = 0;
 744         mpw->wqe->eseg.rsvd2 = 0;
 745         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 746                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 747         mpw->wqe->ctrl[2] = 0;
 748         mpw->wqe->ctrl[3] = 0;
 749         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 750                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 751         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 752                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 753         mpw->data.dseg[2] = &(*dseg)[0];
 754         mpw->data.dseg[3] = &(*dseg)[1];
 755         mpw->data.dseg[4] = &(*dseg)[2];
 756 }
 757
 758 /**
 759  * Close a MPW session.
 760  *
 761  * @param txq
 762  *   Pointer to TX queue structure.
 763  * @param mpw
 764  *   Pointer to MPW session structure.
 765  */
 766 static inline void
 767 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 768 {
 769         unsigned int num = mpw->pkts_n;
 770
 771         /*
 772          * Store size in multiple of 16 bytes. Control and Ethernet segments
 773          * count as 2.
 774          */
 775         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 776         mpw->state = MLX5_MPW_STATE_CLOSED;
 777         if (num < 3)
 778                 ++txq->wqe_ci;
 779         else
 780                 txq->wqe_ci += 2;
 781         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 782         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 783 }
 784
 785 /**
 786  * DPDK callback for TX with MPW support.
 787  *
 788  * @param dpdk_txq
 789  *   Generic pointer to TX queue structure.
 790  * @param[in] pkts
 791  *   Packets to transmit.
 792  * @param pkts_n
 793  *   Number of packets in array.
 794  *
 795  * @return
 796  *   Number of packets successfully transmitted (<= pkts_n).
 797  */
 798 uint16_t
 799 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 800 {
 801         struct txq *txq = (struct txq *)dpdk_txq;
 802         uint16_t elts_head = txq->elts_head;
 803         const uint16_t elts_n = 1 << txq->elts_n;
 804         const uint16_t elts_m = elts_n - 1;
 805         unsigned int i = 0;
 806         unsigned int j = 0;
 807         uint16_t max_elts;
 808         uint16_t max_wqe;
 809         unsigned int comp;
 810         struct mlx5_mpw mpw = {
 811                 .state = MLX5_MPW_STATE_CLOSED,
 812         };
 813
 814         if (unlikely(!pkts_n))
 815                 return 0;
 816         /* Prefetch first packet cacheline. */
 817         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 818         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 819         /* Start processing. */
 820         mlx5_tx_complete(txq);
 821         max_elts = (elts_n - (elts_head - txq->elts_tail));
 822         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 823         if (unlikely(!max_wqe))
 824                 return 0;
 825         do {
 826                 struct rte_mbuf *buf = *(pkts++);
 827                 uint32_t length;
 828                 unsigned int segs_n = buf->nb_segs;
 829                 uint32_t cs_flags = 0;
 830
 831                 /*
 832                  * Make sure there is enough room to store this packet and
 833                  * that one ring entry remains unused.
 834                  */
 835                 assert(segs_n);
 836                 if (max_elts < segs_n)
 837                         break;
 838                 /* Do not bother with large packets MPW cannot handle. */
 839                 if (segs_n > MLX5_MPW_DSEG_MAX)
 840                         break;
 841                 max_elts -= segs_n;
 842                 --pkts_n;
 843                 /* Should we enable HW CKSUM offload */
 844                 if (buf->ol_flags &
 845                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 846                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 847                 /* Retrieve packet information. */
 848                 length = PKT_LEN(buf);
 849                 assert(length);
 850                 /* Start new session if packet differs. */
 851                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 852                     ((mpw.len != length) ||
 853                      (segs_n != 1) ||
 854                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 855                         mlx5_mpw_close(txq, &mpw);
 856                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 857                         /*
 858                          * Multi-Packet WQE consumes at most two WQE.
 859                          * mlx5_mpw_new() expects to be able to use such
 860                          * resources.
 861                          */
 862                         if (unlikely(max_wqe < 2))
 863                                 break;
 864                         max_wqe -= 2;
 865                         mlx5_mpw_new(txq, &mpw, length);
 866                         mpw.wqe->eseg.cs_flags = cs_flags;
 867                 }
 868                 /* Multi-segment packets must be alone in their MPW. */
 869                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 870 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 871                 length = 0;
 872 #endif
 873                 do {
 874                         volatile struct mlx5_wqe_data_seg *dseg;
 875                         uintptr_t addr;
 876
 877                         assert(buf);
 878                         (*txq->elts)[elts_head++ & elts_m] = buf;
 879                         dseg = mpw.data.dseg[mpw.pkts_n];
 880                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 881                         *dseg = (struct mlx5_wqe_data_seg){
 882                                 .byte_count = htonl(DATA_LEN(buf)),
 883                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 884                                 .addr = htonll(addr),
 885                         };
 886 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 887                         length += DATA_LEN(buf);
 888 #endif
 889                         buf = buf->next;
 890                         ++mpw.pkts_n;
 891                         ++j;
 892                 } while (--segs_n);
 893                 assert(length == mpw.len);
 894                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 895                         mlx5_mpw_close(txq, &mpw);
 896 #ifdef MLX5_PMD_SOFT_COUNTERS
 897                 /* Increment sent bytes counter. */
 898                 txq->stats.obytes += length;
 899 #endif
 900                 ++i;
 901         } while (pkts_n);
 902         /* Take a shortcut if nothing must be sent. */
 903         if (unlikely(i == 0))
 904                 return 0;
 905         /* Check whether completion threshold has been reached. */
 906         /* "j" includes both packets and segments. */
 907         comp = txq->elts_comp + j;
 908         if (comp >= MLX5_TX_COMP_THRESH) {
 909                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 910
 911                 /* Request completion on last WQE. */
 912                 wqe->ctrl[2] = htonl(8);
 913                 /* Save elts_head in unused "immediate" field of WQE. */
 914                 wqe->ctrl[3] = elts_head;
 915                 txq->elts_comp = 0;
 916         } else {
 917                 txq->elts_comp = comp;
 918         }
 919 #ifdef MLX5_PMD_SOFT_COUNTERS
 920         /* Increment sent packets counter. */
 921         txq->stats.opackets += i;
 922 #endif
 923         /* Ring QP doorbell. */
 924         if (mpw.state == MLX5_MPW_STATE_OPENED)
 925                 mlx5_mpw_close(txq, &mpw);
 926         mlx5_tx_dbrec(txq, mpw.wqe);
 927         txq->elts_head = elts_head;
 928         return i;
 929 }
 930
 931 /**
 932  * Open a MPW inline session.
 933  *
 934  * @param txq
 935  *   Pointer to TX queue structure.
 936  * @param mpw
 937  *   Pointer to MPW session structure.
 938  * @param length
 939  *   Packet length.
 940  */
 941 static inline void
 942 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 943 {
 944         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 945         struct mlx5_wqe_inl_small *inl;
 946
 947         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 948         mpw->pkts_n = 0;
 949         mpw->len = length;
 950         mpw->total_len = 0;
 951         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 952         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 953                                   (txq->wqe_ci << 8) |
 954                                   MLX5_OPCODE_TSO);
 955         mpw->wqe->ctrl[2] = 0;
 956         mpw->wqe->ctrl[3] = 0;
 957         mpw->wqe->eseg.mss = htons(length);
 958         mpw->wqe->eseg.inline_hdr_sz = 0;
 959         mpw->wqe->eseg.cs_flags = 0;
 960         mpw->wqe->eseg.rsvd0 = 0;
 961         mpw->wqe->eseg.rsvd1 = 0;
 962         mpw->wqe->eseg.rsvd2 = 0;
 963         inl = (struct mlx5_wqe_inl_small *)
 964                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 965         mpw->data.raw = (uint8_t *)&inl->raw;
 966 }
 967
 968 /**
 969  * Close a MPW inline session.
 970  *
 971  * @param txq
 972  *   Pointer to TX queue structure.
 973  * @param mpw
 974  *   Pointer to MPW session structure.
 975  */
 976 static inline void
 977 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
 978 {
 979         unsigned int size;
 980         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 981                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 982
 983         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 984         /*
 985          * Store size in multiple of 16 bytes. Control and Ethernet segments
 986          * count as 2.
 987          */
 988         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
 989         mpw->state = MLX5_MPW_STATE_CLOSED;
 990         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
 991         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 992 }
 993
 994 /**
 995  * DPDK callback for TX with MPW inline support.
 996  *
 997  * @param dpdk_txq
 998  *   Generic pointer to TX queue structure.
 999  * @param[in] pkts
1000  *   Packets to transmit.
1001  * @param pkts_n
1002  *   Number of packets in array.
1003  *
1004  * @return
1005  *   Number of packets successfully transmitted (<= pkts_n).
1006  */
1007 uint16_t
1008 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1009                          uint16_t pkts_n)
1010 {
1011         struct txq *txq = (struct txq *)dpdk_txq;
1012         uint16_t elts_head = txq->elts_head;
1013         const uint16_t elts_n = 1 << txq->elts_n;
1014         const uint16_t elts_m = elts_n - 1;
1015         unsigned int i = 0;
1016         unsigned int j = 0;
1017         uint16_t max_elts;
1018         uint16_t max_wqe;
1019         unsigned int comp;
1020         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1021         struct mlx5_mpw mpw = {
1022                 .state = MLX5_MPW_STATE_CLOSED,
1023         };
1024         /*
1025          * Compute the maximum number of WQE which can be consumed by inline
1026          * code.
1027          * - 2 DSEG for:
1028          *   - 1 control segment,
1029          *   - 1 Ethernet segment,
1030          * - N Dseg from the inline request.
1031          */
1032         const unsigned int wqe_inl_n =
1033                 ((2 * MLX5_WQE_DWORD_SIZE +
1034                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1035                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1036
1037         if (unlikely(!pkts_n))
1038                 return 0;
1039         /* Prefetch first packet cacheline. */
1040         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1041         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1042         /* Start processing. */
1043         mlx5_tx_complete(txq);
1044         max_elts = (elts_n - (elts_head - txq->elts_tail));
1045         do {
1046                 struct rte_mbuf *buf = *(pkts++);
1047                 uintptr_t addr;
1048                 uint32_t length;
1049                 unsigned int segs_n = buf->nb_segs;
1050                 uint32_t cs_flags = 0;
1051
1052                 /*
1053                  * Make sure there is enough room to store this packet and
1054                  * that one ring entry remains unused.
1055                  */
1056                 assert(segs_n);
1057                 if (max_elts < segs_n)
1058                         break;
1059                 /* Do not bother with large packets MPW cannot handle. */
1060                 if (segs_n > MLX5_MPW_DSEG_MAX)
1061                         break;
1062                 max_elts -= segs_n;
1063                 --pkts_n;
1064                 /*
1065                  * Compute max_wqe in case less WQE were consumed in previous
1066                  * iteration.
1067                  */
1068                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1069                 /* Should we enable HW CKSUM offload */
1070                 if (buf->ol_flags &
1071                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1072                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1073                 /* Retrieve packet information. */
1074                 length = PKT_LEN(buf);
1075                 /* Start new session if packet differs. */
1076                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1077                         if ((mpw.len != length) ||
1078                             (segs_n != 1) ||
1079                             (mpw.wqe->eseg.cs_flags != cs_flags))
1080                                 mlx5_mpw_close(txq, &mpw);
1081                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1082                         if ((mpw.len != length) ||
1083                             (segs_n != 1) ||
1084                             (length > inline_room) ||
1085                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1086                                 mlx5_mpw_inline_close(txq, &mpw);
1087                                 inline_room =
1088                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1089                         }
1090                 }
1091                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1092                         if ((segs_n != 1) ||
1093                             (length > inline_room)) {
1094                                 /*
1095                                  * Multi-Packet WQE consumes at most two WQE.
1096                                  * mlx5_mpw_new() expects to be able to use
1097                                  * such resources.
1098                                  */
1099                                 if (unlikely(max_wqe < 2))
1100                                         break;
1101                                 max_wqe -= 2;
1102                                 mlx5_mpw_new(txq, &mpw, length);
1103                                 mpw.wqe->eseg.cs_flags = cs_flags;
1104                         } else {
1105                                 if (unlikely(max_wqe < wqe_inl_n))
1106                                         break;
1107                                 max_wqe -= wqe_inl_n;
1108                                 mlx5_mpw_inline_new(txq, &mpw, length);
1109                                 mpw.wqe->eseg.cs_flags = cs_flags;
1110                         }
1111                 }
1112                 /* Multi-segment packets must be alone in their MPW. */
1113                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1114                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1115                         assert(inline_room ==
1116                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1117 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1118                         length = 0;
1119 #endif
1120                         do {
1121                                 volatile struct mlx5_wqe_data_seg *dseg;
1122
1123                                 assert(buf);
1124                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1125                                 dseg = mpw.data.dseg[mpw.pkts_n];
1126                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1127                                 *dseg = (struct mlx5_wqe_data_seg){
1128                                         .byte_count = htonl(DATA_LEN(buf)),
1129                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1130                                         .addr = htonll(addr),
1131                                 };
1132 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1133                                 length += DATA_LEN(buf);
1134 #endif
1135                                 buf = buf->next;
1136                                 ++mpw.pkts_n;
1137                                 ++j;
1138                         } while (--segs_n);
1139                         assert(length == mpw.len);
1140                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1141                                 mlx5_mpw_close(txq, &mpw);
1142                 } else {
1143                         unsigned int max;
1144
1145                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1146                         assert(length <= inline_room);
1147                         assert(length == DATA_LEN(buf));
1148                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1149                         (*txq->elts)[elts_head++ & elts_m] = buf;
1150                         /* Maximum number of bytes before wrapping. */
1151                         max = ((((uintptr_t)(txq->wqes)) +
1152                                 (1 << txq->wqe_n) *
1153                                 MLX5_WQE_SIZE) -
1154                                (uintptr_t)mpw.data.raw);
1155                         if (length > max) {
1156                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1157                                            (void *)addr,
1158                                            max);
1159                                 mpw.data.raw = (volatile void *)txq->wqes;
1160                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1161                                            (void *)(addr + max),
1162                                            length - max);
1163                                 mpw.data.raw += length - max;
1164                         } else {
1165                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1166                                            (void *)addr,
1167                                            length);
1168
1169                                 if (length == max)
1170                                         mpw.data.raw =
1171                                                 (volatile void *)txq->wqes;
1172                                 else
1173                                         mpw.data.raw += length;
1174                         }
1175                         ++mpw.pkts_n;
1176                         mpw.total_len += length;
1177                         ++j;
1178                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1179                                 mlx5_mpw_inline_close(txq, &mpw);
1180                                 inline_room =
1181                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1182                         } else {
1183                                 inline_room -= length;
1184                         }
1185                 }
1186 #ifdef MLX5_PMD_SOFT_COUNTERS
1187                 /* Increment sent bytes counter. */
1188                 txq->stats.obytes += length;
1189 #endif
1190                 ++i;
1191         } while (pkts_n);
1192         /* Take a shortcut if nothing must be sent. */
1193         if (unlikely(i == 0))
1194                 return 0;
1195         /* Check whether completion threshold has been reached. */
1196         /* "j" includes both packets and segments. */
1197         comp = txq->elts_comp + j;
1198         if (comp >= MLX5_TX_COMP_THRESH) {
1199                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1200
1201                 /* Request completion on last WQE. */
1202                 wqe->ctrl[2] = htonl(8);
1203                 /* Save elts_head in unused "immediate" field of WQE. */
1204                 wqe->ctrl[3] = elts_head;
1205                 txq->elts_comp = 0;
1206         } else {
1207                 txq->elts_comp = comp;
1208         }
1209 #ifdef MLX5_PMD_SOFT_COUNTERS
1210         /* Increment sent packets counter. */
1211         txq->stats.opackets += i;
1212 #endif
1213         /* Ring QP doorbell. */
1214         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1215                 mlx5_mpw_inline_close(txq, &mpw);
1216         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1217                 mlx5_mpw_close(txq, &mpw);
1218         mlx5_tx_dbrec(txq, mpw.wqe);
1219         txq->elts_head = elts_head;
1220         return i;
1221 }
1222
1223 /**
1224  * Open an Enhanced MPW session.
1225  *
1226  * @param txq
1227  *   Pointer to TX queue structure.
1228  * @param mpw
1229  *   Pointer to MPW session structure.
1230  * @param length
1231  *   Packet length.
1232  */
1233 static inline void
1234 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1235 {
1236         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1237
1238         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1239         mpw->pkts_n = 0;
1240         mpw->total_len = sizeof(struct mlx5_wqe);
1241         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1242         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1243                                   (txq->wqe_ci << 8) |
1244                                   MLX5_OPCODE_ENHANCED_MPSW);
1245         mpw->wqe->ctrl[2] = 0;
1246         mpw->wqe->ctrl[3] = 0;
1247         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1248         if (unlikely(padding)) {
1249                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1250
1251                 /* Pad the first 2 DWORDs with zero-length inline header. */
1252                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1253                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1254                         htonl(MLX5_INLINE_SEG);
1255                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1256                 /* Start from the next WQEBB. */
1257                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1258         } else {
1259                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1260         }
1261 }
1262
1263 /**
1264  * Close an Enhanced MPW session.
1265  *
1266  * @param txq
1267  *   Pointer to TX queue structure.
1268  * @param mpw
1269  *   Pointer to MPW session structure.
1270  *
1271  * @return
1272  *   Number of consumed WQEs.
1273  */
1274 static inline uint16_t
1275 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1276 {
1277         uint16_t ret;
1278
1279         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1280          * count as 2.
1281          */
1282         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1283         mpw->state = MLX5_MPW_STATE_CLOSED;
1284         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1285         txq->wqe_ci += ret;
1286         return ret;
1287 }
1288
1289 /**
1290  * DPDK callback for TX with Enhanced MPW support.
1291  *
1292  * @param dpdk_txq
1293  *   Generic pointer to TX queue structure.
1294  * @param[in] pkts
1295  *   Packets to transmit.
1296  * @param pkts_n
1297  *   Number of packets in array.
1298  *
1299  * @return
1300  *   Number of packets successfully transmitted (<= pkts_n).
1301  */
1302 uint16_t
1303 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1304 {
1305         struct txq *txq = (struct txq *)dpdk_txq;
1306         uint16_t elts_head = txq->elts_head;
1307         const uint16_t elts_n = 1 << txq->elts_n;
1308         const uint16_t elts_m = elts_n - 1;
1309         unsigned int i = 0;
1310         unsigned int j = 0;
1311         uint16_t max_elts;
1312         uint16_t max_wqe;
1313         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1314         unsigned int mpw_room = 0;
1315         unsigned int inl_pad = 0;
1316         uint32_t inl_hdr;
1317         struct mlx5_mpw mpw = {
1318                 .state = MLX5_MPW_STATE_CLOSED,
1319         };
1320
1321         if (unlikely(!pkts_n))
1322                 return 0;
1323         /* Start processing. */
1324         mlx5_tx_complete(txq);
1325         max_elts = (elts_n - (elts_head - txq->elts_tail));
1326         /* A CQE slot must always be available. */
1327         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1328         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1329         if (unlikely(!max_wqe))
1330                 return 0;
1331         do {
1332                 struct rte_mbuf *buf = *(pkts++);
1333                 uintptr_t addr;
1334                 uint64_t naddr;
1335                 unsigned int n;
1336                 unsigned int do_inline = 0; /* Whether inline is possible. */
1337                 uint32_t length;
1338                 unsigned int segs_n = buf->nb_segs;
1339                 uint32_t cs_flags = 0;
1340
1341                 /*
1342                  * Make sure there is enough room to store this packet and
1343                  * that one ring entry remains unused.
1344                  */
1345                 assert(segs_n);
1346                 if (max_elts - j < segs_n)
1347                         break;
1348                 /* Do not bother with large packets MPW cannot handle. */
1349                 if (segs_n > MLX5_MPW_DSEG_MAX)
1350                         break;
1351                 /* Should we enable HW CKSUM offload. */
1352                 if (buf->ol_flags &
1353                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1354                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1355                 /* Retrieve packet information. */
1356                 length = PKT_LEN(buf);
1357                 /* Start new session if:
1358                  * - multi-segment packet
1359                  * - no space left even for a dseg
1360                  * - next packet can be inlined with a new WQE
1361                  * - cs_flag differs
1362                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1363                  * segmented packet.
1364                  */
1365                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1366                         if ((segs_n != 1) ||
1367                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1368                               mpw_room) ||
1369                             (length <= txq->inline_max_packet_sz &&
1370                              inl_pad + sizeof(inl_hdr) + length >
1371                               mpw_room) ||
1372                             (mpw.wqe->eseg.cs_flags != cs_flags))
1373                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1374                 }
1375                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1376                         if (unlikely(segs_n != 1)) {
1377                                 /* Fall back to legacy MPW.
1378                                  * A MPW session consumes 2 WQEs at most to
1379                                  * include MLX5_MPW_DSEG_MAX pointers.
1380                                  */
1381                                 if (unlikely(max_wqe < 2))
1382                                         break;
1383                                 mlx5_mpw_new(txq, &mpw, length);
1384                         } else {
1385                                 /* In Enhanced MPW, inline as much as the budget
1386                                  * is allowed. The remaining space is to be
1387                                  * filled with dsegs. If the title WQEBB isn't
1388                                  * padded, it will have 2 dsegs there.
1389                                  */
1390                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1391                                             (max_inline ? max_inline :
1392                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1393                                             MLX5_WQE_SIZE);
1394                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1395                                               mpw_room))
1396                                         break;
1397                                 /* Don't pad the title WQEBB to not waste WQ. */
1398                                 mlx5_empw_new(txq, &mpw, 0);
1399                                 mpw_room -= mpw.total_len;
1400                                 inl_pad = 0;
1401                                 do_inline =
1402                                         length <= txq->inline_max_packet_sz &&
1403                                         sizeof(inl_hdr) + length <= mpw_room &&
1404                                         !txq->mpw_hdr_dseg;
1405                         }
1406                         mpw.wqe->eseg.cs_flags = cs_flags;
1407                 } else {
1408                         /* Evaluate whether the next packet can be inlined.
1409                          * Inlininig is possible when:
1410                          * - length is less than configured value
1411                          * - length fits for remaining space
1412                          * - not required to fill the title WQEBB with dsegs
1413                          */
1414                         do_inline =
1415                                 length <= txq->inline_max_packet_sz &&
1416                                 inl_pad + sizeof(inl_hdr) + length <=
1417                                  mpw_room &&
1418                                 (!txq->mpw_hdr_dseg ||
1419                                  mpw.total_len >= MLX5_WQE_SIZE);
1420                 }
1421                 /* Multi-segment packets must be alone in their MPW. */
1422                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1423                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1424 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1425                         length = 0;
1426 #endif
1427                         do {
1428                                 volatile struct mlx5_wqe_data_seg *dseg;
1429
1430                                 assert(buf);
1431                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1432                                 dseg = mpw.data.dseg[mpw.pkts_n];
1433                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1434                                 *dseg = (struct mlx5_wqe_data_seg){
1435                                         .byte_count = htonl(DATA_LEN(buf)),
1436                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1437                                         .addr = htonll(addr),
1438                                 };
1439 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1440                                 length += DATA_LEN(buf);
1441 #endif
1442                                 buf = buf->next;
1443                                 ++j;
1444                                 ++mpw.pkts_n;
1445                         } while (--segs_n);
1446                         /* A multi-segmented packet takes one MPW session.
1447                          * TODO: Pack more multi-segmented packets if possible.
1448                          */
1449                         mlx5_mpw_close(txq, &mpw);
1450                         if (mpw.pkts_n < 3)
1451                                 max_wqe--;
1452                         else
1453                                 max_wqe -= 2;
1454                 } else if (do_inline) {
1455                         /* Inline packet into WQE. */
1456                         unsigned int max;
1457
1458                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1459                         assert(length == DATA_LEN(buf));
1460                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1461                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1462                         mpw.data.raw = (volatile void *)
1463                                 ((uintptr_t)mpw.data.raw + inl_pad);
1464                         max = tx_mlx5_wq_tailroom(txq,
1465                                         (void *)(uintptr_t)mpw.data.raw);
1466                         /* Copy inline header. */
1467                         mpw.data.raw = (volatile void *)
1468                                 mlx5_copy_to_wq(
1469                                           (void *)(uintptr_t)mpw.data.raw,
1470                                           &inl_hdr,
1471                                           sizeof(inl_hdr),
1472                                           (void *)(uintptr_t)txq->wqes,
1473                                           max);
1474                         max = tx_mlx5_wq_tailroom(txq,
1475                                         (void *)(uintptr_t)mpw.data.raw);
1476                         /* Copy packet data. */
1477                         mpw.data.raw = (volatile void *)
1478                                 mlx5_copy_to_wq(
1479                                           (void *)(uintptr_t)mpw.data.raw,
1480                                           (void *)addr,
1481                                           length,
1482                                           (void *)(uintptr_t)txq->wqes,
1483                                           max);
1484                         ++mpw.pkts_n;
1485                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1486                         /* No need to get completion as the entire packet is
1487                          * copied to WQ. Free the buf right away.
1488                          */
1489                         rte_pktmbuf_free_seg(buf);
1490                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1491                         /* Add pad in the next packet if any. */
1492                         inl_pad = (((uintptr_t)mpw.data.raw +
1493                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1494                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1495                                   (uintptr_t)mpw.data.raw;
1496                 } else {
1497                         /* No inline. Load a dseg of packet pointer. */
1498                         volatile rte_v128u32_t *dseg;
1499
1500                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1501                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1502                         assert(length == DATA_LEN(buf));
1503                         if (!tx_mlx5_wq_tailroom(txq,
1504                                         (void *)((uintptr_t)mpw.data.raw
1505                                                 + inl_pad)))
1506                                 dseg = (volatile void *)txq->wqes;
1507                         else
1508                                 dseg = (volatile void *)
1509                                         ((uintptr_t)mpw.data.raw +
1510                                          inl_pad);
1511                         (*txq->elts)[elts_head++ & elts_m] = buf;
1512                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1513                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1514                                 rte_prefetch2((void *)(addr +
1515                                                 n * RTE_CACHE_LINE_SIZE));
1516                         naddr = htonll(addr);
1517                         *dseg = (rte_v128u32_t) {
1518                                 htonl(length),
1519                                 mlx5_tx_mb2mr(txq, buf),
1520                                 naddr,
1521                                 naddr >> 32,
1522                         };
1523                         mpw.data.raw = (volatile void *)(dseg + 1);
1524                         mpw.total_len += (inl_pad + sizeof(*dseg));
1525                         ++j;
1526                         ++mpw.pkts_n;
1527                         mpw_room -= (inl_pad + sizeof(*dseg));
1528                         inl_pad = 0;
1529                 }
1530 #ifdef MLX5_PMD_SOFT_COUNTERS
1531                 /* Increment sent bytes counter. */
1532                 txq->stats.obytes += length;
1533 #endif
1534                 ++i;
1535         } while (i < pkts_n);
1536         /* Take a shortcut if nothing must be sent. */
1537         if (unlikely(i == 0))
1538                 return 0;
1539         /* Check whether completion threshold has been reached. */
1540         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1541                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1542                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1543                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1544
1545                 /* Request completion on last WQE. */
1546                 wqe->ctrl[2] = htonl(8);
1547                 /* Save elts_head in unused "immediate" field of WQE. */
1548                 wqe->ctrl[3] = elts_head;
1549                 txq->elts_comp = 0;
1550                 txq->mpw_comp = txq->wqe_ci;
1551                 txq->cq_pi++;
1552         } else {
1553                 txq->elts_comp += j;
1554         }
1555 #ifdef MLX5_PMD_SOFT_COUNTERS
1556         /* Increment sent packets counter. */
1557         txq->stats.opackets += i;
1558 #endif
1559         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1560                 mlx5_empw_close(txq, &mpw);
1561         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1562                 mlx5_mpw_close(txq, &mpw);
1563         /* Ring QP doorbell. */
1564         mlx5_tx_dbrec(txq, mpw.wqe);
1565         txq->elts_head = elts_head;
1566         return i;
1567 }
1568
1569 /**
1570  * Translate RX completion flags to packet type.
1571  *
1572  * @param[in] cqe
1573  *   Pointer to CQE.
1574  *
1575  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1576  *
1577  * @return
1578  *   Packet type for struct rte_mbuf.
1579  */
1580 static inline uint32_t
1581 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1582 {
1583         uint8_t idx;
1584         uint8_t pinfo = cqe->pkt_info;
1585         uint16_t ptype = cqe->hdr_type_etc;
1586
1587         /*
1588          * The index to the array should have:
1589          * bit[1:0] = l3_hdr_type
1590          * bit[4:2] = l4_hdr_type
1591          * bit[5] = ip_frag
1592          * bit[6] = tunneled
1593          * bit[7] = outer_l3_type
1594          */
1595         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1596         return mlx5_ptype_table[idx];
1597 }
1598
1599 /**
1600  * Get size of the next packet for a given CQE. For compressed CQEs, the
1601  * consumer index is updated only once all packets of the current one have
1602  * been processed.
1603  *
1604  * @param rxq
1605  *   Pointer to RX queue.
1606  * @param cqe
1607  *   CQE to process.
1608  * @param[out] rss_hash
1609  *   Packet RSS Hash result.
1610  *
1611  * @return
1612  *   Packet size in bytes (0 if there is none), -1 in case of completion
1613  *   with error.
1614  */
1615 static inline int
1616 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1617                  uint16_t cqe_cnt, uint32_t *rss_hash)
1618 {
1619         struct rxq_zip *zip = &rxq->zip;
1620         uint16_t cqe_n = cqe_cnt + 1;
1621         int len = 0;
1622         uint16_t idx, end;
1623
1624         /* Process compressed data in the CQE and mini arrays. */
1625         if (zip->ai) {
1626                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1627                         (volatile struct mlx5_mini_cqe8 (*)[8])
1628                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1629
1630                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1631                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1632                 if ((++zip->ai & 7) == 0) {
1633                         /* Invalidate consumed CQEs */
1634                         idx = zip->ca;
1635                         end = zip->na;
1636                         while (idx != end) {
1637                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1638                                         MLX5_CQE_INVALIDATE;
1639                                 ++idx;
1640                         }
1641                         /*
1642                          * Increment consumer index to skip the number of
1643                          * CQEs consumed. Hardware leaves holes in the CQ
1644                          * ring for software use.
1645                          */
1646                         zip->ca = zip->na;
1647                         zip->na += 8;
1648                 }
1649                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1650                         /* Invalidate the rest */
1651                         idx = zip->ca;
1652                         end = zip->cq_ci;
1653
1654                         while (idx != end) {
1655                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1656                                         MLX5_CQE_INVALIDATE;
1657                                 ++idx;
1658                         }
1659                         rxq->cq_ci = zip->cq_ci;
1660                         zip->ai = 0;
1661                 }
1662         /* No compressed data, get next CQE and verify if it is compressed. */
1663         } else {
1664                 int ret;
1665                 int8_t op_own;
1666
1667                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1668                 if (unlikely(ret == 1))
1669                         return 0;
1670                 ++rxq->cq_ci;
1671                 op_own = cqe->op_own;
1672                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1673                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1674                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1675                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1676                                                           cqe_cnt].pkt_info);
1677
1678                         /* Fix endianness. */
1679                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1680                         /*
1681                          * Current mini array position is the one returned by
1682                          * check_cqe64().
1683                          *
1684                          * If completion comprises several mini arrays, as a
1685                          * special case the second one is located 7 CQEs after
1686                          * the initial CQE instead of 8 for subsequent ones.
1687                          */
1688                         zip->ca = rxq->cq_ci;
1689                         zip->na = zip->ca + 7;
1690                         /* Compute the next non compressed CQE. */
1691                         --rxq->cq_ci;
1692                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1693                         /* Get packet size to return. */
1694                         len = ntohl((*mc)[0].byte_cnt);
1695                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1696                         zip->ai = 1;
1697                         /* Prefetch all the entries to be invalidated */
1698                         idx = zip->ca;
1699                         end = zip->cq_ci;
1700                         while (idx != end) {
1701                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1702                                 ++idx;
1703                         }
1704                 } else {
1705                         len = ntohl(cqe->byte_cnt);
1706                         *rss_hash = ntohl(cqe->rx_hash_res);
1707                 }
1708                 /* Error while receiving packet. */
1709                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1710                         return -1;
1711         }
1712         return len;
1713 }
1714
1715 /**
1716  * Translate RX completion flags to offload flags.
1717  *
1718  * @param[in] rxq
1719  *   Pointer to RX queue structure.
1720  * @param[in] cqe
1721  *   Pointer to CQE.
1722  *
1723  * @return
1724  *   Offload flags (ol_flags) for struct rte_mbuf.
1725  */
1726 static inline uint32_t
1727 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1728 {
1729         uint32_t ol_flags = 0;
1730         uint16_t flags = ntohs(cqe->hdr_type_etc);
1731
1732         ol_flags =
1733                 TRANSPOSE(flags,
1734                           MLX5_CQE_RX_L3_HDR_VALID,
1735                           PKT_RX_IP_CKSUM_GOOD) |
1736                 TRANSPOSE(flags,
1737                           MLX5_CQE_RX_L4_HDR_VALID,
1738                           PKT_RX_L4_CKSUM_GOOD);
1739         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1740                 ol_flags |=
1741                         TRANSPOSE(flags,
1742                                   MLX5_CQE_RX_L3_HDR_VALID,
1743                                   PKT_RX_IP_CKSUM_GOOD) |
1744                         TRANSPOSE(flags,
1745                                   MLX5_CQE_RX_L4_HDR_VALID,
1746                                   PKT_RX_L4_CKSUM_GOOD);
1747         return ol_flags;
1748 }
1749
1750 /**
1751  * DPDK callback for RX.
1752  *
1753  * @param dpdk_rxq
1754  *   Generic pointer to RX queue structure.
1755  * @param[out] pkts
1756  *   Array to store received packets.
1757  * @param pkts_n
1758  *   Maximum number of packets in array.
1759  *
1760  * @return
1761  *   Number of packets successfully received (<= pkts_n).
1762  */
1763 uint16_t
1764 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1765 {
1766         struct rxq *rxq = dpdk_rxq;
1767         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1768         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1769         const unsigned int sges_n = rxq->sges_n;
1770         struct rte_mbuf *pkt = NULL;
1771         struct rte_mbuf *seg = NULL;
1772         volatile struct mlx5_cqe *cqe =
1773                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1774         unsigned int i = 0;
1775         unsigned int rq_ci = rxq->rq_ci << sges_n;
1776         int len = 0; /* keep its value across iterations. */
1777
1778         while (pkts_n) {
1779                 unsigned int idx = rq_ci & wqe_cnt;
1780                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1781                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1782                 uint32_t rss_hash_res = 0;
1783
1784                 if (pkt)
1785                         NEXT(seg) = rep;
1786                 seg = rep;
1787                 rte_prefetch0(seg);
1788                 rte_prefetch0(cqe);
1789                 rte_prefetch0(wqe);
1790                 rep = rte_mbuf_raw_alloc(rxq->mp);
1791                 if (unlikely(rep == NULL)) {
1792                         ++rxq->stats.rx_nombuf;
1793                         if (!pkt) {
1794                                 /*
1795                                  * no buffers before we even started,
1796                                  * bail out silently.
1797                                  */
1798                                 break;
1799                         }
1800                         while (pkt != seg) {
1801                                 assert(pkt != (*rxq->elts)[idx]);
1802                                 rep = NEXT(pkt);
1803                                 NEXT(pkt) = NULL;
1804                                 NB_SEGS(pkt) = 1;
1805                                 rte_mbuf_raw_free(pkt);
1806                                 pkt = rep;
1807                         }
1808                         break;
1809                 }
1810                 if (!pkt) {
1811                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1812                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1813                                                &rss_hash_res);
1814                         if (!len) {
1815                                 rte_mbuf_raw_free(rep);
1816                                 break;
1817                         }
1818                         if (unlikely(len == -1)) {
1819                                 /* RX error, packet is likely too large. */
1820                                 rte_mbuf_raw_free(rep);
1821                                 ++rxq->stats.idropped;
1822                                 goto skip;
1823                         }
1824                         pkt = seg;
1825                         assert(len >= (rxq->crc_present << 2));
1826                         /* Update packet information. */
1827                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1828                         pkt->ol_flags = 0;
1829                         if (rss_hash_res && rxq->rss_hash) {
1830                                 pkt->hash.rss = rss_hash_res;
1831                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1832                         }
1833                         if (rxq->mark &&
1834                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1835                                 pkt->ol_flags |= PKT_RX_FDIR;
1836                                 if (cqe->sop_drop_qpn !=
1837                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1838                                         uint32_t mark = cqe->sop_drop_qpn;
1839
1840                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1841                                         pkt->hash.fdir.hi =
1842                                                 mlx5_flow_mark_get(mark);
1843                                 }
1844                         }
1845                         if (rxq->csum | rxq->csum_l2tun)
1846                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1847                         if (rxq->vlan_strip &&
1848                             (cqe->hdr_type_etc &
1849                              htons(MLX5_CQE_VLAN_STRIPPED))) {
1850                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1851                                         PKT_RX_VLAN_STRIPPED;
1852                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
1853                         }
1854                         if (rxq->crc_present)
1855                                 len -= ETHER_CRC_LEN;
1856                         PKT_LEN(pkt) = len;
1857                 }
1858                 DATA_LEN(rep) = DATA_LEN(seg);
1859                 PKT_LEN(rep) = PKT_LEN(seg);
1860                 SET_DATA_OFF(rep, DATA_OFF(seg));
1861                 PORT(rep) = PORT(seg);
1862                 (*rxq->elts)[idx] = rep;
1863                 /*
1864                  * Fill NIC descriptor with the new buffer.  The lkey and size
1865                  * of the buffers are already known, only the buffer address
1866                  * changes.
1867                  */
1868                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1869                 if (len > DATA_LEN(seg)) {
1870                         len -= DATA_LEN(seg);
1871                         ++NB_SEGS(pkt);
1872                         ++rq_ci;
1873                         continue;
1874                 }
1875                 DATA_LEN(seg) = len;
1876 #ifdef MLX5_PMD_SOFT_COUNTERS
1877                 /* Increment bytes counter. */
1878                 rxq->stats.ibytes += PKT_LEN(pkt);
1879 #endif
1880                 /* Return packet. */
1881                 *(pkts++) = pkt;
1882                 pkt = NULL;
1883                 --pkts_n;
1884                 ++i;
1885 skip:
1886                 /* Align consumer index to the next stride. */
1887                 rq_ci >>= sges_n;
1888                 ++rq_ci;
1889                 rq_ci <<= sges_n;
1890         }
1891         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1892                 return 0;
1893         /* Update the consumer index. */
1894         rxq->rq_ci = rq_ci >> sges_n;
1895         rte_wmb();
1896         *rxq->cq_db = htonl(rxq->cq_ci);
1897         rte_wmb();
1898         *rxq->rq_db = htonl(rxq->rq_ci);
1899 #ifdef MLX5_PMD_SOFT_COUNTERS
1900         /* Increment packets counter. */
1901         rxq->stats.ipackets += i;
1902 #endif
1903         return i;
1904 }
1905
1906 /**
1907  * Dummy DPDK callback for TX.
1908  *
1909  * This function is used to temporarily replace the real callback during
1910  * unsafe control operations on the queue, or in case of error.
1911  *
1912  * @param dpdk_txq
1913  *   Generic pointer to TX queue structure.
1914  * @param[in] pkts
1915  *   Packets to transmit.
1916  * @param pkts_n
1917  *   Number of packets in array.
1918  *
1919  * @return
1920  *   Number of packets successfully transmitted (<= pkts_n).
1921  */
1922 uint16_t
1923 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1924 {
1925         (void)dpdk_txq;
1926         (void)pkts;
1927         (void)pkts_n;
1928         return 0;
1929 }
1930
1931 /**
1932  * Dummy DPDK callback for RX.
1933  *
1934  * This function is used to temporarily replace the real callback during
1935  * unsafe control operations on the queue, or in case of error.
1936  *
1937  * @param dpdk_rxq
1938  *   Generic pointer to RX queue structure.
1939  * @param[out] pkts
1940  *   Array to store received packets.
1941  * @param pkts_n
1942  *   Maximum number of packets in array.
1943  *
1944  * @return
1945  *   Number of packets successfully received (<= pkts_n).
1946  */
1947 uint16_t
1948 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1949 {
1950         (void)dpdk_rxq;
1951         (void)pkts;
1952         (void)pkts_n;
1953         return 0;
1954 }
1955
1956 /*
1957  * Vectorized Rx/Tx routines are not compiled in when required vector
1958  * instructions are not supported on a target architecture. The following null
1959  * stubs are needed for linkage when those are not included outside of this file
1960  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1961  */
1962
1963 uint16_t __attribute__((weak))
1964 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1965 {
1966         (void)dpdk_txq;
1967         (void)pkts;
1968         (void)pkts_n;
1969         return 0;
1970 }
1971
1972 uint16_t __attribute__((weak))
1973 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1974 {
1975         (void)dpdk_txq;
1976         (void)pkts;
1977         (void)pkts_n;
1978         return 0;
1979 }
1980
1981 uint16_t __attribute__((weak))
1982 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1983 {
1984         (void)dpdk_rxq;
1985         (void)pkts;
1986         (void)pkts_n;
1987         return 0;
1988 }
1989
1990 int __attribute__((weak))
1991 priv_check_raw_vec_tx_support(struct priv *priv)
1992 {
1993         (void)priv;
1994         return -ENOTSUP;
1995 }
1996
1997 int __attribute__((weak))
1998 priv_check_vec_tx_support(struct priv *priv)
1999 {
2000         (void)priv;
2001         return -ENOTSUP;
2002 }
2003
2004 int __attribute__((weak))
2005 rxq_check_vec_support(struct rxq *rxq)
2006 {
2007         (void)rxq;
2008         return -ENOTSUP;
2009 }
2010
2011 int __attribute__((weak))
2012 priv_check_vec_rx_support(struct priv *priv)
2013 {
2014         (void)priv;
2015         return -ENOTSUP;
2016 }