drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static __rte_always_inline uint32_t
  73 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  74
  75 static __rte_always_inline int
  76 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  77                  uint16_t cqe_cnt, uint32_t *rss_hash);
  78
  79 static __rte_always_inline uint32_t
  80 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  81
  82 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  83         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  84 };
  85
  86 /**
  87  * Build a table to translate Rx completion flags to packet type.
  88  *
  89  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  90  */
  91 void
  92 mlx5_set_ptype_table(void)
  93 {
  94         unsigned int i;
  95         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  96
  97         for (i = 0; i < RTE_DIM(mlx5_ptype_table); ++i)
  98                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  99         /*
 100          * The index to the array should have:
 101          * bit[1:0] = l3_hdr_type
 102          * bit[4:2] = l4_hdr_type
 103          * bit[5] = ip_frag
 104          * bit[6] = tunneled
 105          * bit[7] = outer_l3_type
 106          */
 107         /* L3 */
 108         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_NONFRAG;
 110         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_NONFRAG;
 112         /* Fragmented */
 113         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_FRAG;
 115         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_FRAG;
 117         /* TCP */
 118         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_TCP;
 120         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_TCP;
 122         /* UDP */
 123         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_UDP;
 125         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_UDP;
 127         /* Repeat with outer_l3_type being set. Just in case. */
 128         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_NONFRAG;
 130         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_NONFRAG;
 132         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_FRAG;
 134         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_FRAG;
 136         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_TCP;
 138         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 139                      RTE_PTYPE_L4_TCP;
 140         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_L4_UDP;
 142         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_L4_UDP;
 144         /* Tunneled - L3 */
 145         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L4_NONFRAG;
 148         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L4_NONFRAG;
 151         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L4_NONFRAG;
 154         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_NONFRAG;
 157         /* Tunneled - Fragmented */
 158         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L4_FRAG;
 161         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L4_FRAG;
 164         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L4_FRAG;
 167         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_FRAG;
 170         /* Tunneled - TCP */
 171         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_L4_TCP;
 174         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_L4_TCP;
 177         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 178                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 179                      RTE_PTYPE_L4_TCP;
 180         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_L4_TCP;
 183         /* Tunneled - UDP */
 184         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_L4_UDP;
 187         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_L4_UDP;
 190         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_L4_UDP;
 193         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 194                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_L4_UDP;
 196 }
 197
 198 /**
 199  * Return the size of tailroom of WQ.
 200  *
 201  * @param txq
 202  *   Pointer to TX queue structure.
 203  * @param addr
 204  *   Pointer to tail of WQ.
 205  *
 206  * @return
 207  *   Size of tailroom.
 208  */
 209 static inline size_t
 210 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 211 {
 212         size_t tailroom;
 213         tailroom = (uintptr_t)(txq->wqes) +
 214                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 215                    (uintptr_t)addr;
 216         return tailroom;
 217 }
 218
 219 /**
 220  * Copy data to tailroom of circular queue.
 221  *
 222  * @param dst
 223  *   Pointer to destination.
 224  * @param src
 225  *   Pointer to source.
 226  * @param n
 227  *   Number of bytes to copy.
 228  * @param base
 229  *   Pointer to head of queue.
 230  * @param tailroom
 231  *   Size of tailroom from dst.
 232  *
 233  * @return
 234  *   Pointer after copied data.
 235  */
 236 static inline void *
 237 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 238                 void *base, size_t tailroom)
 239 {
 240         void *ret;
 241
 242         if (n > tailroom) {
 243                 rte_memcpy(dst, src, tailroom);
 244                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 245                            n - tailroom);
 246                 ret = (uint8_t *)base + n - tailroom;
 247         } else {
 248                 rte_memcpy(dst, src, n);
 249                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 250         }
 251         return ret;
 252 }
 253
 254 /**
 255  * DPDK callback to check the status of a tx descriptor.
 256  *
 257  * @param tx_queue
 258  *   The tx queue.
 259  * @param[in] offset
 260  *   The index of the descriptor in the ring.
 261  *
 262  * @return
 263  *   The status of the tx descriptor.
 264  */
 265 int
 266 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 267 {
 268         struct txq *txq = tx_queue;
 269         uint16_t used;
 270
 271         mlx5_tx_complete(txq);
 272         used = txq->elts_head - txq->elts_tail;
 273         if (offset < used)
 274                 return RTE_ETH_TX_DESC_FULL;
 275         return RTE_ETH_TX_DESC_DONE;
 276 }
 277
 278 /**
 279  * DPDK callback to check the status of a rx descriptor.
 280  *
 281  * @param rx_queue
 282  *   The rx queue.
 283  * @param[in] offset
 284  *   The index of the descriptor in the ring.
 285  *
 286  * @return
 287  *   The status of the tx descriptor.
 288  */
 289 int
 290 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 291 {
 292         struct rxq *rxq = rx_queue;
 293         struct rxq_zip *zip = &rxq->zip;
 294         volatile struct mlx5_cqe *cqe;
 295         const unsigned int cqe_n = (1 << rxq->cqe_n);
 296         const unsigned int cqe_cnt = cqe_n - 1;
 297         unsigned int cq_ci;
 298         unsigned int used;
 299
 300         /* if we are processing a compressed cqe */
 301         if (zip->ai) {
 302                 used = zip->cqe_cnt - zip->ca;
 303                 cq_ci = zip->cq_ci;
 304         } else {
 305                 used = 0;
 306                 cq_ci = rxq->cq_ci;
 307         }
 308         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 309         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 310                 int8_t op_own;
 311                 unsigned int n;
 312
 313                 op_own = cqe->op_own;
 314                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 315                         n = ntohl(cqe->byte_cnt);
 316                 else
 317                         n = 1;
 318                 cq_ci += n;
 319                 used += n;
 320                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 321         }
 322         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 323         if (offset < used)
 324                 return RTE_ETH_RX_DESC_DONE;
 325         return RTE_ETH_RX_DESC_AVAIL;
 326 }
 327
 328 /**
 329  * DPDK callback for TX.
 330  *
 331  * @param dpdk_txq
 332  *   Generic pointer to TX queue structure.
 333  * @param[in] pkts
 334  *   Packets to transmit.
 335  * @param pkts_n
 336  *   Number of packets in array.
 337  *
 338  * @return
 339  *   Number of packets successfully transmitted (<= pkts_n).
 340  */
 341 uint16_t
 342 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 343 {
 344         struct txq *txq = (struct txq *)dpdk_txq;
 345         uint16_t elts_head = txq->elts_head;
 346         const uint16_t elts_n = 1 << txq->elts_n;
 347         const uint16_t elts_m = elts_n - 1;
 348         unsigned int i = 0;
 349         unsigned int j = 0;
 350         unsigned int k = 0;
 351         uint16_t max_elts;
 352         unsigned int max_inline = txq->max_inline;
 353         const unsigned int inline_en = !!max_inline && txq->inline_en;
 354         uint16_t max_wqe;
 355         unsigned int comp;
 356         volatile struct mlx5_wqe_v *wqe = NULL;
 357         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 358         unsigned int segs_n = 0;
 359         struct rte_mbuf *buf = NULL;
 360         uint8_t *raw;
 361
 362         if (unlikely(!pkts_n))
 363                 return 0;
 364         /* Prefetch first packet cacheline. */
 365         rte_prefetch0(*pkts);
 366         /* Start processing. */
 367         mlx5_tx_complete(txq);
 368         max_elts = (elts_n - (elts_head - txq->elts_tail));
 369         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 370         if (unlikely(!max_wqe))
 371                 return 0;
 372         do {
 373                 volatile rte_v128u32_t *dseg = NULL;
 374                 uint32_t length;
 375                 unsigned int ds = 0;
 376                 unsigned int sg = 0; /* counter of additional segs attached. */
 377                 uintptr_t addr;
 378                 uint64_t naddr;
 379                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 380                 uint16_t tso_header_sz = 0;
 381                 uint16_t ehdr;
 382                 uint8_t cs_flags = 0;
 383                 uint64_t tso = 0;
 384                 uint16_t tso_segsz = 0;
 385 #ifdef MLX5_PMD_SOFT_COUNTERS
 386                 uint32_t total_length = 0;
 387 #endif
 388
 389                 /* first_seg */
 390                 buf = *pkts;
 391                 segs_n = buf->nb_segs;
 392                 /*
 393                  * Make sure there is enough room to store this packet and
 394                  * that one ring entry remains unused.
 395                  */
 396                 assert(segs_n);
 397                 if (max_elts < segs_n)
 398                         break;
 399                 max_elts -= segs_n;
 400                 --segs_n;
 401                 if (unlikely(--max_wqe == 0))
 402                         break;
 403                 wqe = (volatile struct mlx5_wqe_v *)
 404                         tx_mlx5_wqe(txq, txq->wqe_ci);
 405                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 406                 if (pkts_n - i > 1)
 407                         rte_prefetch0(*(pkts + 1));
 408                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 409                 length = DATA_LEN(buf);
 410                 ehdr = (((uint8_t *)addr)[1] << 8) |
 411                        ((uint8_t *)addr)[0];
 412 #ifdef MLX5_PMD_SOFT_COUNTERS
 413                 total_length = length;
 414 #endif
 415                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 416                         break;
 417                 /* Update element. */
 418                 (*txq->elts)[elts_head & elts_m] = buf;
 419                 /* Prefetch next buffer data. */
 420                 if (pkts_n - i > 1)
 421                         rte_prefetch0(
 422                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 423                 /* Should we enable HW CKSUM offload */
 424                 if (buf->ol_flags &
 425                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 426                         const uint64_t is_tunneled = buf->ol_flags &
 427                                                      (PKT_TX_TUNNEL_GRE |
 428                                                       PKT_TX_TUNNEL_VXLAN);
 429
 430                         if (is_tunneled && txq->tunnel_en) {
 431                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 432                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 433                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 434                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 435                         } else {
 436                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 437                                            MLX5_ETH_WQE_L4_CSUM;
 438                         }
 439                 }
 440                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 441                 /* Replace the Ethernet type by the VLAN if necessary. */
 442                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 443                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 444                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 445
 446                         addr += 2;
 447                         length -= 2;
 448                         /* Copy Destination and source mac address. */
 449                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 450                         /* Copy VLAN. */
 451                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 452                         /* Copy missing two bytes to end the DSeg. */
 453                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 454                                ((uint8_t *)addr) + len, 2);
 455                         addr += len + 2;
 456                         length -= (len + 2);
 457                 } else {
 458                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 459                                MLX5_WQE_DWORD_SIZE);
 460                         length -= pkt_inline_sz;
 461                         addr += pkt_inline_sz;
 462                 }
 463                 if (txq->tso_en) {
 464                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 465                         if (tso) {
 466                                 uintptr_t end = (uintptr_t)
 467                                                 (((uintptr_t)txq->wqes) +
 468                                                 (1 << txq->wqe_n) *
 469                                                 MLX5_WQE_SIZE);
 470                                 unsigned int copy_b;
 471                                 uint8_t vlan_sz = (buf->ol_flags &
 472                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 473                                 const uint64_t is_tunneled =
 474                                                         buf->ol_flags &
 475                                                         (PKT_TX_TUNNEL_GRE |
 476                                                          PKT_TX_TUNNEL_VXLAN);
 477
 478                                 tso_header_sz = buf->l2_len + vlan_sz +
 479                                                 buf->l3_len + buf->l4_len;
 480                                 tso_segsz = buf->tso_segsz;
 481
 482                                 if (is_tunneled && txq->tunnel_en) {
 483                                         tso_header_sz += buf->outer_l2_len +
 484                                                          buf->outer_l3_len;
 485                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 486                                 } else {
 487                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 488                                 }
 489                                 if (unlikely(tso_header_sz >
 490                                              MLX5_MAX_TSO_HEADER))
 491                                         break;
 492                                 copy_b = tso_header_sz - pkt_inline_sz;
 493                                 /* First seg must contain all headers. */
 494                                 assert(copy_b <= length);
 495                                 raw += MLX5_WQE_DWORD_SIZE;
 496                                 if (copy_b &&
 497                                    ((end - (uintptr_t)raw) > copy_b)) {
 498                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 499                                                       1 + 3) / 4;
 500
 501                                         if (unlikely(max_wqe < n))
 502                                                 break;
 503                                         max_wqe -= n;
 504                                         rte_memcpy((void *)raw,
 505                                                    (void *)addr, copy_b);
 506                                         addr += copy_b;
 507                                         length -= copy_b;
 508                                         pkt_inline_sz += copy_b;
 509                                         /*
 510                                          * Another DWORD will be added
 511                                          * in the inline part.
 512                                          */
 513                                         raw += MLX5_WQE_DS(copy_b) *
 514                                                MLX5_WQE_DWORD_SIZE -
 515                                                MLX5_WQE_DWORD_SIZE;
 516                                 } else {
 517                                         /* NOP WQE. */
 518                                         wqe->ctrl = (rte_v128u32_t){
 519                                                      htonl(txq->wqe_ci << 8),
 520                                                      htonl(txq->qp_num_8s | 1),
 521                                                      0,
 522                                                      0,
 523                                         };
 524                                         ds = 1;
 525                                         total_length = 0;
 526                                         k++;
 527                                         goto next_wqe;
 528                                 }
 529                         }
 530                 }
 531                 /* Inline if enough room. */
 532                 if (inline_en || tso) {
 533                         uintptr_t end = (uintptr_t)
 534                                 (((uintptr_t)txq->wqes) +
 535                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 536                         unsigned int inline_room = max_inline *
 537                                                    RTE_CACHE_LINE_SIZE -
 538                                                    (pkt_inline_sz - 2);
 539                         uintptr_t addr_end = (addr + inline_room) &
 540                                              ~(RTE_CACHE_LINE_SIZE - 1);
 541                         unsigned int copy_b = (addr_end > addr) ?
 542                                 RTE_MIN((addr_end - addr), length) :
 543                                 0;
 544
 545                         raw += MLX5_WQE_DWORD_SIZE;
 546                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 547                                 /*
 548                                  * One Dseg remains in the current WQE.  To
 549                                  * keep the computation positive, it is
 550                                  * removed after the bytes to Dseg conversion.
 551                                  */
 552                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 553
 554                                 if (unlikely(max_wqe < n))
 555                                         break;
 556                                 max_wqe -= n;
 557                                 if (tso) {
 558                                         uint32_t inl =
 559                                                 htonl(copy_b | MLX5_INLINE_SEG);
 560
 561                                         pkt_inline_sz =
 562                                                 MLX5_WQE_DS(tso_header_sz) *
 563                                                 MLX5_WQE_DWORD_SIZE;
 564                                         rte_memcpy((void *)raw,
 565                                                    (void *)&inl, sizeof(inl));
 566                                         raw += sizeof(inl);
 567                                         pkt_inline_sz += sizeof(inl);
 568                                 }
 569                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 570                                 addr += copy_b;
 571                                 length -= copy_b;
 572                                 pkt_inline_sz += copy_b;
 573                         }
 574                         /*
 575                          * 2 DWORDs consumed by the WQE header + ETH segment +
 576                          * the size of the inline part of the packet.
 577                          */
 578                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 579                         if (length > 0) {
 580                                 if (ds % (MLX5_WQE_SIZE /
 581                                           MLX5_WQE_DWORD_SIZE) == 0) {
 582                                         if (unlikely(--max_wqe == 0))
 583                                                 break;
 584                                         dseg = (volatile rte_v128u32_t *)
 585                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 586                                                            ds / 4);
 587                                 } else {
 588                                         dseg = (volatile rte_v128u32_t *)
 589                                                 ((uintptr_t)wqe +
 590                                                  (ds * MLX5_WQE_DWORD_SIZE));
 591                                 }
 592                                 goto use_dseg;
 593                         } else if (!segs_n) {
 594                                 goto next_pkt;
 595                         } else {
 596                                 /* dseg will be advance as part of next_seg */
 597                                 dseg = (volatile rte_v128u32_t *)
 598                                         ((uintptr_t)wqe +
 599                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 600                                 goto next_seg;
 601                         }
 602                 } else {
 603                         /*
 604                          * No inline has been done in the packet, only the
 605                          * Ethernet Header as been stored.
 606                          */
 607                         dseg = (volatile rte_v128u32_t *)
 608                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 609                         ds = 3;
 610 use_dseg:
 611                         /* Add the remaining packet as a simple ds. */
 612                         naddr = htonll(addr);
 613                         *dseg = (rte_v128u32_t){
 614                                 htonl(length),
 615                                 mlx5_tx_mb2mr(txq, buf),
 616                                 naddr,
 617                                 naddr >> 32,
 618                         };
 619                         ++ds;
 620                         if (!segs_n)
 621                                 goto next_pkt;
 622                 }
 623 next_seg:
 624                 assert(buf);
 625                 assert(ds);
 626                 assert(wqe);
 627                 /*
 628                  * Spill on next WQE when the current one does not have
 629                  * enough room left. Size of WQE must a be a multiple
 630                  * of data segment size.
 631                  */
 632                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 633                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 634                         if (unlikely(--max_wqe == 0))
 635                                 break;
 636                         dseg = (volatile rte_v128u32_t *)
 637                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 638                         rte_prefetch0(tx_mlx5_wqe(txq,
 639                                                   txq->wqe_ci + ds / 4 + 1));
 640                 } else {
 641                         ++dseg;
 642                 }
 643                 ++ds;
 644                 buf = buf->next;
 645                 assert(buf);
 646                 length = DATA_LEN(buf);
 647 #ifdef MLX5_PMD_SOFT_COUNTERS
 648                 total_length += length;
 649 #endif
 650                 /* Store segment information. */
 651                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 652                 *dseg = (rte_v128u32_t){
 653                         htonl(length),
 654                         mlx5_tx_mb2mr(txq, buf),
 655                         naddr,
 656                         naddr >> 32,
 657                 };
 658                 (*txq->elts)[++elts_head & elts_m] = buf;
 659                 ++sg;
 660                 /* Advance counter only if all segs are successfully posted. */
 661                 if (sg < segs_n)
 662                         goto next_seg;
 663                 else
 664                         j += sg;
 665 next_pkt:
 666                 ++elts_head;
 667                 ++pkts;
 668                 ++i;
 669                 /* Initialize known and common part of the WQE structure. */
 670                 if (tso) {
 671                         wqe->ctrl = (rte_v128u32_t){
 672                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 673                                 htonl(txq->qp_num_8s | ds),
 674                                 0,
 675                                 0,
 676                         };
 677                         wqe->eseg = (rte_v128u32_t){
 678                                 0,
 679                                 cs_flags | (htons(tso_segsz) << 16),
 680                                 0,
 681                                 (ehdr << 16) | htons(tso_header_sz),
 682                         };
 683                 } else {
 684                         wqe->ctrl = (rte_v128u32_t){
 685                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 686                                 htonl(txq->qp_num_8s | ds),
 687                                 0,
 688                                 0,
 689                         };
 690                         wqe->eseg = (rte_v128u32_t){
 691                                 0,
 692                                 cs_flags,
 693                                 0,
 694                                 (ehdr << 16) | htons(pkt_inline_sz),
 695                         };
 696                 }
 697 next_wqe:
 698                 txq->wqe_ci += (ds + 3) / 4;
 699                 /* Save the last successful WQE for completion request */
 700                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 701 #ifdef MLX5_PMD_SOFT_COUNTERS
 702                 /* Increment sent bytes counter. */
 703                 txq->stats.obytes += total_length;
 704 #endif
 705         } while (i < pkts_n);
 706         /* Take a shortcut if nothing must be sent. */
 707         if (unlikely((i + k) == 0))
 708                 return 0;
 709         txq->elts_head += (i + j);
 710         /* Check whether completion threshold has been reached. */
 711         comp = txq->elts_comp + i + j + k;
 712         if (comp >= MLX5_TX_COMP_THRESH) {
 713                 /* Request completion on last WQE. */
 714                 last_wqe->ctrl2 = htonl(8);
 715                 /* Save elts_head in unused "immediate" field of WQE. */
 716                 last_wqe->ctrl3 = txq->elts_head;
 717                 txq->elts_comp = 0;
 718         } else {
 719                 txq->elts_comp = comp;
 720         }
 721 #ifdef MLX5_PMD_SOFT_COUNTERS
 722         /* Increment sent packets counter. */
 723         txq->stats.opackets += i;
 724 #endif
 725         /* Ring QP doorbell. */
 726         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 727         return i;
 728 }
 729
 730 /**
 731  * Open a MPW session.
 732  *
 733  * @param txq
 734  *   Pointer to TX queue structure.
 735  * @param mpw
 736  *   Pointer to MPW session structure.
 737  * @param length
 738  *   Packet length.
 739  */
 740 static inline void
 741 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 742 {
 743         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 744         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 745                 (volatile struct mlx5_wqe_data_seg (*)[])
 746                 tx_mlx5_wqe(txq, idx + 1);
 747
 748         mpw->state = MLX5_MPW_STATE_OPENED;
 749         mpw->pkts_n = 0;
 750         mpw->len = length;
 751         mpw->total_len = 0;
 752         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 753         mpw->wqe->eseg.mss = htons(length);
 754         mpw->wqe->eseg.inline_hdr_sz = 0;
 755         mpw->wqe->eseg.rsvd0 = 0;
 756         mpw->wqe->eseg.rsvd1 = 0;
 757         mpw->wqe->eseg.rsvd2 = 0;
 758         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 759                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 760         mpw->wqe->ctrl[2] = 0;
 761         mpw->wqe->ctrl[3] = 0;
 762         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 763                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 764         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 765                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 766         mpw->data.dseg[2] = &(*dseg)[0];
 767         mpw->data.dseg[3] = &(*dseg)[1];
 768         mpw->data.dseg[4] = &(*dseg)[2];
 769 }
 770
 771 /**
 772  * Close a MPW session.
 773  *
 774  * @param txq
 775  *   Pointer to TX queue structure.
 776  * @param mpw
 777  *   Pointer to MPW session structure.
 778  */
 779 static inline void
 780 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 781 {
 782         unsigned int num = mpw->pkts_n;
 783
 784         /*
 785          * Store size in multiple of 16 bytes. Control and Ethernet segments
 786          * count as 2.
 787          */
 788         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 789         mpw->state = MLX5_MPW_STATE_CLOSED;
 790         if (num < 3)
 791                 ++txq->wqe_ci;
 792         else
 793                 txq->wqe_ci += 2;
 794         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 795         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 796 }
 797
 798 /**
 799  * DPDK callback for TX with MPW support.
 800  *
 801  * @param dpdk_txq
 802  *   Generic pointer to TX queue structure.
 803  * @param[in] pkts
 804  *   Packets to transmit.
 805  * @param pkts_n
 806  *   Number of packets in array.
 807  *
 808  * @return
 809  *   Number of packets successfully transmitted (<= pkts_n).
 810  */
 811 uint16_t
 812 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 813 {
 814         struct txq *txq = (struct txq *)dpdk_txq;
 815         uint16_t elts_head = txq->elts_head;
 816         const uint16_t elts_n = 1 << txq->elts_n;
 817         const uint16_t elts_m = elts_n - 1;
 818         unsigned int i = 0;
 819         unsigned int j = 0;
 820         uint16_t max_elts;
 821         uint16_t max_wqe;
 822         unsigned int comp;
 823         struct mlx5_mpw mpw = {
 824                 .state = MLX5_MPW_STATE_CLOSED,
 825         };
 826
 827         if (unlikely(!pkts_n))
 828                 return 0;
 829         /* Prefetch first packet cacheline. */
 830         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 831         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 832         /* Start processing. */
 833         mlx5_tx_complete(txq);
 834         max_elts = (elts_n - (elts_head - txq->elts_tail));
 835         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 836         if (unlikely(!max_wqe))
 837                 return 0;
 838         do {
 839                 struct rte_mbuf *buf = *(pkts++);
 840                 uint32_t length;
 841                 unsigned int segs_n = buf->nb_segs;
 842                 uint32_t cs_flags = 0;
 843
 844                 /*
 845                  * Make sure there is enough room to store this packet and
 846                  * that one ring entry remains unused.
 847                  */
 848                 assert(segs_n);
 849                 if (max_elts < segs_n)
 850                         break;
 851                 /* Do not bother with large packets MPW cannot handle. */
 852                 if (segs_n > MLX5_MPW_DSEG_MAX)
 853                         break;
 854                 max_elts -= segs_n;
 855                 --pkts_n;
 856                 /* Should we enable HW CKSUM offload */
 857                 if (buf->ol_flags &
 858                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 859                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 860                 /* Retrieve packet information. */
 861                 length = PKT_LEN(buf);
 862                 assert(length);
 863                 /* Start new session if packet differs. */
 864                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 865                     ((mpw.len != length) ||
 866                      (segs_n != 1) ||
 867                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 868                         mlx5_mpw_close(txq, &mpw);
 869                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 870                         /*
 871                          * Multi-Packet WQE consumes at most two WQE.
 872                          * mlx5_mpw_new() expects to be able to use such
 873                          * resources.
 874                          */
 875                         if (unlikely(max_wqe < 2))
 876                                 break;
 877                         max_wqe -= 2;
 878                         mlx5_mpw_new(txq, &mpw, length);
 879                         mpw.wqe->eseg.cs_flags = cs_flags;
 880                 }
 881                 /* Multi-segment packets must be alone in their MPW. */
 882                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 883 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 884                 length = 0;
 885 #endif
 886                 do {
 887                         volatile struct mlx5_wqe_data_seg *dseg;
 888                         uintptr_t addr;
 889
 890                         assert(buf);
 891                         (*txq->elts)[elts_head++ & elts_m] = buf;
 892                         dseg = mpw.data.dseg[mpw.pkts_n];
 893                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 894                         *dseg = (struct mlx5_wqe_data_seg){
 895                                 .byte_count = htonl(DATA_LEN(buf)),
 896                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 897                                 .addr = htonll(addr),
 898                         };
 899 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 900                         length += DATA_LEN(buf);
 901 #endif
 902                         buf = buf->next;
 903                         ++mpw.pkts_n;
 904                         ++j;
 905                 } while (--segs_n);
 906                 assert(length == mpw.len);
 907                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 908                         mlx5_mpw_close(txq, &mpw);
 909 #ifdef MLX5_PMD_SOFT_COUNTERS
 910                 /* Increment sent bytes counter. */
 911                 txq->stats.obytes += length;
 912 #endif
 913                 ++i;
 914         } while (pkts_n);
 915         /* Take a shortcut if nothing must be sent. */
 916         if (unlikely(i == 0))
 917                 return 0;
 918         /* Check whether completion threshold has been reached. */
 919         /* "j" includes both packets and segments. */
 920         comp = txq->elts_comp + j;
 921         if (comp >= MLX5_TX_COMP_THRESH) {
 922                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 923
 924                 /* Request completion on last WQE. */
 925                 wqe->ctrl[2] = htonl(8);
 926                 /* Save elts_head in unused "immediate" field of WQE. */
 927                 wqe->ctrl[3] = elts_head;
 928                 txq->elts_comp = 0;
 929         } else {
 930                 txq->elts_comp = comp;
 931         }
 932 #ifdef MLX5_PMD_SOFT_COUNTERS
 933         /* Increment sent packets counter. */
 934         txq->stats.opackets += i;
 935 #endif
 936         /* Ring QP doorbell. */
 937         if (mpw.state == MLX5_MPW_STATE_OPENED)
 938                 mlx5_mpw_close(txq, &mpw);
 939         mlx5_tx_dbrec(txq, mpw.wqe);
 940         txq->elts_head = elts_head;
 941         return i;
 942 }
 943
 944 /**
 945  * Open a MPW inline session.
 946  *
 947  * @param txq
 948  *   Pointer to TX queue structure.
 949  * @param mpw
 950  *   Pointer to MPW session structure.
 951  * @param length
 952  *   Packet length.
 953  */
 954 static inline void
 955 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 956 {
 957         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 958         struct mlx5_wqe_inl_small *inl;
 959
 960         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 961         mpw->pkts_n = 0;
 962         mpw->len = length;
 963         mpw->total_len = 0;
 964         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 965         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 966                                   (txq->wqe_ci << 8) |
 967                                   MLX5_OPCODE_TSO);
 968         mpw->wqe->ctrl[2] = 0;
 969         mpw->wqe->ctrl[3] = 0;
 970         mpw->wqe->eseg.mss = htons(length);
 971         mpw->wqe->eseg.inline_hdr_sz = 0;
 972         mpw->wqe->eseg.cs_flags = 0;
 973         mpw->wqe->eseg.rsvd0 = 0;
 974         mpw->wqe->eseg.rsvd1 = 0;
 975         mpw->wqe->eseg.rsvd2 = 0;
 976         inl = (struct mlx5_wqe_inl_small *)
 977                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 978         mpw->data.raw = (uint8_t *)&inl->raw;
 979 }
 980
 981 /**
 982  * Close a MPW inline session.
 983  *
 984  * @param txq
 985  *   Pointer to TX queue structure.
 986  * @param mpw
 987  *   Pointer to MPW session structure.
 988  */
 989 static inline void
 990 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
 991 {
 992         unsigned int size;
 993         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 994                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 995
 996         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 997         /*
 998          * Store size in multiple of 16 bytes. Control and Ethernet segments
 999          * count as 2.
1000          */
1001         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1002         mpw->state = MLX5_MPW_STATE_CLOSED;
1003         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1004         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1005 }
1006
1007 /**
1008  * DPDK callback for TX with MPW inline support.
1009  *
1010  * @param dpdk_txq
1011  *   Generic pointer to TX queue structure.
1012  * @param[in] pkts
1013  *   Packets to transmit.
1014  * @param pkts_n
1015  *   Number of packets in array.
1016  *
1017  * @return
1018  *   Number of packets successfully transmitted (<= pkts_n).
1019  */
1020 uint16_t
1021 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1022                          uint16_t pkts_n)
1023 {
1024         struct txq *txq = (struct txq *)dpdk_txq;
1025         uint16_t elts_head = txq->elts_head;
1026         const uint16_t elts_n = 1 << txq->elts_n;
1027         const uint16_t elts_m = elts_n - 1;
1028         unsigned int i = 0;
1029         unsigned int j = 0;
1030         uint16_t max_elts;
1031         uint16_t max_wqe;
1032         unsigned int comp;
1033         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1034         struct mlx5_mpw mpw = {
1035                 .state = MLX5_MPW_STATE_CLOSED,
1036         };
1037         /*
1038          * Compute the maximum number of WQE which can be consumed by inline
1039          * code.
1040          * - 2 DSEG for:
1041          *   - 1 control segment,
1042          *   - 1 Ethernet segment,
1043          * - N Dseg from the inline request.
1044          */
1045         const unsigned int wqe_inl_n =
1046                 ((2 * MLX5_WQE_DWORD_SIZE +
1047                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1048                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1049
1050         if (unlikely(!pkts_n))
1051                 return 0;
1052         /* Prefetch first packet cacheline. */
1053         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1054         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1055         /* Start processing. */
1056         mlx5_tx_complete(txq);
1057         max_elts = (elts_n - (elts_head - txq->elts_tail));
1058         do {
1059                 struct rte_mbuf *buf = *(pkts++);
1060                 uintptr_t addr;
1061                 uint32_t length;
1062                 unsigned int segs_n = buf->nb_segs;
1063                 uint32_t cs_flags = 0;
1064
1065                 /*
1066                  * Make sure there is enough room to store this packet and
1067                  * that one ring entry remains unused.
1068                  */
1069                 assert(segs_n);
1070                 if (max_elts < segs_n)
1071                         break;
1072                 /* Do not bother with large packets MPW cannot handle. */
1073                 if (segs_n > MLX5_MPW_DSEG_MAX)
1074                         break;
1075                 max_elts -= segs_n;
1076                 --pkts_n;
1077                 /*
1078                  * Compute max_wqe in case less WQE were consumed in previous
1079                  * iteration.
1080                  */
1081                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1082                 /* Should we enable HW CKSUM offload */
1083                 if (buf->ol_flags &
1084                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1085                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1086                 /* Retrieve packet information. */
1087                 length = PKT_LEN(buf);
1088                 /* Start new session if packet differs. */
1089                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1090                         if ((mpw.len != length) ||
1091                             (segs_n != 1) ||
1092                             (mpw.wqe->eseg.cs_flags != cs_flags))
1093                                 mlx5_mpw_close(txq, &mpw);
1094                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1095                         if ((mpw.len != length) ||
1096                             (segs_n != 1) ||
1097                             (length > inline_room) ||
1098                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1099                                 mlx5_mpw_inline_close(txq, &mpw);
1100                                 inline_room =
1101                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1102                         }
1103                 }
1104                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1105                         if ((segs_n != 1) ||
1106                             (length > inline_room)) {
1107                                 /*
1108                                  * Multi-Packet WQE consumes at most two WQE.
1109                                  * mlx5_mpw_new() expects to be able to use
1110                                  * such resources.
1111                                  */
1112                                 if (unlikely(max_wqe < 2))
1113                                         break;
1114                                 max_wqe -= 2;
1115                                 mlx5_mpw_new(txq, &mpw, length);
1116                                 mpw.wqe->eseg.cs_flags = cs_flags;
1117                         } else {
1118                                 if (unlikely(max_wqe < wqe_inl_n))
1119                                         break;
1120                                 max_wqe -= wqe_inl_n;
1121                                 mlx5_mpw_inline_new(txq, &mpw, length);
1122                                 mpw.wqe->eseg.cs_flags = cs_flags;
1123                         }
1124                 }
1125                 /* Multi-segment packets must be alone in their MPW. */
1126                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1127                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1128                         assert(inline_room ==
1129                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1130 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1131                         length = 0;
1132 #endif
1133                         do {
1134                                 volatile struct mlx5_wqe_data_seg *dseg;
1135
1136                                 assert(buf);
1137                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1138                                 dseg = mpw.data.dseg[mpw.pkts_n];
1139                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1140                                 *dseg = (struct mlx5_wqe_data_seg){
1141                                         .byte_count = htonl(DATA_LEN(buf)),
1142                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1143                                         .addr = htonll(addr),
1144                                 };
1145 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1146                                 length += DATA_LEN(buf);
1147 #endif
1148                                 buf = buf->next;
1149                                 ++mpw.pkts_n;
1150                                 ++j;
1151                         } while (--segs_n);
1152                         assert(length == mpw.len);
1153                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1154                                 mlx5_mpw_close(txq, &mpw);
1155                 } else {
1156                         unsigned int max;
1157
1158                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1159                         assert(length <= inline_room);
1160                         assert(length == DATA_LEN(buf));
1161                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1162                         (*txq->elts)[elts_head++ & elts_m] = buf;
1163                         /* Maximum number of bytes before wrapping. */
1164                         max = ((((uintptr_t)(txq->wqes)) +
1165                                 (1 << txq->wqe_n) *
1166                                 MLX5_WQE_SIZE) -
1167                                (uintptr_t)mpw.data.raw);
1168                         if (length > max) {
1169                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1170                                            (void *)addr,
1171                                            max);
1172                                 mpw.data.raw = (volatile void *)txq->wqes;
1173                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1174                                            (void *)(addr + max),
1175                                            length - max);
1176                                 mpw.data.raw += length - max;
1177                         } else {
1178                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1179                                            (void *)addr,
1180                                            length);
1181
1182                                 if (length == max)
1183                                         mpw.data.raw =
1184                                                 (volatile void *)txq->wqes;
1185                                 else
1186                                         mpw.data.raw += length;
1187                         }
1188                         ++mpw.pkts_n;
1189                         mpw.total_len += length;
1190                         ++j;
1191                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1192                                 mlx5_mpw_inline_close(txq, &mpw);
1193                                 inline_room =
1194                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1195                         } else {
1196                                 inline_room -= length;
1197                         }
1198                 }
1199 #ifdef MLX5_PMD_SOFT_COUNTERS
1200                 /* Increment sent bytes counter. */
1201                 txq->stats.obytes += length;
1202 #endif
1203                 ++i;
1204         } while (pkts_n);
1205         /* Take a shortcut if nothing must be sent. */
1206         if (unlikely(i == 0))
1207                 return 0;
1208         /* Check whether completion threshold has been reached. */
1209         /* "j" includes both packets and segments. */
1210         comp = txq->elts_comp + j;
1211         if (comp >= MLX5_TX_COMP_THRESH) {
1212                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1213
1214                 /* Request completion on last WQE. */
1215                 wqe->ctrl[2] = htonl(8);
1216                 /* Save elts_head in unused "immediate" field of WQE. */
1217                 wqe->ctrl[3] = elts_head;
1218                 txq->elts_comp = 0;
1219         } else {
1220                 txq->elts_comp = comp;
1221         }
1222 #ifdef MLX5_PMD_SOFT_COUNTERS
1223         /* Increment sent packets counter. */
1224         txq->stats.opackets += i;
1225 #endif
1226         /* Ring QP doorbell. */
1227         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1228                 mlx5_mpw_inline_close(txq, &mpw);
1229         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1230                 mlx5_mpw_close(txq, &mpw);
1231         mlx5_tx_dbrec(txq, mpw.wqe);
1232         txq->elts_head = elts_head;
1233         return i;
1234 }
1235
1236 /**
1237  * Open an Enhanced MPW session.
1238  *
1239  * @param txq
1240  *   Pointer to TX queue structure.
1241  * @param mpw
1242  *   Pointer to MPW session structure.
1243  * @param length
1244  *   Packet length.
1245  */
1246 static inline void
1247 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1248 {
1249         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1250
1251         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1252         mpw->pkts_n = 0;
1253         mpw->total_len = sizeof(struct mlx5_wqe);
1254         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1255         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1256                                   (txq->wqe_ci << 8) |
1257                                   MLX5_OPCODE_ENHANCED_MPSW);
1258         mpw->wqe->ctrl[2] = 0;
1259         mpw->wqe->ctrl[3] = 0;
1260         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1261         if (unlikely(padding)) {
1262                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1263
1264                 /* Pad the first 2 DWORDs with zero-length inline header. */
1265                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1266                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1267                         htonl(MLX5_INLINE_SEG);
1268                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1269                 /* Start from the next WQEBB. */
1270                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1271         } else {
1272                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1273         }
1274 }
1275
1276 /**
1277  * Close an Enhanced MPW session.
1278  *
1279  * @param txq
1280  *   Pointer to TX queue structure.
1281  * @param mpw
1282  *   Pointer to MPW session structure.
1283  *
1284  * @return
1285  *   Number of consumed WQEs.
1286  */
1287 static inline uint16_t
1288 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1289 {
1290         uint16_t ret;
1291
1292         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1293          * count as 2.
1294          */
1295         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1296         mpw->state = MLX5_MPW_STATE_CLOSED;
1297         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1298         txq->wqe_ci += ret;
1299         return ret;
1300 }
1301
1302 /**
1303  * DPDK callback for TX with Enhanced MPW support.
1304  *
1305  * @param dpdk_txq
1306  *   Generic pointer to TX queue structure.
1307  * @param[in] pkts
1308  *   Packets to transmit.
1309  * @param pkts_n
1310  *   Number of packets in array.
1311  *
1312  * @return
1313  *   Number of packets successfully transmitted (<= pkts_n).
1314  */
1315 uint16_t
1316 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1317 {
1318         struct txq *txq = (struct txq *)dpdk_txq;
1319         uint16_t elts_head = txq->elts_head;
1320         const uint16_t elts_n = 1 << txq->elts_n;
1321         const uint16_t elts_m = elts_n - 1;
1322         unsigned int i = 0;
1323         unsigned int j = 0;
1324         uint16_t max_elts;
1325         uint16_t max_wqe;
1326         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1327         unsigned int mpw_room = 0;
1328         unsigned int inl_pad = 0;
1329         uint32_t inl_hdr;
1330         struct mlx5_mpw mpw = {
1331                 .state = MLX5_MPW_STATE_CLOSED,
1332         };
1333
1334         if (unlikely(!pkts_n))
1335                 return 0;
1336         /* Start processing. */
1337         mlx5_tx_complete(txq);
1338         max_elts = (elts_n - (elts_head - txq->elts_tail));
1339         /* A CQE slot must always be available. */
1340         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1341         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1342         if (unlikely(!max_wqe))
1343                 return 0;
1344         do {
1345                 struct rte_mbuf *buf = *(pkts++);
1346                 uintptr_t addr;
1347                 uint64_t naddr;
1348                 unsigned int n;
1349                 unsigned int do_inline = 0; /* Whether inline is possible. */
1350                 uint32_t length;
1351                 unsigned int segs_n = buf->nb_segs;
1352                 uint32_t cs_flags = 0;
1353
1354                 /*
1355                  * Make sure there is enough room to store this packet and
1356                  * that one ring entry remains unused.
1357                  */
1358                 assert(segs_n);
1359                 if (max_elts - j < segs_n)
1360                         break;
1361                 /* Do not bother with large packets MPW cannot handle. */
1362                 if (segs_n > MLX5_MPW_DSEG_MAX)
1363                         break;
1364                 /* Should we enable HW CKSUM offload. */
1365                 if (buf->ol_flags &
1366                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1367                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1368                 /* Retrieve packet information. */
1369                 length = PKT_LEN(buf);
1370                 /* Start new session if:
1371                  * - multi-segment packet
1372                  * - no space left even for a dseg
1373                  * - next packet can be inlined with a new WQE
1374                  * - cs_flag differs
1375                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1376                  * segmented packet.
1377                  */
1378                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1379                         if ((segs_n != 1) ||
1380                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1381                               mpw_room) ||
1382                             (length <= txq->inline_max_packet_sz &&
1383                              inl_pad + sizeof(inl_hdr) + length >
1384                               mpw_room) ||
1385                             (mpw.wqe->eseg.cs_flags != cs_flags))
1386                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1387                 }
1388                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1389                         if (unlikely(segs_n != 1)) {
1390                                 /* Fall back to legacy MPW.
1391                                  * A MPW session consumes 2 WQEs at most to
1392                                  * include MLX5_MPW_DSEG_MAX pointers.
1393                                  */
1394                                 if (unlikely(max_wqe < 2))
1395                                         break;
1396                                 mlx5_mpw_new(txq, &mpw, length);
1397                         } else {
1398                                 /* In Enhanced MPW, inline as much as the budget
1399                                  * is allowed. The remaining space is to be
1400                                  * filled with dsegs. If the title WQEBB isn't
1401                                  * padded, it will have 2 dsegs there.
1402                                  */
1403                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1404                                             (max_inline ? max_inline :
1405                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1406                                             MLX5_WQE_SIZE);
1407                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1408                                               mpw_room))
1409                                         break;
1410                                 /* Don't pad the title WQEBB to not waste WQ. */
1411                                 mlx5_empw_new(txq, &mpw, 0);
1412                                 mpw_room -= mpw.total_len;
1413                                 inl_pad = 0;
1414                                 do_inline =
1415                                         length <= txq->inline_max_packet_sz &&
1416                                         sizeof(inl_hdr) + length <= mpw_room &&
1417                                         !txq->mpw_hdr_dseg;
1418                         }
1419                         mpw.wqe->eseg.cs_flags = cs_flags;
1420                 } else {
1421                         /* Evaluate whether the next packet can be inlined.
1422                          * Inlininig is possible when:
1423                          * - length is less than configured value
1424                          * - length fits for remaining space
1425                          * - not required to fill the title WQEBB with dsegs
1426                          */
1427                         do_inline =
1428                                 length <= txq->inline_max_packet_sz &&
1429                                 inl_pad + sizeof(inl_hdr) + length <=
1430                                  mpw_room &&
1431                                 (!txq->mpw_hdr_dseg ||
1432                                  mpw.total_len >= MLX5_WQE_SIZE);
1433                 }
1434                 /* Multi-segment packets must be alone in their MPW. */
1435                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1436                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1437 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1438                         length = 0;
1439 #endif
1440                         do {
1441                                 volatile struct mlx5_wqe_data_seg *dseg;
1442
1443                                 assert(buf);
1444                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1445                                 dseg = mpw.data.dseg[mpw.pkts_n];
1446                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1447                                 *dseg = (struct mlx5_wqe_data_seg){
1448                                         .byte_count = htonl(DATA_LEN(buf)),
1449                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1450                                         .addr = htonll(addr),
1451                                 };
1452 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1453                                 length += DATA_LEN(buf);
1454 #endif
1455                                 buf = buf->next;
1456                                 ++j;
1457                                 ++mpw.pkts_n;
1458                         } while (--segs_n);
1459                         /* A multi-segmented packet takes one MPW session.
1460                          * TODO: Pack more multi-segmented packets if possible.
1461                          */
1462                         mlx5_mpw_close(txq, &mpw);
1463                         if (mpw.pkts_n < 3)
1464                                 max_wqe--;
1465                         else
1466                                 max_wqe -= 2;
1467                 } else if (do_inline) {
1468                         /* Inline packet into WQE. */
1469                         unsigned int max;
1470
1471                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1472                         assert(length == DATA_LEN(buf));
1473                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1474                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1475                         mpw.data.raw = (volatile void *)
1476                                 ((uintptr_t)mpw.data.raw + inl_pad);
1477                         max = tx_mlx5_wq_tailroom(txq,
1478                                         (void *)(uintptr_t)mpw.data.raw);
1479                         /* Copy inline header. */
1480                         mpw.data.raw = (volatile void *)
1481                                 mlx5_copy_to_wq(
1482                                           (void *)(uintptr_t)mpw.data.raw,
1483                                           &inl_hdr,
1484                                           sizeof(inl_hdr),
1485                                           (void *)(uintptr_t)txq->wqes,
1486                                           max);
1487                         max = tx_mlx5_wq_tailroom(txq,
1488                                         (void *)(uintptr_t)mpw.data.raw);
1489                         /* Copy packet data. */
1490                         mpw.data.raw = (volatile void *)
1491                                 mlx5_copy_to_wq(
1492                                           (void *)(uintptr_t)mpw.data.raw,
1493                                           (void *)addr,
1494                                           length,
1495                                           (void *)(uintptr_t)txq->wqes,
1496                                           max);
1497                         ++mpw.pkts_n;
1498                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1499                         /* No need to get completion as the entire packet is
1500                          * copied to WQ. Free the buf right away.
1501                          */
1502                         rte_pktmbuf_free_seg(buf);
1503                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1504                         /* Add pad in the next packet if any. */
1505                         inl_pad = (((uintptr_t)mpw.data.raw +
1506                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1507                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1508                                   (uintptr_t)mpw.data.raw;
1509                 } else {
1510                         /* No inline. Load a dseg of packet pointer. */
1511                         volatile rte_v128u32_t *dseg;
1512
1513                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1514                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1515                         assert(length == DATA_LEN(buf));
1516                         if (!tx_mlx5_wq_tailroom(txq,
1517                                         (void *)((uintptr_t)mpw.data.raw
1518                                                 + inl_pad)))
1519                                 dseg = (volatile void *)txq->wqes;
1520                         else
1521                                 dseg = (volatile void *)
1522                                         ((uintptr_t)mpw.data.raw +
1523                                          inl_pad);
1524                         (*txq->elts)[elts_head++ & elts_m] = buf;
1525                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1526                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1527                                 rte_prefetch2((void *)(addr +
1528                                                 n * RTE_CACHE_LINE_SIZE));
1529                         naddr = htonll(addr);
1530                         *dseg = (rte_v128u32_t) {
1531                                 htonl(length),
1532                                 mlx5_tx_mb2mr(txq, buf),
1533                                 naddr,
1534                                 naddr >> 32,
1535                         };
1536                         mpw.data.raw = (volatile void *)(dseg + 1);
1537                         mpw.total_len += (inl_pad + sizeof(*dseg));
1538                         ++j;
1539                         ++mpw.pkts_n;
1540                         mpw_room -= (inl_pad + sizeof(*dseg));
1541                         inl_pad = 0;
1542                 }
1543 #ifdef MLX5_PMD_SOFT_COUNTERS
1544                 /* Increment sent bytes counter. */
1545                 txq->stats.obytes += length;
1546 #endif
1547                 ++i;
1548         } while (i < pkts_n);
1549         /* Take a shortcut if nothing must be sent. */
1550         if (unlikely(i == 0))
1551                 return 0;
1552         /* Check whether completion threshold has been reached. */
1553         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1554                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1555                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1556                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1557
1558                 /* Request completion on last WQE. */
1559                 wqe->ctrl[2] = htonl(8);
1560                 /* Save elts_head in unused "immediate" field of WQE. */
1561                 wqe->ctrl[3] = elts_head;
1562                 txq->elts_comp = 0;
1563                 txq->mpw_comp = txq->wqe_ci;
1564                 txq->cq_pi++;
1565         } else {
1566                 txq->elts_comp += j;
1567         }
1568 #ifdef MLX5_PMD_SOFT_COUNTERS
1569         /* Increment sent packets counter. */
1570         txq->stats.opackets += i;
1571 #endif
1572         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1573                 mlx5_empw_close(txq, &mpw);
1574         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1575                 mlx5_mpw_close(txq, &mpw);
1576         /* Ring QP doorbell. */
1577         mlx5_tx_dbrec(txq, mpw.wqe);
1578         txq->elts_head = elts_head;
1579         return i;
1580 }
1581
1582 /**
1583  * Translate RX completion flags to packet type.
1584  *
1585  * @param[in] cqe
1586  *   Pointer to CQE.
1587  *
1588  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1589  *
1590  * @return
1591  *   Packet type for struct rte_mbuf.
1592  */
1593 static inline uint32_t
1594 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1595 {
1596         uint8_t idx;
1597         uint8_t pinfo = cqe->pkt_info;
1598         uint16_t ptype = cqe->hdr_type_etc;
1599
1600         /*
1601          * The index to the array should have:
1602          * bit[1:0] = l3_hdr_type
1603          * bit[4:2] = l4_hdr_type
1604          * bit[5] = ip_frag
1605          * bit[6] = tunneled
1606          * bit[7] = outer_l3_type
1607          */
1608         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1609         return mlx5_ptype_table[idx];
1610 }
1611
1612 /**
1613  * Get size of the next packet for a given CQE. For compressed CQEs, the
1614  * consumer index is updated only once all packets of the current one have
1615  * been processed.
1616  *
1617  * @param rxq
1618  *   Pointer to RX queue.
1619  * @param cqe
1620  *   CQE to process.
1621  * @param[out] rss_hash
1622  *   Packet RSS Hash result.
1623  *
1624  * @return
1625  *   Packet size in bytes (0 if there is none), -1 in case of completion
1626  *   with error.
1627  */
1628 static inline int
1629 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1630                  uint16_t cqe_cnt, uint32_t *rss_hash)
1631 {
1632         struct rxq_zip *zip = &rxq->zip;
1633         uint16_t cqe_n = cqe_cnt + 1;
1634         int len = 0;
1635         uint16_t idx, end;
1636
1637         /* Process compressed data in the CQE and mini arrays. */
1638         if (zip->ai) {
1639                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1640                         (volatile struct mlx5_mini_cqe8 (*)[8])
1641                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1642
1643                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1644                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1645                 if ((++zip->ai & 7) == 0) {
1646                         /* Invalidate consumed CQEs */
1647                         idx = zip->ca;
1648                         end = zip->na;
1649                         while (idx != end) {
1650                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1651                                         MLX5_CQE_INVALIDATE;
1652                                 ++idx;
1653                         }
1654                         /*
1655                          * Increment consumer index to skip the number of
1656                          * CQEs consumed. Hardware leaves holes in the CQ
1657                          * ring for software use.
1658                          */
1659                         zip->ca = zip->na;
1660                         zip->na += 8;
1661                 }
1662                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1663                         /* Invalidate the rest */
1664                         idx = zip->ca;
1665                         end = zip->cq_ci;
1666
1667                         while (idx != end) {
1668                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1669                                         MLX5_CQE_INVALIDATE;
1670                                 ++idx;
1671                         }
1672                         rxq->cq_ci = zip->cq_ci;
1673                         zip->ai = 0;
1674                 }
1675         /* No compressed data, get next CQE and verify if it is compressed. */
1676         } else {
1677                 int ret;
1678                 int8_t op_own;
1679
1680                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1681                 if (unlikely(ret == 1))
1682                         return 0;
1683                 ++rxq->cq_ci;
1684                 op_own = cqe->op_own;
1685                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1686                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1687                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1688                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1689                                                           cqe_cnt].pkt_info);
1690
1691                         /* Fix endianness. */
1692                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1693                         /*
1694                          * Current mini array position is the one returned by
1695                          * check_cqe64().
1696                          *
1697                          * If completion comprises several mini arrays, as a
1698                          * special case the second one is located 7 CQEs after
1699                          * the initial CQE instead of 8 for subsequent ones.
1700                          */
1701                         zip->ca = rxq->cq_ci;
1702                         zip->na = zip->ca + 7;
1703                         /* Compute the next non compressed CQE. */
1704                         --rxq->cq_ci;
1705                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1706                         /* Get packet size to return. */
1707                         len = ntohl((*mc)[0].byte_cnt);
1708                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1709                         zip->ai = 1;
1710                         /* Prefetch all the entries to be invalidated */
1711                         idx = zip->ca;
1712                         end = zip->cq_ci;
1713                         while (idx != end) {
1714                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1715                                 ++idx;
1716                         }
1717                 } else {
1718                         len = ntohl(cqe->byte_cnt);
1719                         *rss_hash = ntohl(cqe->rx_hash_res);
1720                 }
1721                 /* Error while receiving packet. */
1722                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1723                         return -1;
1724         }
1725         return len;
1726 }
1727
1728 /**
1729  * Translate RX completion flags to offload flags.
1730  *
1731  * @param[in] rxq
1732  *   Pointer to RX queue structure.
1733  * @param[in] cqe
1734  *   Pointer to CQE.
1735  *
1736  * @return
1737  *   Offload flags (ol_flags) for struct rte_mbuf.
1738  */
1739 static inline uint32_t
1740 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1741 {
1742         uint32_t ol_flags = 0;
1743         uint16_t flags = ntohs(cqe->hdr_type_etc);
1744
1745         ol_flags =
1746                 TRANSPOSE(flags,
1747                           MLX5_CQE_RX_L3_HDR_VALID,
1748                           PKT_RX_IP_CKSUM_GOOD) |
1749                 TRANSPOSE(flags,
1750                           MLX5_CQE_RX_L4_HDR_VALID,
1751                           PKT_RX_L4_CKSUM_GOOD);
1752         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1753                 ol_flags |=
1754                         TRANSPOSE(flags,
1755                                   MLX5_CQE_RX_L3_HDR_VALID,
1756                                   PKT_RX_IP_CKSUM_GOOD) |
1757                         TRANSPOSE(flags,
1758                                   MLX5_CQE_RX_L4_HDR_VALID,
1759                                   PKT_RX_L4_CKSUM_GOOD);
1760         return ol_flags;
1761 }
1762
1763 /**
1764  * DPDK callback for RX.
1765  *
1766  * @param dpdk_rxq
1767  *   Generic pointer to RX queue structure.
1768  * @param[out] pkts
1769  *   Array to store received packets.
1770  * @param pkts_n
1771  *   Maximum number of packets in array.
1772  *
1773  * @return
1774  *   Number of packets successfully received (<= pkts_n).
1775  */
1776 uint16_t
1777 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1778 {
1779         struct rxq *rxq = dpdk_rxq;
1780         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1781         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1782         const unsigned int sges_n = rxq->sges_n;
1783         struct rte_mbuf *pkt = NULL;
1784         struct rte_mbuf *seg = NULL;
1785         volatile struct mlx5_cqe *cqe =
1786                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1787         unsigned int i = 0;
1788         unsigned int rq_ci = rxq->rq_ci << sges_n;
1789         int len = 0; /* keep its value across iterations. */
1790
1791         while (pkts_n) {
1792                 unsigned int idx = rq_ci & wqe_cnt;
1793                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1794                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1795                 uint32_t rss_hash_res = 0;
1796
1797                 if (pkt)
1798                         NEXT(seg) = rep;
1799                 seg = rep;
1800                 rte_prefetch0(seg);
1801                 rte_prefetch0(cqe);
1802                 rte_prefetch0(wqe);
1803                 rep = rte_mbuf_raw_alloc(rxq->mp);
1804                 if (unlikely(rep == NULL)) {
1805                         ++rxq->stats.rx_nombuf;
1806                         if (!pkt) {
1807                                 /*
1808                                  * no buffers before we even started,
1809                                  * bail out silently.
1810                                  */
1811                                 break;
1812                         }
1813                         while (pkt != seg) {
1814                                 assert(pkt != (*rxq->elts)[idx]);
1815                                 rep = NEXT(pkt);
1816                                 NEXT(pkt) = NULL;
1817                                 NB_SEGS(pkt) = 1;
1818                                 rte_mbuf_raw_free(pkt);
1819                                 pkt = rep;
1820                         }
1821                         break;
1822                 }
1823                 if (!pkt) {
1824                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1825                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1826                                                &rss_hash_res);
1827                         if (!len) {
1828                                 rte_mbuf_raw_free(rep);
1829                                 break;
1830                         }
1831                         if (unlikely(len == -1)) {
1832                                 /* RX error, packet is likely too large. */
1833                                 rte_mbuf_raw_free(rep);
1834                                 ++rxq->stats.idropped;
1835                                 goto skip;
1836                         }
1837                         pkt = seg;
1838                         assert(len >= (rxq->crc_present << 2));
1839                         /* Update packet information. */
1840                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1841                         pkt->ol_flags = 0;
1842                         if (rss_hash_res && rxq->rss_hash) {
1843                                 pkt->hash.rss = rss_hash_res;
1844                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1845                         }
1846                         if (rxq->mark &&
1847                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1848                                 pkt->ol_flags |= PKT_RX_FDIR;
1849                                 if (cqe->sop_drop_qpn !=
1850                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1851                                         uint32_t mark = cqe->sop_drop_qpn;
1852
1853                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1854                                         pkt->hash.fdir.hi =
1855                                                 mlx5_flow_mark_get(mark);
1856                                 }
1857                         }
1858                         if (rxq->csum | rxq->csum_l2tun)
1859                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1860                         if (rxq->vlan_strip &&
1861                             (cqe->hdr_type_etc &
1862                              htons(MLX5_CQE_VLAN_STRIPPED))) {
1863                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1864                                         PKT_RX_VLAN_STRIPPED;
1865                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
1866                         }
1867                         if (rxq->crc_present)
1868                                 len -= ETHER_CRC_LEN;
1869                         PKT_LEN(pkt) = len;
1870                 }
1871                 DATA_LEN(rep) = DATA_LEN(seg);
1872                 PKT_LEN(rep) = PKT_LEN(seg);
1873                 SET_DATA_OFF(rep, DATA_OFF(seg));
1874                 PORT(rep) = PORT(seg);
1875                 (*rxq->elts)[idx] = rep;
1876                 /*
1877                  * Fill NIC descriptor with the new buffer.  The lkey and size
1878                  * of the buffers are already known, only the buffer address
1879                  * changes.
1880                  */
1881                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1882                 if (len > DATA_LEN(seg)) {
1883                         len -= DATA_LEN(seg);
1884                         ++NB_SEGS(pkt);
1885                         ++rq_ci;
1886                         continue;
1887                 }
1888                 DATA_LEN(seg) = len;
1889 #ifdef MLX5_PMD_SOFT_COUNTERS
1890                 /* Increment bytes counter. */
1891                 rxq->stats.ibytes += PKT_LEN(pkt);
1892 #endif
1893                 /* Return packet. */
1894                 *(pkts++) = pkt;
1895                 pkt = NULL;
1896                 --pkts_n;
1897                 ++i;
1898 skip:
1899                 /* Align consumer index to the next stride. */
1900                 rq_ci >>= sges_n;
1901                 ++rq_ci;
1902                 rq_ci <<= sges_n;
1903         }
1904         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1905                 return 0;
1906         /* Update the consumer index. */
1907         rxq->rq_ci = rq_ci >> sges_n;
1908         rte_wmb();
1909         *rxq->cq_db = htonl(rxq->cq_ci);
1910         rte_wmb();
1911         *rxq->rq_db = htonl(rxq->rq_ci);
1912 #ifdef MLX5_PMD_SOFT_COUNTERS
1913         /* Increment packets counter. */
1914         rxq->stats.ipackets += i;
1915 #endif
1916         return i;
1917 }
1918
1919 /**
1920  * Dummy DPDK callback for TX.
1921  *
1922  * This function is used to temporarily replace the real callback during
1923  * unsafe control operations on the queue, or in case of error.
1924  *
1925  * @param dpdk_txq
1926  *   Generic pointer to TX queue structure.
1927  * @param[in] pkts
1928  *   Packets to transmit.
1929  * @param pkts_n
1930  *   Number of packets in array.
1931  *
1932  * @return
1933  *   Number of packets successfully transmitted (<= pkts_n).
1934  */
1935 uint16_t
1936 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1937 {
1938         (void)dpdk_txq;
1939         (void)pkts;
1940         (void)pkts_n;
1941         return 0;
1942 }
1943
1944 /**
1945  * Dummy DPDK callback for RX.
1946  *
1947  * This function is used to temporarily replace the real callback during
1948  * unsafe control operations on the queue, or in case of error.
1949  *
1950  * @param dpdk_rxq
1951  *   Generic pointer to RX queue structure.
1952  * @param[out] pkts
1953  *   Array to store received packets.
1954  * @param pkts_n
1955  *   Maximum number of packets in array.
1956  *
1957  * @return
1958  *   Number of packets successfully received (<= pkts_n).
1959  */
1960 uint16_t
1961 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1962 {
1963         (void)dpdk_rxq;
1964         (void)pkts;
1965         (void)pkts_n;
1966         return 0;
1967 }
1968
1969 /*
1970  * Vectorized Rx/Tx routines are not compiled in when required vector
1971  * instructions are not supported on a target architecture. The following null
1972  * stubs are needed for linkage when those are not included outside of this file
1973  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1974  */
1975
1976 uint16_t __attribute__((weak))
1977 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1978 {
1979         (void)dpdk_txq;
1980         (void)pkts;
1981         (void)pkts_n;
1982         return 0;
1983 }
1984
1985 uint16_t __attribute__((weak))
1986 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1987 {
1988         (void)dpdk_txq;
1989         (void)pkts;
1990         (void)pkts_n;
1991         return 0;
1992 }
1993
1994 uint16_t __attribute__((weak))
1995 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1996 {
1997         (void)dpdk_rxq;
1998         (void)pkts;
1999         (void)pkts_n;
2000         return 0;
2001 }
2002
2003 int __attribute__((weak))
2004 priv_check_raw_vec_tx_support(struct priv *priv)
2005 {
2006         (void)priv;
2007         return -ENOTSUP;
2008 }
2009
2010 int __attribute__((weak))
2011 priv_check_vec_tx_support(struct priv *priv)
2012 {
2013         (void)priv;
2014         return -ENOTSUP;
2015 }
2016
2017 int __attribute__((weak))
2018 rxq_check_vec_support(struct rxq *rxq)
2019 {
2020         (void)rxq;
2021         return -ENOTSUP;
2022 }
2023
2024 int __attribute__((weak))
2025 priv_check_vec_rx_support(struct priv *priv)
2026 {
2027         (void)priv;
2028         return -ENOTSUP;
2029 }
2030
2031 void __attribute__((weak))
2032 priv_prep_vec_rx_function(struct priv *priv)
2033 {
2034         (void)priv;
2035 }