drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5dv.h>
  46 #ifdef PEDANTIC
  47 #pragma GCC diagnostic error "-Wpedantic"
  48 #endif
  49
  50 #include <rte_mbuf.h>
  51 #include <rte_mempool.h>
  52 #include <rte_prefetch.h>
  53 #include <rte_common.h>
  54 #include <rte_branch_prediction.h>
  55 #include <rte_ether.h>
  56
  57 #include "mlx5.h"
  58 #include "mlx5_utils.h"
  59 #include "mlx5_rxtx.h"
  60 #include "mlx5_autoconf.h"
  61 #include "mlx5_defs.h"
  62 #include "mlx5_prm.h"
  63
  64 static __rte_always_inline uint32_t
  65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  66
  67 static __rte_always_inline int
  68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  69                  uint16_t cqe_cnt, uint32_t *rss_hash);
  70
  71 static __rte_always_inline uint32_t
  72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  73
  74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  75         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  76 };
  77
  78 /**
  79  * Build a table to translate Rx completion flags to packet type.
  80  *
  81  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  82  */
  83 void
  84 mlx5_set_ptype_table(void)
  85 {
  86         unsigned int i;
  87         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  88
  89         /* Last entry must not be overwritten, reserved for errored packet. */
  90         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  91                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  92         /*
  93          * The index to the array should have:
  94          * bit[1:0] = l3_hdr_type
  95          * bit[4:2] = l4_hdr_type
  96          * bit[5] = ip_frag
  97          * bit[6] = tunneled
  98          * bit[7] = outer_l3_type
  99          */
 100         /* L2 */
 101         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
 102         /* L3 */
 103         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         /* Fragmented */
 108         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_FRAG;
 110         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         /* TCP */
 113         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         /* UDP */
 118         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_UDP;
 120         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_UDP;
 122         /* Repeat with outer_l3_type being set. Just in case. */
 123         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_NONFRAG;
 125         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_NONFRAG;
 127         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_FRAG;
 129         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_FRAG;
 131         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_TCP;
 135         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 138                      RTE_PTYPE_L4_UDP;
 139         /* Tunneled - L3 */
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         /* Tunneled - UDP */
 179         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_UDP;
 182         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_UDP;
 185         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_UDP;
 188         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_UDP;
 191 }
 192
 193 /**
 194  * Return the size of tailroom of WQ.
 195  *
 196  * @param txq
 197  *   Pointer to TX queue structure.
 198  * @param addr
 199  *   Pointer to tail of WQ.
 200  *
 201  * @return
 202  *   Size of tailroom.
 203  */
 204 static inline size_t
 205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 206 {
 207         size_t tailroom;
 208         tailroom = (uintptr_t)(txq->wqes) +
 209                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 210                    (uintptr_t)addr;
 211         return tailroom;
 212 }
 213
 214 /**
 215  * Copy data to tailroom of circular queue.
 216  *
 217  * @param dst
 218  *   Pointer to destination.
 219  * @param src
 220  *   Pointer to source.
 221  * @param n
 222  *   Number of bytes to copy.
 223  * @param base
 224  *   Pointer to head of queue.
 225  * @param tailroom
 226  *   Size of tailroom from dst.
 227  *
 228  * @return
 229  *   Pointer after copied data.
 230  */
 231 static inline void *
 232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 233                 void *base, size_t tailroom)
 234 {
 235         void *ret;
 236
 237         if (n > tailroom) {
 238                 rte_memcpy(dst, src, tailroom);
 239                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 240                            n - tailroom);
 241                 ret = (uint8_t *)base + n - tailroom;
 242         } else {
 243                 rte_memcpy(dst, src, n);
 244                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 245         }
 246         return ret;
 247 }
 248
 249 /**
 250  * DPDK callback to check the status of a tx descriptor.
 251  *
 252  * @param tx_queue
 253  *   The tx queue.
 254  * @param[in] offset
 255  *   The index of the descriptor in the ring.
 256  *
 257  * @return
 258  *   The status of the tx descriptor.
 259  */
 260 int
 261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 262 {
 263         struct mlx5_txq_data *txq = tx_queue;
 264         uint16_t used;
 265
 266         mlx5_tx_complete(txq);
 267         used = txq->elts_head - txq->elts_tail;
 268         if (offset < used)
 269                 return RTE_ETH_TX_DESC_FULL;
 270         return RTE_ETH_TX_DESC_DONE;
 271 }
 272
 273 /**
 274  * DPDK callback to check the status of a rx descriptor.
 275  *
 276  * @param rx_queue
 277  *   The rx queue.
 278  * @param[in] offset
 279  *   The index of the descriptor in the ring.
 280  *
 281  * @return
 282  *   The status of the tx descriptor.
 283  */
 284 int
 285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 286 {
 287         struct mlx5_rxq_data *rxq = rx_queue;
 288         struct rxq_zip *zip = &rxq->zip;
 289         volatile struct mlx5_cqe *cqe;
 290         const unsigned int cqe_n = (1 << rxq->cqe_n);
 291         const unsigned int cqe_cnt = cqe_n - 1;
 292         unsigned int cq_ci;
 293         unsigned int used;
 294
 295         /* if we are processing a compressed cqe */
 296         if (zip->ai) {
 297                 used = zip->cqe_cnt - zip->ca;
 298                 cq_ci = zip->cq_ci;
 299         } else {
 300                 used = 0;
 301                 cq_ci = rxq->cq_ci;
 302         }
 303         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 304         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 305                 int8_t op_own;
 306                 unsigned int n;
 307
 308                 op_own = cqe->op_own;
 309                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 310                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 311                 else
 312                         n = 1;
 313                 cq_ci += n;
 314                 used += n;
 315                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 316         }
 317         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 318         if (offset < used)
 319                 return RTE_ETH_RX_DESC_DONE;
 320         return RTE_ETH_RX_DESC_AVAIL;
 321 }
 322
 323 /**
 324  * DPDK callback for TX.
 325  *
 326  * @param dpdk_txq
 327  *   Generic pointer to TX queue structure.
 328  * @param[in] pkts
 329  *   Packets to transmit.
 330  * @param pkts_n
 331  *   Number of packets in array.
 332  *
 333  * @return
 334  *   Number of packets successfully transmitted (<= pkts_n).
 335  */
 336 uint16_t
 337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 338 {
 339         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 340         uint16_t elts_head = txq->elts_head;
 341         const uint16_t elts_n = 1 << txq->elts_n;
 342         const uint16_t elts_m = elts_n - 1;
 343         unsigned int i = 0;
 344         unsigned int j = 0;
 345         unsigned int k = 0;
 346         uint16_t max_elts;
 347         unsigned int max_inline = txq->max_inline;
 348         const unsigned int inline_en = !!max_inline && txq->inline_en;
 349         uint16_t max_wqe;
 350         unsigned int comp;
 351         volatile struct mlx5_wqe_v *wqe = NULL;
 352         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 353         unsigned int segs_n = 0;
 354         struct rte_mbuf *buf = NULL;
 355         uint8_t *raw;
 356
 357         if (unlikely(!pkts_n))
 358                 return 0;
 359         /* Prefetch first packet cacheline. */
 360         rte_prefetch0(*pkts);
 361         /* Start processing. */
 362         mlx5_tx_complete(txq);
 363         max_elts = (elts_n - (elts_head - txq->elts_tail));
 364         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 365         if (unlikely(!max_wqe))
 366                 return 0;
 367         do {
 368                 volatile rte_v128u32_t *dseg = NULL;
 369                 uint32_t length;
 370                 unsigned int ds = 0;
 371                 unsigned int sg = 0; /* counter of additional segs attached. */
 372                 uintptr_t addr;
 373                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 374                 uint16_t tso_header_sz = 0;
 375                 uint16_t ehdr;
 376                 uint8_t cs_flags = 0;
 377                 uint64_t tso = 0;
 378                 uint16_t tso_segsz = 0;
 379 #ifdef MLX5_PMD_SOFT_COUNTERS
 380                 uint32_t total_length = 0;
 381 #endif
 382
 383                 /* first_seg */
 384                 buf = *pkts;
 385                 segs_n = buf->nb_segs;
 386                 /*
 387                  * Make sure there is enough room to store this packet and
 388                  * that one ring entry remains unused.
 389                  */
 390                 assert(segs_n);
 391                 if (max_elts < segs_n)
 392                         break;
 393                 max_elts -= segs_n;
 394                 --segs_n;
 395                 if (unlikely(--max_wqe == 0))
 396                         break;
 397                 wqe = (volatile struct mlx5_wqe_v *)
 398                         tx_mlx5_wqe(txq, txq->wqe_ci);
 399                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 400                 if (pkts_n - i > 1)
 401                         rte_prefetch0(*(pkts + 1));
 402                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 403                 length = DATA_LEN(buf);
 404                 ehdr = (((uint8_t *)addr)[1] << 8) |
 405                        ((uint8_t *)addr)[0];
 406 #ifdef MLX5_PMD_SOFT_COUNTERS
 407                 total_length = length;
 408 #endif
 409                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 410                         txq->stats.oerrors++;
 411                         break;
 412                 }
 413                 /* Update element. */
 414                 (*txq->elts)[elts_head & elts_m] = buf;
 415                 /* Prefetch next buffer data. */
 416                 if (pkts_n - i > 1)
 417                         rte_prefetch0(
 418                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 419                 /* Should we enable HW CKSUM offload */
 420                 if (buf->ol_flags &
 421                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 422                         const uint64_t is_tunneled = buf->ol_flags &
 423                                                      (PKT_TX_TUNNEL_GRE |
 424                                                       PKT_TX_TUNNEL_VXLAN);
 425
 426                         if (is_tunneled && txq->tunnel_en) {
 427                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 428                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 429                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 430                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 431                         } else {
 432                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 433                                            MLX5_ETH_WQE_L4_CSUM;
 434                         }
 435                 }
 436                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 437                 /* Replace the Ethernet type by the VLAN if necessary. */
 438                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 439                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 440                                                          buf->vlan_tci);
 441                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 442
 443                         addr += 2;
 444                         length -= 2;
 445                         /* Copy Destination and source mac address. */
 446                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 447                         /* Copy VLAN. */
 448                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 449                         /* Copy missing two bytes to end the DSeg. */
 450                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 451                                ((uint8_t *)addr) + len, 2);
 452                         addr += len + 2;
 453                         length -= (len + 2);
 454                 } else {
 455                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 456                                MLX5_WQE_DWORD_SIZE);
 457                         length -= pkt_inline_sz;
 458                         addr += pkt_inline_sz;
 459                 }
 460                 raw += MLX5_WQE_DWORD_SIZE;
 461                 if (txq->tso_en) {
 462                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 463                         if (tso) {
 464                                 uintptr_t end = (uintptr_t)
 465                                                 (((uintptr_t)txq->wqes) +
 466                                                 (1 << txq->wqe_n) *
 467                                                 MLX5_WQE_SIZE);
 468                                 unsigned int copy_b;
 469                                 uint8_t vlan_sz = (buf->ol_flags &
 470                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 471                                 const uint64_t is_tunneled =
 472                                                         buf->ol_flags &
 473                                                         (PKT_TX_TUNNEL_GRE |
 474                                                          PKT_TX_TUNNEL_VXLAN);
 475
 476                                 tso_header_sz = buf->l2_len + vlan_sz +
 477                                                 buf->l3_len + buf->l4_len;
 478                                 tso_segsz = buf->tso_segsz;
 479                                 if (unlikely(tso_segsz == 0)) {
 480                                         txq->stats.oerrors++;
 481                                         break;
 482                                 }
 483                                 if (is_tunneled && txq->tunnel_en) {
 484                                         tso_header_sz += buf->outer_l2_len +
 485                                                          buf->outer_l3_len;
 486                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 487                                 } else {
 488                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 489                                 }
 490                                 if (unlikely(tso_header_sz >
 491                                              MLX5_MAX_TSO_HEADER)) {
 492                                         txq->stats.oerrors++;
 493                                         break;
 494                                 }
 495                                 copy_b = tso_header_sz - pkt_inline_sz;
 496                                 /* First seg must contain all headers. */
 497                                 assert(copy_b <= length);
 498                                 if (copy_b &&
 499                                    ((end - (uintptr_t)raw) > copy_b)) {
 500                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 501                                                       1 + 3) / 4;
 502
 503                                         if (unlikely(max_wqe < n))
 504                                                 break;
 505                                         max_wqe -= n;
 506                                         rte_memcpy((void *)raw,
 507                                                    (void *)addr, copy_b);
 508                                         addr += copy_b;
 509                                         length -= copy_b;
 510                                         /* Include padding for TSO header. */
 511                                         copy_b = MLX5_WQE_DS(copy_b) *
 512                                                  MLX5_WQE_DWORD_SIZE;
 513                                         pkt_inline_sz += copy_b;
 514                                         raw += copy_b;
 515                                 } else {
 516                                         /* NOP WQE. */
 517                                         wqe->ctrl = (rte_v128u32_t){
 518                                                      rte_cpu_to_be_32(
 519                                                         txq->wqe_ci << 8),
 520                                                      rte_cpu_to_be_32(
 521                                                         txq->qp_num_8s | 1),
 522                                                      0,
 523                                                      0,
 524                                         };
 525                                         ds = 1;
 526 #ifdef MLX5_PMD_SOFT_COUNTERS
 527                                         total_length = 0;
 528 #endif
 529                                         k++;
 530                                         goto next_wqe;
 531                                 }
 532                         }
 533                 }
 534                 /* Inline if enough room. */
 535                 if (inline_en || tso) {
 536                         uint32_t inl;
 537                         uintptr_t end = (uintptr_t)
 538                                 (((uintptr_t)txq->wqes) +
 539                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 540                         unsigned int inline_room = max_inline *
 541                                                    RTE_CACHE_LINE_SIZE -
 542                                                    (pkt_inline_sz - 2) -
 543                                                    !!tso * sizeof(inl);
 544                         uintptr_t addr_end = (addr + inline_room) &
 545                                              ~(RTE_CACHE_LINE_SIZE - 1);
 546                         unsigned int copy_b = (addr_end > addr) ?
 547                                 RTE_MIN((addr_end - addr), length) :
 548                                 0;
 549
 550                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 551                                 /*
 552                                  * One Dseg remains in the current WQE.  To
 553                                  * keep the computation positive, it is
 554                                  * removed after the bytes to Dseg conversion.
 555                                  */
 556                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 557
 558                                 if (unlikely(max_wqe < n))
 559                                         break;
 560                                 max_wqe -= n;
 561                                 if (tso) {
 562                                         inl = rte_cpu_to_be_32(copy_b |
 563                                                                MLX5_INLINE_SEG);
 564                                         rte_memcpy((void *)raw,
 565                                                    (void *)&inl, sizeof(inl));
 566                                         raw += sizeof(inl);
 567                                         pkt_inline_sz += sizeof(inl);
 568                                 }
 569                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 570                                 addr += copy_b;
 571                                 length -= copy_b;
 572                                 pkt_inline_sz += copy_b;
 573                         }
 574                         /*
 575                          * 2 DWORDs consumed by the WQE header + ETH segment +
 576                          * the size of the inline part of the packet.
 577                          */
 578                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 579                         if (length > 0) {
 580                                 if (ds % (MLX5_WQE_SIZE /
 581                                           MLX5_WQE_DWORD_SIZE) == 0) {
 582                                         if (unlikely(--max_wqe == 0))
 583                                                 break;
 584                                         dseg = (volatile rte_v128u32_t *)
 585                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 586                                                            ds / 4);
 587                                 } else {
 588                                         dseg = (volatile rte_v128u32_t *)
 589                                                 ((uintptr_t)wqe +
 590                                                  (ds * MLX5_WQE_DWORD_SIZE));
 591                                 }
 592                                 goto use_dseg;
 593                         } else if (!segs_n) {
 594                                 goto next_pkt;
 595                         } else {
 596                                 /* dseg will be advance as part of next_seg */
 597                                 dseg = (volatile rte_v128u32_t *)
 598                                         ((uintptr_t)wqe +
 599                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 600                                 goto next_seg;
 601                         }
 602                 } else {
 603                         /*
 604                          * No inline has been done in the packet, only the
 605                          * Ethernet Header as been stored.
 606                          */
 607                         dseg = (volatile rte_v128u32_t *)
 608                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 609                         ds = 3;
 610 use_dseg:
 611                         /* Add the remaining packet as a simple ds. */
 612                         addr = rte_cpu_to_be_64(addr);
 613                         *dseg = (rte_v128u32_t){
 614                                 rte_cpu_to_be_32(length),
 615                                 mlx5_tx_mb2mr(txq, buf),
 616                                 addr,
 617                                 addr >> 32,
 618                         };
 619                         ++ds;
 620                         if (!segs_n)
 621                                 goto next_pkt;
 622                 }
 623 next_seg:
 624                 assert(buf);
 625                 assert(ds);
 626                 assert(wqe);
 627                 /*
 628                  * Spill on next WQE when the current one does not have
 629                  * enough room left. Size of WQE must a be a multiple
 630                  * of data segment size.
 631                  */
 632                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 633                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 634                         if (unlikely(--max_wqe == 0))
 635                                 break;
 636                         dseg = (volatile rte_v128u32_t *)
 637                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 638                         rte_prefetch0(tx_mlx5_wqe(txq,
 639                                                   txq->wqe_ci + ds / 4 + 1));
 640                 } else {
 641                         ++dseg;
 642                 }
 643                 ++ds;
 644                 buf = buf->next;
 645                 assert(buf);
 646                 length = DATA_LEN(buf);
 647 #ifdef MLX5_PMD_SOFT_COUNTERS
 648                 total_length += length;
 649 #endif
 650                 /* Store segment information. */
 651                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 652                 *dseg = (rte_v128u32_t){
 653                         rte_cpu_to_be_32(length),
 654                         mlx5_tx_mb2mr(txq, buf),
 655                         addr,
 656                         addr >> 32,
 657                 };
 658                 (*txq->elts)[++elts_head & elts_m] = buf;
 659                 ++sg;
 660                 /* Advance counter only if all segs are successfully posted. */
 661                 if (sg < segs_n)
 662                         goto next_seg;
 663                 else
 664                         j += sg;
 665 next_pkt:
 666                 if (ds > MLX5_DSEG_MAX) {
 667                         txq->stats.oerrors++;
 668                         break;
 669                 }
 670                 ++elts_head;
 671                 ++pkts;
 672                 ++i;
 673                 /* Initialize known and common part of the WQE structure. */
 674                 if (tso) {
 675                         wqe->ctrl = (rte_v128u32_t){
 676                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 677                                                  MLX5_OPCODE_TSO),
 678                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 679                                 0,
 680                                 0,
 681                         };
 682                         wqe->eseg = (rte_v128u32_t){
 683                                 0,
 684                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 685                                 0,
 686                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 687                         };
 688                 } else {
 689                         wqe->ctrl = (rte_v128u32_t){
 690                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 691                                                  MLX5_OPCODE_SEND),
 692                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 693                                 0,
 694                                 0,
 695                         };
 696                         wqe->eseg = (rte_v128u32_t){
 697                                 0,
 698                                 cs_flags,
 699                                 0,
 700                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 701                         };
 702                 }
 703 next_wqe:
 704                 txq->wqe_ci += (ds + 3) / 4;
 705                 /* Save the last successful WQE for completion request */
 706                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 707 #ifdef MLX5_PMD_SOFT_COUNTERS
 708                 /* Increment sent bytes counter. */
 709                 txq->stats.obytes += total_length;
 710 #endif
 711         } while (i < pkts_n);
 712         /* Take a shortcut if nothing must be sent. */
 713         if (unlikely((i + k) == 0))
 714                 return 0;
 715         txq->elts_head += (i + j);
 716         /* Check whether completion threshold has been reached. */
 717         comp = txq->elts_comp + i + j + k;
 718         if (comp >= MLX5_TX_COMP_THRESH) {
 719                 /* Request completion on last WQE. */
 720                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 721                 /* Save elts_head in unused "immediate" field of WQE. */
 722                 last_wqe->ctrl3 = txq->elts_head;
 723                 txq->elts_comp = 0;
 724         } else {
 725                 txq->elts_comp = comp;
 726         }
 727 #ifdef MLX5_PMD_SOFT_COUNTERS
 728         /* Increment sent packets counter. */
 729         txq->stats.opackets += i;
 730 #endif
 731         /* Ring QP doorbell. */
 732         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 733         return i;
 734 }
 735
 736 /**
 737  * Open a MPW session.
 738  *
 739  * @param txq
 740  *   Pointer to TX queue structure.
 741  * @param mpw
 742  *   Pointer to MPW session structure.
 743  * @param length
 744  *   Packet length.
 745  */
 746 static inline void
 747 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 748 {
 749         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 750         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 751                 (volatile struct mlx5_wqe_data_seg (*)[])
 752                 tx_mlx5_wqe(txq, idx + 1);
 753
 754         mpw->state = MLX5_MPW_STATE_OPENED;
 755         mpw->pkts_n = 0;
 756         mpw->len = length;
 757         mpw->total_len = 0;
 758         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 759         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 760         mpw->wqe->eseg.inline_hdr_sz = 0;
 761         mpw->wqe->eseg.rsvd0 = 0;
 762         mpw->wqe->eseg.rsvd1 = 0;
 763         mpw->wqe->eseg.rsvd2 = 0;
 764         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 765                                              (txq->wqe_ci << 8) |
 766                                              MLX5_OPCODE_TSO);
 767         mpw->wqe->ctrl[2] = 0;
 768         mpw->wqe->ctrl[3] = 0;
 769         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 770                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 771         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 772                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 773         mpw->data.dseg[2] = &(*dseg)[0];
 774         mpw->data.dseg[3] = &(*dseg)[1];
 775         mpw->data.dseg[4] = &(*dseg)[2];
 776 }
 777
 778 /**
 779  * Close a MPW session.
 780  *
 781  * @param txq
 782  *   Pointer to TX queue structure.
 783  * @param mpw
 784  *   Pointer to MPW session structure.
 785  */
 786 static inline void
 787 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 788 {
 789         unsigned int num = mpw->pkts_n;
 790
 791         /*
 792          * Store size in multiple of 16 bytes. Control and Ethernet segments
 793          * count as 2.
 794          */
 795         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 796         mpw->state = MLX5_MPW_STATE_CLOSED;
 797         if (num < 3)
 798                 ++txq->wqe_ci;
 799         else
 800                 txq->wqe_ci += 2;
 801         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 802         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 803 }
 804
 805 /**
 806  * DPDK callback for TX with MPW support.
 807  *
 808  * @param dpdk_txq
 809  *   Generic pointer to TX queue structure.
 810  * @param[in] pkts
 811  *   Packets to transmit.
 812  * @param pkts_n
 813  *   Number of packets in array.
 814  *
 815  * @return
 816  *   Number of packets successfully transmitted (<= pkts_n).
 817  */
 818 uint16_t
 819 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 820 {
 821         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 822         uint16_t elts_head = txq->elts_head;
 823         const uint16_t elts_n = 1 << txq->elts_n;
 824         const uint16_t elts_m = elts_n - 1;
 825         unsigned int i = 0;
 826         unsigned int j = 0;
 827         uint16_t max_elts;
 828         uint16_t max_wqe;
 829         unsigned int comp;
 830         struct mlx5_mpw mpw = {
 831                 .state = MLX5_MPW_STATE_CLOSED,
 832         };
 833
 834         if (unlikely(!pkts_n))
 835                 return 0;
 836         /* Prefetch first packet cacheline. */
 837         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 838         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 839         /* Start processing. */
 840         mlx5_tx_complete(txq);
 841         max_elts = (elts_n - (elts_head - txq->elts_tail));
 842         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 843         if (unlikely(!max_wqe))
 844                 return 0;
 845         do {
 846                 struct rte_mbuf *buf = *(pkts++);
 847                 uint32_t length;
 848                 unsigned int segs_n = buf->nb_segs;
 849                 uint32_t cs_flags = 0;
 850
 851                 /*
 852                  * Make sure there is enough room to store this packet and
 853                  * that one ring entry remains unused.
 854                  */
 855                 assert(segs_n);
 856                 if (max_elts < segs_n)
 857                         break;
 858                 /* Do not bother with large packets MPW cannot handle. */
 859                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 860                         txq->stats.oerrors++;
 861                         break;
 862                 }
 863                 max_elts -= segs_n;
 864                 --pkts_n;
 865                 /* Should we enable HW CKSUM offload */
 866                 if (buf->ol_flags &
 867                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 868                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 869                 /* Retrieve packet information. */
 870                 length = PKT_LEN(buf);
 871                 assert(length);
 872                 /* Start new session if packet differs. */
 873                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 874                     ((mpw.len != length) ||
 875                      (segs_n != 1) ||
 876                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 877                         mlx5_mpw_close(txq, &mpw);
 878                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 879                         /*
 880                          * Multi-Packet WQE consumes at most two WQE.
 881                          * mlx5_mpw_new() expects to be able to use such
 882                          * resources.
 883                          */
 884                         if (unlikely(max_wqe < 2))
 885                                 break;
 886                         max_wqe -= 2;
 887                         mlx5_mpw_new(txq, &mpw, length);
 888                         mpw.wqe->eseg.cs_flags = cs_flags;
 889                 }
 890                 /* Multi-segment packets must be alone in their MPW. */
 891                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 892 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 893                 length = 0;
 894 #endif
 895                 do {
 896                         volatile struct mlx5_wqe_data_seg *dseg;
 897                         uintptr_t addr;
 898
 899                         assert(buf);
 900                         (*txq->elts)[elts_head++ & elts_m] = buf;
 901                         dseg = mpw.data.dseg[mpw.pkts_n];
 902                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 903                         *dseg = (struct mlx5_wqe_data_seg){
 904                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 905                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 906                                 .addr = rte_cpu_to_be_64(addr),
 907                         };
 908 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 909                         length += DATA_LEN(buf);
 910 #endif
 911                         buf = buf->next;
 912                         ++mpw.pkts_n;
 913                         ++j;
 914                 } while (--segs_n);
 915                 assert(length == mpw.len);
 916                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 917                         mlx5_mpw_close(txq, &mpw);
 918 #ifdef MLX5_PMD_SOFT_COUNTERS
 919                 /* Increment sent bytes counter. */
 920                 txq->stats.obytes += length;
 921 #endif
 922                 ++i;
 923         } while (pkts_n);
 924         /* Take a shortcut if nothing must be sent. */
 925         if (unlikely(i == 0))
 926                 return 0;
 927         /* Check whether completion threshold has been reached. */
 928         /* "j" includes both packets and segments. */
 929         comp = txq->elts_comp + j;
 930         if (comp >= MLX5_TX_COMP_THRESH) {
 931                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 932
 933                 /* Request completion on last WQE. */
 934                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 935                 /* Save elts_head in unused "immediate" field of WQE. */
 936                 wqe->ctrl[3] = elts_head;
 937                 txq->elts_comp = 0;
 938         } else {
 939                 txq->elts_comp = comp;
 940         }
 941 #ifdef MLX5_PMD_SOFT_COUNTERS
 942         /* Increment sent packets counter. */
 943         txq->stats.opackets += i;
 944 #endif
 945         /* Ring QP doorbell. */
 946         if (mpw.state == MLX5_MPW_STATE_OPENED)
 947                 mlx5_mpw_close(txq, &mpw);
 948         mlx5_tx_dbrec(txq, mpw.wqe);
 949         txq->elts_head = elts_head;
 950         return i;
 951 }
 952
 953 /**
 954  * Open a MPW inline session.
 955  *
 956  * @param txq
 957  *   Pointer to TX queue structure.
 958  * @param mpw
 959  *   Pointer to MPW session structure.
 960  * @param length
 961  *   Packet length.
 962  */
 963 static inline void
 964 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 965                     uint32_t length)
 966 {
 967         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 968         struct mlx5_wqe_inl_small *inl;
 969
 970         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 971         mpw->pkts_n = 0;
 972         mpw->len = length;
 973         mpw->total_len = 0;
 974         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 975         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 976                                              (txq->wqe_ci << 8) |
 977                                              MLX5_OPCODE_TSO);
 978         mpw->wqe->ctrl[2] = 0;
 979         mpw->wqe->ctrl[3] = 0;
 980         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 981         mpw->wqe->eseg.inline_hdr_sz = 0;
 982         mpw->wqe->eseg.cs_flags = 0;
 983         mpw->wqe->eseg.rsvd0 = 0;
 984         mpw->wqe->eseg.rsvd1 = 0;
 985         mpw->wqe->eseg.rsvd2 = 0;
 986         inl = (struct mlx5_wqe_inl_small *)
 987                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 988         mpw->data.raw = (uint8_t *)&inl->raw;
 989 }
 990
 991 /**
 992  * Close a MPW inline session.
 993  *
 994  * @param txq
 995  *   Pointer to TX queue structure.
 996  * @param mpw
 997  *   Pointer to MPW session structure.
 998  */
 999 static inline void
1000 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1001 {
1002         unsigned int size;
1003         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1004                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1005
1006         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1007         /*
1008          * Store size in multiple of 16 bytes. Control and Ethernet segments
1009          * count as 2.
1010          */
1011         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1012                                              MLX5_WQE_DS(size));
1013         mpw->state = MLX5_MPW_STATE_CLOSED;
1014         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1015         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1016 }
1017
1018 /**
1019  * DPDK callback for TX with MPW inline support.
1020  *
1021  * @param dpdk_txq
1022  *   Generic pointer to TX queue structure.
1023  * @param[in] pkts
1024  *   Packets to transmit.
1025  * @param pkts_n
1026  *   Number of packets in array.
1027  *
1028  * @return
1029  *   Number of packets successfully transmitted (<= pkts_n).
1030  */
1031 uint16_t
1032 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1033                          uint16_t pkts_n)
1034 {
1035         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1036         uint16_t elts_head = txq->elts_head;
1037         const uint16_t elts_n = 1 << txq->elts_n;
1038         const uint16_t elts_m = elts_n - 1;
1039         unsigned int i = 0;
1040         unsigned int j = 0;
1041         uint16_t max_elts;
1042         uint16_t max_wqe;
1043         unsigned int comp;
1044         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1045         struct mlx5_mpw mpw = {
1046                 .state = MLX5_MPW_STATE_CLOSED,
1047         };
1048         /*
1049          * Compute the maximum number of WQE which can be consumed by inline
1050          * code.
1051          * - 2 DSEG for:
1052          *   - 1 control segment,
1053          *   - 1 Ethernet segment,
1054          * - N Dseg from the inline request.
1055          */
1056         const unsigned int wqe_inl_n =
1057                 ((2 * MLX5_WQE_DWORD_SIZE +
1058                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1059                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1060
1061         if (unlikely(!pkts_n))
1062                 return 0;
1063         /* Prefetch first packet cacheline. */
1064         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1065         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1066         /* Start processing. */
1067         mlx5_tx_complete(txq);
1068         max_elts = (elts_n - (elts_head - txq->elts_tail));
1069         do {
1070                 struct rte_mbuf *buf = *(pkts++);
1071                 uintptr_t addr;
1072                 uint32_t length;
1073                 unsigned int segs_n = buf->nb_segs;
1074                 uint32_t cs_flags = 0;
1075
1076                 /*
1077                  * Make sure there is enough room to store this packet and
1078                  * that one ring entry remains unused.
1079                  */
1080                 assert(segs_n);
1081                 if (max_elts < segs_n)
1082                         break;
1083                 /* Do not bother with large packets MPW cannot handle. */
1084                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1085                         txq->stats.oerrors++;
1086                         break;
1087                 }
1088                 max_elts -= segs_n;
1089                 --pkts_n;
1090                 /*
1091                  * Compute max_wqe in case less WQE were consumed in previous
1092                  * iteration.
1093                  */
1094                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1095                 /* Should we enable HW CKSUM offload */
1096                 if (buf->ol_flags &
1097                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1098                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1099                 /* Retrieve packet information. */
1100                 length = PKT_LEN(buf);
1101                 /* Start new session if packet differs. */
1102                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1103                         if ((mpw.len != length) ||
1104                             (segs_n != 1) ||
1105                             (mpw.wqe->eseg.cs_flags != cs_flags))
1106                                 mlx5_mpw_close(txq, &mpw);
1107                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1108                         if ((mpw.len != length) ||
1109                             (segs_n != 1) ||
1110                             (length > inline_room) ||
1111                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1112                                 mlx5_mpw_inline_close(txq, &mpw);
1113                                 inline_room =
1114                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1115                         }
1116                 }
1117                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1118                         if ((segs_n != 1) ||
1119                             (length > inline_room)) {
1120                                 /*
1121                                  * Multi-Packet WQE consumes at most two WQE.
1122                                  * mlx5_mpw_new() expects to be able to use
1123                                  * such resources.
1124                                  */
1125                                 if (unlikely(max_wqe < 2))
1126                                         break;
1127                                 max_wqe -= 2;
1128                                 mlx5_mpw_new(txq, &mpw, length);
1129                                 mpw.wqe->eseg.cs_flags = cs_flags;
1130                         } else {
1131                                 if (unlikely(max_wqe < wqe_inl_n))
1132                                         break;
1133                                 max_wqe -= wqe_inl_n;
1134                                 mlx5_mpw_inline_new(txq, &mpw, length);
1135                                 mpw.wqe->eseg.cs_flags = cs_flags;
1136                         }
1137                 }
1138                 /* Multi-segment packets must be alone in their MPW. */
1139                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1140                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1141                         assert(inline_room ==
1142                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1143 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1144                         length = 0;
1145 #endif
1146                         do {
1147                                 volatile struct mlx5_wqe_data_seg *dseg;
1148
1149                                 assert(buf);
1150                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1151                                 dseg = mpw.data.dseg[mpw.pkts_n];
1152                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1153                                 *dseg = (struct mlx5_wqe_data_seg){
1154                                         .byte_count =
1155                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1156                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1157                                         .addr = rte_cpu_to_be_64(addr),
1158                                 };
1159 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1160                                 length += DATA_LEN(buf);
1161 #endif
1162                                 buf = buf->next;
1163                                 ++mpw.pkts_n;
1164                                 ++j;
1165                         } while (--segs_n);
1166                         assert(length == mpw.len);
1167                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1168                                 mlx5_mpw_close(txq, &mpw);
1169                 } else {
1170                         unsigned int max;
1171
1172                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1173                         assert(length <= inline_room);
1174                         assert(length == DATA_LEN(buf));
1175                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1176                         (*txq->elts)[elts_head++ & elts_m] = buf;
1177                         /* Maximum number of bytes before wrapping. */
1178                         max = ((((uintptr_t)(txq->wqes)) +
1179                                 (1 << txq->wqe_n) *
1180                                 MLX5_WQE_SIZE) -
1181                                (uintptr_t)mpw.data.raw);
1182                         if (length > max) {
1183                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1184                                            (void *)addr,
1185                                            max);
1186                                 mpw.data.raw = (volatile void *)txq->wqes;
1187                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1188                                            (void *)(addr + max),
1189                                            length - max);
1190                                 mpw.data.raw += length - max;
1191                         } else {
1192                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1193                                            (void *)addr,
1194                                            length);
1195
1196                                 if (length == max)
1197                                         mpw.data.raw =
1198                                                 (volatile void *)txq->wqes;
1199                                 else
1200                                         mpw.data.raw += length;
1201                         }
1202                         ++mpw.pkts_n;
1203                         mpw.total_len += length;
1204                         ++j;
1205                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1206                                 mlx5_mpw_inline_close(txq, &mpw);
1207                                 inline_room =
1208                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1209                         } else {
1210                                 inline_room -= length;
1211                         }
1212                 }
1213 #ifdef MLX5_PMD_SOFT_COUNTERS
1214                 /* Increment sent bytes counter. */
1215                 txq->stats.obytes += length;
1216 #endif
1217                 ++i;
1218         } while (pkts_n);
1219         /* Take a shortcut if nothing must be sent. */
1220         if (unlikely(i == 0))
1221                 return 0;
1222         /* Check whether completion threshold has been reached. */
1223         /* "j" includes both packets and segments. */
1224         comp = txq->elts_comp + j;
1225         if (comp >= MLX5_TX_COMP_THRESH) {
1226                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1227
1228                 /* Request completion on last WQE. */
1229                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1230                 /* Save elts_head in unused "immediate" field of WQE. */
1231                 wqe->ctrl[3] = elts_head;
1232                 txq->elts_comp = 0;
1233         } else {
1234                 txq->elts_comp = comp;
1235         }
1236 #ifdef MLX5_PMD_SOFT_COUNTERS
1237         /* Increment sent packets counter. */
1238         txq->stats.opackets += i;
1239 #endif
1240         /* Ring QP doorbell. */
1241         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1242                 mlx5_mpw_inline_close(txq, &mpw);
1243         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1244                 mlx5_mpw_close(txq, &mpw);
1245         mlx5_tx_dbrec(txq, mpw.wqe);
1246         txq->elts_head = elts_head;
1247         return i;
1248 }
1249
1250 /**
1251  * Open an Enhanced MPW session.
1252  *
1253  * @param txq
1254  *   Pointer to TX queue structure.
1255  * @param mpw
1256  *   Pointer to MPW session structure.
1257  * @param length
1258  *   Packet length.
1259  */
1260 static inline void
1261 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1262 {
1263         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1264
1265         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1266         mpw->pkts_n = 0;
1267         mpw->total_len = sizeof(struct mlx5_wqe);
1268         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1269         mpw->wqe->ctrl[0] =
1270                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1271                                  (txq->wqe_ci << 8) |
1272                                  MLX5_OPCODE_ENHANCED_MPSW);
1273         mpw->wqe->ctrl[2] = 0;
1274         mpw->wqe->ctrl[3] = 0;
1275         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1276         if (unlikely(padding)) {
1277                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1278
1279                 /* Pad the first 2 DWORDs with zero-length inline header. */
1280                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1281                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1282                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1283                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1284                 /* Start from the next WQEBB. */
1285                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1286         } else {
1287                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1288         }
1289 }
1290
1291 /**
1292  * Close an Enhanced MPW session.
1293  *
1294  * @param txq
1295  *   Pointer to TX queue structure.
1296  * @param mpw
1297  *   Pointer to MPW session structure.
1298  *
1299  * @return
1300  *   Number of consumed WQEs.
1301  */
1302 static inline uint16_t
1303 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1304 {
1305         uint16_t ret;
1306
1307         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1308          * count as 2.
1309          */
1310         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1311                                              MLX5_WQE_DS(mpw->total_len));
1312         mpw->state = MLX5_MPW_STATE_CLOSED;
1313         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1314         txq->wqe_ci += ret;
1315         return ret;
1316 }
1317
1318 /**
1319  * DPDK callback for TX with Enhanced MPW support.
1320  *
1321  * @param dpdk_txq
1322  *   Generic pointer to TX queue structure.
1323  * @param[in] pkts
1324  *   Packets to transmit.
1325  * @param pkts_n
1326  *   Number of packets in array.
1327  *
1328  * @return
1329  *   Number of packets successfully transmitted (<= pkts_n).
1330  */
1331 uint16_t
1332 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1333 {
1334         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1335         uint16_t elts_head = txq->elts_head;
1336         const uint16_t elts_n = 1 << txq->elts_n;
1337         const uint16_t elts_m = elts_n - 1;
1338         unsigned int i = 0;
1339         unsigned int j = 0;
1340         uint16_t max_elts;
1341         uint16_t max_wqe;
1342         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1343         unsigned int mpw_room = 0;
1344         unsigned int inl_pad = 0;
1345         uint32_t inl_hdr;
1346         struct mlx5_mpw mpw = {
1347                 .state = MLX5_MPW_STATE_CLOSED,
1348         };
1349
1350         if (unlikely(!pkts_n))
1351                 return 0;
1352         /* Start processing. */
1353         mlx5_tx_complete(txq);
1354         max_elts = (elts_n - (elts_head - txq->elts_tail));
1355         /* A CQE slot must always be available. */
1356         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1357         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1358         if (unlikely(!max_wqe))
1359                 return 0;
1360         do {
1361                 struct rte_mbuf *buf = *(pkts++);
1362                 uintptr_t addr;
1363                 unsigned int n;
1364                 unsigned int do_inline = 0; /* Whether inline is possible. */
1365                 uint32_t length;
1366                 unsigned int segs_n = buf->nb_segs;
1367                 uint32_t cs_flags = 0;
1368
1369                 /*
1370                  * Make sure there is enough room to store this packet and
1371                  * that one ring entry remains unused.
1372                  */
1373                 assert(segs_n);
1374                 if (max_elts - j < segs_n)
1375                         break;
1376                 /* Do not bother with large packets MPW cannot handle. */
1377                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1378                         txq->stats.oerrors++;
1379                         break;
1380                 }
1381                 /* Should we enable HW CKSUM offload. */
1382                 if (buf->ol_flags &
1383                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1384                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1385                 /* Retrieve packet information. */
1386                 length = PKT_LEN(buf);
1387                 /* Start new session if:
1388                  * - multi-segment packet
1389                  * - no space left even for a dseg
1390                  * - next packet can be inlined with a new WQE
1391                  * - cs_flag differs
1392                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1393                  * segmented packet.
1394                  */
1395                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1396                         if ((segs_n != 1) ||
1397                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1398                               mpw_room) ||
1399                             (length <= txq->inline_max_packet_sz &&
1400                              inl_pad + sizeof(inl_hdr) + length >
1401                               mpw_room) ||
1402                             (mpw.wqe->eseg.cs_flags != cs_flags))
1403                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1404                 }
1405                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1406                         if (unlikely(segs_n != 1)) {
1407                                 /* Fall back to legacy MPW.
1408                                  * A MPW session consumes 2 WQEs at most to
1409                                  * include MLX5_MPW_DSEG_MAX pointers.
1410                                  */
1411                                 if (unlikely(max_wqe < 2))
1412                                         break;
1413                                 mlx5_mpw_new(txq, &mpw, length);
1414                         } else {
1415                                 /* In Enhanced MPW, inline as much as the budget
1416                                  * is allowed. The remaining space is to be
1417                                  * filled with dsegs. If the title WQEBB isn't
1418                                  * padded, it will have 2 dsegs there.
1419                                  */
1420                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1421                                             (max_inline ? max_inline :
1422                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1423                                             MLX5_WQE_SIZE);
1424                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1425                                               mpw_room))
1426                                         break;
1427                                 /* Don't pad the title WQEBB to not waste WQ. */
1428                                 mlx5_empw_new(txq, &mpw, 0);
1429                                 mpw_room -= mpw.total_len;
1430                                 inl_pad = 0;
1431                                 do_inline =
1432                                         length <= txq->inline_max_packet_sz &&
1433                                         sizeof(inl_hdr) + length <= mpw_room &&
1434                                         !txq->mpw_hdr_dseg;
1435                         }
1436                         mpw.wqe->eseg.cs_flags = cs_flags;
1437                 } else {
1438                         /* Evaluate whether the next packet can be inlined.
1439                          * Inlininig is possible when:
1440                          * - length is less than configured value
1441                          * - length fits for remaining space
1442                          * - not required to fill the title WQEBB with dsegs
1443                          */
1444                         do_inline =
1445                                 length <= txq->inline_max_packet_sz &&
1446                                 inl_pad + sizeof(inl_hdr) + length <=
1447                                  mpw_room &&
1448                                 (!txq->mpw_hdr_dseg ||
1449                                  mpw.total_len >= MLX5_WQE_SIZE);
1450                 }
1451                 /* Multi-segment packets must be alone in their MPW. */
1452                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1453                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1454 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1455                         length = 0;
1456 #endif
1457                         do {
1458                                 volatile struct mlx5_wqe_data_seg *dseg;
1459
1460                                 assert(buf);
1461                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1462                                 dseg = mpw.data.dseg[mpw.pkts_n];
1463                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1464                                 *dseg = (struct mlx5_wqe_data_seg){
1465                                         .byte_count = rte_cpu_to_be_32(
1466                                                                 DATA_LEN(buf)),
1467                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1468                                         .addr = rte_cpu_to_be_64(addr),
1469                                 };
1470 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1471                                 length += DATA_LEN(buf);
1472 #endif
1473                                 buf = buf->next;
1474                                 ++j;
1475                                 ++mpw.pkts_n;
1476                         } while (--segs_n);
1477                         /* A multi-segmented packet takes one MPW session.
1478                          * TODO: Pack more multi-segmented packets if possible.
1479                          */
1480                         mlx5_mpw_close(txq, &mpw);
1481                         if (mpw.pkts_n < 3)
1482                                 max_wqe--;
1483                         else
1484                                 max_wqe -= 2;
1485                 } else if (do_inline) {
1486                         /* Inline packet into WQE. */
1487                         unsigned int max;
1488
1489                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1490                         assert(length == DATA_LEN(buf));
1491                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1492                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1493                         mpw.data.raw = (volatile void *)
1494                                 ((uintptr_t)mpw.data.raw + inl_pad);
1495                         max = tx_mlx5_wq_tailroom(txq,
1496                                         (void *)(uintptr_t)mpw.data.raw);
1497                         /* Copy inline header. */
1498                         mpw.data.raw = (volatile void *)
1499                                 mlx5_copy_to_wq(
1500                                           (void *)(uintptr_t)mpw.data.raw,
1501                                           &inl_hdr,
1502                                           sizeof(inl_hdr),
1503                                           (void *)(uintptr_t)txq->wqes,
1504                                           max);
1505                         max = tx_mlx5_wq_tailroom(txq,
1506                                         (void *)(uintptr_t)mpw.data.raw);
1507                         /* Copy packet data. */
1508                         mpw.data.raw = (volatile void *)
1509                                 mlx5_copy_to_wq(
1510                                           (void *)(uintptr_t)mpw.data.raw,
1511                                           (void *)addr,
1512                                           length,
1513                                           (void *)(uintptr_t)txq->wqes,
1514                                           max);
1515                         ++mpw.pkts_n;
1516                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1517                         /* No need to get completion as the entire packet is
1518                          * copied to WQ. Free the buf right away.
1519                          */
1520                         rte_pktmbuf_free_seg(buf);
1521                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1522                         /* Add pad in the next packet if any. */
1523                         inl_pad = (((uintptr_t)mpw.data.raw +
1524                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1525                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1526                                   (uintptr_t)mpw.data.raw;
1527                 } else {
1528                         /* No inline. Load a dseg of packet pointer. */
1529                         volatile rte_v128u32_t *dseg;
1530
1531                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1532                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1533                         assert(length == DATA_LEN(buf));
1534                         if (!tx_mlx5_wq_tailroom(txq,
1535                                         (void *)((uintptr_t)mpw.data.raw
1536                                                 + inl_pad)))
1537                                 dseg = (volatile void *)txq->wqes;
1538                         else
1539                                 dseg = (volatile void *)
1540                                         ((uintptr_t)mpw.data.raw +
1541                                          inl_pad);
1542                         (*txq->elts)[elts_head++ & elts_m] = buf;
1543                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1544                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1545                                 rte_prefetch2((void *)(addr +
1546                                                 n * RTE_CACHE_LINE_SIZE));
1547                         addr = rte_cpu_to_be_64(addr);
1548                         *dseg = (rte_v128u32_t) {
1549                                 rte_cpu_to_be_32(length),
1550                                 mlx5_tx_mb2mr(txq, buf),
1551                                 addr,
1552                                 addr >> 32,
1553                         };
1554                         mpw.data.raw = (volatile void *)(dseg + 1);
1555                         mpw.total_len += (inl_pad + sizeof(*dseg));
1556                         ++j;
1557                         ++mpw.pkts_n;
1558                         mpw_room -= (inl_pad + sizeof(*dseg));
1559                         inl_pad = 0;
1560                 }
1561 #ifdef MLX5_PMD_SOFT_COUNTERS
1562                 /* Increment sent bytes counter. */
1563                 txq->stats.obytes += length;
1564 #endif
1565                 ++i;
1566         } while (i < pkts_n);
1567         /* Take a shortcut if nothing must be sent. */
1568         if (unlikely(i == 0))
1569                 return 0;
1570         /* Check whether completion threshold has been reached. */
1571         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1572                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1573                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1574                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1575
1576                 /* Request completion on last WQE. */
1577                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1578                 /* Save elts_head in unused "immediate" field of WQE. */
1579                 wqe->ctrl[3] = elts_head;
1580                 txq->elts_comp = 0;
1581                 txq->mpw_comp = txq->wqe_ci;
1582                 txq->cq_pi++;
1583         } else {
1584                 txq->elts_comp += j;
1585         }
1586 #ifdef MLX5_PMD_SOFT_COUNTERS
1587         /* Increment sent packets counter. */
1588         txq->stats.opackets += i;
1589 #endif
1590         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1591                 mlx5_empw_close(txq, &mpw);
1592         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1593                 mlx5_mpw_close(txq, &mpw);
1594         /* Ring QP doorbell. */
1595         mlx5_tx_dbrec(txq, mpw.wqe);
1596         txq->elts_head = elts_head;
1597         return i;
1598 }
1599
1600 /**
1601  * Translate RX completion flags to packet type.
1602  *
1603  * @param[in] cqe
1604  *   Pointer to CQE.
1605  *
1606  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1607  *
1608  * @return
1609  *   Packet type for struct rte_mbuf.
1610  */
1611 static inline uint32_t
1612 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1613 {
1614         uint8_t idx;
1615         uint8_t pinfo = cqe->pkt_info;
1616         uint16_t ptype = cqe->hdr_type_etc;
1617
1618         /*
1619          * The index to the array should have:
1620          * bit[1:0] = l3_hdr_type
1621          * bit[4:2] = l4_hdr_type
1622          * bit[5] = ip_frag
1623          * bit[6] = tunneled
1624          * bit[7] = outer_l3_type
1625          */
1626         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1627         return mlx5_ptype_table[idx];
1628 }
1629
1630 /**
1631  * Get size of the next packet for a given CQE. For compressed CQEs, the
1632  * consumer index is updated only once all packets of the current one have
1633  * been processed.
1634  *
1635  * @param rxq
1636  *   Pointer to RX queue.
1637  * @param cqe
1638  *   CQE to process.
1639  * @param[out] rss_hash
1640  *   Packet RSS Hash result.
1641  *
1642  * @return
1643  *   Packet size in bytes (0 if there is none), -1 in case of completion
1644  *   with error.
1645  */
1646 static inline int
1647 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1648                  uint16_t cqe_cnt, uint32_t *rss_hash)
1649 {
1650         struct rxq_zip *zip = &rxq->zip;
1651         uint16_t cqe_n = cqe_cnt + 1;
1652         int len = 0;
1653         uint16_t idx, end;
1654
1655         /* Process compressed data in the CQE and mini arrays. */
1656         if (zip->ai) {
1657                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1658                         (volatile struct mlx5_mini_cqe8 (*)[8])
1659                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1660
1661                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1662                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1663                 if ((++zip->ai & 7) == 0) {
1664                         /* Invalidate consumed CQEs */
1665                         idx = zip->ca;
1666                         end = zip->na;
1667                         while (idx != end) {
1668                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1669                                         MLX5_CQE_INVALIDATE;
1670                                 ++idx;
1671                         }
1672                         /*
1673                          * Increment consumer index to skip the number of
1674                          * CQEs consumed. Hardware leaves holes in the CQ
1675                          * ring for software use.
1676                          */
1677                         zip->ca = zip->na;
1678                         zip->na += 8;
1679                 }
1680                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1681                         /* Invalidate the rest */
1682                         idx = zip->ca;
1683                         end = zip->cq_ci;
1684
1685                         while (idx != end) {
1686                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1687                                         MLX5_CQE_INVALIDATE;
1688                                 ++idx;
1689                         }
1690                         rxq->cq_ci = zip->cq_ci;
1691                         zip->ai = 0;
1692                 }
1693         /* No compressed data, get next CQE and verify if it is compressed. */
1694         } else {
1695                 int ret;
1696                 int8_t op_own;
1697
1698                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1699                 if (unlikely(ret == 1))
1700                         return 0;
1701                 ++rxq->cq_ci;
1702                 op_own = cqe->op_own;
1703                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1704                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1705                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1706                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1707                                                           cqe_cnt].pkt_info);
1708
1709                         /* Fix endianness. */
1710                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1711                         /*
1712                          * Current mini array position is the one returned by
1713                          * check_cqe64().
1714                          *
1715                          * If completion comprises several mini arrays, as a
1716                          * special case the second one is located 7 CQEs after
1717                          * the initial CQE instead of 8 for subsequent ones.
1718                          */
1719                         zip->ca = rxq->cq_ci;
1720                         zip->na = zip->ca + 7;
1721                         /* Compute the next non compressed CQE. */
1722                         --rxq->cq_ci;
1723                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1724                         /* Get packet size to return. */
1725                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1726                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1727                         zip->ai = 1;
1728                         /* Prefetch all the entries to be invalidated */
1729                         idx = zip->ca;
1730                         end = zip->cq_ci;
1731                         while (idx != end) {
1732                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1733                                 ++idx;
1734                         }
1735                 } else {
1736                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1737                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1738                 }
1739                 /* Error while receiving packet. */
1740                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1741                         return -1;
1742         }
1743         return len;
1744 }
1745
1746 /**
1747  * Translate RX completion flags to offload flags.
1748  *
1749  * @param[in] rxq
1750  *   Pointer to RX queue structure.
1751  * @param[in] cqe
1752  *   Pointer to CQE.
1753  *
1754  * @return
1755  *   Offload flags (ol_flags) for struct rte_mbuf.
1756  */
1757 static inline uint32_t
1758 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1759 {
1760         uint32_t ol_flags = 0;
1761         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1762
1763         ol_flags =
1764                 TRANSPOSE(flags,
1765                           MLX5_CQE_RX_L3_HDR_VALID,
1766                           PKT_RX_IP_CKSUM_GOOD) |
1767                 TRANSPOSE(flags,
1768                           MLX5_CQE_RX_L4_HDR_VALID,
1769                           PKT_RX_L4_CKSUM_GOOD);
1770         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1771                 ol_flags |=
1772                         TRANSPOSE(flags,
1773                                   MLX5_CQE_RX_L3_HDR_VALID,
1774                                   PKT_RX_IP_CKSUM_GOOD) |
1775                         TRANSPOSE(flags,
1776                                   MLX5_CQE_RX_L4_HDR_VALID,
1777                                   PKT_RX_L4_CKSUM_GOOD);
1778         return ol_flags;
1779 }
1780
1781 /**
1782  * DPDK callback for RX.
1783  *
1784  * @param dpdk_rxq
1785  *   Generic pointer to RX queue structure.
1786  * @param[out] pkts
1787  *   Array to store received packets.
1788  * @param pkts_n
1789  *   Maximum number of packets in array.
1790  *
1791  * @return
1792  *   Number of packets successfully received (<= pkts_n).
1793  */
1794 uint16_t
1795 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1796 {
1797         struct mlx5_rxq_data *rxq = dpdk_rxq;
1798         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1799         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1800         const unsigned int sges_n = rxq->sges_n;
1801         struct rte_mbuf *pkt = NULL;
1802         struct rte_mbuf *seg = NULL;
1803         volatile struct mlx5_cqe *cqe =
1804                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1805         unsigned int i = 0;
1806         unsigned int rq_ci = rxq->rq_ci << sges_n;
1807         int len = 0; /* keep its value across iterations. */
1808
1809         while (pkts_n) {
1810                 unsigned int idx = rq_ci & wqe_cnt;
1811                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1812                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1813                 uint32_t rss_hash_res = 0;
1814
1815                 if (pkt)
1816                         NEXT(seg) = rep;
1817                 seg = rep;
1818                 rte_prefetch0(seg);
1819                 rte_prefetch0(cqe);
1820                 rte_prefetch0(wqe);
1821                 rep = rte_mbuf_raw_alloc(rxq->mp);
1822                 if (unlikely(rep == NULL)) {
1823                         ++rxq->stats.rx_nombuf;
1824                         if (!pkt) {
1825                                 /*
1826                                  * no buffers before we even started,
1827                                  * bail out silently.
1828                                  */
1829                                 break;
1830                         }
1831                         while (pkt != seg) {
1832                                 assert(pkt != (*rxq->elts)[idx]);
1833                                 rep = NEXT(pkt);
1834                                 NEXT(pkt) = NULL;
1835                                 NB_SEGS(pkt) = 1;
1836                                 rte_mbuf_raw_free(pkt);
1837                                 pkt = rep;
1838                         }
1839                         break;
1840                 }
1841                 if (!pkt) {
1842                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1843                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1844                                                &rss_hash_res);
1845                         if (!len) {
1846                                 rte_mbuf_raw_free(rep);
1847                                 break;
1848                         }
1849                         if (unlikely(len == -1)) {
1850                                 /* RX error, packet is likely too large. */
1851                                 rte_mbuf_raw_free(rep);
1852                                 ++rxq->stats.idropped;
1853                                 goto skip;
1854                         }
1855                         pkt = seg;
1856                         assert(len >= (rxq->crc_present << 2));
1857                         /* Update packet information. */
1858                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1859                         pkt->ol_flags = 0;
1860                         if (rss_hash_res && rxq->rss_hash) {
1861                                 pkt->hash.rss = rss_hash_res;
1862                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1863                         }
1864                         if (rxq->mark &&
1865                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1866                                 pkt->ol_flags |= PKT_RX_FDIR;
1867                                 if (cqe->sop_drop_qpn !=
1868                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1869                                         uint32_t mark = cqe->sop_drop_qpn;
1870
1871                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1872                                         pkt->hash.fdir.hi =
1873                                                 mlx5_flow_mark_get(mark);
1874                                 }
1875                         }
1876                         if (rxq->csum | rxq->csum_l2tun)
1877                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1878                         if (rxq->vlan_strip &&
1879                             (cqe->hdr_type_etc &
1880                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1881                                 pkt->ol_flags |= PKT_RX_VLAN |
1882                                         PKT_RX_VLAN_STRIPPED;
1883                                 pkt->vlan_tci =
1884                                         rte_be_to_cpu_16(cqe->vlan_info);
1885                         }
1886                         if (rxq->hw_timestamp) {
1887                                 pkt->timestamp =
1888                                         rte_be_to_cpu_64(cqe->timestamp);
1889                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1890                         }
1891                         if (rxq->crc_present)
1892                                 len -= ETHER_CRC_LEN;
1893                         PKT_LEN(pkt) = len;
1894                 }
1895                 DATA_LEN(rep) = DATA_LEN(seg);
1896                 PKT_LEN(rep) = PKT_LEN(seg);
1897                 SET_DATA_OFF(rep, DATA_OFF(seg));
1898                 PORT(rep) = PORT(seg);
1899                 (*rxq->elts)[idx] = rep;
1900                 /*
1901                  * Fill NIC descriptor with the new buffer.  The lkey and size
1902                  * of the buffers are already known, only the buffer address
1903                  * changes.
1904                  */
1905                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1906                 if (len > DATA_LEN(seg)) {
1907                         len -= DATA_LEN(seg);
1908                         ++NB_SEGS(pkt);
1909                         ++rq_ci;
1910                         continue;
1911                 }
1912                 DATA_LEN(seg) = len;
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914                 /* Increment bytes counter. */
1915                 rxq->stats.ibytes += PKT_LEN(pkt);
1916 #endif
1917                 /* Return packet. */
1918                 *(pkts++) = pkt;
1919                 pkt = NULL;
1920                 --pkts_n;
1921                 ++i;
1922 skip:
1923                 /* Align consumer index to the next stride. */
1924                 rq_ci >>= sges_n;
1925                 ++rq_ci;
1926                 rq_ci <<= sges_n;
1927         }
1928         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1929                 return 0;
1930         /* Update the consumer index. */
1931         rxq->rq_ci = rq_ci >> sges_n;
1932         rte_io_wmb();
1933         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1934         rte_io_wmb();
1935         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1936 #ifdef MLX5_PMD_SOFT_COUNTERS
1937         /* Increment packets counter. */
1938         rxq->stats.ipackets += i;
1939 #endif
1940         return i;
1941 }
1942
1943 /**
1944  * Dummy DPDK callback for TX.
1945  *
1946  * This function is used to temporarily replace the real callback during
1947  * unsafe control operations on the queue, or in case of error.
1948  *
1949  * @param dpdk_txq
1950  *   Generic pointer to TX queue structure.
1951  * @param[in] pkts
1952  *   Packets to transmit.
1953  * @param pkts_n
1954  *   Number of packets in array.
1955  *
1956  * @return
1957  *   Number of packets successfully transmitted (<= pkts_n).
1958  */
1959 uint16_t
1960 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1961 {
1962         (void)dpdk_txq;
1963         (void)pkts;
1964         (void)pkts_n;
1965         return 0;
1966 }
1967
1968 /**
1969  * Dummy DPDK callback for RX.
1970  *
1971  * This function is used to temporarily replace the real callback during
1972  * unsafe control operations on the queue, or in case of error.
1973  *
1974  * @param dpdk_rxq
1975  *   Generic pointer to RX queue structure.
1976  * @param[out] pkts
1977  *   Array to store received packets.
1978  * @param pkts_n
1979  *   Maximum number of packets in array.
1980  *
1981  * @return
1982  *   Number of packets successfully received (<= pkts_n).
1983  */
1984 uint16_t
1985 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1986 {
1987         (void)dpdk_rxq;
1988         (void)pkts;
1989         (void)pkts_n;
1990         return 0;
1991 }
1992
1993 /*
1994  * Vectorized Rx/Tx routines are not compiled in when required vector
1995  * instructions are not supported on a target architecture. The following null
1996  * stubs are needed for linkage when those are not included outside of this file
1997  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1998  */
1999
2000 uint16_t __attribute__((weak))
2001 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2002 {
2003         (void)dpdk_txq;
2004         (void)pkts;
2005         (void)pkts_n;
2006         return 0;
2007 }
2008
2009 uint16_t __attribute__((weak))
2010 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2011 {
2012         (void)dpdk_txq;
2013         (void)pkts;
2014         (void)pkts_n;
2015         return 0;
2016 }
2017
2018 uint16_t __attribute__((weak))
2019 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2020 {
2021         (void)dpdk_rxq;
2022         (void)pkts;
2023         (void)pkts_n;
2024         return 0;
2025 }
2026
2027 int __attribute__((weak))
2028 priv_check_raw_vec_tx_support(struct priv *priv)
2029 {
2030         (void)priv;
2031         return -ENOTSUP;
2032 }
2033
2034 int __attribute__((weak))
2035 priv_check_vec_tx_support(struct priv *priv)
2036 {
2037         (void)priv;
2038         return -ENOTSUP;
2039 }
2040
2041 int __attribute__((weak))
2042 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2043 {
2044         (void)rxq;
2045         return -ENOTSUP;
2046 }
2047
2048 int __attribute__((weak))
2049 priv_check_vec_rx_support(struct priv *priv)
2050 {
2051         (void)priv;
2052         return -ENOTSUP;
2053 }