drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Manage TX completions.
 199  *
 200  * When sending a burst, mlx5_tx_burst() posts several WRs.
 201  *
 202  * @param txq
 203  *   Pointer to TX queue structure.
 204  */
 205 static inline void
 206 txq_complete(struct txq *txq)
 207 {
 208         const unsigned int elts_n = 1 << txq->elts_n;
 209         const unsigned int cqe_n = 1 << txq->cqe_n;
 210         const unsigned int cqe_cnt = cqe_n - 1;
 211         uint16_t elts_free = txq->elts_tail;
 212         uint16_t elts_tail;
 213         uint16_t cq_ci = txq->cq_ci;
 214         volatile struct mlx5_cqe *cqe = NULL;
 215         volatile struct mlx5_wqe_ctrl *ctrl;
 216
 217         do {
 218                 volatile struct mlx5_cqe *tmp;
 219
 220                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 221                 if (check_cqe(tmp, cqe_n, cq_ci))
 222                         break;
 223                 cqe = tmp;
 224 #ifndef NDEBUG
 225                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 226                         if (!check_cqe_seen(cqe))
 227                                 ERROR("unexpected compressed CQE, TX stopped");
 228                         return;
 229                 }
 230                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 231                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 232                         if (!check_cqe_seen(cqe))
 233                                 ERROR("unexpected error CQE, TX stopped");
 234                         return;
 235                 }
 236 #endif /* NDEBUG */
 237                 ++cq_ci;
 238         } while (1);
 239         if (unlikely(cqe == NULL))
 240                 return;
 241         txq->wqe_pi = ntohs(cqe->wqe_counter);
 242         ctrl = (volatile struct mlx5_wqe_ctrl *)
 243                 tx_mlx5_wqe(txq, txq->wqe_pi);
 244         elts_tail = ctrl->ctrl3;
 245         assert(elts_tail < (1 << txq->wqe_n));
 246         /* Free buffers. */
 247         while (elts_free != elts_tail) {
 248                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 249                 unsigned int elts_free_next =
 250                         (elts_free + 1) & (elts_n - 1);
 251                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 252
 253 #ifndef NDEBUG
 254                 /* Poisoning. */
 255                 memset(&(*txq->elts)[elts_free],
 256                        0x66,
 257                        sizeof((*txq->elts)[elts_free]));
 258 #endif
 259                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 260                 /* Only one segment needs to be freed. */
 261                 rte_pktmbuf_free_seg(elt);
 262                 elts_free = elts_free_next;
 263         }
 264         txq->cq_ci = cq_ci;
 265         txq->elts_tail = elts_tail;
 266         /* Update the consumer index. */
 267         rte_wmb();
 268         *txq->cq_db = htonl(cq_ci);
 269 }
 270
 271 /**
 272  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 273  * the cloned mbuf is allocated is returned instead.
 274  *
 275  * @param buf
 276  *   Pointer to mbuf.
 277  *
 278  * @return
 279  *   Memory pool where data is located for given mbuf.
 280  */
 281 static struct rte_mempool *
 282 txq_mb2mp(struct rte_mbuf *buf)
 283 {
 284         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 285                 return rte_mbuf_from_indirect(buf)->pool;
 286         return buf->pool;
 287 }
 288
 289 /**
 290  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 291  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 292  * remove an entry first.
 293  *
 294  * @param txq
 295  *   Pointer to TX queue structure.
 296  * @param[in] mp
 297  *   Memory Pool for which a Memory Region lkey must be returned.
 298  *
 299  * @return
 300  *   mr->lkey on success, (uint32_t)-1 on failure.
 301  */
 302 static inline uint32_t
 303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 304 {
 305         unsigned int i;
 306         uint32_t lkey = (uint32_t)-1;
 307
 308         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 309                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 310                         /* Unknown MP, add a new MR for it. */
 311                         break;
 312                 }
 313                 if (txq->mp2mr[i].mp == mp) {
 314                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 315                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 316                                txq->mp2mr[i].lkey);
 317                         lkey = txq->mp2mr[i].lkey;
 318                         break;
 319                 }
 320         }
 321         if (unlikely(lkey == (uint32_t)-1))
 322                 lkey = txq_mp2mr_reg(txq, mp, i);
 323         return lkey;
 324 }
 325
 326 /**
 327  * Ring TX queue doorbell.
 328  *
 329  * @param txq
 330  *   Pointer to TX queue structure.
 331  * @param wqe
 332  *   Pointer to the last WQE posted in the NIC.
 333  */
 334 static inline void
 335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 336 {
 337         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 338         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 339
 340         rte_wmb();
 341         *txq->qp_db = htonl(txq->wqe_ci);
 342         /* Ensure ordering between DB record and BF copy. */
 343         rte_wmb();
 344         *dst = *src;
 345 }
 346
 347 /**
 348  * DPDK callback for TX.
 349  *
 350  * @param dpdk_txq
 351  *   Generic pointer to TX queue structure.
 352  * @param[in] pkts
 353  *   Packets to transmit.
 354  * @param pkts_n
 355  *   Number of packets in array.
 356  *
 357  * @return
 358  *   Number of packets successfully transmitted (<= pkts_n).
 359  */
 360 uint16_t
 361 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 362 {
 363         struct txq *txq = (struct txq *)dpdk_txq;
 364         uint16_t elts_head = txq->elts_head;
 365         const unsigned int elts_n = 1 << txq->elts_n;
 366         unsigned int i = 0;
 367         unsigned int j = 0;
 368         unsigned int max;
 369         uint16_t max_wqe;
 370         unsigned int comp;
 371         volatile struct mlx5_wqe_v *wqe = NULL;
 372         unsigned int segs_n = 0;
 373         struct rte_mbuf *buf = NULL;
 374         uint8_t *raw;
 375
 376         if (unlikely(!pkts_n))
 377                 return 0;
 378         /* Prefetch first packet cacheline. */
 379         rte_prefetch0(*pkts);
 380         /* Start processing. */
 381         txq_complete(txq);
 382         max = (elts_n - (elts_head - txq->elts_tail));
 383         if (max > elts_n)
 384                 max -= elts_n;
 385         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 386         if (unlikely(!max_wqe))
 387                 return 0;
 388         do {
 389                 volatile rte_v128u32_t *dseg = NULL;
 390                 uint32_t length;
 391                 unsigned int ds = 0;
 392                 uintptr_t addr;
 393                 uint64_t naddr;
 394                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 395                 uint16_t ehdr;
 396                 uint8_t cs_flags = 0;
 397 #ifdef MLX5_PMD_SOFT_COUNTERS
 398                 uint32_t total_length = 0;
 399 #endif
 400
 401                 /* first_seg */
 402                 buf = *(pkts++);
 403                 segs_n = buf->nb_segs;
 404                 /*
 405                  * Make sure there is enough room to store this packet and
 406                  * that one ring entry remains unused.
 407                  */
 408                 assert(segs_n);
 409                 if (max < segs_n + 1)
 410                         break;
 411                 max -= segs_n;
 412                 --segs_n;
 413                 if (!segs_n)
 414                         --pkts_n;
 415                 if (unlikely(--max_wqe == 0))
 416                         break;
 417                 wqe = (volatile struct mlx5_wqe_v *)
 418                         tx_mlx5_wqe(txq, txq->wqe_ci);
 419                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 420                 if (pkts_n > 1)
 421                         rte_prefetch0(*pkts);
 422                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 423                 length = DATA_LEN(buf);
 424                 ehdr = (((uint8_t *)addr)[1] << 8) |
 425                        ((uint8_t *)addr)[0];
 426 #ifdef MLX5_PMD_SOFT_COUNTERS
 427                 total_length = length;
 428 #endif
 429                 assert(length >= MLX5_WQE_DWORD_SIZE);
 430                 /* Update element. */
 431                 (*txq->elts)[elts_head] = buf;
 432                 elts_head = (elts_head + 1) & (elts_n - 1);
 433                 /* Prefetch next buffer data. */
 434                 if (pkts_n > 1) {
 435                         volatile void *pkt_addr;
 436
 437                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 438                         rte_prefetch0(pkt_addr);
 439                 }
 440                 /* Should we enable HW CKSUM offload */
 441                 if (buf->ol_flags &
 442                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 443                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 444                 }
 445                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 446                 /* Replace the Ethernet type by the VLAN if necessary. */
 447                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 448                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 449                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 450
 451                         addr += 2;
 452                         length -= 2;
 453                         /* Copy Destination and source mac address. */
 454                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 455                         /* Copy VLAN. */
 456                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 457                         /* Copy missing two bytes to end the DSeg. */
 458                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 459                                ((uint8_t *)addr) + len, 2);
 460                         addr += len + 2;
 461                         length -= (len + 2);
 462                 } else {
 463                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 464                                MLX5_WQE_DWORD_SIZE);
 465                         length -= pkt_inline_sz;
 466                         addr += pkt_inline_sz;
 467                 }
 468                 /* Inline if enough room. */
 469                 if (txq->max_inline != 0) {
 470                         uintptr_t end = (uintptr_t)
 471                                 (((uintptr_t)txq->wqes) +
 472                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 473                         uint16_t max_inline =
 474                                 txq->max_inline * RTE_CACHE_LINE_SIZE;
 475                         uint16_t room;
 476
 477                         /*
 478                          * raw starts two bytes before the boundary to
 479                          * continue the above copy of packet data.
 480                          */
 481                         raw += MLX5_WQE_DWORD_SIZE;
 482                         room = end - (uintptr_t)raw;
 483                         if (room > max_inline) {
 484                                 uintptr_t addr_end = (addr + max_inline) &
 485                                         ~(RTE_CACHE_LINE_SIZE - 1);
 486                                 unsigned int copy_b =
 487                                         RTE_MIN((addr_end - addr), length);
 488                                 uint16_t n;
 489
 490                                 /*
 491                                  * One Dseg remains in the current WQE.  To
 492                                  * keep the computation positive, it is
 493                                  * removed after the bytes to Dseg conversion.
 494                                  */
 495                                 n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 496                                 if (unlikely(max_wqe < n))
 497                                         break;
 498                                 max_wqe -= n;
 499                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 500                                 addr += copy_b;
 501                                 length -= copy_b;
 502                                 pkt_inline_sz += copy_b;
 503                                 /* Sanity check. */
 504                                 assert(addr <= addr_end);
 505                         }
 506                         /*
 507                          * 2 DWORDs consumed by the WQE header + ETH segment +
 508                          * the size of the inline part of the packet.
 509                          */
 510                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 511                         if (length > 0) {
 512                                 if (ds % (MLX5_WQE_SIZE /
 513                                           MLX5_WQE_DWORD_SIZE) == 0) {
 514                                         if (unlikely(--max_wqe == 0))
 515                                                 break;
 516                                         dseg = (volatile rte_v128u32_t *)
 517                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 518                                                            ds / 4);
 519                                 } else {
 520                                         dseg = (volatile rte_v128u32_t *)
 521                                                 ((uintptr_t)wqe +
 522                                                  (ds * MLX5_WQE_DWORD_SIZE));
 523                                 }
 524                                 goto use_dseg;
 525                         } else if (!segs_n) {
 526                                 goto next_pkt;
 527                         } else {
 528                                 /* dseg will be advance as part of next_seg */
 529                                 dseg = (volatile rte_v128u32_t *)
 530                                         ((uintptr_t)wqe +
 531                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 532                                 goto next_seg;
 533                         }
 534                 } else {
 535                         /*
 536                          * No inline has been done in the packet, only the
 537                          * Ethernet Header as been stored.
 538                          */
 539                         dseg = (volatile rte_v128u32_t *)
 540                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 541                         ds = 3;
 542 use_dseg:
 543                         /* Add the remaining packet as a simple ds. */
 544                         naddr = htonll(addr);
 545                         *dseg = (rte_v128u32_t){
 546                                 htonl(length),
 547                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 548                                 naddr,
 549                                 naddr >> 32,
 550                         };
 551                         ++ds;
 552                         if (!segs_n)
 553                                 goto next_pkt;
 554                 }
 555 next_seg:
 556                 assert(buf);
 557                 assert(ds);
 558                 assert(wqe);
 559                 /*
 560                  * Spill on next WQE when the current one does not have
 561                  * enough room left. Size of WQE must a be a multiple
 562                  * of data segment size.
 563                  */
 564                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 565                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 566                         if (unlikely(--max_wqe == 0))
 567                                 break;
 568                         dseg = (volatile rte_v128u32_t *)
 569                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 570                         rte_prefetch0(tx_mlx5_wqe(txq,
 571                                                   txq->wqe_ci + ds / 4 + 1));
 572                 } else {
 573                         ++dseg;
 574                 }
 575                 ++ds;
 576                 buf = buf->next;
 577                 assert(buf);
 578                 length = DATA_LEN(buf);
 579 #ifdef MLX5_PMD_SOFT_COUNTERS
 580                 total_length += length;
 581 #endif
 582                 /* Store segment information. */
 583                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 584                 *dseg = (rte_v128u32_t){
 585                         htonl(length),
 586                         txq_mp2mr(txq, txq_mb2mp(buf)),
 587                         naddr,
 588                         naddr >> 32,
 589                 };
 590                 (*txq->elts)[elts_head] = buf;
 591                 elts_head = (elts_head + 1) & (elts_n - 1);
 592                 ++j;
 593                 --segs_n;
 594                 if (segs_n)
 595                         goto next_seg;
 596                 else
 597                         --pkts_n;
 598 next_pkt:
 599                 ++i;
 600                 /* Initialize known and common part of the WQE structure. */
 601                 wqe->ctrl = (rte_v128u32_t){
 602                         htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 603                         htonl(txq->qp_num_8s | ds),
 604                         0,
 605                         0,
 606                 };
 607                 wqe->eseg = (rte_v128u32_t){
 608                         0,
 609                         cs_flags,
 610                         0,
 611                         (ehdr << 16) | htons(pkt_inline_sz),
 612                 };
 613                 txq->wqe_ci += (ds + 3) / 4;
 614 #ifdef MLX5_PMD_SOFT_COUNTERS
 615                 /* Increment sent bytes counter. */
 616                 txq->stats.obytes += total_length;
 617 #endif
 618         } while (pkts_n);
 619         /* Take a shortcut if nothing must be sent. */
 620         if (unlikely(i == 0))
 621                 return 0;
 622         /* Check whether completion threshold has been reached. */
 623         comp = txq->elts_comp + i + j;
 624         if (comp >= MLX5_TX_COMP_THRESH) {
 625                 volatile struct mlx5_wqe_ctrl *w =
 626                         (volatile struct mlx5_wqe_ctrl *)wqe;
 627
 628                 /* Request completion on last WQE. */
 629                 w->ctrl2 = htonl(8);
 630                 /* Save elts_head in unused "immediate" field of WQE. */
 631                 w->ctrl3 = elts_head;
 632                 txq->elts_comp = 0;
 633         } else {
 634                 txq->elts_comp = comp;
 635         }
 636 #ifdef MLX5_PMD_SOFT_COUNTERS
 637         /* Increment sent packets counter. */
 638         txq->stats.opackets += i;
 639 #endif
 640         /* Ring QP doorbell. */
 641         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
 642         txq->elts_head = elts_head;
 643         return i;
 644 }
 645
 646 /**
 647  * Open a MPW session.
 648  *
 649  * @param txq
 650  *   Pointer to TX queue structure.
 651  * @param mpw
 652  *   Pointer to MPW session structure.
 653  * @param length
 654  *   Packet length.
 655  */
 656 static inline void
 657 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 658 {
 659         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 660         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 661                 (volatile struct mlx5_wqe_data_seg (*)[])
 662                 tx_mlx5_wqe(txq, idx + 1);
 663
 664         mpw->state = MLX5_MPW_STATE_OPENED;
 665         mpw->pkts_n = 0;
 666         mpw->len = length;
 667         mpw->total_len = 0;
 668         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 669         mpw->wqe->eseg.mss = htons(length);
 670         mpw->wqe->eseg.inline_hdr_sz = 0;
 671         mpw->wqe->eseg.rsvd0 = 0;
 672         mpw->wqe->eseg.rsvd1 = 0;
 673         mpw->wqe->eseg.rsvd2 = 0;
 674         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 675                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 676         mpw->wqe->ctrl[2] = 0;
 677         mpw->wqe->ctrl[3] = 0;
 678         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 679                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 680         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 681                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 682         mpw->data.dseg[2] = &(*dseg)[0];
 683         mpw->data.dseg[3] = &(*dseg)[1];
 684         mpw->data.dseg[4] = &(*dseg)[2];
 685 }
 686
 687 /**
 688  * Close a MPW session.
 689  *
 690  * @param txq
 691  *   Pointer to TX queue structure.
 692  * @param mpw
 693  *   Pointer to MPW session structure.
 694  */
 695 static inline void
 696 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 697 {
 698         unsigned int num = mpw->pkts_n;
 699
 700         /*
 701          * Store size in multiple of 16 bytes. Control and Ethernet segments
 702          * count as 2.
 703          */
 704         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 705         mpw->state = MLX5_MPW_STATE_CLOSED;
 706         if (num < 3)
 707                 ++txq->wqe_ci;
 708         else
 709                 txq->wqe_ci += 2;
 710         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 711         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 712 }
 713
 714 /**
 715  * DPDK callback for TX with MPW support.
 716  *
 717  * @param dpdk_txq
 718  *   Generic pointer to TX queue structure.
 719  * @param[in] pkts
 720  *   Packets to transmit.
 721  * @param pkts_n
 722  *   Number of packets in array.
 723  *
 724  * @return
 725  *   Number of packets successfully transmitted (<= pkts_n).
 726  */
 727 uint16_t
 728 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 729 {
 730         struct txq *txq = (struct txq *)dpdk_txq;
 731         uint16_t elts_head = txq->elts_head;
 732         const unsigned int elts_n = 1 << txq->elts_n;
 733         unsigned int i = 0;
 734         unsigned int j = 0;
 735         unsigned int max;
 736         uint16_t max_wqe;
 737         unsigned int comp;
 738         struct mlx5_mpw mpw = {
 739                 .state = MLX5_MPW_STATE_CLOSED,
 740         };
 741
 742         if (unlikely(!pkts_n))
 743                 return 0;
 744         /* Prefetch first packet cacheline. */
 745         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 746         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 747         /* Start processing. */
 748         txq_complete(txq);
 749         max = (elts_n - (elts_head - txq->elts_tail));
 750         if (max > elts_n)
 751                 max -= elts_n;
 752         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 753         if (unlikely(!max_wqe))
 754                 return 0;
 755         do {
 756                 struct rte_mbuf *buf = *(pkts++);
 757                 unsigned int elts_head_next;
 758                 uint32_t length;
 759                 unsigned int segs_n = buf->nb_segs;
 760                 uint32_t cs_flags = 0;
 761
 762                 /*
 763                  * Make sure there is enough room to store this packet and
 764                  * that one ring entry remains unused.
 765                  */
 766                 assert(segs_n);
 767                 if (max < segs_n + 1)
 768                         break;
 769                 /* Do not bother with large packets MPW cannot handle. */
 770                 if (segs_n > MLX5_MPW_DSEG_MAX)
 771                         break;
 772                 max -= segs_n;
 773                 --pkts_n;
 774                 /* Should we enable HW CKSUM offload */
 775                 if (buf->ol_flags &
 776                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 777                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 778                 /* Retrieve packet information. */
 779                 length = PKT_LEN(buf);
 780                 assert(length);
 781                 /* Start new session if packet differs. */
 782                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 783                     ((mpw.len != length) ||
 784                      (segs_n != 1) ||
 785                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 786                         mlx5_mpw_close(txq, &mpw);
 787                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 788                         /*
 789                          * Multi-Packet WQE consumes at most two WQE.
 790                          * mlx5_mpw_new() expects to be able to use such
 791                          * resources.
 792                          */
 793                         if (unlikely(max_wqe < 2))
 794                                 break;
 795                         max_wqe -= 2;
 796                         mlx5_mpw_new(txq, &mpw, length);
 797                         mpw.wqe->eseg.cs_flags = cs_flags;
 798                 }
 799                 /* Multi-segment packets must be alone in their MPW. */
 800                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 801 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 802                 length = 0;
 803 #endif
 804                 do {
 805                         volatile struct mlx5_wqe_data_seg *dseg;
 806                         uintptr_t addr;
 807
 808                         elts_head_next = (elts_head + 1) & (elts_n - 1);
 809                         assert(buf);
 810                         (*txq->elts)[elts_head] = buf;
 811                         dseg = mpw.data.dseg[mpw.pkts_n];
 812                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 813                         *dseg = (struct mlx5_wqe_data_seg){
 814                                 .byte_count = htonl(DATA_LEN(buf)),
 815                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
 816                                 .addr = htonll(addr),
 817                         };
 818                         elts_head = elts_head_next;
 819 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 820                         length += DATA_LEN(buf);
 821 #endif
 822                         buf = buf->next;
 823                         ++mpw.pkts_n;
 824                         ++j;
 825                 } while (--segs_n);
 826                 assert(length == mpw.len);
 827                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 828                         mlx5_mpw_close(txq, &mpw);
 829                 elts_head = elts_head_next;
 830 #ifdef MLX5_PMD_SOFT_COUNTERS
 831                 /* Increment sent bytes counter. */
 832                 txq->stats.obytes += length;
 833 #endif
 834                 ++i;
 835         } while (pkts_n);
 836         /* Take a shortcut if nothing must be sent. */
 837         if (unlikely(i == 0))
 838                 return 0;
 839         /* Check whether completion threshold has been reached. */
 840         /* "j" includes both packets and segments. */
 841         comp = txq->elts_comp + j;
 842         if (comp >= MLX5_TX_COMP_THRESH) {
 843                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 844
 845                 /* Request completion on last WQE. */
 846                 wqe->ctrl[2] = htonl(8);
 847                 /* Save elts_head in unused "immediate" field of WQE. */
 848                 wqe->ctrl[3] = elts_head;
 849                 txq->elts_comp = 0;
 850         } else {
 851                 txq->elts_comp = comp;
 852         }
 853 #ifdef MLX5_PMD_SOFT_COUNTERS
 854         /* Increment sent packets counter. */
 855         txq->stats.opackets += i;
 856 #endif
 857         /* Ring QP doorbell. */
 858         if (mpw.state == MLX5_MPW_STATE_OPENED)
 859                 mlx5_mpw_close(txq, &mpw);
 860         mlx5_tx_dbrec(txq, mpw.wqe);
 861         txq->elts_head = elts_head;
 862         return i;
 863 }
 864
 865 /**
 866  * Open a MPW inline session.
 867  *
 868  * @param txq
 869  *   Pointer to TX queue structure.
 870  * @param mpw
 871  *   Pointer to MPW session structure.
 872  * @param length
 873  *   Packet length.
 874  */
 875 static inline void
 876 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 877 {
 878         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 879         struct mlx5_wqe_inl_small *inl;
 880
 881         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 882         mpw->pkts_n = 0;
 883         mpw->len = length;
 884         mpw->total_len = 0;
 885         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 886         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 887                                   (txq->wqe_ci << 8) |
 888                                   MLX5_OPCODE_TSO);
 889         mpw->wqe->ctrl[2] = 0;
 890         mpw->wqe->ctrl[3] = 0;
 891         mpw->wqe->eseg.mss = htons(length);
 892         mpw->wqe->eseg.inline_hdr_sz = 0;
 893         mpw->wqe->eseg.cs_flags = 0;
 894         mpw->wqe->eseg.rsvd0 = 0;
 895         mpw->wqe->eseg.rsvd1 = 0;
 896         mpw->wqe->eseg.rsvd2 = 0;
 897         inl = (struct mlx5_wqe_inl_small *)
 898                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 899         mpw->data.raw = (uint8_t *)&inl->raw;
 900 }
 901
 902 /**
 903  * Close a MPW inline session.
 904  *
 905  * @param txq
 906  *   Pointer to TX queue structure.
 907  * @param mpw
 908  *   Pointer to MPW session structure.
 909  */
 910 static inline void
 911 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
 912 {
 913         unsigned int size;
 914         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 915                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 916
 917         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 918         /*
 919          * Store size in multiple of 16 bytes. Control and Ethernet segments
 920          * count as 2.
 921          */
 922         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
 923         mpw->state = MLX5_MPW_STATE_CLOSED;
 924         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
 925         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 926 }
 927
 928 /**
 929  * DPDK callback for TX with MPW inline support.
 930  *
 931  * @param dpdk_txq
 932  *   Generic pointer to TX queue structure.
 933  * @param[in] pkts
 934  *   Packets to transmit.
 935  * @param pkts_n
 936  *   Number of packets in array.
 937  *
 938  * @return
 939  *   Number of packets successfully transmitted (<= pkts_n).
 940  */
 941 uint16_t
 942 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
 943                          uint16_t pkts_n)
 944 {
 945         struct txq *txq = (struct txq *)dpdk_txq;
 946         uint16_t elts_head = txq->elts_head;
 947         const unsigned int elts_n = 1 << txq->elts_n;
 948         unsigned int i = 0;
 949         unsigned int j = 0;
 950         unsigned int max;
 951         uint16_t max_wqe;
 952         unsigned int comp;
 953         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
 954         struct mlx5_mpw mpw = {
 955                 .state = MLX5_MPW_STATE_CLOSED,
 956         };
 957         /*
 958          * Compute the maximum number of WQE which can be consumed by inline
 959          * code.
 960          * - 2 DSEG for:
 961          *   - 1 control segment,
 962          *   - 1 Ethernet segment,
 963          * - N Dseg from the inline request.
 964          */
 965         const unsigned int wqe_inl_n =
 966                 ((2 * MLX5_WQE_DWORD_SIZE +
 967                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
 968                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
 969
 970         if (unlikely(!pkts_n))
 971                 return 0;
 972         /* Prefetch first packet cacheline. */
 973         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 974         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 975         /* Start processing. */
 976         txq_complete(txq);
 977         max = (elts_n - (elts_head - txq->elts_tail));
 978         if (max > elts_n)
 979                 max -= elts_n;
 980         do {
 981                 struct rte_mbuf *buf = *(pkts++);
 982                 unsigned int elts_head_next;
 983                 uintptr_t addr;
 984                 uint32_t length;
 985                 unsigned int segs_n = buf->nb_segs;
 986                 uint32_t cs_flags = 0;
 987
 988                 /*
 989                  * Make sure there is enough room to store this packet and
 990                  * that one ring entry remains unused.
 991                  */
 992                 assert(segs_n);
 993                 if (max < segs_n + 1)
 994                         break;
 995                 /* Do not bother with large packets MPW cannot handle. */
 996                 if (segs_n > MLX5_MPW_DSEG_MAX)
 997                         break;
 998                 max -= segs_n;
 999                 --pkts_n;
1000                 /*
1001                  * Compute max_wqe in case less WQE were consumed in previous
1002                  * iteration.
1003                  */
1004                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1005                 /* Should we enable HW CKSUM offload */
1006                 if (buf->ol_flags &
1007                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1008                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1009                 /* Retrieve packet information. */
1010                 length = PKT_LEN(buf);
1011                 /* Start new session if packet differs. */
1012                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1013                         if ((mpw.len != length) ||
1014                             (segs_n != 1) ||
1015                             (mpw.wqe->eseg.cs_flags != cs_flags))
1016                                 mlx5_mpw_close(txq, &mpw);
1017                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1018                         if ((mpw.len != length) ||
1019                             (segs_n != 1) ||
1020                             (length > inline_room) ||
1021                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1022                                 mlx5_mpw_inline_close(txq, &mpw);
1023                                 inline_room =
1024                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1025                         }
1026                 }
1027                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1028                         if ((segs_n != 1) ||
1029                             (length > inline_room)) {
1030                                 /*
1031                                  * Multi-Packet WQE consumes at most two WQE.
1032                                  * mlx5_mpw_new() expects to be able to use
1033                                  * such resources.
1034                                  */
1035                                 if (unlikely(max_wqe < 2))
1036                                         break;
1037                                 max_wqe -= 2;
1038                                 mlx5_mpw_new(txq, &mpw, length);
1039                                 mpw.wqe->eseg.cs_flags = cs_flags;
1040                         } else {
1041                                 if (unlikely(max_wqe < wqe_inl_n))
1042                                         break;
1043                                 max_wqe -= wqe_inl_n;
1044                                 mlx5_mpw_inline_new(txq, &mpw, length);
1045                                 mpw.wqe->eseg.cs_flags = cs_flags;
1046                         }
1047                 }
1048                 /* Multi-segment packets must be alone in their MPW. */
1049                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1050                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1051                         assert(inline_room ==
1052                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1053 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1054                         length = 0;
1055 #endif
1056                         do {
1057                                 volatile struct mlx5_wqe_data_seg *dseg;
1058
1059                                 elts_head_next =
1060                                         (elts_head + 1) & (elts_n - 1);
1061                                 assert(buf);
1062                                 (*txq->elts)[elts_head] = buf;
1063                                 dseg = mpw.data.dseg[mpw.pkts_n];
1064                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1065                                 *dseg = (struct mlx5_wqe_data_seg){
1066                                         .byte_count = htonl(DATA_LEN(buf)),
1067                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1068                                         .addr = htonll(addr),
1069                                 };
1070                                 elts_head = elts_head_next;
1071 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1072                                 length += DATA_LEN(buf);
1073 #endif
1074                                 buf = buf->next;
1075                                 ++mpw.pkts_n;
1076                                 ++j;
1077                         } while (--segs_n);
1078                         assert(length == mpw.len);
1079                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1080                                 mlx5_mpw_close(txq, &mpw);
1081                 } else {
1082                         unsigned int max;
1083
1084                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1085                         assert(length <= inline_room);
1086                         assert(length == DATA_LEN(buf));
1087                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1088                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1089                         (*txq->elts)[elts_head] = buf;
1090                         /* Maximum number of bytes before wrapping. */
1091                         max = ((((uintptr_t)(txq->wqes)) +
1092                                 (1 << txq->wqe_n) *
1093                                 MLX5_WQE_SIZE) -
1094                                (uintptr_t)mpw.data.raw);
1095                         if (length > max) {
1096                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1097                                            (void *)addr,
1098                                            max);
1099                                 mpw.data.raw = (volatile void *)txq->wqes;
1100                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1101                                            (void *)(addr + max),
1102                                            length - max);
1103                                 mpw.data.raw += length - max;
1104                         } else {
1105                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1106                                            (void *)addr,
1107                                            length);
1108
1109                                 if (length == max)
1110                                         mpw.data.raw =
1111                                                 (volatile void *)txq->wqes;
1112                                 else
1113                                         mpw.data.raw += length;
1114                         }
1115                         ++mpw.pkts_n;
1116                         ++j;
1117                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1118                                 mlx5_mpw_inline_close(txq, &mpw);
1119                                 inline_room =
1120                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1121                         } else {
1122                                 inline_room -= length;
1123                         }
1124                 }
1125                 mpw.total_len += length;
1126                 elts_head = elts_head_next;
1127 #ifdef MLX5_PMD_SOFT_COUNTERS
1128                 /* Increment sent bytes counter. */
1129                 txq->stats.obytes += length;
1130 #endif
1131                 ++i;
1132         } while (pkts_n);
1133         /* Take a shortcut if nothing must be sent. */
1134         if (unlikely(i == 0))
1135                 return 0;
1136         /* Check whether completion threshold has been reached. */
1137         /* "j" includes both packets and segments. */
1138         comp = txq->elts_comp + j;
1139         if (comp >= MLX5_TX_COMP_THRESH) {
1140                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1141
1142                 /* Request completion on last WQE. */
1143                 wqe->ctrl[2] = htonl(8);
1144                 /* Save elts_head in unused "immediate" field of WQE. */
1145                 wqe->ctrl[3] = elts_head;
1146                 txq->elts_comp = 0;
1147         } else {
1148                 txq->elts_comp = comp;
1149         }
1150 #ifdef MLX5_PMD_SOFT_COUNTERS
1151         /* Increment sent packets counter. */
1152         txq->stats.opackets += i;
1153 #endif
1154         /* Ring QP doorbell. */
1155         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1156                 mlx5_mpw_inline_close(txq, &mpw);
1157         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1158                 mlx5_mpw_close(txq, &mpw);
1159         mlx5_tx_dbrec(txq, mpw.wqe);
1160         txq->elts_head = elts_head;
1161         return i;
1162 }
1163
1164 /**
1165  * Translate RX completion flags to packet type.
1166  *
1167  * @param[in] cqe
1168  *   Pointer to CQE.
1169  *
1170  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1171  *
1172  * @return
1173  *   Packet type for struct rte_mbuf.
1174  */
1175 static inline uint32_t
1176 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1177 {
1178         uint32_t pkt_type;
1179         uint16_t flags = ntohs(cqe->hdr_type_etc);
1180
1181         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1182                 pkt_type =
1183                         TRANSPOSE(flags,
1184                                   MLX5_CQE_RX_IPV4_PACKET,
1185                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1186                         TRANSPOSE(flags,
1187                                   MLX5_CQE_RX_IPV6_PACKET,
1188                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1189                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1190                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1191                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1192         } else {
1193                 pkt_type =
1194                         TRANSPOSE(flags,
1195                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1196                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1197                         TRANSPOSE(flags,
1198                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1199                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1200         }
1201         return pkt_type;
1202 }
1203
1204 /**
1205  * Get size of the next packet for a given CQE. For compressed CQEs, the
1206  * consumer index is updated only once all packets of the current one have
1207  * been processed.
1208  *
1209  * @param rxq
1210  *   Pointer to RX queue.
1211  * @param cqe
1212  *   CQE to process.
1213  * @param[out] rss_hash
1214  *   Packet RSS Hash result.
1215  *
1216  * @return
1217  *   Packet size in bytes (0 if there is none), -1 in case of completion
1218  *   with error.
1219  */
1220 static inline int
1221 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1222                  uint16_t cqe_cnt, uint32_t *rss_hash)
1223 {
1224         struct rxq_zip *zip = &rxq->zip;
1225         uint16_t cqe_n = cqe_cnt + 1;
1226         int len = 0;
1227         uint16_t idx, end;
1228
1229         /* Process compressed data in the CQE and mini arrays. */
1230         if (zip->ai) {
1231                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1232                         (volatile struct mlx5_mini_cqe8 (*)[8])
1233                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1234
1235                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1236                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1237                 if ((++zip->ai & 7) == 0) {
1238                         /* Invalidate consumed CQEs */
1239                         idx = zip->ca;
1240                         end = zip->na;
1241                         while (idx != end) {
1242                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1243                                         MLX5_CQE_INVALIDATE;
1244                                 ++idx;
1245                         }
1246                         /*
1247                          * Increment consumer index to skip the number of
1248                          * CQEs consumed. Hardware leaves holes in the CQ
1249                          * ring for software use.
1250                          */
1251                         zip->ca = zip->na;
1252                         zip->na += 8;
1253                 }
1254                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1255                         /* Invalidate the rest */
1256                         idx = zip->ca;
1257                         end = zip->cq_ci;
1258
1259                         while (idx != end) {
1260                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1261                                         MLX5_CQE_INVALIDATE;
1262                                 ++idx;
1263                         }
1264                         rxq->cq_ci = zip->cq_ci;
1265                         zip->ai = 0;
1266                 }
1267         /* No compressed data, get next CQE and verify if it is compressed. */
1268         } else {
1269                 int ret;
1270                 int8_t op_own;
1271
1272                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1273                 if (unlikely(ret == 1))
1274                         return 0;
1275                 ++rxq->cq_ci;
1276                 op_own = cqe->op_own;
1277                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1278                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1279                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1280                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1281                                                           cqe_cnt]);
1282
1283                         /* Fix endianness. */
1284                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1285                         /*
1286                          * Current mini array position is the one returned by
1287                          * check_cqe64().
1288                          *
1289                          * If completion comprises several mini arrays, as a
1290                          * special case the second one is located 7 CQEs after
1291                          * the initial CQE instead of 8 for subsequent ones.
1292                          */
1293                         zip->ca = rxq->cq_ci;
1294                         zip->na = zip->ca + 7;
1295                         /* Compute the next non compressed CQE. */
1296                         --rxq->cq_ci;
1297                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1298                         /* Get packet size to return. */
1299                         len = ntohl((*mc)[0].byte_cnt);
1300                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1301                         zip->ai = 1;
1302                         /* Prefetch all the entries to be invalidated */
1303                         idx = zip->ca;
1304                         end = zip->cq_ci;
1305                         while (idx != end) {
1306                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1307                                 ++idx;
1308                         }
1309                 } else {
1310                         len = ntohl(cqe->byte_cnt);
1311                         *rss_hash = ntohl(cqe->rx_hash_res);
1312                 }
1313                 /* Error while receiving packet. */
1314                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1315                         return -1;
1316         }
1317         return len;
1318 }
1319
1320 /**
1321  * Translate RX completion flags to offload flags.
1322  *
1323  * @param[in] rxq
1324  *   Pointer to RX queue structure.
1325  * @param[in] cqe
1326  *   Pointer to CQE.
1327  *
1328  * @return
1329  *   Offload flags (ol_flags) for struct rte_mbuf.
1330  */
1331 static inline uint32_t
1332 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1333 {
1334         uint32_t ol_flags = 0;
1335         uint16_t flags = ntohs(cqe->hdr_type_etc);
1336
1337         ol_flags =
1338                 TRANSPOSE(flags,
1339                           MLX5_CQE_RX_L3_HDR_VALID,
1340                           PKT_RX_IP_CKSUM_GOOD) |
1341                 TRANSPOSE(flags,
1342                           MLX5_CQE_RX_L4_HDR_VALID,
1343                           PKT_RX_L4_CKSUM_GOOD);
1344         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1345                 ol_flags |=
1346                         TRANSPOSE(flags,
1347                                   MLX5_CQE_RX_L3_HDR_VALID,
1348                                   PKT_RX_IP_CKSUM_GOOD) |
1349                         TRANSPOSE(flags,
1350                                   MLX5_CQE_RX_L4_HDR_VALID,
1351                                   PKT_RX_L4_CKSUM_GOOD);
1352         return ol_flags;
1353 }
1354
1355 /**
1356  * DPDK callback for RX.
1357  *
1358  * @param dpdk_rxq
1359  *   Generic pointer to RX queue structure.
1360  * @param[out] pkts
1361  *   Array to store received packets.
1362  * @param pkts_n
1363  *   Maximum number of packets in array.
1364  *
1365  * @return
1366  *   Number of packets successfully received (<= pkts_n).
1367  */
1368 uint16_t
1369 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1370 {
1371         struct rxq *rxq = dpdk_rxq;
1372         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1373         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1374         const unsigned int sges_n = rxq->sges_n;
1375         struct rte_mbuf *pkt = NULL;
1376         struct rte_mbuf *seg = NULL;
1377         volatile struct mlx5_cqe *cqe =
1378                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1379         unsigned int i = 0;
1380         unsigned int rq_ci = rxq->rq_ci << sges_n;
1381         int len; /* keep its value across iterations. */
1382
1383         while (pkts_n) {
1384                 unsigned int idx = rq_ci & wqe_cnt;
1385                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1386                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1387                 uint32_t rss_hash_res = 0;
1388
1389                 if (pkt)
1390                         NEXT(seg) = rep;
1391                 seg = rep;
1392                 rte_prefetch0(seg);
1393                 rte_prefetch0(cqe);
1394                 rte_prefetch0(wqe);
1395                 rep = rte_mbuf_raw_alloc(rxq->mp);
1396                 if (unlikely(rep == NULL)) {
1397                         ++rxq->stats.rx_nombuf;
1398                         if (!pkt) {
1399                                 /*
1400                                  * no buffers before we even started,
1401                                  * bail out silently.
1402                                  */
1403                                 break;
1404                         }
1405                         while (pkt != seg) {
1406                                 assert(pkt != (*rxq->elts)[idx]);
1407                                 rep = NEXT(pkt);
1408                                 rte_mbuf_refcnt_set(pkt, 0);
1409                                 __rte_mbuf_raw_free(pkt);
1410                                 pkt = rep;
1411                         }
1412                         break;
1413                 }
1414                 if (!pkt) {
1415                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1416                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1417                                                &rss_hash_res);
1418                         if (!len) {
1419                                 rte_mbuf_refcnt_set(rep, 0);
1420                                 __rte_mbuf_raw_free(rep);
1421                                 break;
1422                         }
1423                         if (unlikely(len == -1)) {
1424                                 /* RX error, packet is likely too large. */
1425                                 rte_mbuf_refcnt_set(rep, 0);
1426                                 __rte_mbuf_raw_free(rep);
1427                                 ++rxq->stats.idropped;
1428                                 goto skip;
1429                         }
1430                         pkt = seg;
1431                         assert(len >= (rxq->crc_present << 2));
1432                         /* Update packet information. */
1433                         pkt->packet_type = 0;
1434                         pkt->ol_flags = 0;
1435                         if (rss_hash_res && rxq->rss_hash) {
1436                                 pkt->hash.rss = rss_hash_res;
1437                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1438                         }
1439                         if (rxq->mark &&
1440                             ((cqe->sop_drop_qpn !=
1441                               htonl(MLX5_FLOW_MARK_INVALID)) ||
1442                              (cqe->sop_drop_qpn !=
1443                               htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1444                                 pkt->hash.fdir.hi =
1445                                         mlx5_flow_mark_get(cqe->sop_drop_qpn);
1446                                 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1447                                 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1448                         }
1449                         if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1450                             rxq->crc_present) {
1451                                 if (rxq->csum) {
1452                                         pkt->packet_type =
1453                                                 rxq_cq_to_pkt_type(cqe);
1454                                         pkt->ol_flags |=
1455                                                 rxq_cq_to_ol_flags(rxq, cqe);
1456                                 }
1457                                 if (cqe->hdr_type_etc &
1458                                     MLX5_CQE_VLAN_STRIPPED) {
1459                                         pkt->ol_flags |= PKT_RX_VLAN_PKT |
1460                                                 PKT_RX_VLAN_STRIPPED;
1461                                         pkt->vlan_tci = ntohs(cqe->vlan_info);
1462                                 }
1463                                 if (rxq->crc_present)
1464                                         len -= ETHER_CRC_LEN;
1465                         }
1466                         PKT_LEN(pkt) = len;
1467                 }
1468                 DATA_LEN(rep) = DATA_LEN(seg);
1469                 PKT_LEN(rep) = PKT_LEN(seg);
1470                 SET_DATA_OFF(rep, DATA_OFF(seg));
1471                 NB_SEGS(rep) = NB_SEGS(seg);
1472                 PORT(rep) = PORT(seg);
1473                 NEXT(rep) = NULL;
1474                 (*rxq->elts)[idx] = rep;
1475                 /*
1476                  * Fill NIC descriptor with the new buffer.  The lkey and size
1477                  * of the buffers are already known, only the buffer address
1478                  * changes.
1479                  */
1480                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1481                 if (len > DATA_LEN(seg)) {
1482                         len -= DATA_LEN(seg);
1483                         ++NB_SEGS(pkt);
1484                         ++rq_ci;
1485                         continue;
1486                 }
1487                 DATA_LEN(seg) = len;
1488 #ifdef MLX5_PMD_SOFT_COUNTERS
1489                 /* Increment bytes counter. */
1490                 rxq->stats.ibytes += PKT_LEN(pkt);
1491 #endif
1492                 /* Return packet. */
1493                 *(pkts++) = pkt;
1494                 pkt = NULL;
1495                 --pkts_n;
1496                 ++i;
1497 skip:
1498                 /* Align consumer index to the next stride. */
1499                 rq_ci >>= sges_n;
1500                 ++rq_ci;
1501                 rq_ci <<= sges_n;
1502         }
1503         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1504                 return 0;
1505         /* Update the consumer index. */
1506         rxq->rq_ci = rq_ci >> sges_n;
1507         rte_wmb();
1508         *rxq->cq_db = htonl(rxq->cq_ci);
1509         rte_wmb();
1510         *rxq->rq_db = htonl(rxq->rq_ci);
1511 #ifdef MLX5_PMD_SOFT_COUNTERS
1512         /* Increment packets counter. */
1513         rxq->stats.ipackets += i;
1514 #endif
1515         return i;
1516 }
1517
1518 /**
1519  * Dummy DPDK callback for TX.
1520  *
1521  * This function is used to temporarily replace the real callback during
1522  * unsafe control operations on the queue, or in case of error.
1523  *
1524  * @param dpdk_txq
1525  *   Generic pointer to TX queue structure.
1526  * @param[in] pkts
1527  *   Packets to transmit.
1528  * @param pkts_n
1529  *   Number of packets in array.
1530  *
1531  * @return
1532  *   Number of packets successfully transmitted (<= pkts_n).
1533  */
1534 uint16_t
1535 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1536 {
1537         (void)dpdk_txq;
1538         (void)pkts;
1539         (void)pkts_n;
1540         return 0;
1541 }
1542
1543 /**
1544  * Dummy DPDK callback for RX.
1545  *
1546  * This function is used to temporarily replace the real callback during
1547  * unsafe control operations on the queue, or in case of error.
1548  *
1549  * @param dpdk_rxq
1550  *   Generic pointer to RX queue structure.
1551  * @param[out] pkts
1552  *   Array to store received packets.
1553  * @param pkts_n
1554  *   Maximum number of packets in array.
1555  *
1556  * @return
1557  *   Number of packets successfully received (<= pkts_n).
1558  */
1559 uint16_t
1560 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1561 {
1562         (void)dpdk_rxq;
1563         (void)pkts;
1564         (void)pkts_n;
1565         return 0;
1566 }