drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Manage TX completions.
 199  *
 200  * When sending a burst, mlx5_tx_burst() posts several WRs.
 201  *
 202  * @param txq
 203  *   Pointer to TX queue structure.
 204  */
 205 static inline void
 206 txq_complete(struct txq *txq)
 207 {
 208         const unsigned int elts_n = 1 << txq->elts_n;
 209         const unsigned int cqe_n = 1 << txq->cqe_n;
 210         const unsigned int cqe_cnt = cqe_n - 1;
 211         uint16_t elts_free = txq->elts_tail;
 212         uint16_t elts_tail;
 213         uint16_t cq_ci = txq->cq_ci;
 214         volatile struct mlx5_cqe *cqe = NULL;
 215         volatile struct mlx5_wqe_ctrl *ctrl;
 216
 217         do {
 218                 volatile struct mlx5_cqe *tmp;
 219
 220                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 221                 if (check_cqe(tmp, cqe_n, cq_ci))
 222                         break;
 223                 cqe = tmp;
 224 #ifndef NDEBUG
 225                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 226                         if (!check_cqe_seen(cqe))
 227                                 ERROR("unexpected compressed CQE, TX stopped");
 228                         return;
 229                 }
 230                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 231                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 232                         if (!check_cqe_seen(cqe))
 233                                 ERROR("unexpected error CQE, TX stopped");
 234                         return;
 235                 }
 236 #endif /* NDEBUG */
 237                 ++cq_ci;
 238         } while (1);
 239         if (unlikely(cqe == NULL))
 240                 return;
 241         txq->wqe_pi = ntohs(cqe->wqe_counter);
 242         ctrl = (volatile struct mlx5_wqe_ctrl *)
 243                 tx_mlx5_wqe(txq, txq->wqe_pi);
 244         elts_tail = ctrl->ctrl3;
 245         assert(elts_tail < (1 << txq->wqe_n));
 246         /* Free buffers. */
 247         while (elts_free != elts_tail) {
 248                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 249                 unsigned int elts_free_next =
 250                         (elts_free + 1) & (elts_n - 1);
 251                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 252
 253 #ifndef NDEBUG
 254                 /* Poisoning. */
 255                 memset(&(*txq->elts)[elts_free],
 256                        0x66,
 257                        sizeof((*txq->elts)[elts_free]));
 258 #endif
 259                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 260                 /* Only one segment needs to be freed. */
 261                 rte_pktmbuf_free_seg(elt);
 262                 elts_free = elts_free_next;
 263         }
 264         txq->cq_ci = cq_ci;
 265         txq->elts_tail = elts_tail;
 266         /* Update the consumer index. */
 267         rte_wmb();
 268         *txq->cq_db = htonl(cq_ci);
 269 }
 270
 271 /**
 272  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 273  * the cloned mbuf is allocated is returned instead.
 274  *
 275  * @param buf
 276  *   Pointer to mbuf.
 277  *
 278  * @return
 279  *   Memory pool where data is located for given mbuf.
 280  */
 281 static struct rte_mempool *
 282 txq_mb2mp(struct rte_mbuf *buf)
 283 {
 284         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 285                 return rte_mbuf_from_indirect(buf)->pool;
 286         return buf->pool;
 287 }
 288
 289 /**
 290  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 291  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 292  * remove an entry first.
 293  *
 294  * @param txq
 295  *   Pointer to TX queue structure.
 296  * @param[in] mp
 297  *   Memory Pool for which a Memory Region lkey must be returned.
 298  *
 299  * @return
 300  *   mr->lkey on success, (uint32_t)-1 on failure.
 301  */
 302 static inline uint32_t
 303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 304 {
 305         unsigned int i;
 306         uint32_t lkey = (uint32_t)-1;
 307
 308         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 309                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 310                         /* Unknown MP, add a new MR for it. */
 311                         break;
 312                 }
 313                 if (txq->mp2mr[i].mp == mp) {
 314                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 315                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 316                                txq->mp2mr[i].lkey);
 317                         lkey = txq->mp2mr[i].lkey;
 318                         break;
 319                 }
 320         }
 321         if (unlikely(lkey == (uint32_t)-1))
 322                 lkey = txq_mp2mr_reg(txq, mp, i);
 323         return lkey;
 324 }
 325
 326 /**
 327  * Ring TX queue doorbell.
 328  *
 329  * @param txq
 330  *   Pointer to TX queue structure.
 331  * @param wqe
 332  *   Pointer to the last WQE posted in the NIC.
 333  */
 334 static inline void
 335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 336 {
 337         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 338         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 339
 340         rte_wmb();
 341         *txq->qp_db = htonl(txq->wqe_ci);
 342         /* Ensure ordering between DB record and BF copy. */
 343         rte_wmb();
 344         *dst = *src;
 345 }
 346
 347 /**
 348  * DPDK callback to check the status of a tx descriptor.
 349  *
 350  * @param tx_queue
 351  *   The tx queue.
 352  * @param[in] offset
 353  *   The index of the descriptor in the ring.
 354  *
 355  * @return
 356  *   The status of the tx descriptor.
 357  */
 358 int
 359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 360 {
 361         struct txq *txq = tx_queue;
 362         const unsigned int elts_n = 1 << txq->elts_n;
 363         const unsigned int elts_cnt = elts_n - 1;
 364         unsigned int used;
 365
 366         txq_complete(txq);
 367         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 368         if (offset < used)
 369                 return RTE_ETH_TX_DESC_FULL;
 370         return RTE_ETH_TX_DESC_DONE;
 371 }
 372
 373 /**
 374  * DPDK callback to check the status of a rx descriptor.
 375  *
 376  * @param rx_queue
 377  *   The rx queue.
 378  * @param[in] offset
 379  *   The index of the descriptor in the ring.
 380  *
 381  * @return
 382  *   The status of the tx descriptor.
 383  */
 384 int
 385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 386 {
 387         struct rxq *rxq = rx_queue;
 388         struct rxq_zip *zip = &rxq->zip;
 389         volatile struct mlx5_cqe *cqe;
 390         const unsigned int cqe_n = (1 << rxq->cqe_n);
 391         const unsigned int cqe_cnt = cqe_n - 1;
 392         unsigned int cq_ci;
 393         unsigned int used;
 394
 395         /* if we are processing a compressed cqe */
 396         if (zip->ai) {
 397                 used = zip->cqe_cnt - zip->ca;
 398                 cq_ci = zip->cq_ci;
 399         } else {
 400                 used = 0;
 401                 cq_ci = rxq->cq_ci;
 402         }
 403         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 404         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 405                 int8_t op_own;
 406                 unsigned int n;
 407
 408                 op_own = cqe->op_own;
 409                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 410                         n = ntohl(cqe->byte_cnt);
 411                 else
 412                         n = 1;
 413                 cq_ci += n;
 414                 used += n;
 415                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 416         }
 417         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 418         if (offset < used)
 419                 return RTE_ETH_RX_DESC_DONE;
 420         return RTE_ETH_RX_DESC_AVAIL;
 421 }
 422
 423 /**
 424  * DPDK callback for TX.
 425  *
 426  * @param dpdk_txq
 427  *   Generic pointer to TX queue structure.
 428  * @param[in] pkts
 429  *   Packets to transmit.
 430  * @param pkts_n
 431  *   Number of packets in array.
 432  *
 433  * @return
 434  *   Number of packets successfully transmitted (<= pkts_n).
 435  */
 436 uint16_t
 437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 438 {
 439         struct txq *txq = (struct txq *)dpdk_txq;
 440         uint16_t elts_head = txq->elts_head;
 441         const unsigned int elts_n = 1 << txq->elts_n;
 442         unsigned int i = 0;
 443         unsigned int j = 0;
 444         unsigned int k = 0;
 445         unsigned int max;
 446         uint16_t max_wqe;
 447         unsigned int comp;
 448         volatile struct mlx5_wqe_v *wqe = NULL;
 449         unsigned int segs_n = 0;
 450         struct rte_mbuf *buf = NULL;
 451         uint8_t *raw;
 452
 453         if (unlikely(!pkts_n))
 454                 return 0;
 455         /* Prefetch first packet cacheline. */
 456         rte_prefetch0(*pkts);
 457         /* Start processing. */
 458         txq_complete(txq);
 459         max = (elts_n - (elts_head - txq->elts_tail));
 460         if (max > elts_n)
 461                 max -= elts_n;
 462         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 463         if (unlikely(!max_wqe))
 464                 return 0;
 465         do {
 466                 volatile rte_v128u32_t *dseg = NULL;
 467                 uint32_t length;
 468                 unsigned int ds = 0;
 469                 uintptr_t addr;
 470                 uint64_t naddr;
 471                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 472                 uint16_t tso_header_sz = 0;
 473                 uint16_t ehdr;
 474                 uint8_t cs_flags = 0;
 475                 uint64_t tso = 0;
 476 #ifdef MLX5_PMD_SOFT_COUNTERS
 477                 uint32_t total_length = 0;
 478 #endif
 479
 480                 /* first_seg */
 481                 buf = *(pkts++);
 482                 segs_n = buf->nb_segs;
 483                 /*
 484                  * Make sure there is enough room to store this packet and
 485                  * that one ring entry remains unused.
 486                  */
 487                 assert(segs_n);
 488                 if (max < segs_n + 1)
 489                         break;
 490                 max -= segs_n;
 491                 --segs_n;
 492                 if (!segs_n)
 493                         --pkts_n;
 494                 if (unlikely(--max_wqe == 0))
 495                         break;
 496                 wqe = (volatile struct mlx5_wqe_v *)
 497                         tx_mlx5_wqe(txq, txq->wqe_ci);
 498                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 499                 if (pkts_n > 1)
 500                         rte_prefetch0(*pkts);
 501                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 502                 length = DATA_LEN(buf);
 503                 ehdr = (((uint8_t *)addr)[1] << 8) |
 504                        ((uint8_t *)addr)[0];
 505 #ifdef MLX5_PMD_SOFT_COUNTERS
 506                 total_length = length;
 507 #endif
 508                 assert(length >= MLX5_WQE_DWORD_SIZE);
 509                 /* Update element. */
 510                 (*txq->elts)[elts_head] = buf;
 511                 elts_head = (elts_head + 1) & (elts_n - 1);
 512                 /* Prefetch next buffer data. */
 513                 if (pkts_n > 1) {
 514                         volatile void *pkt_addr;
 515
 516                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 517                         rte_prefetch0(pkt_addr);
 518                 }
 519                 /* Should we enable HW CKSUM offload */
 520                 if (buf->ol_flags &
 521                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 522                         const uint64_t is_tunneled = buf->ol_flags &
 523                                                      (PKT_TX_TUNNEL_GRE |
 524                                                       PKT_TX_TUNNEL_VXLAN);
 525
 526                         if (is_tunneled && txq->tunnel_en) {
 527                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 528                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 529                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 530                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 531                         } else {
 532                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 533                                            MLX5_ETH_WQE_L4_CSUM;
 534                         }
 535                 }
 536                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 537                 /* Replace the Ethernet type by the VLAN if necessary. */
 538                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 539                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 540                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 541
 542                         addr += 2;
 543                         length -= 2;
 544                         /* Copy Destination and source mac address. */
 545                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 546                         /* Copy VLAN. */
 547                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 548                         /* Copy missing two bytes to end the DSeg. */
 549                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 550                                ((uint8_t *)addr) + len, 2);
 551                         addr += len + 2;
 552                         length -= (len + 2);
 553                 } else {
 554                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 555                                MLX5_WQE_DWORD_SIZE);
 556                         length -= pkt_inline_sz;
 557                         addr += pkt_inline_sz;
 558                 }
 559                 if (txq->tso_en) {
 560                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 561                         if (tso) {
 562                                 uintptr_t end = (uintptr_t)
 563                                                 (((uintptr_t)txq->wqes) +
 564                                                 (1 << txq->wqe_n) *
 565                                                 MLX5_WQE_SIZE);
 566                                 unsigned int copy_b;
 567                                 uint8_t vlan_sz = (buf->ol_flags &
 568                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 569
 570                                 tso_header_sz = buf->l2_len + vlan_sz +
 571                                                 buf->l3_len + buf->l4_len;
 572
 573                                 if (unlikely(tso_header_sz >
 574                                              MLX5_MAX_TSO_HEADER))
 575                                         break;
 576                                 copy_b = tso_header_sz - pkt_inline_sz;
 577                                 /* First seg must contain all headers. */
 578                                 assert(copy_b <= length);
 579                                 raw += MLX5_WQE_DWORD_SIZE;
 580                                 if (copy_b &&
 581                                    ((end - (uintptr_t)raw) > copy_b)) {
 582                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 583                                                       1 + 3) / 4;
 584
 585                                         if (unlikely(max_wqe < n))
 586                                                 break;
 587                                         max_wqe -= n;
 588                                         rte_memcpy((void *)raw,
 589                                                    (void *)addr, copy_b);
 590                                         addr += copy_b;
 591                                         length -= copy_b;
 592                                         pkt_inline_sz += copy_b;
 593                                         /*
 594                                          * Another DWORD will be added
 595                                          * in the inline part.
 596                                          */
 597                                         raw += MLX5_WQE_DS(copy_b) *
 598                                                MLX5_WQE_DWORD_SIZE -
 599                                                MLX5_WQE_DWORD_SIZE;
 600                                 } else {
 601                                         /* NOP WQE. */
 602                                         wqe->ctrl = (rte_v128u32_t){
 603                                                      htonl(txq->wqe_ci << 8),
 604                                                      htonl(txq->qp_num_8s | 1),
 605                                                      0,
 606                                                      0,
 607                                         };
 608                                         ds = 1;
 609                                         total_length = 0;
 610                                         pkts--;
 611                                         pkts_n++;
 612                                         elts_head = (elts_head - 1) &
 613                                                     (elts_n - 1);
 614                                         k++;
 615                                         goto next_wqe;
 616                                 }
 617                         }
 618                 }
 619                 /* Inline if enough room. */
 620                 if (txq->inline_en || tso) {
 621                         uintptr_t end = (uintptr_t)
 622                                 (((uintptr_t)txq->wqes) +
 623                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 624                         unsigned int max_inline = txq->max_inline *
 625                                                   RTE_CACHE_LINE_SIZE -
 626                                                   (pkt_inline_sz - 2);
 627                         uintptr_t addr_end = (addr + max_inline) &
 628                                              ~(RTE_CACHE_LINE_SIZE - 1);
 629                         unsigned int copy_b = (addr_end > addr) ?
 630                                 RTE_MIN((addr_end - addr), length) :
 631                                 0;
 632
 633                         raw += MLX5_WQE_DWORD_SIZE;
 634                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 635                                 /*
 636                                  * One Dseg remains in the current WQE.  To
 637                                  * keep the computation positive, it is
 638                                  * removed after the bytes to Dseg conversion.
 639                                  */
 640                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 641
 642                                 if (unlikely(max_wqe < n))
 643                                         break;
 644                                 max_wqe -= n;
 645                                 if (tso) {
 646                                         uint32_t inl =
 647                                                 htonl(copy_b | MLX5_INLINE_SEG);
 648
 649                                         pkt_inline_sz =
 650                                                 MLX5_WQE_DS(tso_header_sz) *
 651                                                 MLX5_WQE_DWORD_SIZE;
 652                                         rte_memcpy((void *)raw,
 653                                                    (void *)&inl, sizeof(inl));
 654                                         raw += sizeof(inl);
 655                                         pkt_inline_sz += sizeof(inl);
 656                                 }
 657                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 658                                 addr += copy_b;
 659                                 length -= copy_b;
 660                                 pkt_inline_sz += copy_b;
 661                         }
 662                         /*
 663                          * 2 DWORDs consumed by the WQE header + ETH segment +
 664                          * the size of the inline part of the packet.
 665                          */
 666                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 667                         if (length > 0) {
 668                                 if (ds % (MLX5_WQE_SIZE /
 669                                           MLX5_WQE_DWORD_SIZE) == 0) {
 670                                         if (unlikely(--max_wqe == 0))
 671                                                 break;
 672                                         dseg = (volatile rte_v128u32_t *)
 673                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 674                                                            ds / 4);
 675                                 } else {
 676                                         dseg = (volatile rte_v128u32_t *)
 677                                                 ((uintptr_t)wqe +
 678                                                  (ds * MLX5_WQE_DWORD_SIZE));
 679                                 }
 680                                 goto use_dseg;
 681                         } else if (!segs_n) {
 682                                 goto next_pkt;
 683                         } else {
 684                                 /* dseg will be advance as part of next_seg */
 685                                 dseg = (volatile rte_v128u32_t *)
 686                                         ((uintptr_t)wqe +
 687                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 688                                 goto next_seg;
 689                         }
 690                 } else {
 691                         /*
 692                          * No inline has been done in the packet, only the
 693                          * Ethernet Header as been stored.
 694                          */
 695                         dseg = (volatile rte_v128u32_t *)
 696                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 697                         ds = 3;
 698 use_dseg:
 699                         /* Add the remaining packet as a simple ds. */
 700                         naddr = htonll(addr);
 701                         *dseg = (rte_v128u32_t){
 702                                 htonl(length),
 703                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 704                                 naddr,
 705                                 naddr >> 32,
 706                         };
 707                         ++ds;
 708                         if (!segs_n)
 709                                 goto next_pkt;
 710                 }
 711 next_seg:
 712                 assert(buf);
 713                 assert(ds);
 714                 assert(wqe);
 715                 /*
 716                  * Spill on next WQE when the current one does not have
 717                  * enough room left. Size of WQE must a be a multiple
 718                  * of data segment size.
 719                  */
 720                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 721                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 722                         if (unlikely(--max_wqe == 0))
 723                                 break;
 724                         dseg = (volatile rte_v128u32_t *)
 725                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 726                         rte_prefetch0(tx_mlx5_wqe(txq,
 727                                                   txq->wqe_ci + ds / 4 + 1));
 728                 } else {
 729                         ++dseg;
 730                 }
 731                 ++ds;
 732                 buf = buf->next;
 733                 assert(buf);
 734                 length = DATA_LEN(buf);
 735 #ifdef MLX5_PMD_SOFT_COUNTERS
 736                 total_length += length;
 737 #endif
 738                 /* Store segment information. */
 739                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 740                 *dseg = (rte_v128u32_t){
 741                         htonl(length),
 742                         txq_mp2mr(txq, txq_mb2mp(buf)),
 743                         naddr,
 744                         naddr >> 32,
 745                 };
 746                 (*txq->elts)[elts_head] = buf;
 747                 elts_head = (elts_head + 1) & (elts_n - 1);
 748                 ++j;
 749                 --segs_n;
 750                 if (segs_n)
 751                         goto next_seg;
 752                 else
 753                         --pkts_n;
 754 next_pkt:
 755                 ++i;
 756                 /* Initialize known and common part of the WQE structure. */
 757                 if (tso) {
 758                         wqe->ctrl = (rte_v128u32_t){
 759                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 760                                 htonl(txq->qp_num_8s | ds),
 761                                 0,
 762                                 0,
 763                         };
 764                         wqe->eseg = (rte_v128u32_t){
 765                                 0,
 766                                 cs_flags | (htons(buf->tso_segsz) << 16),
 767                                 0,
 768                                 (ehdr << 16) | htons(tso_header_sz),
 769                         };
 770                 } else {
 771                         wqe->ctrl = (rte_v128u32_t){
 772                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 773                                 htonl(txq->qp_num_8s | ds),
 774                                 0,
 775                                 0,
 776                         };
 777                         wqe->eseg = (rte_v128u32_t){
 778                                 0,
 779                                 cs_flags,
 780                                 0,
 781                                 (ehdr << 16) | htons(pkt_inline_sz),
 782                         };
 783                 }
 784 next_wqe:
 785                 txq->wqe_ci += (ds + 3) / 4;
 786 #ifdef MLX5_PMD_SOFT_COUNTERS
 787                 /* Increment sent bytes counter. */
 788                 txq->stats.obytes += total_length;
 789 #endif
 790         } while (pkts_n);
 791         /* Take a shortcut if nothing must be sent. */
 792         if (unlikely((i + k) == 0))
 793                 return 0;
 794         /* Check whether completion threshold has been reached. */
 795         comp = txq->elts_comp + i + j + k;
 796         if (comp >= MLX5_TX_COMP_THRESH) {
 797                 volatile struct mlx5_wqe_ctrl *w =
 798                         (volatile struct mlx5_wqe_ctrl *)wqe;
 799
 800                 /* Request completion on last WQE. */
 801                 w->ctrl2 = htonl(8);
 802                 /* Save elts_head in unused "immediate" field of WQE. */
 803                 w->ctrl3 = elts_head;
 804                 txq->elts_comp = 0;
 805         } else {
 806                 txq->elts_comp = comp;
 807         }
 808 #ifdef MLX5_PMD_SOFT_COUNTERS
 809         /* Increment sent packets counter. */
 810         txq->stats.opackets += i;
 811 #endif
 812         /* Ring QP doorbell. */
 813         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
 814         txq->elts_head = elts_head;
 815         return i;
 816 }
 817
 818 /**
 819  * Open a MPW session.
 820  *
 821  * @param txq
 822  *   Pointer to TX queue structure.
 823  * @param mpw
 824  *   Pointer to MPW session structure.
 825  * @param length
 826  *   Packet length.
 827  */
 828 static inline void
 829 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 830 {
 831         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 832         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 833                 (volatile struct mlx5_wqe_data_seg (*)[])
 834                 tx_mlx5_wqe(txq, idx + 1);
 835
 836         mpw->state = MLX5_MPW_STATE_OPENED;
 837         mpw->pkts_n = 0;
 838         mpw->len = length;
 839         mpw->total_len = 0;
 840         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 841         mpw->wqe->eseg.mss = htons(length);
 842         mpw->wqe->eseg.inline_hdr_sz = 0;
 843         mpw->wqe->eseg.rsvd0 = 0;
 844         mpw->wqe->eseg.rsvd1 = 0;
 845         mpw->wqe->eseg.rsvd2 = 0;
 846         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 847                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 848         mpw->wqe->ctrl[2] = 0;
 849         mpw->wqe->ctrl[3] = 0;
 850         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 851                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 852         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 853                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 854         mpw->data.dseg[2] = &(*dseg)[0];
 855         mpw->data.dseg[3] = &(*dseg)[1];
 856         mpw->data.dseg[4] = &(*dseg)[2];
 857 }
 858
 859 /**
 860  * Close a MPW session.
 861  *
 862  * @param txq
 863  *   Pointer to TX queue structure.
 864  * @param mpw
 865  *   Pointer to MPW session structure.
 866  */
 867 static inline void
 868 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 869 {
 870         unsigned int num = mpw->pkts_n;
 871
 872         /*
 873          * Store size in multiple of 16 bytes. Control and Ethernet segments
 874          * count as 2.
 875          */
 876         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 877         mpw->state = MLX5_MPW_STATE_CLOSED;
 878         if (num < 3)
 879                 ++txq->wqe_ci;
 880         else
 881                 txq->wqe_ci += 2;
 882         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 883         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 884 }
 885
 886 /**
 887  * DPDK callback for TX with MPW support.
 888  *
 889  * @param dpdk_txq
 890  *   Generic pointer to TX queue structure.
 891  * @param[in] pkts
 892  *   Packets to transmit.
 893  * @param pkts_n
 894  *   Number of packets in array.
 895  *
 896  * @return
 897  *   Number of packets successfully transmitted (<= pkts_n).
 898  */
 899 uint16_t
 900 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 901 {
 902         struct txq *txq = (struct txq *)dpdk_txq;
 903         uint16_t elts_head = txq->elts_head;
 904         const unsigned int elts_n = 1 << txq->elts_n;
 905         unsigned int i = 0;
 906         unsigned int j = 0;
 907         unsigned int max;
 908         uint16_t max_wqe;
 909         unsigned int comp;
 910         struct mlx5_mpw mpw = {
 911                 .state = MLX5_MPW_STATE_CLOSED,
 912         };
 913
 914         if (unlikely(!pkts_n))
 915                 return 0;
 916         /* Prefetch first packet cacheline. */
 917         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 918         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 919         /* Start processing. */
 920         txq_complete(txq);
 921         max = (elts_n - (elts_head - txq->elts_tail));
 922         if (max > elts_n)
 923                 max -= elts_n;
 924         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 925         if (unlikely(!max_wqe))
 926                 return 0;
 927         do {
 928                 struct rte_mbuf *buf = *(pkts++);
 929                 unsigned int elts_head_next;
 930                 uint32_t length;
 931                 unsigned int segs_n = buf->nb_segs;
 932                 uint32_t cs_flags = 0;
 933
 934                 /*
 935                  * Make sure there is enough room to store this packet and
 936                  * that one ring entry remains unused.
 937                  */
 938                 assert(segs_n);
 939                 if (max < segs_n + 1)
 940                         break;
 941                 /* Do not bother with large packets MPW cannot handle. */
 942                 if (segs_n > MLX5_MPW_DSEG_MAX)
 943                         break;
 944                 max -= segs_n;
 945                 --pkts_n;
 946                 /* Should we enable HW CKSUM offload */
 947                 if (buf->ol_flags &
 948                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 949                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 950                 /* Retrieve packet information. */
 951                 length = PKT_LEN(buf);
 952                 assert(length);
 953                 /* Start new session if packet differs. */
 954                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 955                     ((mpw.len != length) ||
 956                      (segs_n != 1) ||
 957                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 958                         mlx5_mpw_close(txq, &mpw);
 959                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 960                         /*
 961                          * Multi-Packet WQE consumes at most two WQE.
 962                          * mlx5_mpw_new() expects to be able to use such
 963                          * resources.
 964                          */
 965                         if (unlikely(max_wqe < 2))
 966                                 break;
 967                         max_wqe -= 2;
 968                         mlx5_mpw_new(txq, &mpw, length);
 969                         mpw.wqe->eseg.cs_flags = cs_flags;
 970                 }
 971                 /* Multi-segment packets must be alone in their MPW. */
 972                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 973 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 974                 length = 0;
 975 #endif
 976                 do {
 977                         volatile struct mlx5_wqe_data_seg *dseg;
 978                         uintptr_t addr;
 979
 980                         elts_head_next = (elts_head + 1) & (elts_n - 1);
 981                         assert(buf);
 982                         (*txq->elts)[elts_head] = buf;
 983                         dseg = mpw.data.dseg[mpw.pkts_n];
 984                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 985                         *dseg = (struct mlx5_wqe_data_seg){
 986                                 .byte_count = htonl(DATA_LEN(buf)),
 987                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
 988                                 .addr = htonll(addr),
 989                         };
 990                         elts_head = elts_head_next;
 991 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 992                         length += DATA_LEN(buf);
 993 #endif
 994                         buf = buf->next;
 995                         ++mpw.pkts_n;
 996                         ++j;
 997                 } while (--segs_n);
 998                 assert(length == mpw.len);
 999                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1000                         mlx5_mpw_close(txq, &mpw);
1001                 elts_head = elts_head_next;
1002 #ifdef MLX5_PMD_SOFT_COUNTERS
1003                 /* Increment sent bytes counter. */
1004                 txq->stats.obytes += length;
1005 #endif
1006                 ++i;
1007         } while (pkts_n);
1008         /* Take a shortcut if nothing must be sent. */
1009         if (unlikely(i == 0))
1010                 return 0;
1011         /* Check whether completion threshold has been reached. */
1012         /* "j" includes both packets and segments. */
1013         comp = txq->elts_comp + j;
1014         if (comp >= MLX5_TX_COMP_THRESH) {
1015                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1016
1017                 /* Request completion on last WQE. */
1018                 wqe->ctrl[2] = htonl(8);
1019                 /* Save elts_head in unused "immediate" field of WQE. */
1020                 wqe->ctrl[3] = elts_head;
1021                 txq->elts_comp = 0;
1022         } else {
1023                 txq->elts_comp = comp;
1024         }
1025 #ifdef MLX5_PMD_SOFT_COUNTERS
1026         /* Increment sent packets counter. */
1027         txq->stats.opackets += i;
1028 #endif
1029         /* Ring QP doorbell. */
1030         if (mpw.state == MLX5_MPW_STATE_OPENED)
1031                 mlx5_mpw_close(txq, &mpw);
1032         mlx5_tx_dbrec(txq, mpw.wqe);
1033         txq->elts_head = elts_head;
1034         return i;
1035 }
1036
1037 /**
1038  * Open a MPW inline session.
1039  *
1040  * @param txq
1041  *   Pointer to TX queue structure.
1042  * @param mpw
1043  *   Pointer to MPW session structure.
1044  * @param length
1045  *   Packet length.
1046  */
1047 static inline void
1048 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1049 {
1050         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1051         struct mlx5_wqe_inl_small *inl;
1052
1053         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1054         mpw->pkts_n = 0;
1055         mpw->len = length;
1056         mpw->total_len = 0;
1057         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1058         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1059                                   (txq->wqe_ci << 8) |
1060                                   MLX5_OPCODE_TSO);
1061         mpw->wqe->ctrl[2] = 0;
1062         mpw->wqe->ctrl[3] = 0;
1063         mpw->wqe->eseg.mss = htons(length);
1064         mpw->wqe->eseg.inline_hdr_sz = 0;
1065         mpw->wqe->eseg.cs_flags = 0;
1066         mpw->wqe->eseg.rsvd0 = 0;
1067         mpw->wqe->eseg.rsvd1 = 0;
1068         mpw->wqe->eseg.rsvd2 = 0;
1069         inl = (struct mlx5_wqe_inl_small *)
1070                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1071         mpw->data.raw = (uint8_t *)&inl->raw;
1072 }
1073
1074 /**
1075  * Close a MPW inline session.
1076  *
1077  * @param txq
1078  *   Pointer to TX queue structure.
1079  * @param mpw
1080  *   Pointer to MPW session structure.
1081  */
1082 static inline void
1083 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1084 {
1085         unsigned int size;
1086         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1087                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1088
1089         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1090         /*
1091          * Store size in multiple of 16 bytes. Control and Ethernet segments
1092          * count as 2.
1093          */
1094         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1095         mpw->state = MLX5_MPW_STATE_CLOSED;
1096         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1097         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1098 }
1099
1100 /**
1101  * DPDK callback for TX with MPW inline support.
1102  *
1103  * @param dpdk_txq
1104  *   Generic pointer to TX queue structure.
1105  * @param[in] pkts
1106  *   Packets to transmit.
1107  * @param pkts_n
1108  *   Number of packets in array.
1109  *
1110  * @return
1111  *   Number of packets successfully transmitted (<= pkts_n).
1112  */
1113 uint16_t
1114 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1115                          uint16_t pkts_n)
1116 {
1117         struct txq *txq = (struct txq *)dpdk_txq;
1118         uint16_t elts_head = txq->elts_head;
1119         const unsigned int elts_n = 1 << txq->elts_n;
1120         unsigned int i = 0;
1121         unsigned int j = 0;
1122         unsigned int max;
1123         uint16_t max_wqe;
1124         unsigned int comp;
1125         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1126         struct mlx5_mpw mpw = {
1127                 .state = MLX5_MPW_STATE_CLOSED,
1128         };
1129         /*
1130          * Compute the maximum number of WQE which can be consumed by inline
1131          * code.
1132          * - 2 DSEG for:
1133          *   - 1 control segment,
1134          *   - 1 Ethernet segment,
1135          * - N Dseg from the inline request.
1136          */
1137         const unsigned int wqe_inl_n =
1138                 ((2 * MLX5_WQE_DWORD_SIZE +
1139                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1140                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1141
1142         if (unlikely(!pkts_n))
1143                 return 0;
1144         /* Prefetch first packet cacheline. */
1145         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1146         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1147         /* Start processing. */
1148         txq_complete(txq);
1149         max = (elts_n - (elts_head - txq->elts_tail));
1150         if (max > elts_n)
1151                 max -= elts_n;
1152         do {
1153                 struct rte_mbuf *buf = *(pkts++);
1154                 unsigned int elts_head_next;
1155                 uintptr_t addr;
1156                 uint32_t length;
1157                 unsigned int segs_n = buf->nb_segs;
1158                 uint32_t cs_flags = 0;
1159
1160                 /*
1161                  * Make sure there is enough room to store this packet and
1162                  * that one ring entry remains unused.
1163                  */
1164                 assert(segs_n);
1165                 if (max < segs_n + 1)
1166                         break;
1167                 /* Do not bother with large packets MPW cannot handle. */
1168                 if (segs_n > MLX5_MPW_DSEG_MAX)
1169                         break;
1170                 max -= segs_n;
1171                 --pkts_n;
1172                 /*
1173                  * Compute max_wqe in case less WQE were consumed in previous
1174                  * iteration.
1175                  */
1176                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1177                 /* Should we enable HW CKSUM offload */
1178                 if (buf->ol_flags &
1179                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1180                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1181                 /* Retrieve packet information. */
1182                 length = PKT_LEN(buf);
1183                 /* Start new session if packet differs. */
1184                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1185                         if ((mpw.len != length) ||
1186                             (segs_n != 1) ||
1187                             (mpw.wqe->eseg.cs_flags != cs_flags))
1188                                 mlx5_mpw_close(txq, &mpw);
1189                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1190                         if ((mpw.len != length) ||
1191                             (segs_n != 1) ||
1192                             (length > inline_room) ||
1193                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1194                                 mlx5_mpw_inline_close(txq, &mpw);
1195                                 inline_room =
1196                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1197                         }
1198                 }
1199                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1200                         if ((segs_n != 1) ||
1201                             (length > inline_room)) {
1202                                 /*
1203                                  * Multi-Packet WQE consumes at most two WQE.
1204                                  * mlx5_mpw_new() expects to be able to use
1205                                  * such resources.
1206                                  */
1207                                 if (unlikely(max_wqe < 2))
1208                                         break;
1209                                 max_wqe -= 2;
1210                                 mlx5_mpw_new(txq, &mpw, length);
1211                                 mpw.wqe->eseg.cs_flags = cs_flags;
1212                         } else {
1213                                 if (unlikely(max_wqe < wqe_inl_n))
1214                                         break;
1215                                 max_wqe -= wqe_inl_n;
1216                                 mlx5_mpw_inline_new(txq, &mpw, length);
1217                                 mpw.wqe->eseg.cs_flags = cs_flags;
1218                         }
1219                 }
1220                 /* Multi-segment packets must be alone in their MPW. */
1221                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1222                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1223                         assert(inline_room ==
1224                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1225 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1226                         length = 0;
1227 #endif
1228                         do {
1229                                 volatile struct mlx5_wqe_data_seg *dseg;
1230
1231                                 elts_head_next =
1232                                         (elts_head + 1) & (elts_n - 1);
1233                                 assert(buf);
1234                                 (*txq->elts)[elts_head] = buf;
1235                                 dseg = mpw.data.dseg[mpw.pkts_n];
1236                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1237                                 *dseg = (struct mlx5_wqe_data_seg){
1238                                         .byte_count = htonl(DATA_LEN(buf)),
1239                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1240                                         .addr = htonll(addr),
1241                                 };
1242                                 elts_head = elts_head_next;
1243 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1244                                 length += DATA_LEN(buf);
1245 #endif
1246                                 buf = buf->next;
1247                                 ++mpw.pkts_n;
1248                                 ++j;
1249                         } while (--segs_n);
1250                         assert(length == mpw.len);
1251                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1252                                 mlx5_mpw_close(txq, &mpw);
1253                 } else {
1254                         unsigned int max;
1255
1256                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1257                         assert(length <= inline_room);
1258                         assert(length == DATA_LEN(buf));
1259                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1260                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1261                         (*txq->elts)[elts_head] = buf;
1262                         /* Maximum number of bytes before wrapping. */
1263                         max = ((((uintptr_t)(txq->wqes)) +
1264                                 (1 << txq->wqe_n) *
1265                                 MLX5_WQE_SIZE) -
1266                                (uintptr_t)mpw.data.raw);
1267                         if (length > max) {
1268                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1269                                            (void *)addr,
1270                                            max);
1271                                 mpw.data.raw = (volatile void *)txq->wqes;
1272                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1273                                            (void *)(addr + max),
1274                                            length - max);
1275                                 mpw.data.raw += length - max;
1276                         } else {
1277                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1278                                            (void *)addr,
1279                                            length);
1280
1281                                 if (length == max)
1282                                         mpw.data.raw =
1283                                                 (volatile void *)txq->wqes;
1284                                 else
1285                                         mpw.data.raw += length;
1286                         }
1287                         ++mpw.pkts_n;
1288                         mpw.total_len += length;
1289                         ++j;
1290                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1291                                 mlx5_mpw_inline_close(txq, &mpw);
1292                                 inline_room =
1293                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1294                         } else {
1295                                 inline_room -= length;
1296                         }
1297                 }
1298                 elts_head = elts_head_next;
1299 #ifdef MLX5_PMD_SOFT_COUNTERS
1300                 /* Increment sent bytes counter. */
1301                 txq->stats.obytes += length;
1302 #endif
1303                 ++i;
1304         } while (pkts_n);
1305         /* Take a shortcut if nothing must be sent. */
1306         if (unlikely(i == 0))
1307                 return 0;
1308         /* Check whether completion threshold has been reached. */
1309         /* "j" includes both packets and segments. */
1310         comp = txq->elts_comp + j;
1311         if (comp >= MLX5_TX_COMP_THRESH) {
1312                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1313
1314                 /* Request completion on last WQE. */
1315                 wqe->ctrl[2] = htonl(8);
1316                 /* Save elts_head in unused "immediate" field of WQE. */
1317                 wqe->ctrl[3] = elts_head;
1318                 txq->elts_comp = 0;
1319         } else {
1320                 txq->elts_comp = comp;
1321         }
1322 #ifdef MLX5_PMD_SOFT_COUNTERS
1323         /* Increment sent packets counter. */
1324         txq->stats.opackets += i;
1325 #endif
1326         /* Ring QP doorbell. */
1327         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1328                 mlx5_mpw_inline_close(txq, &mpw);
1329         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1330                 mlx5_mpw_close(txq, &mpw);
1331         mlx5_tx_dbrec(txq, mpw.wqe);
1332         txq->elts_head = elts_head;
1333         return i;
1334 }
1335
1336 /**
1337  * Translate RX completion flags to packet type.
1338  *
1339  * @param[in] cqe
1340  *   Pointer to CQE.
1341  *
1342  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1343  *
1344  * @return
1345  *   Packet type for struct rte_mbuf.
1346  */
1347 static inline uint32_t
1348 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1349 {
1350         uint32_t pkt_type;
1351         uint16_t flags = ntohs(cqe->hdr_type_etc);
1352
1353         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1354                 pkt_type =
1355                         TRANSPOSE(flags,
1356                                   MLX5_CQE_RX_IPV4_PACKET,
1357                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1358                         TRANSPOSE(flags,
1359                                   MLX5_CQE_RX_IPV6_PACKET,
1360                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1361                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1362                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1363                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1364         } else {
1365                 pkt_type =
1366                         TRANSPOSE(flags,
1367                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1368                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1369                         TRANSPOSE(flags,
1370                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1371                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1372         }
1373         return pkt_type;
1374 }
1375
1376 /**
1377  * Get size of the next packet for a given CQE. For compressed CQEs, the
1378  * consumer index is updated only once all packets of the current one have
1379  * been processed.
1380  *
1381  * @param rxq
1382  *   Pointer to RX queue.
1383  * @param cqe
1384  *   CQE to process.
1385  * @param[out] rss_hash
1386  *   Packet RSS Hash result.
1387  *
1388  * @return
1389  *   Packet size in bytes (0 if there is none), -1 in case of completion
1390  *   with error.
1391  */
1392 static inline int
1393 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1394                  uint16_t cqe_cnt, uint32_t *rss_hash)
1395 {
1396         struct rxq_zip *zip = &rxq->zip;
1397         uint16_t cqe_n = cqe_cnt + 1;
1398         int len = 0;
1399         uint16_t idx, end;
1400
1401         /* Process compressed data in the CQE and mini arrays. */
1402         if (zip->ai) {
1403                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1404                         (volatile struct mlx5_mini_cqe8 (*)[8])
1405                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1406
1407                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1408                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1409                 if ((++zip->ai & 7) == 0) {
1410                         /* Invalidate consumed CQEs */
1411                         idx = zip->ca;
1412                         end = zip->na;
1413                         while (idx != end) {
1414                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1415                                         MLX5_CQE_INVALIDATE;
1416                                 ++idx;
1417                         }
1418                         /*
1419                          * Increment consumer index to skip the number of
1420                          * CQEs consumed. Hardware leaves holes in the CQ
1421                          * ring for software use.
1422                          */
1423                         zip->ca = zip->na;
1424                         zip->na += 8;
1425                 }
1426                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1427                         /* Invalidate the rest */
1428                         idx = zip->ca;
1429                         end = zip->cq_ci;
1430
1431                         while (idx != end) {
1432                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1433                                         MLX5_CQE_INVALIDATE;
1434                                 ++idx;
1435                         }
1436                         rxq->cq_ci = zip->cq_ci;
1437                         zip->ai = 0;
1438                 }
1439         /* No compressed data, get next CQE and verify if it is compressed. */
1440         } else {
1441                 int ret;
1442                 int8_t op_own;
1443
1444                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1445                 if (unlikely(ret == 1))
1446                         return 0;
1447                 ++rxq->cq_ci;
1448                 op_own = cqe->op_own;
1449                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1450                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1451                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1452                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1453                                                           cqe_cnt]);
1454
1455                         /* Fix endianness. */
1456                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1457                         /*
1458                          * Current mini array position is the one returned by
1459                          * check_cqe64().
1460                          *
1461                          * If completion comprises several mini arrays, as a
1462                          * special case the second one is located 7 CQEs after
1463                          * the initial CQE instead of 8 for subsequent ones.
1464                          */
1465                         zip->ca = rxq->cq_ci;
1466                         zip->na = zip->ca + 7;
1467                         /* Compute the next non compressed CQE. */
1468                         --rxq->cq_ci;
1469                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1470                         /* Get packet size to return. */
1471                         len = ntohl((*mc)[0].byte_cnt);
1472                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1473                         zip->ai = 1;
1474                         /* Prefetch all the entries to be invalidated */
1475                         idx = zip->ca;
1476                         end = zip->cq_ci;
1477                         while (idx != end) {
1478                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1479                                 ++idx;
1480                         }
1481                 } else {
1482                         len = ntohl(cqe->byte_cnt);
1483                         *rss_hash = ntohl(cqe->rx_hash_res);
1484                 }
1485                 /* Error while receiving packet. */
1486                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1487                         return -1;
1488         }
1489         return len;
1490 }
1491
1492 /**
1493  * Translate RX completion flags to offload flags.
1494  *
1495  * @param[in] rxq
1496  *   Pointer to RX queue structure.
1497  * @param[in] cqe
1498  *   Pointer to CQE.
1499  *
1500  * @return
1501  *   Offload flags (ol_flags) for struct rte_mbuf.
1502  */
1503 static inline uint32_t
1504 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1505 {
1506         uint32_t ol_flags = 0;
1507         uint16_t flags = ntohs(cqe->hdr_type_etc);
1508
1509         ol_flags =
1510                 TRANSPOSE(flags,
1511                           MLX5_CQE_RX_L3_HDR_VALID,
1512                           PKT_RX_IP_CKSUM_GOOD) |
1513                 TRANSPOSE(flags,
1514                           MLX5_CQE_RX_L4_HDR_VALID,
1515                           PKT_RX_L4_CKSUM_GOOD);
1516         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1517                 ol_flags |=
1518                         TRANSPOSE(flags,
1519                                   MLX5_CQE_RX_L3_HDR_VALID,
1520                                   PKT_RX_IP_CKSUM_GOOD) |
1521                         TRANSPOSE(flags,
1522                                   MLX5_CQE_RX_L4_HDR_VALID,
1523                                   PKT_RX_L4_CKSUM_GOOD);
1524         return ol_flags;
1525 }
1526
1527 /**
1528  * DPDK callback for RX.
1529  *
1530  * @param dpdk_rxq
1531  *   Generic pointer to RX queue structure.
1532  * @param[out] pkts
1533  *   Array to store received packets.
1534  * @param pkts_n
1535  *   Maximum number of packets in array.
1536  *
1537  * @return
1538  *   Number of packets successfully received (<= pkts_n).
1539  */
1540 uint16_t
1541 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1542 {
1543         struct rxq *rxq = dpdk_rxq;
1544         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1545         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1546         const unsigned int sges_n = rxq->sges_n;
1547         struct rte_mbuf *pkt = NULL;
1548         struct rte_mbuf *seg = NULL;
1549         volatile struct mlx5_cqe *cqe =
1550                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1551         unsigned int i = 0;
1552         unsigned int rq_ci = rxq->rq_ci << sges_n;
1553         int len; /* keep its value across iterations. */
1554
1555         while (pkts_n) {
1556                 unsigned int idx = rq_ci & wqe_cnt;
1557                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1558                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1559                 uint32_t rss_hash_res = 0;
1560
1561                 if (pkt)
1562                         NEXT(seg) = rep;
1563                 seg = rep;
1564                 rte_prefetch0(seg);
1565                 rte_prefetch0(cqe);
1566                 rte_prefetch0(wqe);
1567                 rep = rte_mbuf_raw_alloc(rxq->mp);
1568                 if (unlikely(rep == NULL)) {
1569                         ++rxq->stats.rx_nombuf;
1570                         if (!pkt) {
1571                                 /*
1572                                  * no buffers before we even started,
1573                                  * bail out silently.
1574                                  */
1575                                 break;
1576                         }
1577                         while (pkt != seg) {
1578                                 assert(pkt != (*rxq->elts)[idx]);
1579                                 rep = NEXT(pkt);
1580                                 rte_mbuf_refcnt_set(pkt, 0);
1581                                 __rte_mbuf_raw_free(pkt);
1582                                 pkt = rep;
1583                         }
1584                         break;
1585                 }
1586                 if (!pkt) {
1587                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1588                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1589                                                &rss_hash_res);
1590                         if (!len) {
1591                                 rte_mbuf_refcnt_set(rep, 0);
1592                                 __rte_mbuf_raw_free(rep);
1593                                 break;
1594                         }
1595                         if (unlikely(len == -1)) {
1596                                 /* RX error, packet is likely too large. */
1597                                 rte_mbuf_refcnt_set(rep, 0);
1598                                 __rte_mbuf_raw_free(rep);
1599                                 ++rxq->stats.idropped;
1600                                 goto skip;
1601                         }
1602                         pkt = seg;
1603                         assert(len >= (rxq->crc_present << 2));
1604                         /* Update packet information. */
1605                         pkt->packet_type = 0;
1606                         pkt->ol_flags = 0;
1607                         if (rss_hash_res && rxq->rss_hash) {
1608                                 pkt->hash.rss = rss_hash_res;
1609                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1610                         }
1611                         if (rxq->mark && (cqe->sop_drop_qpn !=
1612                                           htonl(MLX5_FLOW_MARK_INVALID))) {
1613                                 pkt->ol_flags |= PKT_RX_FDIR;
1614                                 if (cqe->sop_drop_qpn !=
1615                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1616                                         uint32_t mark = cqe->sop_drop_qpn;
1617
1618                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1619                                         pkt->hash.fdir.hi =
1620                                                 mlx5_flow_mark_get(mark);
1621                                 }
1622                         }
1623                         if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1624                             rxq->crc_present) {
1625                                 if (rxq->csum) {
1626                                         pkt->packet_type =
1627                                                 rxq_cq_to_pkt_type(cqe);
1628                                         pkt->ol_flags |=
1629                                                 rxq_cq_to_ol_flags(rxq, cqe);
1630                                 }
1631                                 if (ntohs(cqe->hdr_type_etc) &
1632                                     MLX5_CQE_VLAN_STRIPPED) {
1633                                         pkt->ol_flags |= PKT_RX_VLAN_PKT |
1634                                                 PKT_RX_VLAN_STRIPPED;
1635                                         pkt->vlan_tci = ntohs(cqe->vlan_info);
1636                                 }
1637                                 if (rxq->crc_present)
1638                                         len -= ETHER_CRC_LEN;
1639                         }
1640                         PKT_LEN(pkt) = len;
1641                 }
1642                 DATA_LEN(rep) = DATA_LEN(seg);
1643                 PKT_LEN(rep) = PKT_LEN(seg);
1644                 SET_DATA_OFF(rep, DATA_OFF(seg));
1645                 NB_SEGS(rep) = NB_SEGS(seg);
1646                 PORT(rep) = PORT(seg);
1647                 NEXT(rep) = NULL;
1648                 (*rxq->elts)[idx] = rep;
1649                 /*
1650                  * Fill NIC descriptor with the new buffer.  The lkey and size
1651                  * of the buffers are already known, only the buffer address
1652                  * changes.
1653                  */
1654                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1655                 if (len > DATA_LEN(seg)) {
1656                         len -= DATA_LEN(seg);
1657                         ++NB_SEGS(pkt);
1658                         ++rq_ci;
1659                         continue;
1660                 }
1661                 DATA_LEN(seg) = len;
1662 #ifdef MLX5_PMD_SOFT_COUNTERS
1663                 /* Increment bytes counter. */
1664                 rxq->stats.ibytes += PKT_LEN(pkt);
1665 #endif
1666                 /* Return packet. */
1667                 *(pkts++) = pkt;
1668                 pkt = NULL;
1669                 --pkts_n;
1670                 ++i;
1671 skip:
1672                 /* Align consumer index to the next stride. */
1673                 rq_ci >>= sges_n;
1674                 ++rq_ci;
1675                 rq_ci <<= sges_n;
1676         }
1677         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1678                 return 0;
1679         /* Update the consumer index. */
1680         rxq->rq_ci = rq_ci >> sges_n;
1681         rte_wmb();
1682         *rxq->cq_db = htonl(rxq->cq_ci);
1683         rte_wmb();
1684         *rxq->rq_db = htonl(rxq->rq_ci);
1685 #ifdef MLX5_PMD_SOFT_COUNTERS
1686         /* Increment packets counter. */
1687         rxq->stats.ipackets += i;
1688 #endif
1689         return i;
1690 }
1691
1692 /**
1693  * Dummy DPDK callback for TX.
1694  *
1695  * This function is used to temporarily replace the real callback during
1696  * unsafe control operations on the queue, or in case of error.
1697  *
1698  * @param dpdk_txq
1699  *   Generic pointer to TX queue structure.
1700  * @param[in] pkts
1701  *   Packets to transmit.
1702  * @param pkts_n
1703  *   Number of packets in array.
1704  *
1705  * @return
1706  *   Number of packets successfully transmitted (<= pkts_n).
1707  */
1708 uint16_t
1709 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1710 {
1711         (void)dpdk_txq;
1712         (void)pkts;
1713         (void)pkts_n;
1714         return 0;
1715 }
1716
1717 /**
1718  * Dummy DPDK callback for RX.
1719  *
1720  * This function is used to temporarily replace the real callback during
1721  * unsafe control operations on the queue, or in case of error.
1722  *
1723  * @param dpdk_rxq
1724  *   Generic pointer to RX queue structure.
1725  * @param[out] pkts
1726  *   Array to store received packets.
1727  * @param pkts_n
1728  *   Maximum number of packets in array.
1729  *
1730  * @return
1731  *   Number of packets successfully received (<= pkts_n).
1732  */
1733 uint16_t
1734 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1735 {
1736         (void)dpdk_rxq;
1737         (void)pkts;
1738         (void)pkts_n;
1739         return 0;
1740 }