drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5dv.h>
  46 #ifdef PEDANTIC
  47 #pragma GCC diagnostic error "-Wpedantic"
  48 #endif
  49
  50 #include <rte_mbuf.h>
  51 #include <rte_mempool.h>
  52 #include <rte_prefetch.h>
  53 #include <rte_common.h>
  54 #include <rte_branch_prediction.h>
  55 #include <rte_ether.h>
  56
  57 #include "mlx5.h"
  58 #include "mlx5_utils.h"
  59 #include "mlx5_rxtx.h"
  60 #include "mlx5_autoconf.h"
  61 #include "mlx5_defs.h"
  62 #include "mlx5_prm.h"
  63
  64 static __rte_always_inline uint32_t
  65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  66
  67 static __rte_always_inline int
  68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  69                  uint16_t cqe_cnt, uint32_t *rss_hash);
  70
  71 static __rte_always_inline uint32_t
  72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  73
  74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  75         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  76 };
  77
  78 /**
  79  * Build a table to translate Rx completion flags to packet type.
  80  *
  81  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  82  */
  83 void
  84 mlx5_set_ptype_table(void)
  85 {
  86         unsigned int i;
  87         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  88
  89         /* Last entry must not be overwritten, reserved for errored packet. */
  90         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  91                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  92         /*
  93          * The index to the array should have:
  94          * bit[1:0] = l3_hdr_type
  95          * bit[4:2] = l4_hdr_type
  96          * bit[5] = ip_frag
  97          * bit[6] = tunneled
  98          * bit[7] = outer_l3_type
  99          */
 100         /* L2 */
 101         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
 102         /* L3 */
 103         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         /* Fragmented */
 108         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_FRAG;
 110         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         /* TCP */
 113         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         /* UDP */
 118         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_UDP;
 120         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_UDP;
 122         /* Repeat with outer_l3_type being set. Just in case. */
 123         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_NONFRAG;
 125         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_NONFRAG;
 127         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_FRAG;
 129         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_FRAG;
 131         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_TCP;
 135         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 138                      RTE_PTYPE_L4_UDP;
 139         /* Tunneled - L3 */
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         /* Tunneled - UDP */
 179         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_UDP;
 182         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_UDP;
 185         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_UDP;
 188         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_UDP;
 191 }
 192
 193 /**
 194  * Return the size of tailroom of WQ.
 195  *
 196  * @param txq
 197  *   Pointer to TX queue structure.
 198  * @param addr
 199  *   Pointer to tail of WQ.
 200  *
 201  * @return
 202  *   Size of tailroom.
 203  */
 204 static inline size_t
 205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 206 {
 207         size_t tailroom;
 208         tailroom = (uintptr_t)(txq->wqes) +
 209                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 210                    (uintptr_t)addr;
 211         return tailroom;
 212 }
 213
 214 /**
 215  * Copy data to tailroom of circular queue.
 216  *
 217  * @param dst
 218  *   Pointer to destination.
 219  * @param src
 220  *   Pointer to source.
 221  * @param n
 222  *   Number of bytes to copy.
 223  * @param base
 224  *   Pointer to head of queue.
 225  * @param tailroom
 226  *   Size of tailroom from dst.
 227  *
 228  * @return
 229  *   Pointer after copied data.
 230  */
 231 static inline void *
 232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 233                 void *base, size_t tailroom)
 234 {
 235         void *ret;
 236
 237         if (n > tailroom) {
 238                 rte_memcpy(dst, src, tailroom);
 239                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 240                            n - tailroom);
 241                 ret = (uint8_t *)base + n - tailroom;
 242         } else {
 243                 rte_memcpy(dst, src, n);
 244                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 245         }
 246         return ret;
 247 }
 248
 249 /**
 250  * DPDK callback to check the status of a tx descriptor.
 251  *
 252  * @param tx_queue
 253  *   The tx queue.
 254  * @param[in] offset
 255  *   The index of the descriptor in the ring.
 256  *
 257  * @return
 258  *   The status of the tx descriptor.
 259  */
 260 int
 261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 262 {
 263         struct mlx5_txq_data *txq = tx_queue;
 264         uint16_t used;
 265
 266         mlx5_tx_complete(txq);
 267         used = txq->elts_head - txq->elts_tail;
 268         if (offset < used)
 269                 return RTE_ETH_TX_DESC_FULL;
 270         return RTE_ETH_TX_DESC_DONE;
 271 }
 272
 273 /**
 274  * DPDK callback to check the status of a rx descriptor.
 275  *
 276  * @param rx_queue
 277  *   The rx queue.
 278  * @param[in] offset
 279  *   The index of the descriptor in the ring.
 280  *
 281  * @return
 282  *   The status of the tx descriptor.
 283  */
 284 int
 285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 286 {
 287         struct mlx5_rxq_data *rxq = rx_queue;
 288         struct rxq_zip *zip = &rxq->zip;
 289         volatile struct mlx5_cqe *cqe;
 290         const unsigned int cqe_n = (1 << rxq->cqe_n);
 291         const unsigned int cqe_cnt = cqe_n - 1;
 292         unsigned int cq_ci;
 293         unsigned int used;
 294
 295         /* if we are processing a compressed cqe */
 296         if (zip->ai) {
 297                 used = zip->cqe_cnt - zip->ca;
 298                 cq_ci = zip->cq_ci;
 299         } else {
 300                 used = 0;
 301                 cq_ci = rxq->cq_ci;
 302         }
 303         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 304         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 305                 int8_t op_own;
 306                 unsigned int n;
 307
 308                 op_own = cqe->op_own;
 309                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 310                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 311                 else
 312                         n = 1;
 313                 cq_ci += n;
 314                 used += n;
 315                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 316         }
 317         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 318         if (offset < used)
 319                 return RTE_ETH_RX_DESC_DONE;
 320         return RTE_ETH_RX_DESC_AVAIL;
 321 }
 322
 323 /**
 324  * DPDK callback for TX.
 325  *
 326  * @param dpdk_txq
 327  *   Generic pointer to TX queue structure.
 328  * @param[in] pkts
 329  *   Packets to transmit.
 330  * @param pkts_n
 331  *   Number of packets in array.
 332  *
 333  * @return
 334  *   Number of packets successfully transmitted (<= pkts_n).
 335  */
 336 uint16_t
 337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 338 {
 339         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 340         uint16_t elts_head = txq->elts_head;
 341         const uint16_t elts_n = 1 << txq->elts_n;
 342         const uint16_t elts_m = elts_n - 1;
 343         unsigned int i = 0;
 344         unsigned int j = 0;
 345         unsigned int k = 0;
 346         uint16_t max_elts;
 347         uint16_t max_wqe;
 348         unsigned int comp;
 349         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 350         unsigned int segs_n = 0;
 351         const unsigned int max_inline = txq->max_inline;
 352
 353         if (unlikely(!pkts_n))
 354                 return 0;
 355         /* Prefetch first packet cacheline. */
 356         rte_prefetch0(*pkts);
 357         /* Start processing. */
 358         mlx5_tx_complete(txq);
 359         max_elts = (elts_n - (elts_head - txq->elts_tail));
 360         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 361         if (unlikely(!max_wqe))
 362                 return 0;
 363         do {
 364                 struct rte_mbuf *buf = NULL;
 365                 uint8_t *raw;
 366                 volatile struct mlx5_wqe_v *wqe = NULL;
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 373                 uint16_t tso_header_sz = 0;
 374                 uint16_t ehdr;
 375                 uint8_t cs_flags;
 376                 uint64_t tso = 0;
 377                 uint16_t tso_segsz = 0;
 378 #ifdef MLX5_PMD_SOFT_COUNTERS
 379                 uint32_t total_length = 0;
 380 #endif
 381
 382                 /* first_seg */
 383                 buf = *pkts;
 384                 segs_n = buf->nb_segs;
 385                 /*
 386                  * Make sure there is enough room to store this packet and
 387                  * that one ring entry remains unused.
 388                  */
 389                 assert(segs_n);
 390                 if (max_elts < segs_n)
 391                         break;
 392                 max_elts -= segs_n;
 393                 sg = --segs_n;
 394                 if (unlikely(--max_wqe == 0))
 395                         break;
 396                 wqe = (volatile struct mlx5_wqe_v *)
 397                         tx_mlx5_wqe(txq, txq->wqe_ci);
 398                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 399                 if (pkts_n - i > 1)
 400                         rte_prefetch0(*(pkts + 1));
 401                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 402                 length = DATA_LEN(buf);
 403                 ehdr = (((uint8_t *)addr)[1] << 8) |
 404                        ((uint8_t *)addr)[0];
 405 #ifdef MLX5_PMD_SOFT_COUNTERS
 406                 total_length = length;
 407 #endif
 408                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 409                         txq->stats.oerrors++;
 410                         break;
 411                 }
 412                 /* Update element. */
 413                 (*txq->elts)[elts_head & elts_m] = buf;
 414                 /* Prefetch next buffer data. */
 415                 if (pkts_n - i > 1)
 416                         rte_prefetch0(
 417                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 418                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 419                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 420                 /* Replace the Ethernet type by the VLAN if necessary. */
 421                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 422                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 423                                                          buf->vlan_tci);
 424                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 425
 426                         addr += 2;
 427                         length -= 2;
 428                         /* Copy Destination and source mac address. */
 429                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 430                         /* Copy VLAN. */
 431                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 432                         /* Copy missing two bytes to end the DSeg. */
 433                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 434                                ((uint8_t *)addr) + len, 2);
 435                         addr += len + 2;
 436                         length -= (len + 2);
 437                 } else {
 438                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 439                                MLX5_WQE_DWORD_SIZE);
 440                         length -= pkt_inline_sz;
 441                         addr += pkt_inline_sz;
 442                 }
 443                 raw += MLX5_WQE_DWORD_SIZE;
 444                 if (txq->tso_en) {
 445                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 446                         if (tso) {
 447                                 uintptr_t end = (uintptr_t)
 448                                                 (((uintptr_t)txq->wqes) +
 449                                                 (1 << txq->wqe_n) *
 450                                                 MLX5_WQE_SIZE);
 451                                 unsigned int copy_b;
 452                                 uint8_t vlan_sz = (buf->ol_flags &
 453                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 454                                 const uint64_t is_tunneled =
 455                                                         buf->ol_flags &
 456                                                         (PKT_TX_TUNNEL_GRE |
 457                                                          PKT_TX_TUNNEL_VXLAN);
 458
 459                                 tso_header_sz = buf->l2_len + vlan_sz +
 460                                                 buf->l3_len + buf->l4_len;
 461                                 tso_segsz = buf->tso_segsz;
 462                                 if (unlikely(tso_segsz == 0)) {
 463                                         txq->stats.oerrors++;
 464                                         break;
 465                                 }
 466                                 if (is_tunneled && txq->tunnel_en) {
 467                                         tso_header_sz += buf->outer_l2_len +
 468                                                          buf->outer_l3_len;
 469                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 470                                 } else {
 471                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 472                                 }
 473                                 if (unlikely(tso_header_sz >
 474                                              MLX5_MAX_TSO_HEADER)) {
 475                                         txq->stats.oerrors++;
 476                                         break;
 477                                 }
 478                                 copy_b = tso_header_sz - pkt_inline_sz;
 479                                 /* First seg must contain all headers. */
 480                                 assert(copy_b <= length);
 481                                 if (copy_b &&
 482                                    ((end - (uintptr_t)raw) > copy_b)) {
 483                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 484                                                       1 + 3) / 4;
 485
 486                                         if (unlikely(max_wqe < n))
 487                                                 break;
 488                                         max_wqe -= n;
 489                                         rte_memcpy((void *)raw,
 490                                                    (void *)addr, copy_b);
 491                                         addr += copy_b;
 492                                         length -= copy_b;
 493                                         /* Include padding for TSO header. */
 494                                         copy_b = MLX5_WQE_DS(copy_b) *
 495                                                  MLX5_WQE_DWORD_SIZE;
 496                                         pkt_inline_sz += copy_b;
 497                                         raw += copy_b;
 498                                 } else {
 499                                         /* NOP WQE. */
 500                                         wqe->ctrl = (rte_v128u32_t){
 501                                                      rte_cpu_to_be_32(
 502                                                         txq->wqe_ci << 8),
 503                                                      rte_cpu_to_be_32(
 504                                                         txq->qp_num_8s | 1),
 505                                                      0,
 506                                                      0,
 507                                         };
 508                                         ds = 1;
 509 #ifdef MLX5_PMD_SOFT_COUNTERS
 510                                         total_length = 0;
 511 #endif
 512                                         k++;
 513                                         goto next_wqe;
 514                                 }
 515                         }
 516                 }
 517                 /* Inline if enough room. */
 518                 if (max_inline || tso) {
 519                         uint32_t inl = 0;
 520                         uintptr_t end = (uintptr_t)
 521                                 (((uintptr_t)txq->wqes) +
 522                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 523                         unsigned int inline_room = max_inline *
 524                                                    RTE_CACHE_LINE_SIZE -
 525                                                    (pkt_inline_sz - 2) -
 526                                                    !!tso * sizeof(inl);
 527                         uintptr_t addr_end;
 528                         unsigned int copy_b;
 529
 530 pkt_inline:
 531                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 532                                                    RTE_CACHE_LINE_SIZE);
 533                         copy_b = (addr_end > addr) ?
 534                                  RTE_MIN((addr_end - addr), length) : 0;
 535                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 536                                 /*
 537                                  * One Dseg remains in the current WQE.  To
 538                                  * keep the computation positive, it is
 539                                  * removed after the bytes to Dseg conversion.
 540                                  */
 541                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 542
 543                                 if (unlikely(max_wqe < n))
 544                                         break;
 545                                 max_wqe -= n;
 546                                 if (tso && !inl) {
 547                                         inl = rte_cpu_to_be_32(copy_b |
 548                                                                MLX5_INLINE_SEG);
 549                                         rte_memcpy((void *)raw,
 550                                                    (void *)&inl, sizeof(inl));
 551                                         raw += sizeof(inl);
 552                                         pkt_inline_sz += sizeof(inl);
 553                                 }
 554                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 555                                 addr += copy_b;
 556                                 length -= copy_b;
 557                                 pkt_inline_sz += copy_b;
 558                         }
 559                         /*
 560                          * 2 DWORDs consumed by the WQE header + ETH segment +
 561                          * the size of the inline part of the packet.
 562                          */
 563                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 564                         if (length > 0) {
 565                                 if (ds % (MLX5_WQE_SIZE /
 566                                           MLX5_WQE_DWORD_SIZE) == 0) {
 567                                         if (unlikely(--max_wqe == 0))
 568                                                 break;
 569                                         dseg = (volatile rte_v128u32_t *)
 570                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 571                                                            ds / 4);
 572                                 } else {
 573                                         dseg = (volatile rte_v128u32_t *)
 574                                                 ((uintptr_t)wqe +
 575                                                  (ds * MLX5_WQE_DWORD_SIZE));
 576                                 }
 577                                 goto use_dseg;
 578                         } else if (!segs_n) {
 579                                 goto next_pkt;
 580                         } else {
 581                                 raw += copy_b;
 582                                 inline_room -= copy_b;
 583                                 --segs_n;
 584                                 buf = buf->next;
 585                                 assert(buf);
 586                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 587                                 length = DATA_LEN(buf);
 588 #ifdef MLX5_PMD_SOFT_COUNTERS
 589                                 total_length += length;
 590 #endif
 591                                 (*txq->elts)[++elts_head & elts_m] = buf;
 592                                 goto pkt_inline;
 593                         }
 594                 } else {
 595                         /*
 596                          * No inline has been done in the packet, only the
 597                          * Ethernet Header as been stored.
 598                          */
 599                         dseg = (volatile rte_v128u32_t *)
 600                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 601                         ds = 3;
 602 use_dseg:
 603                         /* Add the remaining packet as a simple ds. */
 604                         addr = rte_cpu_to_be_64(addr);
 605                         *dseg = (rte_v128u32_t){
 606                                 rte_cpu_to_be_32(length),
 607                                 mlx5_tx_mb2mr(txq, buf),
 608                                 addr,
 609                                 addr >> 32,
 610                         };
 611                         ++ds;
 612                         if (!segs_n)
 613                                 goto next_pkt;
 614                 }
 615 next_seg:
 616                 assert(buf);
 617                 assert(ds);
 618                 assert(wqe);
 619                 /*
 620                  * Spill on next WQE when the current one does not have
 621                  * enough room left. Size of WQE must a be a multiple
 622                  * of data segment size.
 623                  */
 624                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 625                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 626                         if (unlikely(--max_wqe == 0))
 627                                 break;
 628                         dseg = (volatile rte_v128u32_t *)
 629                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 630                         rte_prefetch0(tx_mlx5_wqe(txq,
 631                                                   txq->wqe_ci + ds / 4 + 1));
 632                 } else {
 633                         ++dseg;
 634                 }
 635                 ++ds;
 636                 buf = buf->next;
 637                 assert(buf);
 638                 length = DATA_LEN(buf);
 639 #ifdef MLX5_PMD_SOFT_COUNTERS
 640                 total_length += length;
 641 #endif
 642                 /* Store segment information. */
 643                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 644                 *dseg = (rte_v128u32_t){
 645                         rte_cpu_to_be_32(length),
 646                         mlx5_tx_mb2mr(txq, buf),
 647                         addr,
 648                         addr >> 32,
 649                 };
 650                 (*txq->elts)[++elts_head & elts_m] = buf;
 651                 if (--segs_n)
 652                         goto next_seg;
 653 next_pkt:
 654                 if (ds > MLX5_DSEG_MAX) {
 655                         txq->stats.oerrors++;
 656                         break;
 657                 }
 658                 ++elts_head;
 659                 ++pkts;
 660                 ++i;
 661                 j += sg;
 662                 /* Initialize known and common part of the WQE structure. */
 663                 if (tso) {
 664                         wqe->ctrl = (rte_v128u32_t){
 665                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 666                                                  MLX5_OPCODE_TSO),
 667                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 668                                 0,
 669                                 0,
 670                         };
 671                         wqe->eseg = (rte_v128u32_t){
 672                                 0,
 673                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 674                                 0,
 675                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 676                         };
 677                 } else {
 678                         wqe->ctrl = (rte_v128u32_t){
 679                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 680                                                  MLX5_OPCODE_SEND),
 681                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 682                                 0,
 683                                 0,
 684                         };
 685                         wqe->eseg = (rte_v128u32_t){
 686                                 0,
 687                                 cs_flags,
 688                                 0,
 689                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 690                         };
 691                 }
 692 next_wqe:
 693                 txq->wqe_ci += (ds + 3) / 4;
 694                 /* Save the last successful WQE for completion request */
 695                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 696 #ifdef MLX5_PMD_SOFT_COUNTERS
 697                 /* Increment sent bytes counter. */
 698                 txq->stats.obytes += total_length;
 699 #endif
 700         } while (i < pkts_n);
 701         /* Take a shortcut if nothing must be sent. */
 702         if (unlikely((i + k) == 0))
 703                 return 0;
 704         txq->elts_head += (i + j);
 705         /* Check whether completion threshold has been reached. */
 706         comp = txq->elts_comp + i + j + k;
 707         if (comp >= MLX5_TX_COMP_THRESH) {
 708                 /* Request completion on last WQE. */
 709                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 710                 /* Save elts_head in unused "immediate" field of WQE. */
 711                 last_wqe->ctrl3 = txq->elts_head;
 712                 txq->elts_comp = 0;
 713         } else {
 714                 txq->elts_comp = comp;
 715         }
 716 #ifdef MLX5_PMD_SOFT_COUNTERS
 717         /* Increment sent packets counter. */
 718         txq->stats.opackets += i;
 719 #endif
 720         /* Ring QP doorbell. */
 721         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 722         return i;
 723 }
 724
 725 /**
 726  * Open a MPW session.
 727  *
 728  * @param txq
 729  *   Pointer to TX queue structure.
 730  * @param mpw
 731  *   Pointer to MPW session structure.
 732  * @param length
 733  *   Packet length.
 734  */
 735 static inline void
 736 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 737 {
 738         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 739         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 740                 (volatile struct mlx5_wqe_data_seg (*)[])
 741                 tx_mlx5_wqe(txq, idx + 1);
 742
 743         mpw->state = MLX5_MPW_STATE_OPENED;
 744         mpw->pkts_n = 0;
 745         mpw->len = length;
 746         mpw->total_len = 0;
 747         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 748         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 749         mpw->wqe->eseg.inline_hdr_sz = 0;
 750         mpw->wqe->eseg.rsvd0 = 0;
 751         mpw->wqe->eseg.rsvd1 = 0;
 752         mpw->wqe->eseg.rsvd2 = 0;
 753         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 754                                              (txq->wqe_ci << 8) |
 755                                              MLX5_OPCODE_TSO);
 756         mpw->wqe->ctrl[2] = 0;
 757         mpw->wqe->ctrl[3] = 0;
 758         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 759                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 760         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 761                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 762         mpw->data.dseg[2] = &(*dseg)[0];
 763         mpw->data.dseg[3] = &(*dseg)[1];
 764         mpw->data.dseg[4] = &(*dseg)[2];
 765 }
 766
 767 /**
 768  * Close a MPW session.
 769  *
 770  * @param txq
 771  *   Pointer to TX queue structure.
 772  * @param mpw
 773  *   Pointer to MPW session structure.
 774  */
 775 static inline void
 776 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 777 {
 778         unsigned int num = mpw->pkts_n;
 779
 780         /*
 781          * Store size in multiple of 16 bytes. Control and Ethernet segments
 782          * count as 2.
 783          */
 784         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 785         mpw->state = MLX5_MPW_STATE_CLOSED;
 786         if (num < 3)
 787                 ++txq->wqe_ci;
 788         else
 789                 txq->wqe_ci += 2;
 790         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 791         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 792 }
 793
 794 /**
 795  * DPDK callback for TX with MPW support.
 796  *
 797  * @param dpdk_txq
 798  *   Generic pointer to TX queue structure.
 799  * @param[in] pkts
 800  *   Packets to transmit.
 801  * @param pkts_n
 802  *   Number of packets in array.
 803  *
 804  * @return
 805  *   Number of packets successfully transmitted (<= pkts_n).
 806  */
 807 uint16_t
 808 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 809 {
 810         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 811         uint16_t elts_head = txq->elts_head;
 812         const uint16_t elts_n = 1 << txq->elts_n;
 813         const uint16_t elts_m = elts_n - 1;
 814         unsigned int i = 0;
 815         unsigned int j = 0;
 816         uint16_t max_elts;
 817         uint16_t max_wqe;
 818         unsigned int comp;
 819         struct mlx5_mpw mpw = {
 820                 .state = MLX5_MPW_STATE_CLOSED,
 821         };
 822
 823         if (unlikely(!pkts_n))
 824                 return 0;
 825         /* Prefetch first packet cacheline. */
 826         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 827         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 828         /* Start processing. */
 829         mlx5_tx_complete(txq);
 830         max_elts = (elts_n - (elts_head - txq->elts_tail));
 831         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 832         if (unlikely(!max_wqe))
 833                 return 0;
 834         do {
 835                 struct rte_mbuf *buf = *(pkts++);
 836                 uint32_t length;
 837                 unsigned int segs_n = buf->nb_segs;
 838                 uint32_t cs_flags;
 839
 840                 /*
 841                  * Make sure there is enough room to store this packet and
 842                  * that one ring entry remains unused.
 843                  */
 844                 assert(segs_n);
 845                 if (max_elts < segs_n)
 846                         break;
 847                 /* Do not bother with large packets MPW cannot handle. */
 848                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 849                         txq->stats.oerrors++;
 850                         break;
 851                 }
 852                 max_elts -= segs_n;
 853                 --pkts_n;
 854                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 855                 /* Retrieve packet information. */
 856                 length = PKT_LEN(buf);
 857                 assert(length);
 858                 /* Start new session if packet differs. */
 859                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 860                     ((mpw.len != length) ||
 861                      (segs_n != 1) ||
 862                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 863                         mlx5_mpw_close(txq, &mpw);
 864                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 865                         /*
 866                          * Multi-Packet WQE consumes at most two WQE.
 867                          * mlx5_mpw_new() expects to be able to use such
 868                          * resources.
 869                          */
 870                         if (unlikely(max_wqe < 2))
 871                                 break;
 872                         max_wqe -= 2;
 873                         mlx5_mpw_new(txq, &mpw, length);
 874                         mpw.wqe->eseg.cs_flags = cs_flags;
 875                 }
 876                 /* Multi-segment packets must be alone in their MPW. */
 877                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 878 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 879                 length = 0;
 880 #endif
 881                 do {
 882                         volatile struct mlx5_wqe_data_seg *dseg;
 883                         uintptr_t addr;
 884
 885                         assert(buf);
 886                         (*txq->elts)[elts_head++ & elts_m] = buf;
 887                         dseg = mpw.data.dseg[mpw.pkts_n];
 888                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 889                         *dseg = (struct mlx5_wqe_data_seg){
 890                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 891                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 892                                 .addr = rte_cpu_to_be_64(addr),
 893                         };
 894 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 895                         length += DATA_LEN(buf);
 896 #endif
 897                         buf = buf->next;
 898                         ++mpw.pkts_n;
 899                         ++j;
 900                 } while (--segs_n);
 901                 assert(length == mpw.len);
 902                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 903                         mlx5_mpw_close(txq, &mpw);
 904 #ifdef MLX5_PMD_SOFT_COUNTERS
 905                 /* Increment sent bytes counter. */
 906                 txq->stats.obytes += length;
 907 #endif
 908                 ++i;
 909         } while (pkts_n);
 910         /* Take a shortcut if nothing must be sent. */
 911         if (unlikely(i == 0))
 912                 return 0;
 913         /* Check whether completion threshold has been reached. */
 914         /* "j" includes both packets and segments. */
 915         comp = txq->elts_comp + j;
 916         if (comp >= MLX5_TX_COMP_THRESH) {
 917                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 918
 919                 /* Request completion on last WQE. */
 920                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 921                 /* Save elts_head in unused "immediate" field of WQE. */
 922                 wqe->ctrl[3] = elts_head;
 923                 txq->elts_comp = 0;
 924         } else {
 925                 txq->elts_comp = comp;
 926         }
 927 #ifdef MLX5_PMD_SOFT_COUNTERS
 928         /* Increment sent packets counter. */
 929         txq->stats.opackets += i;
 930 #endif
 931         /* Ring QP doorbell. */
 932         if (mpw.state == MLX5_MPW_STATE_OPENED)
 933                 mlx5_mpw_close(txq, &mpw);
 934         mlx5_tx_dbrec(txq, mpw.wqe);
 935         txq->elts_head = elts_head;
 936         return i;
 937 }
 938
 939 /**
 940  * Open a MPW inline session.
 941  *
 942  * @param txq
 943  *   Pointer to TX queue structure.
 944  * @param mpw
 945  *   Pointer to MPW session structure.
 946  * @param length
 947  *   Packet length.
 948  */
 949 static inline void
 950 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 951                     uint32_t length)
 952 {
 953         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 954         struct mlx5_wqe_inl_small *inl;
 955
 956         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 957         mpw->pkts_n = 0;
 958         mpw->len = length;
 959         mpw->total_len = 0;
 960         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 961         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 962                                              (txq->wqe_ci << 8) |
 963                                              MLX5_OPCODE_TSO);
 964         mpw->wqe->ctrl[2] = 0;
 965         mpw->wqe->ctrl[3] = 0;
 966         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 967         mpw->wqe->eseg.inline_hdr_sz = 0;
 968         mpw->wqe->eseg.cs_flags = 0;
 969         mpw->wqe->eseg.rsvd0 = 0;
 970         mpw->wqe->eseg.rsvd1 = 0;
 971         mpw->wqe->eseg.rsvd2 = 0;
 972         inl = (struct mlx5_wqe_inl_small *)
 973                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 974         mpw->data.raw = (uint8_t *)&inl->raw;
 975 }
 976
 977 /**
 978  * Close a MPW inline session.
 979  *
 980  * @param txq
 981  *   Pointer to TX queue structure.
 982  * @param mpw
 983  *   Pointer to MPW session structure.
 984  */
 985 static inline void
 986 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 987 {
 988         unsigned int size;
 989         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 990                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 991
 992         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 993         /*
 994          * Store size in multiple of 16 bytes. Control and Ethernet segments
 995          * count as 2.
 996          */
 997         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
 998                                              MLX5_WQE_DS(size));
 999         mpw->state = MLX5_MPW_STATE_CLOSED;
1000         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1001         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1002 }
1003
1004 /**
1005  * DPDK callback for TX with MPW inline support.
1006  *
1007  * @param dpdk_txq
1008  *   Generic pointer to TX queue structure.
1009  * @param[in] pkts
1010  *   Packets to transmit.
1011  * @param pkts_n
1012  *   Number of packets in array.
1013  *
1014  * @return
1015  *   Number of packets successfully transmitted (<= pkts_n).
1016  */
1017 uint16_t
1018 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1019                          uint16_t pkts_n)
1020 {
1021         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1022         uint16_t elts_head = txq->elts_head;
1023         const uint16_t elts_n = 1 << txq->elts_n;
1024         const uint16_t elts_m = elts_n - 1;
1025         unsigned int i = 0;
1026         unsigned int j = 0;
1027         uint16_t max_elts;
1028         uint16_t max_wqe;
1029         unsigned int comp;
1030         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1031         struct mlx5_mpw mpw = {
1032                 .state = MLX5_MPW_STATE_CLOSED,
1033         };
1034         /*
1035          * Compute the maximum number of WQE which can be consumed by inline
1036          * code.
1037          * - 2 DSEG for:
1038          *   - 1 control segment,
1039          *   - 1 Ethernet segment,
1040          * - N Dseg from the inline request.
1041          */
1042         const unsigned int wqe_inl_n =
1043                 ((2 * MLX5_WQE_DWORD_SIZE +
1044                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1045                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1046
1047         if (unlikely(!pkts_n))
1048                 return 0;
1049         /* Prefetch first packet cacheline. */
1050         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1051         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1052         /* Start processing. */
1053         mlx5_tx_complete(txq);
1054         max_elts = (elts_n - (elts_head - txq->elts_tail));
1055         do {
1056                 struct rte_mbuf *buf = *(pkts++);
1057                 uintptr_t addr;
1058                 uint32_t length;
1059                 unsigned int segs_n = buf->nb_segs;
1060                 uint8_t cs_flags;
1061
1062                 /*
1063                  * Make sure there is enough room to store this packet and
1064                  * that one ring entry remains unused.
1065                  */
1066                 assert(segs_n);
1067                 if (max_elts < segs_n)
1068                         break;
1069                 /* Do not bother with large packets MPW cannot handle. */
1070                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1071                         txq->stats.oerrors++;
1072                         break;
1073                 }
1074                 max_elts -= segs_n;
1075                 --pkts_n;
1076                 /*
1077                  * Compute max_wqe in case less WQE were consumed in previous
1078                  * iteration.
1079                  */
1080                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1081                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1082                 /* Retrieve packet information. */
1083                 length = PKT_LEN(buf);
1084                 /* Start new session if packet differs. */
1085                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1086                         if ((mpw.len != length) ||
1087                             (segs_n != 1) ||
1088                             (mpw.wqe->eseg.cs_flags != cs_flags))
1089                                 mlx5_mpw_close(txq, &mpw);
1090                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1091                         if ((mpw.len != length) ||
1092                             (segs_n != 1) ||
1093                             (length > inline_room) ||
1094                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1095                                 mlx5_mpw_inline_close(txq, &mpw);
1096                                 inline_room =
1097                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1098                         }
1099                 }
1100                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1101                         if ((segs_n != 1) ||
1102                             (length > inline_room)) {
1103                                 /*
1104                                  * Multi-Packet WQE consumes at most two WQE.
1105                                  * mlx5_mpw_new() expects to be able to use
1106                                  * such resources.
1107                                  */
1108                                 if (unlikely(max_wqe < 2))
1109                                         break;
1110                                 max_wqe -= 2;
1111                                 mlx5_mpw_new(txq, &mpw, length);
1112                                 mpw.wqe->eseg.cs_flags = cs_flags;
1113                         } else {
1114                                 if (unlikely(max_wqe < wqe_inl_n))
1115                                         break;
1116                                 max_wqe -= wqe_inl_n;
1117                                 mlx5_mpw_inline_new(txq, &mpw, length);
1118                                 mpw.wqe->eseg.cs_flags = cs_flags;
1119                         }
1120                 }
1121                 /* Multi-segment packets must be alone in their MPW. */
1122                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1123                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1124                         assert(inline_room ==
1125                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1126 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1127                         length = 0;
1128 #endif
1129                         do {
1130                                 volatile struct mlx5_wqe_data_seg *dseg;
1131
1132                                 assert(buf);
1133                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1134                                 dseg = mpw.data.dseg[mpw.pkts_n];
1135                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1136                                 *dseg = (struct mlx5_wqe_data_seg){
1137                                         .byte_count =
1138                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1139                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1140                                         .addr = rte_cpu_to_be_64(addr),
1141                                 };
1142 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1143                                 length += DATA_LEN(buf);
1144 #endif
1145                                 buf = buf->next;
1146                                 ++mpw.pkts_n;
1147                                 ++j;
1148                         } while (--segs_n);
1149                         assert(length == mpw.len);
1150                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1151                                 mlx5_mpw_close(txq, &mpw);
1152                 } else {
1153                         unsigned int max;
1154
1155                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1156                         assert(length <= inline_room);
1157                         assert(length == DATA_LEN(buf));
1158                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1159                         (*txq->elts)[elts_head++ & elts_m] = buf;
1160                         /* Maximum number of bytes before wrapping. */
1161                         max = ((((uintptr_t)(txq->wqes)) +
1162                                 (1 << txq->wqe_n) *
1163                                 MLX5_WQE_SIZE) -
1164                                (uintptr_t)mpw.data.raw);
1165                         if (length > max) {
1166                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1167                                            (void *)addr,
1168                                            max);
1169                                 mpw.data.raw = (volatile void *)txq->wqes;
1170                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1171                                            (void *)(addr + max),
1172                                            length - max);
1173                                 mpw.data.raw += length - max;
1174                         } else {
1175                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1176                                            (void *)addr,
1177                                            length);
1178
1179                                 if (length == max)
1180                                         mpw.data.raw =
1181                                                 (volatile void *)txq->wqes;
1182                                 else
1183                                         mpw.data.raw += length;
1184                         }
1185                         ++mpw.pkts_n;
1186                         mpw.total_len += length;
1187                         ++j;
1188                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1189                                 mlx5_mpw_inline_close(txq, &mpw);
1190                                 inline_room =
1191                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1192                         } else {
1193                                 inline_room -= length;
1194                         }
1195                 }
1196 #ifdef MLX5_PMD_SOFT_COUNTERS
1197                 /* Increment sent bytes counter. */
1198                 txq->stats.obytes += length;
1199 #endif
1200                 ++i;
1201         } while (pkts_n);
1202         /* Take a shortcut if nothing must be sent. */
1203         if (unlikely(i == 0))
1204                 return 0;
1205         /* Check whether completion threshold has been reached. */
1206         /* "j" includes both packets and segments. */
1207         comp = txq->elts_comp + j;
1208         if (comp >= MLX5_TX_COMP_THRESH) {
1209                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1210
1211                 /* Request completion on last WQE. */
1212                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1213                 /* Save elts_head in unused "immediate" field of WQE. */
1214                 wqe->ctrl[3] = elts_head;
1215                 txq->elts_comp = 0;
1216         } else {
1217                 txq->elts_comp = comp;
1218         }
1219 #ifdef MLX5_PMD_SOFT_COUNTERS
1220         /* Increment sent packets counter. */
1221         txq->stats.opackets += i;
1222 #endif
1223         /* Ring QP doorbell. */
1224         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1225                 mlx5_mpw_inline_close(txq, &mpw);
1226         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1227                 mlx5_mpw_close(txq, &mpw);
1228         mlx5_tx_dbrec(txq, mpw.wqe);
1229         txq->elts_head = elts_head;
1230         return i;
1231 }
1232
1233 /**
1234  * Open an Enhanced MPW session.
1235  *
1236  * @param txq
1237  *   Pointer to TX queue structure.
1238  * @param mpw
1239  *   Pointer to MPW session structure.
1240  * @param length
1241  *   Packet length.
1242  */
1243 static inline void
1244 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1245 {
1246         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1247
1248         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1249         mpw->pkts_n = 0;
1250         mpw->total_len = sizeof(struct mlx5_wqe);
1251         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1252         mpw->wqe->ctrl[0] =
1253                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1254                                  (txq->wqe_ci << 8) |
1255                                  MLX5_OPCODE_ENHANCED_MPSW);
1256         mpw->wqe->ctrl[2] = 0;
1257         mpw->wqe->ctrl[3] = 0;
1258         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1259         if (unlikely(padding)) {
1260                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1261
1262                 /* Pad the first 2 DWORDs with zero-length inline header. */
1263                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1264                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1265                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1266                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1267                 /* Start from the next WQEBB. */
1268                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1269         } else {
1270                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1271         }
1272 }
1273
1274 /**
1275  * Close an Enhanced MPW session.
1276  *
1277  * @param txq
1278  *   Pointer to TX queue structure.
1279  * @param mpw
1280  *   Pointer to MPW session structure.
1281  *
1282  * @return
1283  *   Number of consumed WQEs.
1284  */
1285 static inline uint16_t
1286 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1287 {
1288         uint16_t ret;
1289
1290         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1291          * count as 2.
1292          */
1293         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1294                                              MLX5_WQE_DS(mpw->total_len));
1295         mpw->state = MLX5_MPW_STATE_CLOSED;
1296         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1297         txq->wqe_ci += ret;
1298         return ret;
1299 }
1300
1301 /**
1302  * DPDK callback for TX with Enhanced MPW support.
1303  *
1304  * @param dpdk_txq
1305  *   Generic pointer to TX queue structure.
1306  * @param[in] pkts
1307  *   Packets to transmit.
1308  * @param pkts_n
1309  *   Number of packets in array.
1310  *
1311  * @return
1312  *   Number of packets successfully transmitted (<= pkts_n).
1313  */
1314 uint16_t
1315 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1316 {
1317         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1318         uint16_t elts_head = txq->elts_head;
1319         const uint16_t elts_n = 1 << txq->elts_n;
1320         const uint16_t elts_m = elts_n - 1;
1321         unsigned int i = 0;
1322         unsigned int j = 0;
1323         uint16_t max_elts;
1324         uint16_t max_wqe;
1325         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1326         unsigned int mpw_room = 0;
1327         unsigned int inl_pad = 0;
1328         uint32_t inl_hdr;
1329         struct mlx5_mpw mpw = {
1330                 .state = MLX5_MPW_STATE_CLOSED,
1331         };
1332
1333         if (unlikely(!pkts_n))
1334                 return 0;
1335         /* Start processing. */
1336         mlx5_tx_complete(txq);
1337         max_elts = (elts_n - (elts_head - txq->elts_tail));
1338         /* A CQE slot must always be available. */
1339         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1340         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1341         if (unlikely(!max_wqe))
1342                 return 0;
1343         do {
1344                 struct rte_mbuf *buf = *(pkts++);
1345                 uintptr_t addr;
1346                 unsigned int n;
1347                 unsigned int do_inline = 0; /* Whether inline is possible. */
1348                 uint32_t length;
1349                 unsigned int segs_n = buf->nb_segs;
1350                 uint8_t cs_flags;
1351
1352                 /*
1353                  * Make sure there is enough room to store this packet and
1354                  * that one ring entry remains unused.
1355                  */
1356                 assert(segs_n);
1357                 if (max_elts - j < segs_n)
1358                         break;
1359                 /* Do not bother with large packets MPW cannot handle. */
1360                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1361                         txq->stats.oerrors++;
1362                         break;
1363                 }
1364                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1365                 /* Retrieve packet information. */
1366                 length = PKT_LEN(buf);
1367                 /* Start new session if:
1368                  * - multi-segment packet
1369                  * - no space left even for a dseg
1370                  * - next packet can be inlined with a new WQE
1371                  * - cs_flag differs
1372                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1373                  * segmented packet.
1374                  */
1375                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1376                         if ((segs_n != 1) ||
1377                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1378                               mpw_room) ||
1379                             (length <= txq->inline_max_packet_sz &&
1380                              inl_pad + sizeof(inl_hdr) + length >
1381                               mpw_room) ||
1382                             (mpw.wqe->eseg.cs_flags != cs_flags))
1383                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1384                 }
1385                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1386                         if (unlikely(segs_n != 1)) {
1387                                 /* Fall back to legacy MPW.
1388                                  * A MPW session consumes 2 WQEs at most to
1389                                  * include MLX5_MPW_DSEG_MAX pointers.
1390                                  */
1391                                 if (unlikely(max_wqe < 2))
1392                                         break;
1393                                 mlx5_mpw_new(txq, &mpw, length);
1394                         } else {
1395                                 /* In Enhanced MPW, inline as much as the budget
1396                                  * is allowed. The remaining space is to be
1397                                  * filled with dsegs. If the title WQEBB isn't
1398                                  * padded, it will have 2 dsegs there.
1399                                  */
1400                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1401                                             (max_inline ? max_inline :
1402                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1403                                             MLX5_WQE_SIZE);
1404                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1405                                               mpw_room))
1406                                         break;
1407                                 /* Don't pad the title WQEBB to not waste WQ. */
1408                                 mlx5_empw_new(txq, &mpw, 0);
1409                                 mpw_room -= mpw.total_len;
1410                                 inl_pad = 0;
1411                                 do_inline =
1412                                         length <= txq->inline_max_packet_sz &&
1413                                         sizeof(inl_hdr) + length <= mpw_room &&
1414                                         !txq->mpw_hdr_dseg;
1415                         }
1416                         mpw.wqe->eseg.cs_flags = cs_flags;
1417                 } else {
1418                         /* Evaluate whether the next packet can be inlined.
1419                          * Inlininig is possible when:
1420                          * - length is less than configured value
1421                          * - length fits for remaining space
1422                          * - not required to fill the title WQEBB with dsegs
1423                          */
1424                         do_inline =
1425                                 length <= txq->inline_max_packet_sz &&
1426                                 inl_pad + sizeof(inl_hdr) + length <=
1427                                  mpw_room &&
1428                                 (!txq->mpw_hdr_dseg ||
1429                                  mpw.total_len >= MLX5_WQE_SIZE);
1430                 }
1431                 /* Multi-segment packets must be alone in their MPW. */
1432                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1433                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1434 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1435                         length = 0;
1436 #endif
1437                         do {
1438                                 volatile struct mlx5_wqe_data_seg *dseg;
1439
1440                                 assert(buf);
1441                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1442                                 dseg = mpw.data.dseg[mpw.pkts_n];
1443                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1444                                 *dseg = (struct mlx5_wqe_data_seg){
1445                                         .byte_count = rte_cpu_to_be_32(
1446                                                                 DATA_LEN(buf)),
1447                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1448                                         .addr = rte_cpu_to_be_64(addr),
1449                                 };
1450 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1451                                 length += DATA_LEN(buf);
1452 #endif
1453                                 buf = buf->next;
1454                                 ++j;
1455                                 ++mpw.pkts_n;
1456                         } while (--segs_n);
1457                         /* A multi-segmented packet takes one MPW session.
1458                          * TODO: Pack more multi-segmented packets if possible.
1459                          */
1460                         mlx5_mpw_close(txq, &mpw);
1461                         if (mpw.pkts_n < 3)
1462                                 max_wqe--;
1463                         else
1464                                 max_wqe -= 2;
1465                 } else if (do_inline) {
1466                         /* Inline packet into WQE. */
1467                         unsigned int max;
1468
1469                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1470                         assert(length == DATA_LEN(buf));
1471                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1472                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1473                         mpw.data.raw = (volatile void *)
1474                                 ((uintptr_t)mpw.data.raw + inl_pad);
1475                         max = tx_mlx5_wq_tailroom(txq,
1476                                         (void *)(uintptr_t)mpw.data.raw);
1477                         /* Copy inline header. */
1478                         mpw.data.raw = (volatile void *)
1479                                 mlx5_copy_to_wq(
1480                                           (void *)(uintptr_t)mpw.data.raw,
1481                                           &inl_hdr,
1482                                           sizeof(inl_hdr),
1483                                           (void *)(uintptr_t)txq->wqes,
1484                                           max);
1485                         max = tx_mlx5_wq_tailroom(txq,
1486                                         (void *)(uintptr_t)mpw.data.raw);
1487                         /* Copy packet data. */
1488                         mpw.data.raw = (volatile void *)
1489                                 mlx5_copy_to_wq(
1490                                           (void *)(uintptr_t)mpw.data.raw,
1491                                           (void *)addr,
1492                                           length,
1493                                           (void *)(uintptr_t)txq->wqes,
1494                                           max);
1495                         ++mpw.pkts_n;
1496                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1497                         /* No need to get completion as the entire packet is
1498                          * copied to WQ. Free the buf right away.
1499                          */
1500                         rte_pktmbuf_free_seg(buf);
1501                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1502                         /* Add pad in the next packet if any. */
1503                         inl_pad = (((uintptr_t)mpw.data.raw +
1504                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1505                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1506                                   (uintptr_t)mpw.data.raw;
1507                 } else {
1508                         /* No inline. Load a dseg of packet pointer. */
1509                         volatile rte_v128u32_t *dseg;
1510
1511                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1512                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1513                         assert(length == DATA_LEN(buf));
1514                         if (!tx_mlx5_wq_tailroom(txq,
1515                                         (void *)((uintptr_t)mpw.data.raw
1516                                                 + inl_pad)))
1517                                 dseg = (volatile void *)txq->wqes;
1518                         else
1519                                 dseg = (volatile void *)
1520                                         ((uintptr_t)mpw.data.raw +
1521                                          inl_pad);
1522                         (*txq->elts)[elts_head++ & elts_m] = buf;
1523                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1524                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1525                                 rte_prefetch2((void *)(addr +
1526                                                 n * RTE_CACHE_LINE_SIZE));
1527                         addr = rte_cpu_to_be_64(addr);
1528                         *dseg = (rte_v128u32_t) {
1529                                 rte_cpu_to_be_32(length),
1530                                 mlx5_tx_mb2mr(txq, buf),
1531                                 addr,
1532                                 addr >> 32,
1533                         };
1534                         mpw.data.raw = (volatile void *)(dseg + 1);
1535                         mpw.total_len += (inl_pad + sizeof(*dseg));
1536                         ++j;
1537                         ++mpw.pkts_n;
1538                         mpw_room -= (inl_pad + sizeof(*dseg));
1539                         inl_pad = 0;
1540                 }
1541 #ifdef MLX5_PMD_SOFT_COUNTERS
1542                 /* Increment sent bytes counter. */
1543                 txq->stats.obytes += length;
1544 #endif
1545                 ++i;
1546         } while (i < pkts_n);
1547         /* Take a shortcut if nothing must be sent. */
1548         if (unlikely(i == 0))
1549                 return 0;
1550         /* Check whether completion threshold has been reached. */
1551         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1552                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1553                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1554                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1555
1556                 /* Request completion on last WQE. */
1557                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1558                 /* Save elts_head in unused "immediate" field of WQE. */
1559                 wqe->ctrl[3] = elts_head;
1560                 txq->elts_comp = 0;
1561                 txq->mpw_comp = txq->wqe_ci;
1562                 txq->cq_pi++;
1563         } else {
1564                 txq->elts_comp += j;
1565         }
1566 #ifdef MLX5_PMD_SOFT_COUNTERS
1567         /* Increment sent packets counter. */
1568         txq->stats.opackets += i;
1569 #endif
1570         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1571                 mlx5_empw_close(txq, &mpw);
1572         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1573                 mlx5_mpw_close(txq, &mpw);
1574         /* Ring QP doorbell. */
1575         mlx5_tx_dbrec(txq, mpw.wqe);
1576         txq->elts_head = elts_head;
1577         return i;
1578 }
1579
1580 /**
1581  * Translate RX completion flags to packet type.
1582  *
1583  * @param[in] cqe
1584  *   Pointer to CQE.
1585  *
1586  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1587  *
1588  * @return
1589  *   Packet type for struct rte_mbuf.
1590  */
1591 static inline uint32_t
1592 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1593 {
1594         uint8_t idx;
1595         uint8_t pinfo = cqe->pkt_info;
1596         uint16_t ptype = cqe->hdr_type_etc;
1597
1598         /*
1599          * The index to the array should have:
1600          * bit[1:0] = l3_hdr_type
1601          * bit[4:2] = l4_hdr_type
1602          * bit[5] = ip_frag
1603          * bit[6] = tunneled
1604          * bit[7] = outer_l3_type
1605          */
1606         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1607         return mlx5_ptype_table[idx];
1608 }
1609
1610 /**
1611  * Get size of the next packet for a given CQE. For compressed CQEs, the
1612  * consumer index is updated only once all packets of the current one have
1613  * been processed.
1614  *
1615  * @param rxq
1616  *   Pointer to RX queue.
1617  * @param cqe
1618  *   CQE to process.
1619  * @param[out] rss_hash
1620  *   Packet RSS Hash result.
1621  *
1622  * @return
1623  *   Packet size in bytes (0 if there is none), -1 in case of completion
1624  *   with error.
1625  */
1626 static inline int
1627 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1628                  uint16_t cqe_cnt, uint32_t *rss_hash)
1629 {
1630         struct rxq_zip *zip = &rxq->zip;
1631         uint16_t cqe_n = cqe_cnt + 1;
1632         int len = 0;
1633         uint16_t idx, end;
1634
1635         /* Process compressed data in the CQE and mini arrays. */
1636         if (zip->ai) {
1637                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1638                         (volatile struct mlx5_mini_cqe8 (*)[8])
1639                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1640
1641                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1642                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1643                 if ((++zip->ai & 7) == 0) {
1644                         /* Invalidate consumed CQEs */
1645                         idx = zip->ca;
1646                         end = zip->na;
1647                         while (idx != end) {
1648                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1649                                         MLX5_CQE_INVALIDATE;
1650                                 ++idx;
1651                         }
1652                         /*
1653                          * Increment consumer index to skip the number of
1654                          * CQEs consumed. Hardware leaves holes in the CQ
1655                          * ring for software use.
1656                          */
1657                         zip->ca = zip->na;
1658                         zip->na += 8;
1659                 }
1660                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1661                         /* Invalidate the rest */
1662                         idx = zip->ca;
1663                         end = zip->cq_ci;
1664
1665                         while (idx != end) {
1666                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1667                                         MLX5_CQE_INVALIDATE;
1668                                 ++idx;
1669                         }
1670                         rxq->cq_ci = zip->cq_ci;
1671                         zip->ai = 0;
1672                 }
1673         /* No compressed data, get next CQE and verify if it is compressed. */
1674         } else {
1675                 int ret;
1676                 int8_t op_own;
1677
1678                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1679                 if (unlikely(ret == 1))
1680                         return 0;
1681                 ++rxq->cq_ci;
1682                 op_own = cqe->op_own;
1683                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1684                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1685                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1686                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1687                                                           cqe_cnt].pkt_info);
1688
1689                         /* Fix endianness. */
1690                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1691                         /*
1692                          * Current mini array position is the one returned by
1693                          * check_cqe64().
1694                          *
1695                          * If completion comprises several mini arrays, as a
1696                          * special case the second one is located 7 CQEs after
1697                          * the initial CQE instead of 8 for subsequent ones.
1698                          */
1699                         zip->ca = rxq->cq_ci;
1700                         zip->na = zip->ca + 7;
1701                         /* Compute the next non compressed CQE. */
1702                         --rxq->cq_ci;
1703                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1704                         /* Get packet size to return. */
1705                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1706                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1707                         zip->ai = 1;
1708                         /* Prefetch all the entries to be invalidated */
1709                         idx = zip->ca;
1710                         end = zip->cq_ci;
1711                         while (idx != end) {
1712                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1713                                 ++idx;
1714                         }
1715                 } else {
1716                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1717                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1718                 }
1719                 /* Error while receiving packet. */
1720                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1721                         return -1;
1722         }
1723         return len;
1724 }
1725
1726 /**
1727  * Translate RX completion flags to offload flags.
1728  *
1729  * @param[in] rxq
1730  *   Pointer to RX queue structure.
1731  * @param[in] cqe
1732  *   Pointer to CQE.
1733  *
1734  * @return
1735  *   Offload flags (ol_flags) for struct rte_mbuf.
1736  */
1737 static inline uint32_t
1738 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1739 {
1740         uint32_t ol_flags = 0;
1741         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1742
1743         ol_flags =
1744                 TRANSPOSE(flags,
1745                           MLX5_CQE_RX_L3_HDR_VALID,
1746                           PKT_RX_IP_CKSUM_GOOD) |
1747                 TRANSPOSE(flags,
1748                           MLX5_CQE_RX_L4_HDR_VALID,
1749                           PKT_RX_L4_CKSUM_GOOD);
1750         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1751                 ol_flags |=
1752                         TRANSPOSE(flags,
1753                                   MLX5_CQE_RX_L3_HDR_VALID,
1754                                   PKT_RX_IP_CKSUM_GOOD) |
1755                         TRANSPOSE(flags,
1756                                   MLX5_CQE_RX_L4_HDR_VALID,
1757                                   PKT_RX_L4_CKSUM_GOOD);
1758         return ol_flags;
1759 }
1760
1761 /**
1762  * DPDK callback for RX.
1763  *
1764  * @param dpdk_rxq
1765  *   Generic pointer to RX queue structure.
1766  * @param[out] pkts
1767  *   Array to store received packets.
1768  * @param pkts_n
1769  *   Maximum number of packets in array.
1770  *
1771  * @return
1772  *   Number of packets successfully received (<= pkts_n).
1773  */
1774 uint16_t
1775 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1776 {
1777         struct mlx5_rxq_data *rxq = dpdk_rxq;
1778         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1779         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1780         const unsigned int sges_n = rxq->sges_n;
1781         struct rte_mbuf *pkt = NULL;
1782         struct rte_mbuf *seg = NULL;
1783         volatile struct mlx5_cqe *cqe =
1784                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1785         unsigned int i = 0;
1786         unsigned int rq_ci = rxq->rq_ci << sges_n;
1787         int len = 0; /* keep its value across iterations. */
1788
1789         while (pkts_n) {
1790                 unsigned int idx = rq_ci & wqe_cnt;
1791                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1792                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1793                 uint32_t rss_hash_res = 0;
1794
1795                 if (pkt)
1796                         NEXT(seg) = rep;
1797                 seg = rep;
1798                 rte_prefetch0(seg);
1799                 rte_prefetch0(cqe);
1800                 rte_prefetch0(wqe);
1801                 rep = rte_mbuf_raw_alloc(rxq->mp);
1802                 if (unlikely(rep == NULL)) {
1803                         ++rxq->stats.rx_nombuf;
1804                         if (!pkt) {
1805                                 /*
1806                                  * no buffers before we even started,
1807                                  * bail out silently.
1808                                  */
1809                                 break;
1810                         }
1811                         while (pkt != seg) {
1812                                 assert(pkt != (*rxq->elts)[idx]);
1813                                 rep = NEXT(pkt);
1814                                 NEXT(pkt) = NULL;
1815                                 NB_SEGS(pkt) = 1;
1816                                 rte_mbuf_raw_free(pkt);
1817                                 pkt = rep;
1818                         }
1819                         break;
1820                 }
1821                 if (!pkt) {
1822                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1823                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1824                                                &rss_hash_res);
1825                         if (!len) {
1826                                 rte_mbuf_raw_free(rep);
1827                                 break;
1828                         }
1829                         if (unlikely(len == -1)) {
1830                                 /* RX error, packet is likely too large. */
1831                                 rte_mbuf_raw_free(rep);
1832                                 ++rxq->stats.idropped;
1833                                 goto skip;
1834                         }
1835                         pkt = seg;
1836                         assert(len >= (rxq->crc_present << 2));
1837                         /* Update packet information. */
1838                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1839                         pkt->ol_flags = 0;
1840                         if (rss_hash_res && rxq->rss_hash) {
1841                                 pkt->hash.rss = rss_hash_res;
1842                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1843                         }
1844                         if (rxq->mark &&
1845                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1846                                 pkt->ol_flags |= PKT_RX_FDIR;
1847                                 if (cqe->sop_drop_qpn !=
1848                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1849                                         uint32_t mark = cqe->sop_drop_qpn;
1850
1851                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1852                                         pkt->hash.fdir.hi =
1853                                                 mlx5_flow_mark_get(mark);
1854                                 }
1855                         }
1856                         if (rxq->csum | rxq->csum_l2tun)
1857                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1858                         if (rxq->vlan_strip &&
1859                             (cqe->hdr_type_etc &
1860                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1861                                 pkt->ol_flags |= PKT_RX_VLAN |
1862                                         PKT_RX_VLAN_STRIPPED;
1863                                 pkt->vlan_tci =
1864                                         rte_be_to_cpu_16(cqe->vlan_info);
1865                         }
1866                         if (rxq->hw_timestamp) {
1867                                 pkt->timestamp =
1868                                         rte_be_to_cpu_64(cqe->timestamp);
1869                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1870                         }
1871                         if (rxq->crc_present)
1872                                 len -= ETHER_CRC_LEN;
1873                         PKT_LEN(pkt) = len;
1874                 }
1875                 DATA_LEN(rep) = DATA_LEN(seg);
1876                 PKT_LEN(rep) = PKT_LEN(seg);
1877                 SET_DATA_OFF(rep, DATA_OFF(seg));
1878                 PORT(rep) = PORT(seg);
1879                 (*rxq->elts)[idx] = rep;
1880                 /*
1881                  * Fill NIC descriptor with the new buffer.  The lkey and size
1882                  * of the buffers are already known, only the buffer address
1883                  * changes.
1884                  */
1885                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1886                 if (len > DATA_LEN(seg)) {
1887                         len -= DATA_LEN(seg);
1888                         ++NB_SEGS(pkt);
1889                         ++rq_ci;
1890                         continue;
1891                 }
1892                 DATA_LEN(seg) = len;
1893 #ifdef MLX5_PMD_SOFT_COUNTERS
1894                 /* Increment bytes counter. */
1895                 rxq->stats.ibytes += PKT_LEN(pkt);
1896 #endif
1897                 /* Return packet. */
1898                 *(pkts++) = pkt;
1899                 pkt = NULL;
1900                 --pkts_n;
1901                 ++i;
1902 skip:
1903                 /* Align consumer index to the next stride. */
1904                 rq_ci >>= sges_n;
1905                 ++rq_ci;
1906                 rq_ci <<= sges_n;
1907         }
1908         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1909                 return 0;
1910         /* Update the consumer index. */
1911         rxq->rq_ci = rq_ci >> sges_n;
1912         rte_io_wmb();
1913         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1914         rte_io_wmb();
1915         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1916 #ifdef MLX5_PMD_SOFT_COUNTERS
1917         /* Increment packets counter. */
1918         rxq->stats.ipackets += i;
1919 #endif
1920         return i;
1921 }
1922
1923 /**
1924  * Dummy DPDK callback for TX.
1925  *
1926  * This function is used to temporarily replace the real callback during
1927  * unsafe control operations on the queue, or in case of error.
1928  *
1929  * @param dpdk_txq
1930  *   Generic pointer to TX queue structure.
1931  * @param[in] pkts
1932  *   Packets to transmit.
1933  * @param pkts_n
1934  *   Number of packets in array.
1935  *
1936  * @return
1937  *   Number of packets successfully transmitted (<= pkts_n).
1938  */
1939 uint16_t
1940 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1941 {
1942         (void)dpdk_txq;
1943         (void)pkts;
1944         (void)pkts_n;
1945         return 0;
1946 }
1947
1948 /**
1949  * Dummy DPDK callback for RX.
1950  *
1951  * This function is used to temporarily replace the real callback during
1952  * unsafe control operations on the queue, or in case of error.
1953  *
1954  * @param dpdk_rxq
1955  *   Generic pointer to RX queue structure.
1956  * @param[out] pkts
1957  *   Array to store received packets.
1958  * @param pkts_n
1959  *   Maximum number of packets in array.
1960  *
1961  * @return
1962  *   Number of packets successfully received (<= pkts_n).
1963  */
1964 uint16_t
1965 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1966 {
1967         (void)dpdk_rxq;
1968         (void)pkts;
1969         (void)pkts_n;
1970         return 0;
1971 }
1972
1973 /*
1974  * Vectorized Rx/Tx routines are not compiled in when required vector
1975  * instructions are not supported on a target architecture. The following null
1976  * stubs are needed for linkage when those are not included outside of this file
1977  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1978  */
1979
1980 uint16_t __attribute__((weak))
1981 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1982 {
1983         (void)dpdk_txq;
1984         (void)pkts;
1985         (void)pkts_n;
1986         return 0;
1987 }
1988
1989 uint16_t __attribute__((weak))
1990 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1991 {
1992         (void)dpdk_txq;
1993         (void)pkts;
1994         (void)pkts_n;
1995         return 0;
1996 }
1997
1998 uint16_t __attribute__((weak))
1999 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2000 {
2001         (void)dpdk_rxq;
2002         (void)pkts;
2003         (void)pkts_n;
2004         return 0;
2005 }
2006
2007 int __attribute__((weak))
2008 priv_check_raw_vec_tx_support(struct priv *priv)
2009 {
2010         (void)priv;
2011         return -ENOTSUP;
2012 }
2013
2014 int __attribute__((weak))
2015 priv_check_vec_tx_support(struct priv *priv)
2016 {
2017         (void)priv;
2018         return -ENOTSUP;
2019 }
2020
2021 int __attribute__((weak))
2022 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2023 {
2024         (void)rxq;
2025         return -ENOTSUP;
2026 }
2027
2028 int __attribute__((weak))
2029 priv_check_vec_rx_support(struct priv *priv)
2030 {
2031         (void)priv;
2032         return -ENOTSUP;
2033 }