4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe_seen(volatile struct mlx5_cqe *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe(volatile struct mlx5_cqe *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe(volatile struct mlx5_cqe *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 * Return the address of the WQE.
159 * Pointer to TX queue structure.
161 * WQE consumer index.
166 static inline uintptr_t *
167 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
169 ci &= ((1 << txq->wqe_n) - 1);
170 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
174 txq_complete(struct txq *txq) __attribute__((always_inline));
177 * Manage TX completions.
179 * When sending a burst, mlx5_tx_burst() posts several WRs.
182 * Pointer to TX queue structure.
185 txq_complete(struct txq *txq)
187 const unsigned int elts_n = 1 << txq->elts_n;
188 const unsigned int cqe_n = 1 << txq->cqe_n;
189 const unsigned int cqe_cnt = cqe_n - 1;
190 uint16_t elts_free = txq->elts_tail;
192 uint16_t cq_ci = txq->cq_ci;
193 volatile struct mlx5_cqe *cqe = NULL;
194 volatile struct mlx5_wqe_ctrl *ctrl;
197 volatile struct mlx5_cqe *tmp;
199 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
200 if (check_cqe(tmp, cqe_n, cq_ci))
204 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
205 if (!check_cqe_seen(cqe))
206 ERROR("unexpected compressed CQE, TX stopped");
209 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
210 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
211 if (!check_cqe_seen(cqe))
212 ERROR("unexpected error CQE, TX stopped");
218 if (unlikely(cqe == NULL))
220 ctrl = (volatile struct mlx5_wqe_ctrl *)
221 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
222 elts_tail = ctrl->ctrl3;
223 assert(elts_tail < (1 << txq->wqe_n));
225 while (elts_free != elts_tail) {
226 struct rte_mbuf *elt = (*txq->elts)[elts_free];
227 unsigned int elts_free_next =
228 (elts_free + 1) & (elts_n - 1);
229 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
233 memset(&(*txq->elts)[elts_free],
235 sizeof((*txq->elts)[elts_free]));
237 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
238 /* Only one segment needs to be freed. */
239 rte_pktmbuf_free_seg(elt);
240 elts_free = elts_free_next;
243 txq->elts_tail = elts_tail;
244 /* Update the consumer index. */
246 *txq->cq_db = htonl(cq_ci);
250 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
251 * the cloned mbuf is allocated is returned instead.
257 * Memory pool where data is located for given mbuf.
259 static struct rte_mempool *
260 txq_mb2mp(struct rte_mbuf *buf)
262 if (unlikely(RTE_MBUF_INDIRECT(buf)))
263 return rte_mbuf_from_indirect(buf)->pool;
267 static inline uint32_t
268 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
269 __attribute__((always_inline));
272 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
273 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
274 * remove an entry first.
277 * Pointer to TX queue structure.
279 * Memory Pool for which a Memory Region lkey must be returned.
282 * mr->lkey on success, (uint32_t)-1 on failure.
284 static inline uint32_t
285 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
288 uint32_t lkey = (uint32_t)-1;
290 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
291 if (unlikely(txq->mp2mr[i].mp == NULL)) {
292 /* Unknown MP, add a new MR for it. */
295 if (txq->mp2mr[i].mp == mp) {
296 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
297 assert(htonl(txq->mp2mr[i].mr->lkey) ==
299 lkey = txq->mp2mr[i].lkey;
303 if (unlikely(lkey == (uint32_t)-1))
304 lkey = txq_mp2mr_reg(txq, mp, i);
309 * Ring TX queue doorbell.
312 * Pointer to TX queue structure.
315 mlx5_tx_dbrec(struct txq *txq)
317 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
319 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
320 htonl(txq->qp_num_8s),
325 *txq->qp_db = htonl(txq->wqe_ci);
326 /* Ensure ordering between DB record and BF copy. */
328 memcpy(dst, (uint8_t *)data, 16);
329 txq->bf_offset ^= (1 << txq->bf_buf_size);
336 * Pointer to TX queue structure.
338 * CQE consumer index.
341 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
343 volatile struct mlx5_cqe *cqe;
345 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
350 * DPDK callback for TX.
353 * Generic pointer to TX queue structure.
355 * Packets to transmit.
357 * Number of packets in array.
360 * Number of packets successfully transmitted (<= pkts_n).
363 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
365 struct txq *txq = (struct txq *)dpdk_txq;
366 uint16_t elts_head = txq->elts_head;
367 const unsigned int elts_n = 1 << txq->elts_n;
372 volatile struct mlx5_wqe *wqe = NULL;
373 unsigned int segs_n = 0;
374 struct rte_mbuf *buf = NULL;
377 if (unlikely(!pkts_n))
379 /* Prefetch first packet cacheline. */
380 tx_prefetch_cqe(txq, txq->cq_ci);
381 tx_prefetch_cqe(txq, txq->cq_ci + 1);
382 rte_prefetch0(*pkts);
383 /* Start processing. */
385 max = (elts_n - (elts_head - txq->elts_tail));
389 volatile struct mlx5_wqe_data_seg *dseg = NULL;
393 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
395 #ifdef MLX5_PMD_SOFT_COUNTERS
396 uint32_t total_length = 0;
401 segs_n = buf->nb_segs;
403 * Make sure there is enough room to store this packet and
404 * that one ring entry remains unused.
407 if (max < segs_n + 1)
413 wqe = (volatile struct mlx5_wqe *)
414 tx_mlx5_wqe(txq, txq->wqe_ci);
415 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
417 rte_prefetch0(*pkts);
418 addr = rte_pktmbuf_mtod(buf, uintptr_t);
419 length = DATA_LEN(buf);
420 ehdr[0] = ((uint8_t *)addr)[0];
421 ehdr[1] = ((uint8_t *)addr)[1];
422 #ifdef MLX5_PMD_SOFT_COUNTERS
423 total_length = length;
425 assert(length >= MLX5_WQE_DWORD_SIZE);
426 /* Update element. */
427 (*txq->elts)[elts_head] = buf;
428 elts_head = (elts_head + 1) & (elts_n - 1);
429 /* Prefetch next buffer data. */
431 volatile void *pkt_addr;
433 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
434 rte_prefetch0(pkt_addr);
436 /* Should we enable HW CKSUM offload */
438 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
440 MLX5_ETH_WQE_L3_CSUM |
441 MLX5_ETH_WQE_L4_CSUM;
443 wqe->eseg.cs_flags = 0;
445 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
447 * Start by copying the Ethernet header minus the first two
448 * bytes which will be appended at the end of the Ethernet
451 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
452 length -= MLX5_WQE_DWORD_SIZE;
453 addr += MLX5_WQE_DWORD_SIZE;
454 /* Replace the Ethernet type by the VLAN if necessary. */
455 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
456 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
458 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
460 &vlan, sizeof(vlan));
461 addr -= sizeof(vlan);
462 length += sizeof(vlan);
464 /* Inline if enough room. */
465 if (txq->max_inline != 0) {
466 uintptr_t end = (uintptr_t)
467 (((uintptr_t)txq->wqes) +
468 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
469 uint16_t max_inline =
470 txq->max_inline * RTE_CACHE_LINE_SIZE;
474 * raw starts two bytes before the boundary to
475 * continue the above copy of packet data.
477 raw += MLX5_WQE_DWORD_SIZE - 2;
478 room = end - (uintptr_t)raw;
479 if (room > max_inline) {
480 uintptr_t addr_end = (addr + max_inline) &
481 ~(RTE_CACHE_LINE_SIZE - 1);
482 uint16_t copy_b = ((addr_end - addr) > length) ?
486 rte_memcpy((void *)raw, (void *)addr, copy_b);
489 pkt_inline_sz += copy_b;
491 assert(addr <= addr_end);
494 * 2 DWORDs consumed by the WQE header + 1 DSEG +
495 * the size of the inline part of the packet.
497 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
499 dseg = (volatile struct mlx5_wqe_data_seg *)
501 (ds * MLX5_WQE_DWORD_SIZE));
502 if ((uintptr_t)dseg >= end)
503 dseg = (volatile struct
507 } else if (!segs_n) {
514 * No inline has been done in the packet, only the
515 * Ethernet Header as been stored.
517 wqe->eseg.inline_hdr_sz = htons(MLX5_WQE_DWORD_SIZE);
518 dseg = (volatile struct mlx5_wqe_data_seg *)
519 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
522 /* Add the remaining packet as a simple ds. */
523 *dseg = (volatile struct mlx5_wqe_data_seg) {
524 .addr = htonll(addr),
525 .byte_count = htonl(length),
526 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
537 * Spill on next WQE when the current one does not have
538 * enough room left. Size of WQE must a be a multiple
539 * of data segment size.
541 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
542 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
543 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
544 ((1 << txq->wqe_n) - 1);
546 dseg = (volatile struct mlx5_wqe_data_seg *)
548 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
555 length = DATA_LEN(buf);
556 #ifdef MLX5_PMD_SOFT_COUNTERS
557 total_length += length;
559 /* Store segment information. */
560 *dseg = (volatile struct mlx5_wqe_data_seg) {
561 .addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t)),
562 .byte_count = htonl(length),
563 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
565 (*txq->elts)[elts_head] = buf;
566 elts_head = (elts_head + 1) & (elts_n - 1);
575 /* Initialize known and common part of the WQE structure. */
576 wqe->ctrl[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
577 wqe->ctrl[1] = htonl(txq->qp_num_8s | ds);
584 wqe->eseg.inline_hdr_sz = htons(pkt_inline_sz);
585 wqe->eseg.inline_hdr[0] = ehdr[0];
586 wqe->eseg.inline_hdr[1] = ehdr[1];
587 txq->wqe_ci += (ds + 3) / 4;
588 #ifdef MLX5_PMD_SOFT_COUNTERS
589 /* Increment sent bytes counter. */
590 txq->stats.obytes += total_length;
593 /* Take a shortcut if nothing must be sent. */
594 if (unlikely(i == 0))
596 /* Check whether completion threshold has been reached. */
597 comp = txq->elts_comp + i + j;
598 if (comp >= MLX5_TX_COMP_THRESH) {
599 /* Request completion on last WQE. */
600 wqe->ctrl[2] = htonl(8);
601 /* Save elts_head in unused "immediate" field of WQE. */
602 wqe->ctrl[3] = elts_head;
605 txq->elts_comp = comp;
607 #ifdef MLX5_PMD_SOFT_COUNTERS
608 /* Increment sent packets counter. */
609 txq->stats.opackets += i;
611 /* Ring QP doorbell. */
613 txq->elts_head = elts_head;
618 * Open a MPW session.
621 * Pointer to TX queue structure.
623 * Pointer to MPW session structure.
628 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
630 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
631 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
632 (volatile struct mlx5_wqe_data_seg (*)[])
633 tx_mlx5_wqe(txq, idx + 1);
635 mpw->state = MLX5_MPW_STATE_OPENED;
639 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
640 mpw->wqe->eseg.mss = htons(length);
641 mpw->wqe->eseg.inline_hdr_sz = 0;
642 mpw->wqe->eseg.rsvd0 = 0;
643 mpw->wqe->eseg.rsvd1 = 0;
644 mpw->wqe->eseg.rsvd2 = 0;
645 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
646 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
647 mpw->wqe->ctrl[2] = 0;
648 mpw->wqe->ctrl[3] = 0;
649 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
650 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
651 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
652 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
653 mpw->data.dseg[2] = &(*dseg)[0];
654 mpw->data.dseg[3] = &(*dseg)[1];
655 mpw->data.dseg[4] = &(*dseg)[2];
659 * Close a MPW session.
662 * Pointer to TX queue structure.
664 * Pointer to MPW session structure.
667 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
669 unsigned int num = mpw->pkts_n;
672 * Store size in multiple of 16 bytes. Control and Ethernet segments
675 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
676 mpw->state = MLX5_MPW_STATE_CLOSED;
681 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
682 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
686 * DPDK callback for TX with MPW support.
689 * Generic pointer to TX queue structure.
691 * Packets to transmit.
693 * Number of packets in array.
696 * Number of packets successfully transmitted (<= pkts_n).
699 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
701 struct txq *txq = (struct txq *)dpdk_txq;
702 uint16_t elts_head = txq->elts_head;
703 const unsigned int elts_n = 1 << txq->elts_n;
708 struct mlx5_mpw mpw = {
709 .state = MLX5_MPW_STATE_CLOSED,
712 if (unlikely(!pkts_n))
714 /* Prefetch first packet cacheline. */
715 tx_prefetch_cqe(txq, txq->cq_ci);
716 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
717 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
718 /* Start processing. */
720 max = (elts_n - (elts_head - txq->elts_tail));
724 struct rte_mbuf *buf = *(pkts++);
725 unsigned int elts_head_next;
727 unsigned int segs_n = buf->nb_segs;
728 uint32_t cs_flags = 0;
731 * Make sure there is enough room to store this packet and
732 * that one ring entry remains unused.
735 if (max < segs_n + 1)
737 /* Do not bother with large packets MPW cannot handle. */
738 if (segs_n > MLX5_MPW_DSEG_MAX)
742 /* Should we enable HW CKSUM offload */
744 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
745 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
746 /* Retrieve packet information. */
747 length = PKT_LEN(buf);
749 /* Start new session if packet differs. */
750 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
751 ((mpw.len != length) ||
753 (mpw.wqe->eseg.cs_flags != cs_flags)))
754 mlx5_mpw_close(txq, &mpw);
755 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
756 mlx5_mpw_new(txq, &mpw, length);
757 mpw.wqe->eseg.cs_flags = cs_flags;
759 /* Multi-segment packets must be alone in their MPW. */
760 assert((segs_n == 1) || (mpw.pkts_n == 0));
761 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
765 volatile struct mlx5_wqe_data_seg *dseg;
768 elts_head_next = (elts_head + 1) & (elts_n - 1);
770 (*txq->elts)[elts_head] = buf;
771 dseg = mpw.data.dseg[mpw.pkts_n];
772 addr = rte_pktmbuf_mtod(buf, uintptr_t);
773 *dseg = (struct mlx5_wqe_data_seg){
774 .byte_count = htonl(DATA_LEN(buf)),
775 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
776 .addr = htonll(addr),
778 elts_head = elts_head_next;
779 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
780 length += DATA_LEN(buf);
786 assert(length == mpw.len);
787 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
788 mlx5_mpw_close(txq, &mpw);
789 elts_head = elts_head_next;
790 #ifdef MLX5_PMD_SOFT_COUNTERS
791 /* Increment sent bytes counter. */
792 txq->stats.obytes += length;
796 /* Take a shortcut if nothing must be sent. */
797 if (unlikely(i == 0))
799 /* Check whether completion threshold has been reached. */
800 /* "j" includes both packets and segments. */
801 comp = txq->elts_comp + j;
802 if (comp >= MLX5_TX_COMP_THRESH) {
803 volatile struct mlx5_wqe *wqe = mpw.wqe;
805 /* Request completion on last WQE. */
806 wqe->ctrl[2] = htonl(8);
807 /* Save elts_head in unused "immediate" field of WQE. */
808 wqe->ctrl[3] = elts_head;
811 txq->elts_comp = comp;
813 #ifdef MLX5_PMD_SOFT_COUNTERS
814 /* Increment sent packets counter. */
815 txq->stats.opackets += i;
817 /* Ring QP doorbell. */
818 if (mpw.state == MLX5_MPW_STATE_OPENED)
819 mlx5_mpw_close(txq, &mpw);
821 txq->elts_head = elts_head;
826 * Open a MPW inline session.
829 * Pointer to TX queue structure.
831 * Pointer to MPW session structure.
836 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
838 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
839 struct mlx5_wqe_inl_small *inl;
841 mpw->state = MLX5_MPW_INL_STATE_OPENED;
845 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
846 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
849 mpw->wqe->ctrl[2] = 0;
850 mpw->wqe->ctrl[3] = 0;
851 mpw->wqe->eseg.mss = htons(length);
852 mpw->wqe->eseg.inline_hdr_sz = 0;
853 mpw->wqe->eseg.cs_flags = 0;
854 mpw->wqe->eseg.rsvd0 = 0;
855 mpw->wqe->eseg.rsvd1 = 0;
856 mpw->wqe->eseg.rsvd2 = 0;
857 inl = (struct mlx5_wqe_inl_small *)
858 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
859 mpw->data.raw = (uint8_t *)&inl->raw;
863 * Close a MPW inline session.
866 * Pointer to TX queue structure.
868 * Pointer to MPW session structure.
871 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
874 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
875 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
877 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
879 * Store size in multiple of 16 bytes. Control and Ethernet segments
882 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
883 mpw->state = MLX5_MPW_STATE_CLOSED;
884 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
885 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
889 * DPDK callback for TX with MPW inline support.
892 * Generic pointer to TX queue structure.
894 * Packets to transmit.
896 * Number of packets in array.
899 * Number of packets successfully transmitted (<= pkts_n).
902 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
905 struct txq *txq = (struct txq *)dpdk_txq;
906 uint16_t elts_head = txq->elts_head;
907 const unsigned int elts_n = 1 << txq->elts_n;
912 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
913 struct mlx5_mpw mpw = {
914 .state = MLX5_MPW_STATE_CLOSED,
917 if (unlikely(!pkts_n))
919 /* Prefetch first packet cacheline. */
920 tx_prefetch_cqe(txq, txq->cq_ci);
921 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
922 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
923 /* Start processing. */
925 max = (elts_n - (elts_head - txq->elts_tail));
929 struct rte_mbuf *buf = *(pkts++);
930 unsigned int elts_head_next;
933 unsigned int segs_n = buf->nb_segs;
934 uint32_t cs_flags = 0;
937 * Make sure there is enough room to store this packet and
938 * that one ring entry remains unused.
941 if (max < segs_n + 1)
943 /* Do not bother with large packets MPW cannot handle. */
944 if (segs_n > MLX5_MPW_DSEG_MAX)
948 /* Should we enable HW CKSUM offload */
950 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
951 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
952 /* Retrieve packet information. */
953 length = PKT_LEN(buf);
954 /* Start new session if packet differs. */
955 if (mpw.state == MLX5_MPW_STATE_OPENED) {
956 if ((mpw.len != length) ||
958 (mpw.wqe->eseg.cs_flags != cs_flags))
959 mlx5_mpw_close(txq, &mpw);
960 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
961 if ((mpw.len != length) ||
963 (length > inline_room) ||
964 (mpw.wqe->eseg.cs_flags != cs_flags)) {
965 mlx5_mpw_inline_close(txq, &mpw);
967 txq->max_inline * RTE_CACHE_LINE_SIZE;
970 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
972 (length > inline_room)) {
973 mlx5_mpw_new(txq, &mpw, length);
974 mpw.wqe->eseg.cs_flags = cs_flags;
976 mlx5_mpw_inline_new(txq, &mpw, length);
977 mpw.wqe->eseg.cs_flags = cs_flags;
980 /* Multi-segment packets must be alone in their MPW. */
981 assert((segs_n == 1) || (mpw.pkts_n == 0));
982 if (mpw.state == MLX5_MPW_STATE_OPENED) {
983 assert(inline_room ==
984 txq->max_inline * RTE_CACHE_LINE_SIZE);
985 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
989 volatile struct mlx5_wqe_data_seg *dseg;
992 (elts_head + 1) & (elts_n - 1);
994 (*txq->elts)[elts_head] = buf;
995 dseg = mpw.data.dseg[mpw.pkts_n];
996 addr = rte_pktmbuf_mtod(buf, uintptr_t);
997 *dseg = (struct mlx5_wqe_data_seg){
998 .byte_count = htonl(DATA_LEN(buf)),
999 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1000 .addr = htonll(addr),
1002 elts_head = elts_head_next;
1003 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1004 length += DATA_LEN(buf);
1010 assert(length == mpw.len);
1011 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1012 mlx5_mpw_close(txq, &mpw);
1016 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1017 assert(length <= inline_room);
1018 assert(length == DATA_LEN(buf));
1019 elts_head_next = (elts_head + 1) & (elts_n - 1);
1020 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1021 (*txq->elts)[elts_head] = buf;
1022 /* Maximum number of bytes before wrapping. */
1023 max = ((((uintptr_t)(txq->wqes)) +
1026 (uintptr_t)mpw.data.raw);
1028 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1031 mpw.data.raw = (volatile void *)txq->wqes;
1032 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1033 (void *)(addr + max),
1035 mpw.data.raw += length - max;
1037 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1040 mpw.data.raw += length;
1042 if ((uintptr_t)mpw.data.raw ==
1043 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1044 mpw.data.raw = (volatile void *)txq->wqes;
1047 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1048 mlx5_mpw_inline_close(txq, &mpw);
1050 txq->max_inline * RTE_CACHE_LINE_SIZE;
1052 inline_room -= length;
1055 mpw.total_len += length;
1056 elts_head = elts_head_next;
1057 #ifdef MLX5_PMD_SOFT_COUNTERS
1058 /* Increment sent bytes counter. */
1059 txq->stats.obytes += length;
1063 /* Take a shortcut if nothing must be sent. */
1064 if (unlikely(i == 0))
1066 /* Check whether completion threshold has been reached. */
1067 /* "j" includes both packets and segments. */
1068 comp = txq->elts_comp + j;
1069 if (comp >= MLX5_TX_COMP_THRESH) {
1070 volatile struct mlx5_wqe *wqe = mpw.wqe;
1072 /* Request completion on last WQE. */
1073 wqe->ctrl[2] = htonl(8);
1074 /* Save elts_head in unused "immediate" field of WQE. */
1075 wqe->ctrl[3] = elts_head;
1078 txq->elts_comp = comp;
1080 #ifdef MLX5_PMD_SOFT_COUNTERS
1081 /* Increment sent packets counter. */
1082 txq->stats.opackets += i;
1084 /* Ring QP doorbell. */
1085 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1086 mlx5_mpw_inline_close(txq, &mpw);
1087 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1088 mlx5_mpw_close(txq, &mpw);
1090 txq->elts_head = elts_head;
1095 * Translate RX completion flags to packet type.
1100 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1103 * Packet type for struct rte_mbuf.
1105 static inline uint32_t
1106 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1109 uint8_t flags = cqe->l4_hdr_type_etc;
1111 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1114 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1115 RTE_PTYPE_L3_IPV4) |
1117 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1118 RTE_PTYPE_L3_IPV6) |
1120 MLX5_CQE_RX_IPV4_PACKET,
1121 RTE_PTYPE_INNER_L3_IPV4) |
1123 MLX5_CQE_RX_IPV6_PACKET,
1124 RTE_PTYPE_INNER_L3_IPV6);
1128 MLX5_CQE_L3_HDR_TYPE_IPV6,
1129 RTE_PTYPE_L3_IPV6) |
1131 MLX5_CQE_L3_HDR_TYPE_IPV4,
1137 * Get size of the next packet for a given CQE. For compressed CQEs, the
1138 * consumer index is updated only once all packets of the current one have
1142 * Pointer to RX queue.
1145 * @param[out] rss_hash
1146 * Packet RSS Hash result.
1149 * Packet size in bytes (0 if there is none), -1 in case of completion
1153 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1154 uint16_t cqe_cnt, uint32_t *rss_hash)
1156 struct rxq_zip *zip = &rxq->zip;
1157 uint16_t cqe_n = cqe_cnt + 1;
1160 /* Process compressed data in the CQE and mini arrays. */
1162 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1163 (volatile struct mlx5_mini_cqe8 (*)[8])
1164 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1166 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1167 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1168 if ((++zip->ai & 7) == 0) {
1170 * Increment consumer index to skip the number of
1171 * CQEs consumed. Hardware leaves holes in the CQ
1172 * ring for software use.
1177 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1178 uint16_t idx = rxq->cq_ci + 1;
1179 uint16_t end = zip->cq_ci;
1181 while (idx != end) {
1182 (*rxq->cqes)[idx & cqe_cnt].op_own =
1183 MLX5_CQE_INVALIDATE;
1186 rxq->cq_ci = zip->cq_ci;
1189 /* No compressed data, get next CQE and verify if it is compressed. */
1194 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1195 if (unlikely(ret == 1))
1198 op_own = cqe->op_own;
1199 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1200 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1201 (volatile struct mlx5_mini_cqe8 (*)[8])
1202 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1205 /* Fix endianness. */
1206 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1208 * Current mini array position is the one returned by
1211 * If completion comprises several mini arrays, as a
1212 * special case the second one is located 7 CQEs after
1213 * the initial CQE instead of 8 for subsequent ones.
1215 zip->ca = rxq->cq_ci & cqe_cnt;
1216 zip->na = zip->ca + 7;
1217 /* Compute the next non compressed CQE. */
1219 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1220 /* Get packet size to return. */
1221 len = ntohl((*mc)[0].byte_cnt);
1222 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1225 len = ntohl(cqe->byte_cnt);
1226 *rss_hash = ntohl(cqe->rx_hash_res);
1228 /* Error while receiving packet. */
1229 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1236 * Translate RX completion flags to offload flags.
1239 * Pointer to RX queue structure.
1244 * Offload flags (ol_flags) for struct rte_mbuf.
1246 static inline uint32_t
1247 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1249 uint32_t ol_flags = 0;
1250 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1251 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1253 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1254 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1255 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1257 PKT_RX_IP_CKSUM_GOOD);
1258 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1259 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1260 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1261 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1262 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1264 PKT_RX_L4_CKSUM_GOOD);
1265 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1267 TRANSPOSE(cqe->l4_hdr_type_etc,
1268 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1269 PKT_RX_IP_CKSUM_GOOD) |
1270 TRANSPOSE(cqe->l4_hdr_type_etc,
1271 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1272 PKT_RX_L4_CKSUM_GOOD);
1277 * DPDK callback for RX.
1280 * Generic pointer to RX queue structure.
1282 * Array to store received packets.
1284 * Maximum number of packets in array.
1287 * Number of packets successfully received (<= pkts_n).
1290 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1292 struct rxq *rxq = dpdk_rxq;
1293 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1294 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1295 const unsigned int sges_n = rxq->sges_n;
1296 struct rte_mbuf *pkt = NULL;
1297 struct rte_mbuf *seg = NULL;
1298 volatile struct mlx5_cqe *cqe =
1299 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1301 unsigned int rq_ci = rxq->rq_ci << sges_n;
1302 int len; /* keep its value across iterations. */
1305 unsigned int idx = rq_ci & wqe_cnt;
1306 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1307 struct rte_mbuf *rep = (*rxq->elts)[idx];
1308 uint32_t rss_hash_res = 0;
1316 rep = rte_mbuf_raw_alloc(rxq->mp);
1317 if (unlikely(rep == NULL)) {
1318 ++rxq->stats.rx_nombuf;
1321 * no buffers before we even started,
1322 * bail out silently.
1326 while (pkt != seg) {
1327 assert(pkt != (*rxq->elts)[idx]);
1329 rte_mbuf_refcnt_set(pkt, 0);
1330 __rte_mbuf_raw_free(pkt);
1336 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1337 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1340 rte_mbuf_refcnt_set(rep, 0);
1341 __rte_mbuf_raw_free(rep);
1344 if (unlikely(len == -1)) {
1345 /* RX error, packet is likely too large. */
1346 rte_mbuf_refcnt_set(rep, 0);
1347 __rte_mbuf_raw_free(rep);
1348 ++rxq->stats.idropped;
1352 assert(len >= (rxq->crc_present << 2));
1353 /* Update packet information. */
1354 pkt->packet_type = 0;
1356 if (rss_hash_res && rxq->rss_hash) {
1357 pkt->hash.rss = rss_hash_res;
1358 pkt->ol_flags = PKT_RX_RSS_HASH;
1361 ((cqe->sop_drop_qpn !=
1362 htonl(MLX5_FLOW_MARK_INVALID)) ||
1363 (cqe->sop_drop_qpn !=
1364 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1366 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1367 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1368 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1370 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1374 rxq_cq_to_pkt_type(cqe);
1376 rxq_cq_to_ol_flags(rxq, cqe);
1378 if (cqe->l4_hdr_type_etc &
1379 MLX5_CQE_VLAN_STRIPPED) {
1380 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1381 PKT_RX_VLAN_STRIPPED;
1382 pkt->vlan_tci = ntohs(cqe->vlan_info);
1384 if (rxq->crc_present)
1385 len -= ETHER_CRC_LEN;
1389 DATA_LEN(rep) = DATA_LEN(seg);
1390 PKT_LEN(rep) = PKT_LEN(seg);
1391 SET_DATA_OFF(rep, DATA_OFF(seg));
1392 NB_SEGS(rep) = NB_SEGS(seg);
1393 PORT(rep) = PORT(seg);
1395 (*rxq->elts)[idx] = rep;
1397 * Fill NIC descriptor with the new buffer. The lkey and size
1398 * of the buffers are already known, only the buffer address
1401 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1402 if (len > DATA_LEN(seg)) {
1403 len -= DATA_LEN(seg);
1408 DATA_LEN(seg) = len;
1409 #ifdef MLX5_PMD_SOFT_COUNTERS
1410 /* Increment bytes counter. */
1411 rxq->stats.ibytes += PKT_LEN(pkt);
1413 /* Return packet. */
1419 /* Align consumer index to the next stride. */
1424 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1426 /* Update the consumer index. */
1427 rxq->rq_ci = rq_ci >> sges_n;
1429 *rxq->cq_db = htonl(rxq->cq_ci);
1431 *rxq->rq_db = htonl(rxq->rq_ci);
1432 #ifdef MLX5_PMD_SOFT_COUNTERS
1433 /* Increment packets counter. */
1434 rxq->stats.ipackets += i;
1440 * Dummy DPDK callback for TX.
1442 * This function is used to temporarily replace the real callback during
1443 * unsafe control operations on the queue, or in case of error.
1446 * Generic pointer to TX queue structure.
1448 * Packets to transmit.
1450 * Number of packets in array.
1453 * Number of packets successfully transmitted (<= pkts_n).
1456 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1465 * Dummy DPDK callback for RX.
1467 * This function is used to temporarily replace the real callback during
1468 * unsafe control operations on the queue, or in case of error.
1471 * Generic pointer to RX queue structure.
1473 * Array to store received packets.
1475 * Maximum number of packets in array.
1478 * Number of packets successfully received (<= pkts_n).
1481 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)