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34 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
35 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
44 #include <rte_mempool.h>
45 #include <rte_prefetch.h>
48 #include "mlx5_utils.h"
49 #include "mlx5_rxtx.h"
50 #include "mlx5_rxtx_vec.h"
51 #include "mlx5_autoconf.h"
52 #include "mlx5_defs.h"
55 #pragma GCC diagnostic ignored "-Wcast-qual"
58 * Fill in buffer descriptors in a multi-packet send descriptor.
61 * Pointer to TX queue structure.
63 * Pointer to buffer descriptor to be writen.
65 * Pointer to array of packets to be sent.
67 * Number of packets to be filled.
70 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg,
71 struct rte_mbuf **pkts, unsigned int n)
75 const uint8x16_t dseg_shuf_m = {
76 3, 2, 1, 0, /* length, bswap32 */
77 4, 5, 6, 7, /* lkey */
78 15, 14, 13, 12, /* addr, bswap64 */
81 #ifdef MLX5_PMD_SOFT_COUNTERS
85 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) {
87 struct rte_mbuf *pkt = pkts[pos];
89 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
90 desc = vreinterpretq_u8_u32((uint32x4_t) {
92 mlx5_tx_mb2mr(txq, pkt),
95 desc = vqtbl1q_u8(desc, dseg_shuf_m);
97 #ifdef MLX5_PMD_SOFT_COUNTERS
98 tx_byte += DATA_LEN(pkt);
101 #ifdef MLX5_PMD_SOFT_COUNTERS
102 txq->stats.obytes += tx_byte;
107 * Send multi-segmented packets until it encounters a single segment packet in
111 * Pointer to TX queue structure.
113 * Pointer to array of packets to be sent.
115 * Number of packets to be sent.
118 * Number of packets successfully transmitted (<= pkts_n).
121 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
124 uint16_t elts_head = txq->elts_head;
125 const uint16_t elts_n = 1 << txq->elts_n;
126 const uint16_t elts_m = elts_n - 1;
127 const uint16_t wq_n = 1 << txq->wqe_n;
128 const uint16_t wq_mask = wq_n - 1;
129 const unsigned int nb_dword_per_wqebb =
130 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
131 const unsigned int nb_dword_in_hdr =
132 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
134 volatile struct mlx5_wqe *wqe = NULL;
136 assert(elts_n > pkts_n);
137 mlx5_tx_complete(txq);
138 if (unlikely(!pkts_n))
140 for (n = 0; n < pkts_n; ++n) {
141 struct rte_mbuf *buf = pkts[n];
142 unsigned int segs_n = buf->nb_segs;
143 unsigned int ds = nb_dword_in_hdr;
144 unsigned int len = PKT_LEN(buf);
145 uint16_t wqe_ci = txq->wqe_ci;
146 const uint8x16_t ctrl_shuf_m = {
147 3, 2, 1, 0, /* bswap32 */
148 7, 6, 5, 4, /* bswap32 */
149 11, 10, 9, 8, /* bswap32 */
152 uint8_t cs_flags = 0;
160 max_elts = elts_n - (elts_head - txq->elts_tail);
161 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
163 * A MPW session consumes 2 WQEs at most to
164 * include MLX5_MPW_DSEG_MAX pointers.
167 max_elts < segs_n || max_wqe < 2)
169 wqe = &((volatile struct mlx5_wqe64 *)
170 txq->wqes)[wqe_ci & wq_mask].hdr;
172 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
173 const uint64_t is_tunneled =
174 buf->ol_flags & (PKT_TX_TUNNEL_GRE |
175 PKT_TX_TUNNEL_VXLAN);
177 if (is_tunneled && txq->tunnel_en) {
178 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
179 MLX5_ETH_WQE_L4_INNER_CSUM;
180 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
181 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
183 cs_flags = MLX5_ETH_WQE_L3_CSUM |
184 MLX5_ETH_WQE_L4_CSUM;
187 /* Title WQEBB pointer. */
188 t_wqe = (uint8x16_t *)wqe;
189 dseg = (uint8_t *)(wqe + 1);
191 if (!(ds++ % nb_dword_per_wqebb)) {
193 &((volatile struct mlx5_wqe64 *)
194 txq->wqes)[++wqe_ci & wq_mask];
196 txq_wr_dseg_v(txq, dseg, &buf, 1);
197 dseg += MLX5_WQE_DWORD_SIZE;
198 (*txq->elts)[elts_head++ & elts_m] = buf;
202 /* Fill CTRL in the header. */
203 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
204 MLX5_OPC_MOD_MPW << 24 |
205 txq->wqe_ci << 8 | MLX5_OPCODE_TSO,
206 txq->qp_num_8s | ds, 0, 0});
207 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
208 vst1q_u8((void *)t_wqe, ctrl);
209 /* Fill ESEG in the header. */
210 vst1q_u16((void *)(t_wqe + 1),
211 (uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len),
213 txq->wqe_ci = wqe_ci;
217 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
218 txq->elts_head = elts_head;
219 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
220 wqe->ctrl[2] = rte_cpu_to_be_32(8);
221 wqe->ctrl[3] = txq->elts_head;
225 #ifdef MLX5_PMD_SOFT_COUNTERS
226 txq->stats.opackets += n;
228 mlx5_tx_dbrec(txq, wqe);
233 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
234 * it returns to make it processed by txq_scatter_v(). All the packets in
235 * the pkts list should be single segment packets having same offload flags.
236 * This must be checked by txq_check_multiseg() and txq_calc_offload().
239 * Pointer to TX queue structure.
241 * Pointer to array of packets to be sent.
243 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
245 * Checksum offload flags to be written in the descriptor.
248 * Number of packets successfully transmitted (<= pkts_n).
250 static inline uint16_t
251 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
254 struct rte_mbuf **elts;
255 uint16_t elts_head = txq->elts_head;
256 const uint16_t elts_n = 1 << txq->elts_n;
257 const uint16_t elts_m = elts_n - 1;
258 const unsigned int nb_dword_per_wqebb =
259 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
260 const unsigned int nb_dword_in_hdr =
261 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
266 uint32_t comp_req = 0;
267 const uint16_t wq_n = 1 << txq->wqe_n;
268 const uint16_t wq_mask = wq_n - 1;
269 uint16_t wq_idx = txq->wqe_ci & wq_mask;
270 volatile struct mlx5_wqe64 *wq =
271 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
272 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
273 const uint8x16_t ctrl_shuf_m = {
274 3, 2, 1, 0, /* bswap32 */
275 7, 6, 5, 4, /* bswap32 */
276 11, 10, 9, 8, /* bswap32 */
283 /* Make sure all packets can fit into a single WQE. */
284 assert(elts_n > pkts_n);
285 mlx5_tx_complete(txq);
286 max_elts = (elts_n - (elts_head - txq->elts_tail));
287 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
288 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
289 if (unlikely(!pkts_n))
291 elts = &(*txq->elts)[elts_head & elts_m];
292 /* Loop for available tailroom first. */
293 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
294 for (pos = 0; pos < (n & -2); pos += 2)
295 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos]));
297 elts[pos] = pkts[pos];
298 /* Check if it crosses the end of the queue. */
299 if (unlikely(n < pkts_n)) {
300 elts = &(*txq->elts)[0];
301 for (pos = 0; pos < pkts_n - n; ++pos)
302 elts[pos] = pkts[n + pos];
304 txq->elts_head += pkts_n;
305 /* Save title WQEBB pointer. */
306 t_wqe = (uint8x16_t *)wqe;
307 dseg = (uint8_t *)(wqe + 1);
308 /* Calculate the number of entries to the end. */
310 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
313 txq_wr_dseg_v(txq, dseg, pkts, n);
314 /* Check if it crosses the end of the queue. */
316 dseg = (uint8_t *)txq->wqes;
317 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
319 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
320 txq->elts_comp += pkts_n;
322 /* Request a completion. */
327 /* Fill CTRL in the header. */
328 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
329 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
330 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW,
331 txq->qp_num_8s | (pkts_n + 2),
334 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
335 vst1q_u8((void *)t_wqe, ctrl);
336 /* Fill ESEG in the header. */
337 vst1q_u8((void *)(t_wqe + 1),
338 (uint8x16_t) { 0, 0, 0, 0,
342 #ifdef MLX5_PMD_SOFT_COUNTERS
343 txq->stats.opackets += pkts_n;
345 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
347 /* Ring QP doorbell. */
348 mlx5_tx_dbrec(txq, wqe);
353 * Store free buffers to RX SW ring.
356 * Pointer to RX queue structure.
358 * Pointer to array of packets to be stored.
360 * Number of packets to be stored.
363 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
365 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
366 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
370 for (pos = 0; pos < p; pos += 2) {
373 mbp = vld1q_u64((void *)&elts[pos]);
374 vst1q_u64((void *)&pkts[pos], mbp);
377 pkts[pos] = elts[pos];
381 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
382 * extracted from the title completion descriptor.
385 * Pointer to RX queue structure.
387 * Pointer to completion array having a compressed completion at first.
389 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
390 * the title completion descriptor to be copied to the rest of mbufs.
393 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
394 struct rte_mbuf **elts)
396 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
397 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
400 unsigned int inv = 0;
401 /* Mask to shuffle from extracted mini CQE to mbuf. */
402 const uint8x16_t mcqe_shuf_m1 = {
403 -1, -1, -1, -1, /* skip packet_type */
404 7, 6, -1, -1, /* pkt_len, bswap16 */
405 7, 6, /* data_len, bswap16 */
406 -1, -1, /* skip vlan_tci */
407 3, 2, 1, 0 /* hash.rss, bswap32 */
409 const uint8x16_t mcqe_shuf_m2 = {
410 -1, -1, -1, -1, /* skip packet_type */
411 15, 14, -1, -1, /* pkt_len, bswap16 */
412 15, 14, /* data_len, bswap16 */
413 -1, -1, /* skip vlan_tci */
414 11, 10, 9, 8 /* hash.rss, bswap32 */
416 /* Restore the compressed count. Must be 16 bits. */
417 const uint16_t mcqe_n = t_pkt->data_len +
418 (rxq->crc_present * ETHER_CRC_LEN);
419 const uint64x2_t rearm =
420 vld1q_u64((void *)&t_pkt->rearm_data);
421 const uint32x4_t rxdf_mask = {
422 0xffffffff, /* packet_type */
423 0, /* skip pkt_len */
424 0xffff0000, /* vlan_tci, skip data_len */
425 0, /* skip hash.rss */
427 const uint8x16_t rxdf =
428 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
429 vreinterpretq_u8_u32(rxdf_mask));
430 const uint16x8_t crc_adj = {
432 rxq->crc_present * ETHER_CRC_LEN, 0,
433 rxq->crc_present * ETHER_CRC_LEN, 0,
436 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
437 #ifdef MLX5_PMD_SOFT_COUNTERS
438 uint32_t rcvd_byte = 0;
440 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
441 const uint8x8_t len_shuf_m = {
443 15, 14, /* 2nd mCQE */
444 23, 22, /* 3rd mCQE */
445 31, 30 /* 4th mCQE */
449 * Not to overflow elts array. Decompress next time after mbuf
452 if (unlikely(mcqe_n + MLX5_VPMD_DESCS_PER_LOOP >
453 (uint16_t)(rxq->rq_ci - rxq->cq_ci)))
456 * A. load mCQEs into a 128bit register.
457 * B. store rearm data to mbuf.
458 * C. combine data from mCQEs with rx_descriptor_fields1.
459 * D. store rx_descriptor_fields1.
460 * E. store flow tag (rte_flow mark).
462 for (pos = 0; pos < mcqe_n; ) {
463 uint8_t *p = (void *)&mcq[pos % 8];
464 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
465 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
466 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
467 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
469 #ifdef MLX5_PMD_SOFT_COUNTERS
470 uint16x4_t invalid_mask =
471 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
472 -1UL << ((mcqe_n - pos) *
473 sizeof(uint16_t) * 8) : 0);
476 if (!(pos & 0x7) && pos + 8 < mcqe_n)
477 rte_prefetch0((void *)(cq + pos + 8));
479 /* A.1 load mCQEs into a 128bit register. */
480 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
481 /* B.1 store rearm data to mbuf. */
482 "st1 {%[rearm].2d}, [%[e0]] \n\t"
483 "add %[e0], %[e0], #16 \n\t"
484 "st1 {%[rearm].2d}, [%[e1]] \n\t"
485 "add %[e1], %[e1], #16 \n\t"
486 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
487 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
488 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
489 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
490 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
491 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
492 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
493 /* D.1 store rx_descriptor_fields1. */
494 "st1 {v18.2d}, [%[e0]] \n\t"
495 "st1 {v19.2d}, [%[e1]] \n\t"
496 /* B.1 store rearm data to mbuf. */
497 "st1 {%[rearm].2d}, [%[e2]] \n\t"
498 "add %[e2], %[e2], #16 \n\t"
499 "st1 {%[rearm].2d}, [%[e3]] \n\t"
500 "add %[e3], %[e3], #16 \n\t"
501 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
502 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
503 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
504 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
505 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
506 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
507 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
508 /* D.1 store rx_descriptor_fields1. */
509 "st1 {v18.2d}, [%[e2]] \n\t"
510 "st1 {v19.2d}, [%[e3]] \n\t"
511 #ifdef MLX5_PMD_SOFT_COUNTERS
512 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
514 :[byte_cnt]"=&w"(byte_cnt)
518 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
519 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
520 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
521 [crc_adj]"w"(crc_adj),
522 [len_shuf_m]"w"(len_shuf_m)
523 :"memory", "v16", "v17", "v18", "v19");
524 #ifdef MLX5_PMD_SOFT_COUNTERS
525 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
526 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
529 /* E.1 store flow tag (rte_flow mark). */
530 elts[pos]->hash.fdir.hi = flow_tag;
531 elts[pos + 1]->hash.fdir.hi = flow_tag;
532 elts[pos + 2]->hash.fdir.hi = flow_tag;
533 elts[pos + 3]->hash.fdir.hi = flow_tag;
535 pos += MLX5_VPMD_DESCS_PER_LOOP;
536 /* Move to next CQE and invalidate consumed CQEs. */
537 if (!(pos & 0x7) && pos < mcqe_n) {
538 mcq = (void *)&(cq + pos)->pkt_info;
539 for (i = 0; i < 8; ++i)
540 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
543 /* Invalidate the rest of CQEs. */
544 for (; inv < mcqe_n; ++inv)
545 cq[inv].op_own = MLX5_CQE_INVALIDATE;
546 #ifdef MLX5_PMD_SOFT_COUNTERS
547 rxq->stats.ipackets += mcqe_n;
548 rxq->stats.ibytes += rcvd_byte;
550 rxq->cq_ci += mcqe_n;
554 * Calculate packet type and offload flag for mbuf and store it.
557 * Pointer to RX queue structure.
559 * Array of four 4bytes packet type info extracted from the original
560 * completion descriptor.
562 * Array of four 4bytes flow ID extracted from the original completion
565 * Opcode vector having responder error status. Each field is 4B.
567 * Pointer to array of packets to be filled.
570 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
571 uint32x4_t ptype_info, uint32x4_t flow_tag,
572 uint16x4_t op_err, struct rte_mbuf **pkts)
575 uint32x4_t pinfo, cv_flags;
576 uint32x4_t ol_flags = vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH);
577 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
578 const uint8x16_t cv_flag_sel = {
580 (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
581 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
583 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
585 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
586 0, 0, 0, 0, 0, 0, 0, 0, 0
588 const uint32x4_t cv_mask =
589 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
590 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
591 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
592 const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
593 uint64x2_t rearm0, rearm1, rearm2, rearm3;
596 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
597 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
598 const uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
600 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
601 ol_flags = vorrq_u32(ol_flags, vbicq_u32(fdir_flags,
602 vceqzq_u32(flow_tag)));
603 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
604 ol_flags = vorrq_u32(ol_flags,
605 vbicq_u32(fdir_id_flags,
606 vceqq_u32(flow_tag, ft_def)));
609 * ptype_info has the following:
613 * bit[11:10] = l3_hdr_type
614 * bit[14:12] = l4_hdr_type
617 * bit[17] = outer_l3_type
619 ptype = vshrn_n_u32(ptype_info, 10);
620 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
621 ptype = vorr_u16(ptype, op_err);
622 pkts[0]->packet_type =
623 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 6)];
624 pkts[1]->packet_type =
625 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 4)];
626 pkts[2]->packet_type =
627 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 2)];
628 pkts[3]->packet_type =
629 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 0)];
630 /* Fill flags for checksum and VLAN. */
631 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
632 pinfo = vreinterpretq_u32_u8(
633 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
634 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
635 cv_flags = vshlq_n_u32(pinfo, 9);
636 cv_flags = vorrq_u32(pinfo, cv_flags);
637 /* Move back flags to start from byte[0]. */
638 cv_flags = vshrq_n_u32(cv_flags, 8);
639 /* Mask out garbage bits. */
640 cv_flags = vandq_u32(cv_flags, cv_mask);
641 /* Merge to ol_flags. */
642 ol_flags = vorrq_u32(ol_flags, cv_flags);
643 /* Merge mbuf_init and ol_flags, and store. */
644 rearm0 = vcombine_u64(mbuf_init,
645 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32(
647 rearm1 = vcombine_u64(mbuf_init,
648 vand_u64(vget_high_u64(vreinterpretq_u64_u32(
649 ol_flags)), r32_mask));
650 rearm2 = vcombine_u64(mbuf_init,
651 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32(
653 rearm3 = vcombine_u64(mbuf_init,
654 vand_u64(vget_low_u64(vreinterpretq_u64_u32(
655 ol_flags)), r32_mask));
656 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
657 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
658 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
659 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
663 * Receive burst of packets. An errored completion also consumes a mbuf, but the
664 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
665 * before returning to application.
668 * Pointer to RX queue structure.
670 * Array to store received packets.
672 * Maximum number of packets in array.
675 * Number of packets received including errors (<= pkts_n).
677 static inline uint16_t
678 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
680 const uint16_t q_n = 1 << rxq->cqe_n;
681 const uint16_t q_mask = q_n - 1;
682 volatile struct mlx5_cqe *cq;
683 struct rte_mbuf **elts;
687 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
688 uint16_t nocmp_n = 0;
689 uint16_t rcvd_pkt = 0;
690 unsigned int cq_idx = rxq->cq_ci & q_mask;
691 unsigned int elts_idx;
692 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
693 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
694 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
695 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
696 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
697 #ifdef MLX5_PMD_SOFT_COUNTERS
698 uint32_t rcvd_byte = 0;
700 /* Mask to generate 16B length vector. */
701 const uint8x8_t len_shuf_m = {
702 52, 53, /* 4th CQE */
703 36, 37, /* 3rd CQE */
704 20, 21, /* 2nd CQE */
707 /* Mask to extract 16B data from a 64B CQE. */
708 const uint8x16_t cqe_shuf_m = {
709 28, 29, /* hdr_type_etc */
712 47, 46, /* byte_cnt, bswap16 */
713 31, 30, /* vlan_info, bswap16 */
714 15, 14, 13, 12, /* rx_hash_res, bswap32 */
715 57, 58, 59, /* flow_tag */
718 /* Mask to generate 16B data for mbuf. */
719 const uint8x16_t mb_shuf_m = {
720 4, 5, -1, -1, /* pkt_len */
723 8, 9, 10, 11, /* hash.rss */
724 12, 13, 14, -1 /* hash.fdir.hi */
726 /* Mask to generate 16B owner vector. */
727 const uint8x8_t owner_shuf_m = {
728 63, -1, /* 4th CQE */
729 47, -1, /* 3rd CQE */
730 31, -1, /* 2nd CQE */
733 /* Mask to generate a vector having packet_type/ol_flags. */
734 const uint8x16_t ptype_shuf_m = {
735 48, 49, 50, -1, /* 4th CQE */
736 32, 33, 34, -1, /* 3rd CQE */
737 16, 17, 18, -1, /* 2nd CQE */
738 0, 1, 2, -1 /* 1st CQE */
740 /* Mask to generate a vector having flow tags. */
741 const uint8x16_t ftag_shuf_m = {
742 60, 61, 62, -1, /* 4th CQE */
743 44, 45, 46, -1, /* 3rd CQE */
744 28, 29, 30, -1, /* 2nd CQE */
745 12, 13, 14, -1 /* 1st CQE */
747 const uint16x8_t crc_adj = {
748 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0
750 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
752 assert(rxq->sges_n == 0);
753 assert(rxq->cqe_n == rxq->elts_n);
754 cq = &(*rxq->cqes)[cq_idx];
755 rte_prefetch_non_temporal(cq);
756 rte_prefetch_non_temporal(cq + 1);
757 rte_prefetch_non_temporal(cq + 2);
758 rte_prefetch_non_temporal(cq + 3);
759 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
762 * rq_ci >= cq_ci >= rq_pi
763 * Definition of indexes:
764 * rq_ci - cq_ci := # of buffers owned by HW (posted).
765 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
766 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
768 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
769 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
770 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
771 /* See if there're unreturned mbufs from compressed CQE. */
772 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
774 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
775 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
776 rxq->rq_pi += rcvd_pkt;
779 elts_idx = rxq->rq_pi & q_mask;
780 elts = &(*rxq->elts)[elts_idx];
781 pkts_n = RTE_MIN(pkts_n - rcvd_pkt,
782 (uint16_t)(rxq->rq_ci - rxq->cq_ci));
783 /* Not to overflow pkts/elts array. */
784 pkts_n = RTE_ALIGN_FLOOR(pkts_n, MLX5_VPMD_DESCS_PER_LOOP);
785 /* Not to cross queue end. */
786 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
789 /* At this point, there shouldn't be any remained packets. */
790 assert(rxq->rq_pi == rxq->cq_ci);
792 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
793 * there's no instruction to count trailing zeros. __builtin_clzl() is
796 * A. copy 4 mbuf pointers from elts ring to returing pkts.
797 * B. load 64B CQE and extract necessary fields
798 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
799 * following structure:
801 * uint16_t hdr_type_etc;
805 * uint16_t vlan_info;
806 * uint32_t rx_has_res;
807 * uint8_t flow_tag[3];
812 * E. find compressed CQE.
816 pos += MLX5_VPMD_DESCS_PER_LOOP) {
818 uint16x4_t opcode, owner_mask, invalid_mask;
819 uint16x4_t comp_mask;
822 uint32x4_t ptype_info, flow_tag;
823 uint8_t *p0, *p1, *p2, *p3;
824 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
825 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
826 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
827 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
828 void *elts_p = (void *)&elts[pos];
829 void *pkts_p = (void *)&pkts[pos];
831 /* A.0 do not cross the end of CQ. */
832 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
833 -1UL >> ((pkts_n - pos) *
834 sizeof(uint16_t) * 8) : 0);
835 p0 = (void *)&cq[pos].pkt_info;
836 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
837 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
838 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
839 /* Prefetch next 4 CQEs. */
840 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
841 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
842 rte_prefetch_non_temporal(&cq[next]);
843 rte_prefetch_non_temporal(&cq[next + 1]);
844 rte_prefetch_non_temporal(&cq[next + 2]);
845 rte_prefetch_non_temporal(&cq[next + 3]);
848 /* B.1 (CQE 3) load a block having op_own. */
849 "ld1 {v19.16b}, [%[p3]] \n\t"
850 "sub %[p3], %[p3], #48 \n\t"
851 /* B.2 (CQE 3) load the rest blocks. */
852 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
853 /* B.3 (CQE 3) extract 16B fields. */
854 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
855 /* B.4 (CQE 3) adjust CRC length. */
856 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
857 /* B.1 (CQE 2) load a block having op_own. */
858 "ld1 {v19.16b}, [%[p2]] \n\t"
859 "sub %[p2], %[p2], #48 \n\t"
860 /* C.1 (CQE 3) generate final structure for mbuf. */
861 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
862 /* B.2 (CQE 2) load the rest blocks. */
863 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
864 /* B.3 (CQE 2) extract 16B fields. */
865 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
866 /* B.4 (CQE 2) adjust CRC length. */
867 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
868 /* B.1 (CQE 1) load a block having op_own. */
869 "ld1 {v19.16b}, [%[p1]] \n\t"
870 "sub %[p1], %[p1], #48 \n\t"
871 /* C.1 (CQE 2) generate final structure for mbuf. */
872 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
873 /* B.2 (CQE 1) load the rest blocks. */
874 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
875 /* B.3 (CQE 1) extract 16B fields. */
876 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
877 /* B.4 (CQE 1) adjust CRC length. */
878 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
879 /* B.1 (CQE 0) load a block having op_own. */
880 "ld1 {v19.16b}, [%[p0]] \n\t"
881 "sub %[p0], %[p0], #48 \n\t"
882 /* C.1 (CQE 1) generate final structure for mbuf. */
883 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
884 /* B.2 (CQE 0) load the rest blocks. */
885 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
886 /* B.3 (CQE 0) extract 16B fields. */
887 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
888 /* B.4 (CQE 0) adjust CRC length. */
889 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
890 /* A.1 load mbuf pointers. */
891 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
892 /* D.1 extract op_own byte. */
893 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
894 /* C.2 (CQE 3) adjust flow mark. */
895 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
896 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
897 "st1 {v15.2d}, [%[e3]] \n\t"
898 /* C.2 (CQE 2) adjust flow mark. */
899 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
900 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
901 "st1 {v14.2d}, [%[e2]] \n\t"
902 /* C.1 (CQE 0) generate final structure for mbuf. */
903 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
904 /* C.2 (CQE 1) adjust flow mark. */
905 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
906 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
907 "st1 {v13.2d}, [%[e1]] \n\t"
908 #ifdef MLX5_PMD_SOFT_COUNTERS
909 /* Extract byte_cnt. */
910 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
912 /* Extract ptype_info. */
913 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
914 /* Extract flow_tag. */
915 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
916 /* A.2 copy mbuf pointers. */
917 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
918 /* C.2 (CQE 0) adjust flow mark. */
919 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
920 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
921 "st1 {v12.2d}, [%[e0]] \n\t"
922 :[op_own]"=&w"(op_own),
923 [byte_cnt]"=&w"(byte_cnt),
924 [ptype_info]"=&w"(ptype_info),
925 [flow_tag]"=&w"(flow_tag)
926 :[p3]"r"(p3 + 48), [p2]"r"(p2 + 48),
927 [p1]"r"(p1 + 48), [p0]"r"(p0 + 48),
928 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
931 [cqe_shuf_m]"w"(cqe_shuf_m),
932 [mb_shuf_m]"w"(mb_shuf_m),
933 [owner_shuf_m]"w"(owner_shuf_m),
934 [len_shuf_m]"w"(len_shuf_m),
935 [ptype_shuf_m]"w"(ptype_shuf_m),
936 [ftag_shuf_m]"w"(ftag_shuf_m),
937 [crc_adj]"w"(crc_adj),
938 [flow_mark_adj]"w"(flow_mark_adj)
940 "v12", "v13", "v14", "v15",
941 "v16", "v17", "v18", "v19",
942 "v20", "v21", "v22", "v23",
944 /* D.2 flip owner bit to mark CQEs from last round. */
945 owner_mask = vand_u16(op_own, owner_check);
946 owner_mask = vceq_u16(owner_mask, ownership);
947 /* D.3 get mask for invalidated CQEs. */
948 opcode = vand_u16(op_own, opcode_check);
949 invalid_mask = vceq_u16(opcode_check, opcode);
950 /* E.1 find compressed CQE format. */
951 comp_mask = vand_u16(op_own, format_check);
952 comp_mask = vceq_u16(comp_mask, format_check);
953 /* D.4 mask out beyond boundary. */
954 invalid_mask = vorr_u16(invalid_mask, mask);
955 /* D.5 merge invalid_mask with invalid owner. */
956 invalid_mask = vorr_u16(invalid_mask, owner_mask);
957 /* E.2 mask out invalid entries. */
958 comp_mask = vbic_u16(comp_mask, invalid_mask);
959 /* E.3 get the first compressed CQE. */
960 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
962 (sizeof(uint16_t) * 8);
963 /* D.6 mask out entries after the compressed CQE. */
964 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
965 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
967 invalid_mask = vorr_u16(invalid_mask, mask);
968 /* D.7 count non-compressed valid CQEs. */
969 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
970 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
972 /* D.2 get the final invalid mask. */
973 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
974 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
975 invalid_mask = vorr_u16(invalid_mask, mask);
976 /* D.3 check error in opcode. */
977 opcode = vceq_u16(resp_err_check, opcode);
978 opcode = vbic_u16(opcode, invalid_mask);
979 /* D.4 mark if any error is set */
981 !!vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
982 /* C.4 fill in mbuf - rearm_data and packet_type. */
983 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
985 #ifdef MLX5_PMD_SOFT_COUNTERS
986 /* Add up received bytes count. */
987 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
988 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
991 * Break the loop unless more valid CQE is expected, or if
992 * there's a compressed CQE.
994 if (n != MLX5_VPMD_DESCS_PER_LOOP)
997 /* If no new CQE seen, return without updating cq_db. */
998 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1000 /* Update the consumer indexes for non-compressed CQEs. */
1001 assert(nocmp_n <= pkts_n);
1002 rxq->cq_ci += nocmp_n;
1003 rxq->rq_pi += nocmp_n;
1004 rcvd_pkt += nocmp_n;
1005 #ifdef MLX5_PMD_SOFT_COUNTERS
1006 rxq->stats.ipackets += nocmp_n;
1007 rxq->stats.ibytes += rcvd_byte;
1009 /* Decompress the last CQE if compressed. */
1010 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1011 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1012 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1013 /* Return more packets if needed. */
1014 if (nocmp_n < pkts_n) {
1015 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1017 n = RTE_MIN(n, pkts_n - nocmp_n);
1018 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1023 rte_compiler_barrier();
1024 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1028 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */