1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_
12 #include <smmintrin.h>
15 #include <rte_mempool.h>
16 #include <rte_prefetch.h>
20 #include "mlx5_defs.h"
22 #include "mlx5_utils.h"
23 #include "mlx5_rxtx.h"
24 #include "mlx5_rxtx_vec.h"
25 #include "mlx5_autoconf.h"
27 #ifndef __INTEL_COMPILER
28 #pragma GCC diagnostic ignored "-Wcast-qual"
32 * Store free buffers to RX SW ring.
35 * Pointer to RX queue structure.
37 * Pointer to array of packets to be stored.
39 * Number of packets to be stored.
42 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
44 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
45 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
49 for (pos = 0; pos < p; pos += 2) {
52 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
53 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
56 pkts[pos] = elts[pos];
60 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
61 * extracted from the title completion descriptor.
64 * Pointer to RX queue structure.
66 * Pointer to completion array having a compressed completion at first.
68 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
69 * the title completion descriptor to be copied to the rest of mbufs.
72 * Number of mini-CQEs successfully decompressed.
74 static inline uint16_t
75 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
76 struct rte_mbuf **elts)
78 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
79 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
83 /* Mask to shuffle from extracted mini CQE to mbuf. */
84 const __m128i shuf_mask1 =
85 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
86 -1, -1, /* skip vlan_tci */
87 6, 7, /* data_len, bswap16 */
88 -1, -1, 6, 7, /* pkt_len, bswap16 */
89 -1, -1, -1, -1 /* skip packet_type */);
90 const __m128i shuf_mask2 =
91 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
92 -1, -1, /* skip vlan_tci */
93 14, 15, /* data_len, bswap16 */
94 -1, -1, 14, 15, /* pkt_len, bswap16 */
95 -1, -1, -1, -1 /* skip packet_type */);
96 /* Restore the compressed count. Must be 16 bits. */
97 const uint16_t mcqe_n = t_pkt->data_len +
98 (rxq->crc_present * RTE_ETHER_CRC_LEN);
100 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
102 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
103 const __m128i crc_adj =
104 _mm_set_epi16(0, 0, 0,
105 rxq->crc_present * RTE_ETHER_CRC_LEN,
107 rxq->crc_present * RTE_ETHER_CRC_LEN,
109 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
110 #ifdef MLX5_PMD_SOFT_COUNTERS
111 const __m128i zero = _mm_setzero_si128();
112 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
113 uint32_t rcvd_byte = 0;
114 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
115 const __m128i len_shuf_mask =
116 _mm_set_epi8(-1, -1, -1, -1,
122 * A. load mCQEs into a 128bit register.
123 * B. store rearm data to mbuf.
124 * C. combine data from mCQEs with rx_descriptor_fields1.
125 * D. store rx_descriptor_fields1.
126 * E. store flow tag (rte_flow mark).
128 for (pos = 0; pos < mcqe_n; ) {
129 __m128i mcqe1, mcqe2;
130 __m128i rxdf1, rxdf2;
131 #ifdef MLX5_PMD_SOFT_COUNTERS
132 __m128i byte_cnt, invalid_mask;
135 if (!(pos & 0x7) && pos + 8 < mcqe_n)
136 rte_prefetch0((void *)(cq + pos + 8));
137 /* A.1 load mCQEs into a 128bit register. */
138 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
139 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
140 /* B.1 store rearm data to mbuf. */
141 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
142 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
143 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
144 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
145 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
146 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
147 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
148 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
149 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
150 /* D.1 store rx_descriptor_fields1. */
151 _mm_storeu_si128((__m128i *)
152 &elts[pos]->rx_descriptor_fields1,
154 _mm_storeu_si128((__m128i *)
155 &elts[pos + 1]->rx_descriptor_fields1,
157 /* B.1 store rearm data to mbuf. */
158 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
159 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
160 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
161 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
162 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
163 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
164 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
165 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
166 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
167 /* D.1 store rx_descriptor_fields1. */
168 _mm_storeu_si128((__m128i *)
169 &elts[pos + 2]->rx_descriptor_fields1,
171 _mm_storeu_si128((__m128i *)
172 &elts[pos + 3]->rx_descriptor_fields1,
174 #ifdef MLX5_PMD_SOFT_COUNTERS
175 invalid_mask = _mm_set_epi64x(0,
177 sizeof(uint16_t) * 8);
178 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
179 mcqe1 = _mm_srli_si128(mcqe1, 4);
180 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
181 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
182 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
183 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
184 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
187 /* E.1 store flow tag (rte_flow mark). */
188 elts[pos]->hash.fdir.hi = flow_tag;
189 elts[pos + 1]->hash.fdir.hi = flow_tag;
190 elts[pos + 2]->hash.fdir.hi = flow_tag;
191 elts[pos + 3]->hash.fdir.hi = flow_tag;
193 if (rte_flow_dynf_metadata_avail()) {
194 const uint32_t meta = *RTE_FLOW_DYNF_METADATA(t_pkt);
196 /* Check if title packet has valid metadata. */
198 MLX5_ASSERT(t_pkt->ol_flags &
199 PKT_RX_DYNF_METADATA);
200 *RTE_FLOW_DYNF_METADATA(elts[pos]) = meta;
201 *RTE_FLOW_DYNF_METADATA(elts[pos + 1]) = meta;
202 *RTE_FLOW_DYNF_METADATA(elts[pos + 2]) = meta;
203 *RTE_FLOW_DYNF_METADATA(elts[pos + 3]) = meta;
206 pos += MLX5_VPMD_DESCS_PER_LOOP;
207 /* Move to next CQE and invalidate consumed CQEs. */
208 if (!(pos & 0x7) && pos < mcqe_n) {
209 mcq = (void *)(cq + pos);
210 for (i = 0; i < 8; ++i)
211 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
214 /* Invalidate the rest of CQEs. */
215 for (; inv < mcqe_n; ++inv)
216 cq[inv].op_own = MLX5_CQE_INVALIDATE;
217 #ifdef MLX5_PMD_SOFT_COUNTERS
218 rxq->stats.ipackets += mcqe_n;
219 rxq->stats.ibytes += rcvd_byte;
221 rxq->cq_ci += mcqe_n;
226 * Calculate packet type and offload flag for mbuf and store it.
229 * Pointer to RX queue structure.
231 * Array of four 16bytes completions extracted from the original completion
234 * Opcode vector having responder error status. Each field is 4B.
236 * Pointer to array of packets to be filled.
239 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
240 __m128i op_err, struct rte_mbuf **pkts)
242 __m128i pinfo0, pinfo1;
243 __m128i pinfo, ptype;
244 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
245 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
247 const __m128i zero = _mm_setzero_si128();
248 const __m128i ptype_mask =
249 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
250 const __m128i ptype_ol_mask =
251 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
252 const __m128i pinfo_mask =
253 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
254 const __m128i cv_flag_sel =
255 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
256 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
257 PKT_RX_L4_CKSUM_GOOD) >> 1),
259 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
261 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
262 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
264 const __m128i cv_mask =
265 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
266 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
267 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
268 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
269 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
270 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
271 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
272 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
273 const __m128i mbuf_init =
274 _mm_load_si128((__m128i *)&rxq->mbuf_initializer);
275 __m128i rearm0, rearm1, rearm2, rearm3;
276 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
278 /* Extract pkt_info field. */
279 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
280 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
281 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
282 /* Extract hdr_type_etc field. */
283 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
284 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
285 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
287 const __m128i pinfo_ft_mask =
288 _mm_set_epi32(0xffffff00, 0xffffff00,
289 0xffffff00, 0xffffff00);
290 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
291 __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
292 __m128i flow_tag, invalid_mask;
294 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
295 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
296 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
297 ol_flags = _mm_or_si128(ol_flags,
298 _mm_andnot_si128(invalid_mask,
300 /* Mask out invalid entries. */
301 fdir_id_flags = _mm_andnot_si128(invalid_mask, fdir_id_flags);
302 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
303 ol_flags = _mm_or_si128(ol_flags,
305 _mm_cmpeq_epi32(flow_tag,
310 * Merge the two fields to generate the following:
314 * bit[11:10] = l3_hdr_type
315 * bit[14:12] = l4_hdr_type
318 * bit[17] = outer_l3_type
320 ptype = _mm_and_si128(ptype, ptype_mask);
321 pinfo = _mm_and_si128(pinfo, pinfo_mask);
322 pinfo = _mm_slli_epi32(pinfo, 16);
323 /* Make pinfo has merged fields for ol_flags calculation. */
324 pinfo = _mm_or_si128(ptype, pinfo);
325 ptype = _mm_srli_epi32(pinfo, 10);
326 ptype = _mm_packs_epi32(ptype, zero);
327 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
328 op_err = _mm_srli_epi16(op_err, 8);
329 ptype = _mm_or_si128(ptype, op_err);
330 pt_idx0 = _mm_extract_epi8(ptype, 0);
331 pt_idx1 = _mm_extract_epi8(ptype, 2);
332 pt_idx2 = _mm_extract_epi8(ptype, 4);
333 pt_idx3 = _mm_extract_epi8(ptype, 6);
334 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
335 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
336 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
337 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
338 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
339 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
340 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
341 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
342 /* Fill flags for checksum and VLAN. */
343 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
344 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
345 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
346 cv_flags = _mm_slli_epi32(pinfo, 9);
347 cv_flags = _mm_or_si128(pinfo, cv_flags);
348 /* Move back flags to start from byte[0]. */
349 cv_flags = _mm_srli_epi32(cv_flags, 8);
350 /* Mask out garbage bits. */
351 cv_flags = _mm_and_si128(cv_flags, cv_mask);
352 /* Merge to ol_flags. */
353 ol_flags = _mm_or_si128(ol_flags, cv_flags);
354 /* Merge mbuf_init and ol_flags. */
355 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
356 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
357 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
358 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
359 /* Write 8B rearm_data and 8B ol_flags. */
360 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
361 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
362 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
363 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
367 * Receive burst of packets. An errored completion also consumes a mbuf, but the
368 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
369 * before returning to application.
372 * Pointer to RX queue structure.
374 * Array to store received packets.
376 * Maximum number of packets in array.
378 * Pointer to a flag. Set non-zero value if pkts array has at least one error
382 * Number of packets received including errors (<= pkts_n).
384 static inline uint16_t
385 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
388 const uint16_t q_n = 1 << rxq->cqe_n;
389 const uint16_t q_mask = q_n - 1;
390 volatile struct mlx5_cqe *cq;
391 struct rte_mbuf **elts;
395 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
396 uint16_t nocmp_n = 0;
397 uint16_t rcvd_pkt = 0;
398 unsigned int cq_idx = rxq->cq_ci & q_mask;
399 unsigned int elts_idx;
400 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
401 const __m128i owner_check =
402 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
403 const __m128i opcode_check =
404 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
405 const __m128i format_check =
406 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
407 const __m128i resp_err_check =
408 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
409 #ifdef MLX5_PMD_SOFT_COUNTERS
410 uint32_t rcvd_byte = 0;
411 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
412 const __m128i len_shuf_mask =
413 _mm_set_epi8(-1, -1, -1, -1,
418 /* Mask to shuffle from extracted CQE to mbuf. */
419 const __m128i shuf_mask =
420 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
421 12, 13, 14, 15, /* rss, bswap32 */
422 10, 11, /* vlan_tci, bswap16 */
423 4, 5, /* data_len, bswap16 */
424 -1, -1, /* zero out 2nd half of pkt_len */
425 4, 5 /* pkt_len, bswap16 */);
426 /* Mask to blend from the last Qword to the first DQword. */
427 const __m128i blend_mask =
428 _mm_set_epi8(-1, -1, -1, -1,
432 const __m128i zero = _mm_setzero_si128();
433 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
434 const __m128i crc_adj =
435 _mm_set_epi16(0, 0, 0, 0, 0,
436 rxq->crc_present * RTE_ETHER_CRC_LEN,
438 rxq->crc_present * RTE_ETHER_CRC_LEN);
439 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
441 MLX5_ASSERT(rxq->sges_n == 0);
442 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n);
443 cq = &(*rxq->cqes)[cq_idx];
445 rte_prefetch0(cq + 1);
446 rte_prefetch0(cq + 2);
447 rte_prefetch0(cq + 3);
448 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
449 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
450 if (repl_n >= rxq->rq_repl_thresh)
451 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
452 /* See if there're unreturned mbufs from compressed CQE. */
453 rcvd_pkt = rxq->decompressed;
455 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
456 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
457 rxq->rq_pi += rcvd_pkt;
458 rxq->decompressed -= rcvd_pkt;
461 elts_idx = rxq->rq_pi & q_mask;
462 elts = &(*rxq->elts)[elts_idx];
463 /* Not to overflow pkts array. */
464 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
465 /* Not to cross queue end. */
466 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
467 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx);
470 /* At this point, there shouldn't be any remained packets. */
471 MLX5_ASSERT(rxq->decompressed == 0);
473 * A. load first Qword (8bytes) in one loop.
474 * B. copy 4 mbuf pointers from elts ring to returing pkts.
475 * C. load remained CQE data and extract necessary fields.
476 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
477 * following structure:
480 * uint8_t flow_tag[3];
484 * uint16_t hdr_type_etc;
485 * uint16_t vlan_info;
486 * uint32_t rx_has_res;
490 * F. find compressed CQE.
494 pos += MLX5_VPMD_DESCS_PER_LOOP) {
495 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
496 __m128i cqe_tmp1, cqe_tmp2;
497 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
498 __m128i op_own, op_own_tmp1, op_own_tmp2;
499 __m128i opcode, owner_mask, invalid_mask;
502 #ifdef MLX5_PMD_SOFT_COUNTERS
506 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
507 unsigned int p1, p2, p3;
509 /* Prefetch next 4 CQEs. */
510 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
511 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
512 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
513 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
514 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
516 /* A.0 do not cross the end of CQ. */
517 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
518 mask = _mm_sll_epi64(ones, mask);
519 p = _mm_andnot_si128(mask, p);
521 p3 = _mm_extract_epi16(p, 3);
522 cqes[3] = _mm_loadl_epi64((__m128i *)
523 &cq[pos + p3].sop_drop_qpn);
524 rte_compiler_barrier();
525 p2 = _mm_extract_epi16(p, 2);
526 cqes[2] = _mm_loadl_epi64((__m128i *)
527 &cq[pos + p2].sop_drop_qpn);
528 rte_compiler_barrier();
529 /* B.1 load mbuf pointers. */
530 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
531 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
532 /* A.1 load a block having op_own. */
533 p1 = _mm_extract_epi16(p, 1);
534 cqes[1] = _mm_loadl_epi64((__m128i *)
535 &cq[pos + p1].sop_drop_qpn);
536 rte_compiler_barrier();
537 cqes[0] = _mm_loadl_epi64((__m128i *)
538 &cq[pos].sop_drop_qpn);
539 /* B.2 copy mbuf pointers. */
540 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
541 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
543 /* C.1 load remained CQE data and extract necessary fields. */
544 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
545 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
546 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
547 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
548 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].csum);
549 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].csum);
550 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
551 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
552 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd4[2]);
553 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd4[2]);
554 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
555 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
556 /* C.2 generate final structure for mbuf with swapping bytes. */
557 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
558 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
559 /* C.3 adjust CRC length. */
560 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
561 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
562 /* C.4 adjust flow mark. */
563 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
564 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
565 /* D.1 fill in mbuf - rx_descriptor_fields1. */
566 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
567 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
568 /* E.1 extract op_own field. */
569 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
570 /* C.1 load remained CQE data and extract necessary fields. */
571 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
572 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
573 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
574 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
575 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].csum);
576 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].csum);
577 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
578 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
579 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd4[2]);
580 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd4[2]);
581 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
582 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
583 /* C.2 generate final structure for mbuf with swapping bytes. */
584 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
585 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
586 /* C.3 adjust CRC length. */
587 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
588 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
589 /* C.4 adjust flow mark. */
590 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
591 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
592 /* E.1 extract op_own byte. */
593 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
594 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
595 /* D.1 fill in mbuf - rx_descriptor_fields1. */
596 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
597 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
598 /* E.2 flip owner bit to mark CQEs from last round. */
599 owner_mask = _mm_and_si128(op_own, owner_check);
601 owner_mask = _mm_xor_si128(owner_mask, owner_check);
602 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
603 owner_mask = _mm_packs_epi32(owner_mask, zero);
604 /* E.3 get mask for invalidated CQEs. */
605 opcode = _mm_and_si128(op_own, opcode_check);
606 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
607 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
608 /* E.4 mask out beyond boundary. */
609 invalid_mask = _mm_or_si128(invalid_mask, mask);
610 /* E.5 merge invalid_mask with invalid owner. */
611 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
612 /* F.1 find compressed CQE format. */
613 comp_mask = _mm_and_si128(op_own, format_check);
614 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
615 comp_mask = _mm_packs_epi32(comp_mask, zero);
616 /* F.2 mask out invalid entries. */
617 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
618 comp_idx = _mm_cvtsi128_si64(comp_mask);
619 /* F.3 get the first compressed CQE. */
620 comp_idx = comp_idx ?
621 __builtin_ctzll(comp_idx) /
622 (sizeof(uint16_t) * 8) :
623 MLX5_VPMD_DESCS_PER_LOOP;
624 /* E.6 mask out entries after the compressed CQE. */
625 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
626 mask = _mm_sll_epi64(ones, mask);
627 invalid_mask = _mm_or_si128(invalid_mask, mask);
628 /* E.7 count non-compressed valid CQEs. */
629 n = _mm_cvtsi128_si64(invalid_mask);
630 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
631 MLX5_VPMD_DESCS_PER_LOOP;
633 /* D.2 get the final invalid mask. */
634 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
635 mask = _mm_sll_epi64(ones, mask);
636 invalid_mask = _mm_or_si128(invalid_mask, mask);
637 /* D.3 check error in opcode. */
638 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
639 opcode = _mm_packs_epi32(opcode, zero);
640 opcode = _mm_andnot_si128(invalid_mask, opcode);
641 /* D.4 mark if any error is set */
642 *err |= _mm_cvtsi128_si64(opcode);
643 /* D.5 fill in mbuf - rearm_data and packet_type. */
644 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
645 if (rxq->hw_timestamp) {
646 pkts[pos]->timestamp =
647 rte_be_to_cpu_64(cq[pos].timestamp);
648 pkts[pos + 1]->timestamp =
649 rte_be_to_cpu_64(cq[pos + p1].timestamp);
650 pkts[pos + 2]->timestamp =
651 rte_be_to_cpu_64(cq[pos + p2].timestamp);
652 pkts[pos + 3]->timestamp =
653 rte_be_to_cpu_64(cq[pos + p3].timestamp);
655 if (rte_flow_dynf_metadata_avail()) {
656 /* This code is subject for futher optimization. */
657 *RTE_FLOW_DYNF_METADATA(pkts[pos]) =
658 cq[pos].flow_table_metadata;
659 *RTE_FLOW_DYNF_METADATA(pkts[pos + 1]) =
660 cq[pos + p1].flow_table_metadata;
661 *RTE_FLOW_DYNF_METADATA(pkts[pos + 2]) =
662 cq[pos + p2].flow_table_metadata;
663 *RTE_FLOW_DYNF_METADATA(pkts[pos + 3]) =
664 cq[pos + p3].flow_table_metadata;
665 if (*RTE_FLOW_DYNF_METADATA(pkts[pos]))
666 pkts[pos]->ol_flags |= PKT_RX_DYNF_METADATA;
667 if (*RTE_FLOW_DYNF_METADATA(pkts[pos + 1]))
668 pkts[pos + 1]->ol_flags |= PKT_RX_DYNF_METADATA;
669 if (*RTE_FLOW_DYNF_METADATA(pkts[pos + 2]))
670 pkts[pos + 2]->ol_flags |= PKT_RX_DYNF_METADATA;
671 if (*RTE_FLOW_DYNF_METADATA(pkts[pos + 3]))
672 pkts[pos + 3]->ol_flags |= PKT_RX_DYNF_METADATA;
674 #ifdef MLX5_PMD_SOFT_COUNTERS
675 /* Add up received bytes count. */
676 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
677 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
678 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
679 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
682 * Break the loop unless more valid CQE is expected, or if
683 * there's a compressed CQE.
685 if (n != MLX5_VPMD_DESCS_PER_LOOP)
688 /* If no new CQE seen, return without updating cq_db. */
689 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
691 /* Update the consumer indexes for non-compressed CQEs. */
692 MLX5_ASSERT(nocmp_n <= pkts_n);
693 rxq->cq_ci += nocmp_n;
694 rxq->rq_pi += nocmp_n;
696 #ifdef MLX5_PMD_SOFT_COUNTERS
697 rxq->stats.ipackets += nocmp_n;
698 rxq->stats.ibytes += rcvd_byte;
700 /* Decompress the last CQE if compressed. */
701 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
702 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
703 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],
705 /* Return more packets if needed. */
706 if (nocmp_n < pkts_n) {
707 uint16_t n = rxq->decompressed;
709 n = RTE_MIN(n, pkts_n - nocmp_n);
710 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
713 rxq->decompressed -= n;
716 rte_compiler_barrier();
717 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
721 #endif /* RTE_PMD_MLX5_RXTX_VEC_SSE_H_ */