drivers/net/mrvl/mrvl_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Marvell International Ltd.
   5  *   Copyright(c) 2017 Semihalf.
   6  *   All rights reserved.
   7  *
   8  *   Redistribution and use in source and binary forms, with or without
   9  *   modification, are permitted provided that the following conditions
  10  *   are met:
  11  *
  12  *     * Redistributions of source code must retain the above copyright
  13  *       notice, this list of conditions and the following disclaimer.
  14  *     * Redistributions in binary form must reproduce the above copyright
  15  *       notice, this list of conditions and the following disclaimer in
  16  *       the documentation and/or other materials provided with the
  17  *       distribution.
  18  *     * Neither the name of Semihalf nor the names of its
  19  *       contributors may be used to endorse or promote products derived
  20  *       from this software without specific prior written permission.
  21  *
  22  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <rte_ethdev.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_log.h>
  38 #include <rte_malloc.h>
  39 #include <rte_bus_vdev.h>
  40
  41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  42  * we'll declare only one version.
  43  *
  44  * Note that it is not used in this PMD anyway.
  45  */
  46 #ifdef container_of
  47 #undef container_of
  48 #endif
  49
  50 #include <fcntl.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/sockios.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <sys/ioctl.h>
  56 #include <sys/socket.h>
  57 #include <sys/stat.h>
  58 #include <sys/types.h>
  59
  60 #include "mrvl_ethdev.h"
  61 #include "mrvl_qos.h"
  62
  63 /* bitmask with reserved hifs */
  64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  65 /* bitmask with reserved bpools */
  66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  67 /* bitmask with reserved kernel RSS tables */
  68 #define MRVL_MUSDK_RSS_RESERVED 0x01
  69 /* maximum number of available hifs */
  70 #define MRVL_MUSDK_HIFS_MAX 9
  71
  72 /* prefetch shift */
  73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  74
  75 /* TCAM has 25 entries reserved for uc/mc filter entries */
  76 #define MRVL_MAC_ADDRS_MAX 25
  77 #define MRVL_MATCH_LEN 16
  78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  79 /* Maximum allowable packet size */
  80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  81
  82 #define MRVL_IFACE_NAME_ARG "iface"
  83 #define MRVL_CFG_ARG "cfg"
  84
  85 #define MRVL_BURST_SIZE 64
  86
  87 #define MRVL_ARP_LENGTH 28
  88
  89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  90
  91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  92 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  93
  94 /* Memory size (in bytes) for MUSDK dma buffers */
  95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
  96
  97 static const char * const valid_args[] = {
  98         MRVL_IFACE_NAME_ARG,
  99         MRVL_CFG_ARG,
 100         NULL
 101 };
 102
 103 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 104 static struct pp2_hif *hifs[RTE_MAX_LCORE];
 105 static int used_bpools[PP2_NUM_PKT_PROC] = {
 106         MRVL_MUSDK_BPOOLS_RESERVED,
 107         MRVL_MUSDK_BPOOLS_RESERVED
 108 };
 109
 110 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
 111 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
 112 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 113
 114 /*
 115  * To use buffer harvesting based on loopback port shadow queue structure
 116  * was introduced for buffers information bookkeeping.
 117  *
 118  * Before sending the packet, related buffer information (pp2_buff_inf) is
 119  * stored in shadow queue. After packet is transmitted no longer used
 120  * packet buffer is released back to it's original hardware pool,
 121  * on condition it originated from interface.
 122  * In case it  was generated by application itself i.e: mbuf->port field is
 123  * 0xff then its released to software mempool.
 124  */
 125 struct mrvl_shadow_txq {
 126         int head;           /* write index - used when sending buffers */
 127         int tail;           /* read index - used when releasing buffers */
 128         u16 size;           /* queue occupied size */
 129         u16 num_to_release; /* number of buffers sent, that can be released */
 130         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 131 };
 132
 133 struct mrvl_rxq {
 134         struct mrvl_priv *priv;
 135         struct rte_mempool *mp;
 136         int queue_id;
 137         int port_id;
 138         int cksum_enabled;
 139         uint64_t bytes_recv;
 140         uint64_t drop_mac;
 141 };
 142
 143 struct mrvl_txq {
 144         struct mrvl_priv *priv;
 145         int queue_id;
 146         int port_id;
 147         uint64_t bytes_sent;
 148 };
 149
 150 /*
 151  * Every tx queue should have dedicated shadow tx queue.
 152  *
 153  * Ports assigned by DPDK might not start at zero or be continuous so
 154  * as a workaround define shadow queues for each possible port so that
 155  * we eventually fit somewhere.
 156  */
 157 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
 158
 159 /** Number of ports configured. */
 160 int mrvl_ports_nb;
 161 static int mrvl_lcore_first;
 162 static int mrvl_lcore_last;
 163
 164 static inline int
 165 mrvl_get_bpool_size(int pp2_id, int pool_id)
 166 {
 167         int i;
 168         int size = 0;
 169
 170         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 171                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 172
 173         return size;
 174 }
 175
 176 static inline int
 177 mrvl_reserve_bit(int *bitmap, int max)
 178 {
 179         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 180
 181         if (n >= max)
 182                 return -1;
 183
 184         *bitmap |= 1 << n;
 185
 186         return n;
 187 }
 188
 189 /**
 190  * Configure rss based on dpdk rss configuration.
 191  *
 192  * @param priv
 193  *   Pointer to private structure.
 194  * @param rss_conf
 195  *   Pointer to RSS configuration.
 196  *
 197  * @return
 198  *   0 on success, negative error value otherwise.
 199  */
 200 static int
 201 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 202 {
 203         if (rss_conf->rss_key)
 204                 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
 205
 206         if (rss_conf->rss_hf == 0) {
 207                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 208         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 209                 priv->ppio_params.inqs_params.hash_type =
 210                         PP2_PPIO_HASH_T_2_TUPLE;
 211         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 212                 priv->ppio_params.inqs_params.hash_type =
 213                         PP2_PPIO_HASH_T_5_TUPLE;
 214                 priv->rss_hf_tcp = 1;
 215         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 216                 priv->ppio_params.inqs_params.hash_type =
 217                         PP2_PPIO_HASH_T_5_TUPLE;
 218                 priv->rss_hf_tcp = 0;
 219         } else {
 220                 return -EINVAL;
 221         }
 222
 223         return 0;
 224 }
 225
 226 /**
 227  * Ethernet device configuration.
 228  *
 229  * Prepare the driver for a given number of TX and RX queues and
 230  * configure RSS.
 231  *
 232  * @param dev
 233  *   Pointer to Ethernet device structure.
 234  *
 235  * @return
 236  *   0 on success, negative error value otherwise.
 237  */
 238 static int
 239 mrvl_dev_configure(struct rte_eth_dev *dev)
 240 {
 241         struct mrvl_priv *priv = dev->data->dev_private;
 242         int ret;
 243
 244         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 245             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 246                 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
 247                         dev->data->dev_conf.rxmode.mq_mode);
 248                 return -EINVAL;
 249         }
 250
 251         if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
 252                 RTE_LOG(INFO, PMD,
 253                         "L2 CRC stripping is always enabled in hw\n");
 254                 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
 255         }
 256
 257         if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
 258                 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
 259                 return -EINVAL;
 260         }
 261
 262         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 263                 RTE_LOG(INFO, PMD, "Split headers not supported\n");
 264                 return -EINVAL;
 265         }
 266
 267         if (dev->data->dev_conf.rxmode.enable_scatter) {
 268                 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
 269                 return -EINVAL;
 270         }
 271
 272         if (dev->data->dev_conf.rxmode.enable_lro) {
 273                 RTE_LOG(INFO, PMD, "LRO not supported\n");
 274                 return -EINVAL;
 275         }
 276
 277         if (dev->data->dev_conf.rxmode.jumbo_frame)
 278                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 279                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 280
 281         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 282                                   dev->data->nb_rx_queues);
 283         if (ret < 0)
 284                 return ret;
 285
 286         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 287         priv->ppio_params.maintain_stats = 1;
 288         priv->nb_rx_queues = dev->data->nb_rx_queues;
 289
 290         if (dev->data->nb_rx_queues == 1 &&
 291             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 292                 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
 293                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 294
 295                 return 0;
 296         }
 297
 298         return mrvl_configure_rss(priv,
 299                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 300 }
 301
 302 /**
 303  * DPDK callback to change the MTU.
 304  *
 305  * Setting the MTU affects hardware MRU (packets larger than the MRU
 306  * will be dropped).
 307  *
 308  * @param dev
 309  *   Pointer to Ethernet device structure.
 310  * @param mtu
 311  *   New MTU.
 312  *
 313  * @return
 314  *   0 on success, negative error value otherwise.
 315  */
 316 static int
 317 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 318 {
 319         struct mrvl_priv *priv = dev->data->dev_private;
 320         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 321         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 322         int ret;
 323
 324         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 325                 return -EINVAL;
 326
 327         if (!priv->ppio)
 328                 return -EPERM;
 329
 330         ret = pp2_ppio_set_mru(priv->ppio, mru);
 331         if (ret)
 332                 return ret;
 333
 334         return pp2_ppio_set_mtu(priv->ppio, mtu);
 335 }
 336
 337 /**
 338  * DPDK callback to bring the link up.
 339  *
 340  * @param dev
 341  *   Pointer to Ethernet device structure.
 342  *
 343  * @return
 344  *   0 on success, negative error value otherwise.
 345  */
 346 static int
 347 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 348 {
 349         struct mrvl_priv *priv = dev->data->dev_private;
 350         int ret;
 351
 352         if (!priv->ppio)
 353                 return -EPERM;
 354
 355         ret = pp2_ppio_enable(priv->ppio);
 356         if (ret)
 357                 return ret;
 358
 359         /*
 360          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 361          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 362          * PP2_TRAFFIC_INGRESS_EGRESS.
 363          *
 364          * Set mtu to default DPDK value here.
 365          */
 366         ret = mrvl_mtu_set(dev, dev->data->mtu);
 367         if (ret)
 368                 pp2_ppio_disable(priv->ppio);
 369
 370         return ret;
 371 }
 372
 373 /**
 374  * DPDK callback to bring the link down.
 375  *
 376  * @param dev
 377  *   Pointer to Ethernet device structure.
 378  *
 379  * @return
 380  *   0 on success, negative error value otherwise.
 381  */
 382 static int
 383 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 384 {
 385         struct mrvl_priv *priv = dev->data->dev_private;
 386
 387         if (!priv->ppio)
 388                 return -EPERM;
 389
 390         return pp2_ppio_disable(priv->ppio);
 391 }
 392
 393 /**
 394  * DPDK callback to start the device.
 395  *
 396  * @param dev
 397  *   Pointer to Ethernet device structure.
 398  *
 399  * @return
 400  *   0 on success, negative errno value on failure.
 401  */
 402 static int
 403 mrvl_dev_start(struct rte_eth_dev *dev)
 404 {
 405         struct mrvl_priv *priv = dev->data->dev_private;
 406         char match[MRVL_MATCH_LEN];
 407         int ret;
 408
 409         snprintf(match, sizeof(match), "ppio-%d:%d",
 410                  priv->pp_id, priv->ppio_id);
 411         priv->ppio_params.match = match;
 412
 413         /*
 414          * Calculate the maximum bpool size for refill feature to 1.5 of the
 415          * configured size. In case the bpool size will exceed this value,
 416          * superfluous buffers will be removed
 417          */
 418         priv->bpool_max_size = priv->bpool_init_size +
 419                               (priv->bpool_init_size >> 1);
 420         /*
 421          * Calculate the minimum bpool size for refill feature as follows:
 422          * 2 default burst sizes multiply by number of rx queues.
 423          * If the bpool size will be below this value, new buffers will
 424          * be added to the pool.
 425          */
 426         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 427
 428         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 429         if (ret)
 430                 return ret;
 431
 432         /*
 433          * In case there are some some stale uc/mc mac addresses flush them
 434          * here. It cannot be done during mrvl_dev_close() as port information
 435          * is already gone at that point (due to pp2_ppio_deinit() in
 436          * mrvl_dev_stop()).
 437          */
 438         if (!priv->uc_mc_flushed) {
 439                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 440                 if (ret) {
 441                         RTE_LOG(ERR, PMD,
 442                                 "Failed to flush uc/mc filter list\n");
 443                         goto out;
 444                 }
 445                 priv->uc_mc_flushed = 1;
 446         }
 447
 448         if (!priv->vlan_flushed) {
 449                 ret = pp2_ppio_flush_vlan(priv->ppio);
 450                 if (ret) {
 451                         RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
 452                         /*
 453                          * TODO
 454                          * once pp2_ppio_flush_vlan() is supported jump to out
 455                          * goto out;
 456                          */
 457                 }
 458                 priv->vlan_flushed = 1;
 459         }
 460
 461         /* For default QoS config, don't start classifier. */
 462         if (mrvl_qos_cfg) {
 463                 ret = mrvl_start_qos_mapping(priv);
 464                 if (ret) {
 465                         pp2_ppio_deinit(priv->ppio);
 466                         return ret;
 467                 }
 468         }
 469
 470         ret = mrvl_dev_set_link_up(dev);
 471         if (ret)
 472                 goto out;
 473
 474         return 0;
 475 out:
 476         pp2_ppio_deinit(priv->ppio);
 477         return ret;
 478 }
 479
 480 /**
 481  * Flush receive queues.
 482  *
 483  * @param dev
 484  *   Pointer to Ethernet device structure.
 485  */
 486 static void
 487 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 488 {
 489         int i;
 490
 491         RTE_LOG(INFO, PMD, "Flushing rx queues\n");
 492         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 493                 int ret, num;
 494
 495                 do {
 496                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 497                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 498
 499                         num = MRVL_PP2_RXD_MAX;
 500                         ret = pp2_ppio_recv(q->priv->ppio,
 501                                             q->priv->rxq_map[q->queue_id].tc,
 502                                             q->priv->rxq_map[q->queue_id].inq,
 503                                             descs, (uint16_t *)&num);
 504                 } while (ret == 0 && num);
 505         }
 506 }
 507
 508 /**
 509  * Flush transmit shadow queues.
 510  *
 511  * @param dev
 512  *   Pointer to Ethernet device structure.
 513  */
 514 static void
 515 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 516 {
 517         int i;
 518
 519         RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
 520         for (i = 0; i < RTE_MAX_LCORE; i++) {
 521                 struct mrvl_shadow_txq *sq =
 522                         &shadow_txqs[dev->data->port_id][i];
 523
 524                 while (sq->tail != sq->head) {
 525                         uint64_t addr = cookie_addr_high |
 526                                         sq->ent[sq->tail].buff.cookie;
 527                         rte_pktmbuf_free((struct rte_mbuf *)addr);
 528                         sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
 529                 }
 530
 531                 memset(sq, 0, sizeof(*sq));
 532         }
 533 }
 534
 535 /**
 536  * Flush hardware bpool (buffer-pool).
 537  *
 538  * @param dev
 539  *   Pointer to Ethernet device structure.
 540  */
 541 static void
 542 mrvl_flush_bpool(struct rte_eth_dev *dev)
 543 {
 544         struct mrvl_priv *priv = dev->data->dev_private;
 545         uint32_t num;
 546         int ret;
 547
 548         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 549         if (ret) {
 550                 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
 551                 return;
 552         }
 553
 554         while (num--) {
 555                 struct pp2_buff_inf inf;
 556                 uint64_t addr;
 557
 558                 ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
 559                                          &inf);
 560                 if (ret)
 561                         break;
 562
 563                 addr = cookie_addr_high | inf.cookie;
 564                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 565         }
 566 }
 567
 568 /**
 569  * DPDK callback to stop the device.
 570  *
 571  * @param dev
 572  *   Pointer to Ethernet device structure.
 573  */
 574 static void
 575 mrvl_dev_stop(struct rte_eth_dev *dev)
 576 {
 577         struct mrvl_priv *priv = dev->data->dev_private;
 578
 579         mrvl_dev_set_link_down(dev);
 580         mrvl_flush_rx_queues(dev);
 581         mrvl_flush_tx_shadow_queues(dev);
 582         if (priv->qos_tbl)
 583                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 584         pp2_ppio_deinit(priv->ppio);
 585         priv->ppio = NULL;
 586 }
 587
 588 /**
 589  * DPDK callback to close the device.
 590  *
 591  * @param dev
 592  *   Pointer to Ethernet device structure.
 593  */
 594 static void
 595 mrvl_dev_close(struct rte_eth_dev *dev)
 596 {
 597         struct mrvl_priv *priv = dev->data->dev_private;
 598         size_t i;
 599
 600         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 601                 struct pp2_ppio_tc_params *tc_params =
 602                         &priv->ppio_params.inqs_params.tcs_params[i];
 603
 604                 if (tc_params->inqs_params) {
 605                         rte_free(tc_params->inqs_params);
 606                         tc_params->inqs_params = NULL;
 607                 }
 608         }
 609
 610         mrvl_flush_bpool(dev);
 611 }
 612
 613 /**
 614  * DPDK callback to retrieve physical link information.
 615  *
 616  * @param dev
 617  *   Pointer to Ethernet device structure.
 618  * @param wait_to_complete
 619  *   Wait for request completion (ignored).
 620  *
 621  * @return
 622  *   0 on success, negative error value otherwise.
 623  */
 624 static int
 625 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 626 {
 627         /*
 628          * TODO
 629          * once MUSDK provides necessary API use it here
 630          */
 631         struct mrvl_priv *priv = dev->data->dev_private;
 632         struct ethtool_cmd edata;
 633         struct ifreq req;
 634         int ret, fd, link_up;
 635
 636         if (!priv->ppio)
 637                 return -EPERM;
 638
 639         edata.cmd = ETHTOOL_GSET;
 640
 641         strcpy(req.ifr_name, dev->data->name);
 642         req.ifr_data = (void *)&edata;
 643
 644         fd = socket(AF_INET, SOCK_DGRAM, 0);
 645         if (fd == -1)
 646                 return -EFAULT;
 647
 648         ret = ioctl(fd, SIOCETHTOOL, &req);
 649         if (ret == -1) {
 650                 close(fd);
 651                 return -EFAULT;
 652         }
 653
 654         close(fd);
 655
 656         switch (ethtool_cmd_speed(&edata)) {
 657         case SPEED_10:
 658                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 659                 break;
 660         case SPEED_100:
 661                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 662                 break;
 663         case SPEED_1000:
 664                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 665                 break;
 666         case SPEED_10000:
 667                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 668                 break;
 669         default:
 670                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 671         }
 672
 673         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 674                                                          ETH_LINK_HALF_DUPLEX;
 675         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 676                                                            ETH_LINK_FIXED;
 677         pp2_ppio_get_link_state(priv->ppio, &link_up);
 678         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
 679
 680         return 0;
 681 }
 682
 683 /**
 684  * DPDK callback to enable promiscuous mode.
 685  *
 686  * @param dev
 687  *   Pointer to Ethernet device structure.
 688  */
 689 static void
 690 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 691 {
 692         struct mrvl_priv *priv = dev->data->dev_private;
 693         int ret;
 694
 695         if (!priv->ppio)
 696                 return;
 697
 698         ret = pp2_ppio_set_promisc(priv->ppio, 1);
 699         if (ret)
 700                 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
 701 }
 702
 703 /**
 704  * DPDK callback to enable allmulti mode.
 705  *
 706  * @param dev
 707  *   Pointer to Ethernet device structure.
 708  */
 709 static void
 710 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 711 {
 712         struct mrvl_priv *priv = dev->data->dev_private;
 713         int ret;
 714
 715         if (!priv->ppio)
 716                 return;
 717
 718         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 719         if (ret)
 720                 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
 721 }
 722
 723 /**
 724  * DPDK callback to disable promiscuous mode.
 725  *
 726  * @param dev
 727  *   Pointer to Ethernet device structure.
 728  */
 729 static void
 730 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 731 {
 732         struct mrvl_priv *priv = dev->data->dev_private;
 733         int ret;
 734
 735         if (!priv->ppio)
 736                 return;
 737
 738         ret = pp2_ppio_set_promisc(priv->ppio, 0);
 739         if (ret)
 740                 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
 741 }
 742
 743 /**
 744  * DPDK callback to disable allmulticast mode.
 745  *
 746  * @param dev
 747  *   Pointer to Ethernet device structure.
 748  */
 749 static void
 750 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 751 {
 752         struct mrvl_priv *priv = dev->data->dev_private;
 753         int ret;
 754
 755         if (!priv->ppio)
 756                 return;
 757
 758         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 759         if (ret)
 760                 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
 761 }
 762
 763 /**
 764  * DPDK callback to remove a MAC address.
 765  *
 766  * @param dev
 767  *   Pointer to Ethernet device structure.
 768  * @param index
 769  *   MAC address index.
 770  */
 771 static void
 772 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 773 {
 774         struct mrvl_priv *priv = dev->data->dev_private;
 775         char buf[ETHER_ADDR_FMT_SIZE];
 776         int ret;
 777
 778         if (!priv->ppio)
 779                 return;
 780
 781         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 782                                        dev->data->mac_addrs[index].addr_bytes);
 783         if (ret) {
 784                 ether_format_addr(buf, sizeof(buf),
 785                                   &dev->data->mac_addrs[index]);
 786                 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
 787         }
 788 }
 789
 790 /**
 791  * DPDK callback to add a MAC address.
 792  *
 793  * @param dev
 794  *   Pointer to Ethernet device structure.
 795  * @param mac_addr
 796  *   MAC address to register.
 797  * @param index
 798  *   MAC address index.
 799  * @param vmdq
 800  *   VMDq pool index to associate address with (unused).
 801  *
 802  * @return
 803  *   0 on success, negative error value otherwise.
 804  */
 805 static int
 806 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 807                   uint32_t index, uint32_t vmdq __rte_unused)
 808 {
 809         struct mrvl_priv *priv = dev->data->dev_private;
 810         char buf[ETHER_ADDR_FMT_SIZE];
 811         int ret;
 812
 813         if (index == 0)
 814                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
 815                 return -1;
 816
 817         if (!priv->ppio)
 818                 return -EPERM;
 819
 820         /*
 821          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
 822          * parameter uc_filter_max. Maximum number of mc addresses is then
 823          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
 824          * 21 respectively.
 825          *
 826          * If more than uc_filter_max uc addresses were added to filter list
 827          * then NIC will switch to promiscuous mode automatically.
 828          *
 829          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
 830          * were added to filter list then NIC will switch to all-multicast mode
 831          * automatically.
 832          */
 833         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
 834         if (ret) {
 835                 ether_format_addr(buf, sizeof(buf), mac_addr);
 836                 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
 837                 return -1;
 838         }
 839
 840         return 0;
 841 }
 842
 843 /**
 844  * DPDK callback to set the primary MAC address.
 845  *
 846  * @param dev
 847  *   Pointer to Ethernet device structure.
 848  * @param mac_addr
 849  *   MAC address to register.
 850  */
 851 static void
 852 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 853 {
 854         struct mrvl_priv *priv = dev->data->dev_private;
 855         int ret;
 856
 857         if (!priv->ppio)
 858                 return;
 859
 860         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
 861         if (ret) {
 862                 char buf[ETHER_ADDR_FMT_SIZE];
 863                 ether_format_addr(buf, sizeof(buf), mac_addr);
 864                 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
 865         }
 866 }
 867
 868 /**
 869  * DPDK callback to get device statistics.
 870  *
 871  * @param dev
 872  *   Pointer to Ethernet device structure.
 873  * @param stats
 874  *   Stats structure output buffer.
 875  *
 876  * @return
 877  *   0 on success, negative error value otherwise.
 878  */
 879 static int
 880 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 881 {
 882         struct mrvl_priv *priv = dev->data->dev_private;
 883         struct pp2_ppio_statistics ppio_stats;
 884         uint64_t drop_mac = 0;
 885         unsigned int i, idx, ret;
 886
 887         if (!priv->ppio)
 888                 return -EPERM;
 889
 890         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 891                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
 892                 struct pp2_ppio_inq_statistics rx_stats;
 893
 894                 if (!rxq)
 895                         continue;
 896
 897                 idx = rxq->queue_id;
 898                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
 899                         RTE_LOG(ERR, PMD,
 900                                 "rx queue %d stats out of range (0 - %d)\n",
 901                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
 902                         continue;
 903                 }
 904
 905                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
 906                                                   priv->rxq_map[idx].tc,
 907                                                   priv->rxq_map[idx].inq,
 908                                                   &rx_stats, 0);
 909                 if (unlikely(ret)) {
 910                         RTE_LOG(ERR, PMD,
 911                                 "Failed to update rx queue %d stats\n", idx);
 912                         break;
 913                 }
 914
 915                 stats->q_ibytes[idx] = rxq->bytes_recv;
 916                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
 917                 stats->q_errors[idx] = rx_stats.drop_early +
 918                                        rx_stats.drop_fullq +
 919                                        rx_stats.drop_bm +
 920                                        rxq->drop_mac;
 921                 stats->ibytes += rxq->bytes_recv;
 922                 drop_mac += rxq->drop_mac;
 923         }
 924
 925         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 926                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 927                 struct pp2_ppio_outq_statistics tx_stats;
 928
 929                 if (!txq)
 930                         continue;
 931
 932                 idx = txq->queue_id;
 933                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
 934                         RTE_LOG(ERR, PMD,
 935                                 "tx queue %d stats out of range (0 - %d)\n",
 936                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
 937                 }
 938
 939                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
 940                                                    &tx_stats, 0);
 941                 if (unlikely(ret)) {
 942                         RTE_LOG(ERR, PMD,
 943                                 "Failed to update tx queue %d stats\n", idx);
 944                         break;
 945                 }
 946
 947                 stats->q_opackets[idx] = tx_stats.deq_desc;
 948                 stats->q_obytes[idx] = txq->bytes_sent;
 949                 stats->obytes += txq->bytes_sent;
 950         }
 951
 952         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
 953         if (unlikely(ret)) {
 954                 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
 955                 return ret;
 956         }
 957
 958         stats->ipackets += ppio_stats.rx_packets - drop_mac;
 959         stats->opackets += ppio_stats.tx_packets;
 960         stats->imissed += ppio_stats.rx_fullq_dropped +
 961                           ppio_stats.rx_bm_dropped +
 962                           ppio_stats.rx_early_dropped +
 963                           ppio_stats.rx_fifo_dropped +
 964                           ppio_stats.rx_cls_dropped;
 965         stats->ierrors = drop_mac;
 966
 967         return 0;
 968 }
 969
 970 /**
 971  * DPDK callback to clear device statistics.
 972  *
 973  * @param dev
 974  *   Pointer to Ethernet device structure.
 975  */
 976 static void
 977 mrvl_stats_reset(struct rte_eth_dev *dev)
 978 {
 979         struct mrvl_priv *priv = dev->data->dev_private;
 980         int i;
 981
 982         if (!priv->ppio)
 983                 return;
 984
 985         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 986                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
 987
 988                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
 989                                             priv->rxq_map[i].inq, NULL, 1);
 990                 rxq->bytes_recv = 0;
 991                 rxq->drop_mac = 0;
 992         }
 993
 994         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 995                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 996
 997                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
 998                 txq->bytes_sent = 0;
 999         }
1000
1001         pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1002 }
1003
1004 /**
1005  * DPDK callback to get information about the device.
1006  *
1007  * @param dev
1008  *   Pointer to Ethernet device structure (unused).
1009  * @param info
1010  *   Info structure output buffer.
1011  */
1012 static void
1013 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1014                    struct rte_eth_dev_info *info)
1015 {
1016         info->speed_capa = ETH_LINK_SPEED_10M |
1017                            ETH_LINK_SPEED_100M |
1018                            ETH_LINK_SPEED_1G |
1019                            ETH_LINK_SPEED_10G;
1020
1021         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1022         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1023         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1024
1025         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1026         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1027         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1028
1029         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1030         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1031         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1032
1033         info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
1034                                 DEV_RX_OFFLOAD_VLAN_FILTER |
1035                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1036                                 DEV_RX_OFFLOAD_UDP_CKSUM |
1037                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1038
1039         info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1040                                 DEV_TX_OFFLOAD_UDP_CKSUM |
1041                                 DEV_TX_OFFLOAD_TCP_CKSUM;
1042
1043         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1044                                        ETH_RSS_NONFRAG_IPV4_TCP |
1045                                        ETH_RSS_NONFRAG_IPV4_UDP;
1046
1047         /* By default packets are dropped if no descriptors are available */
1048         info->default_rxconf.rx_drop_en = 1;
1049
1050         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1051 }
1052
1053 /**
1054  * Return supported packet types.
1055  *
1056  * @param dev
1057  *   Pointer to Ethernet device structure (unused).
1058  *
1059  * @return
1060  *   Const pointer to the table with supported packet types.
1061  */
1062 static const uint32_t *
1063 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1064 {
1065         static const uint32_t ptypes[] = {
1066                 RTE_PTYPE_L2_ETHER,
1067                 RTE_PTYPE_L3_IPV4,
1068                 RTE_PTYPE_L3_IPV4_EXT,
1069                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1070                 RTE_PTYPE_L3_IPV6,
1071                 RTE_PTYPE_L3_IPV6_EXT,
1072                 RTE_PTYPE_L2_ETHER_ARP,
1073                 RTE_PTYPE_L4_TCP,
1074                 RTE_PTYPE_L4_UDP
1075         };
1076
1077         return ptypes;
1078 }
1079
1080 /**
1081  * DPDK callback to get information about specific receive queue.
1082  *
1083  * @param dev
1084  *   Pointer to Ethernet device structure.
1085  * @param rx_queue_id
1086  *   Receive queue index.
1087  * @param qinfo
1088  *   Receive queue information structure.
1089  */
1090 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1091                               struct rte_eth_rxq_info *qinfo)
1092 {
1093         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1094         struct mrvl_priv *priv = dev->data->dev_private;
1095         int inq = priv->rxq_map[rx_queue_id].inq;
1096         int tc = priv->rxq_map[rx_queue_id].tc;
1097         struct pp2_ppio_tc_params *tc_params =
1098                 &priv->ppio_params.inqs_params.tcs_params[tc];
1099
1100         qinfo->mp = q->mp;
1101         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1102 }
1103
1104 /**
1105  * DPDK callback to get information about specific transmit queue.
1106  *
1107  * @param dev
1108  *   Pointer to Ethernet device structure.
1109  * @param tx_queue_id
1110  *   Transmit queue index.
1111  * @param qinfo
1112  *   Transmit queue information structure.
1113  */
1114 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1115                               struct rte_eth_txq_info *qinfo)
1116 {
1117         struct mrvl_priv *priv = dev->data->dev_private;
1118
1119         qinfo->nb_desc =
1120                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1121 }
1122
1123 /**
1124  * DPDK callback to Configure a VLAN filter.
1125  *
1126  * @param dev
1127  *   Pointer to Ethernet device structure.
1128  * @param vlan_id
1129  *   VLAN ID to filter.
1130  * @param on
1131  *   Toggle filter.
1132  *
1133  * @return
1134  *   0 on success, negative error value otherwise.
1135  */
1136 static int
1137 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1138 {
1139         struct mrvl_priv *priv = dev->data->dev_private;
1140
1141         if (!priv->ppio)
1142                 return -EPERM;
1143
1144         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1145                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1146 }
1147
1148 /**
1149  * Release buffers to hardware bpool (buffer-pool)
1150  *
1151  * @param rxq
1152  *   Receive queue pointer.
1153  * @param num
1154  *   Number of buffers to release to bpool.
1155  *
1156  * @return
1157  *   0 on success, negative error value otherwise.
1158  */
1159 static int
1160 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1161 {
1162         struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1163         struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1164         int i, ret;
1165         unsigned int core_id = rte_lcore_id();
1166         struct pp2_hif *hif = hifs[core_id];
1167         struct pp2_bpool *bpool = rxq->priv->bpool;
1168
1169         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1170         if (ret)
1171                 return ret;
1172
1173         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1174                 cookie_addr_high =
1175                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1176
1177         for (i = 0; i < num; i++) {
1178                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1179                         != cookie_addr_high) {
1180                         RTE_LOG(ERR, PMD,
1181                                 "mbuf virtual addr high 0x%lx out of range\n",
1182                                 (uint64_t)mbufs[i] >> 32);
1183                         goto out;
1184                 }
1185
1186                 entries[i].buff.addr =
1187                         rte_mbuf_data_iova_default(mbufs[i]);
1188                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1189                 entries[i].bpool = bpool;
1190         }
1191
1192         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1193         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1194
1195         if (i != num)
1196                 goto out;
1197
1198         return 0;
1199 out:
1200         for (; i < num; i++)
1201                 rte_pktmbuf_free(mbufs[i]);
1202
1203         return -1;
1204 }
1205
1206 /**
1207  * DPDK callback to configure the receive queue.
1208  *
1209  * @param dev
1210  *   Pointer to Ethernet device structure.
1211  * @param idx
1212  *   RX queue index.
1213  * @param desc
1214  *   Number of descriptors to configure in queue.
1215  * @param socket
1216  *   NUMA socket on which memory must be allocated.
1217  * @param conf
1218  *   Thresholds parameters (unused_).
1219  * @param mp
1220  *   Memory pool for buffer allocations.
1221  *
1222  * @return
1223  *   0 on success, negative error value otherwise.
1224  */
1225 static int
1226 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1227                     unsigned int socket,
1228                     const struct rte_eth_rxconf *conf __rte_unused,
1229                     struct rte_mempool *mp)
1230 {
1231         struct mrvl_priv *priv = dev->data->dev_private;
1232         struct mrvl_rxq *rxq;
1233         uint32_t min_size,
1234                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1235         int ret, tc, inq;
1236
1237         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1238                 /*
1239                  * Unknown TC mapping, mapping will not have a correct queue.
1240                  */
1241                 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1242                         idx, priv->ppio_id);
1243                 return -EFAULT;
1244         }
1245
1246         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1247                    MRVL_PKT_EFFEC_OFFS;
1248         if (min_size < max_rx_pkt_len) {
1249                 RTE_LOG(ERR, PMD,
1250                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1251                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1252                         MRVL_PKT_EFFEC_OFFS,
1253                         max_rx_pkt_len);
1254                 return -EINVAL;
1255         }
1256
1257         if (dev->data->rx_queues[idx]) {
1258                 rte_free(dev->data->rx_queues[idx]);
1259                 dev->data->rx_queues[idx] = NULL;
1260         }
1261
1262         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1263         if (!rxq)
1264                 return -ENOMEM;
1265
1266         rxq->priv = priv;
1267         rxq->mp = mp;
1268         rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1269         rxq->queue_id = idx;
1270         rxq->port_id = dev->data->port_id;
1271         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1272
1273         tc = priv->rxq_map[rxq->queue_id].tc,
1274         inq = priv->rxq_map[rxq->queue_id].inq;
1275         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1276                 desc;
1277
1278         ret = mrvl_fill_bpool(rxq, desc);
1279         if (ret) {
1280                 rte_free(rxq);
1281                 return ret;
1282         }
1283
1284         priv->bpool_init_size += desc;
1285
1286         dev->data->rx_queues[idx] = rxq;
1287
1288         return 0;
1289 }
1290
1291 /**
1292  * DPDK callback to release the receive queue.
1293  *
1294  * @param rxq
1295  *   Generic receive queue pointer.
1296  */
1297 static void
1298 mrvl_rx_queue_release(void *rxq)
1299 {
1300         struct mrvl_rxq *q = rxq;
1301         struct pp2_ppio_tc_params *tc_params;
1302         int i, num, tc, inq;
1303
1304         if (!q)
1305                 return;
1306
1307         tc = q->priv->rxq_map[q->queue_id].tc;
1308         inq = q->priv->rxq_map[q->queue_id].inq;
1309         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1310         num = tc_params->inqs_params[inq].size;
1311         for (i = 0; i < num; i++) {
1312                 struct pp2_buff_inf inf;
1313                 uint64_t addr;
1314
1315                 pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
1316                 addr = cookie_addr_high | inf.cookie;
1317                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1318         }
1319
1320         rte_free(q);
1321 }
1322
1323 /**
1324  * DPDK callback to configure the transmit queue.
1325  *
1326  * @param dev
1327  *   Pointer to Ethernet device structure.
1328  * @param idx
1329  *   Transmit queue index.
1330  * @param desc
1331  *   Number of descriptors to configure in the queue.
1332  * @param socket
1333  *   NUMA socket on which memory must be allocated.
1334  * @param conf
1335  *   Thresholds parameters (unused).
1336  *
1337  * @return
1338  *   0 on success, negative error value otherwise.
1339  */
1340 static int
1341 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1342                     unsigned int socket,
1343                     const struct rte_eth_txconf *conf __rte_unused)
1344 {
1345         struct mrvl_priv *priv = dev->data->dev_private;
1346         struct mrvl_txq *txq;
1347
1348         if (dev->data->tx_queues[idx]) {
1349                 rte_free(dev->data->tx_queues[idx]);
1350                 dev->data->tx_queues[idx] = NULL;
1351         }
1352
1353         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1354         if (!txq)
1355                 return -ENOMEM;
1356
1357         txq->priv = priv;
1358         txq->queue_id = idx;
1359         txq->port_id = dev->data->port_id;
1360         dev->data->tx_queues[idx] = txq;
1361
1362         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1363         priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1364
1365         return 0;
1366 }
1367
1368 /**
1369  * DPDK callback to release the transmit queue.
1370  *
1371  * @param txq
1372  *   Generic transmit queue pointer.
1373  */
1374 static void
1375 mrvl_tx_queue_release(void *txq)
1376 {
1377         struct mrvl_txq *q = txq;
1378
1379         if (!q)
1380                 return;
1381
1382         rte_free(q);
1383 }
1384
1385 /**
1386  * Update RSS hash configuration
1387  *
1388  * @param dev
1389  *   Pointer to Ethernet device structure.
1390  * @param rss_conf
1391  *   Pointer to RSS configuration.
1392  *
1393  * @return
1394  *   0 on success, negative error value otherwise.
1395  */
1396 static int
1397 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1398                      struct rte_eth_rss_conf *rss_conf)
1399 {
1400         struct mrvl_priv *priv = dev->data->dev_private;
1401
1402         return mrvl_configure_rss(priv, rss_conf);
1403 }
1404
1405 /**
1406  * DPDK callback to get RSS hash configuration.
1407  *
1408  * @param dev
1409  *   Pointer to Ethernet device structure.
1410  * @rss_conf
1411  *   Pointer to RSS configuration.
1412  *
1413  * @return
1414  *   Always 0.
1415  */
1416 static int
1417 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1418                        struct rte_eth_rss_conf *rss_conf)
1419 {
1420         struct mrvl_priv *priv = dev->data->dev_private;
1421         enum pp2_ppio_hash_type hash_type =
1422                 priv->ppio_params.inqs_params.hash_type;
1423
1424         rss_conf->rss_key = NULL;
1425
1426         if (hash_type == PP2_PPIO_HASH_T_NONE)
1427                 rss_conf->rss_hf = 0;
1428         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1429                 rss_conf->rss_hf = ETH_RSS_IPV4;
1430         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1431                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1432         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1433                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1434
1435         return 0;
1436 }
1437
1438 static const struct eth_dev_ops mrvl_ops = {
1439         .dev_configure = mrvl_dev_configure,
1440         .dev_start = mrvl_dev_start,
1441         .dev_stop = mrvl_dev_stop,
1442         .dev_set_link_up = mrvl_dev_set_link_up,
1443         .dev_set_link_down = mrvl_dev_set_link_down,
1444         .dev_close = mrvl_dev_close,
1445         .link_update = mrvl_link_update,
1446         .promiscuous_enable = mrvl_promiscuous_enable,
1447         .allmulticast_enable = mrvl_allmulticast_enable,
1448         .promiscuous_disable = mrvl_promiscuous_disable,
1449         .allmulticast_disable = mrvl_allmulticast_disable,
1450         .mac_addr_remove = mrvl_mac_addr_remove,
1451         .mac_addr_add = mrvl_mac_addr_add,
1452         .mac_addr_set = mrvl_mac_addr_set,
1453         .mtu_set = mrvl_mtu_set,
1454         .stats_get = mrvl_stats_get,
1455         .stats_reset = mrvl_stats_reset,
1456         .dev_infos_get = mrvl_dev_infos_get,
1457         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1458         .rxq_info_get = mrvl_rxq_info_get,
1459         .txq_info_get = mrvl_txq_info_get,
1460         .vlan_filter_set = mrvl_vlan_filter_set,
1461         .rx_queue_setup = mrvl_rx_queue_setup,
1462         .rx_queue_release = mrvl_rx_queue_release,
1463         .tx_queue_setup = mrvl_tx_queue_setup,
1464         .tx_queue_release = mrvl_tx_queue_release,
1465         .rss_hash_update = mrvl_rss_hash_update,
1466         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1467 };
1468
1469 /**
1470  * Return packet type information and l3/l4 offsets.
1471  *
1472  * @param desc
1473  *   Pointer to the received packet descriptor.
1474  * @param l3_offset
1475  *   l3 packet offset.
1476  * @param l4_offset
1477  *   l4 packet offset.
1478  *
1479  * @return
1480  *   Packet type information.
1481  */
1482 static inline uint64_t
1483 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1484                                     uint8_t *l3_offset, uint8_t *l4_offset)
1485 {
1486         enum pp2_inq_l3_type l3_type;
1487         enum pp2_inq_l4_type l4_type;
1488         uint64_t packet_type;
1489
1490         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1491         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1492
1493         packet_type = RTE_PTYPE_L2_ETHER;
1494
1495         switch (l3_type) {
1496         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1497                 packet_type |= RTE_PTYPE_L3_IPV4;
1498                 break;
1499         case PP2_INQ_L3_TYPE_IPV4_OK:
1500                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1501                 break;
1502         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1503                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1504                 break;
1505         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1506                 packet_type |= RTE_PTYPE_L3_IPV6;
1507                 break;
1508         case PP2_INQ_L3_TYPE_IPV6_EXT:
1509                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1510                 break;
1511         case PP2_INQ_L3_TYPE_ARP:
1512                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1513                 /*
1514                  * In case of ARP l4_offset is set to wrong value.
1515                  * Set it to proper one so that later on mbuf->l3_len can be
1516                  * calculated subtracting l4_offset and l3_offset.
1517                  */
1518                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1519                 break;
1520         default:
1521                 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1522                 break;
1523         }
1524
1525         switch (l4_type) {
1526         case PP2_INQ_L4_TYPE_TCP:
1527                 packet_type |= RTE_PTYPE_L4_TCP;
1528                 break;
1529         case PP2_INQ_L4_TYPE_UDP:
1530                 packet_type |= RTE_PTYPE_L4_UDP;
1531                 break;
1532         default:
1533                 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1534                 break;
1535         }
1536
1537         return packet_type;
1538 }
1539
1540 /**
1541  * Get offload information from the received packet descriptor.
1542  *
1543  * @param desc
1544  *   Pointer to the received packet descriptor.
1545  *
1546  * @return
1547  *   Mbuf offload flags.
1548  */
1549 static inline uint64_t
1550 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1551 {
1552         uint64_t flags;
1553         enum pp2_inq_desc_status status;
1554
1555         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1556         if (unlikely(status != PP2_DESC_ERR_OK))
1557                 flags = PKT_RX_IP_CKSUM_BAD;
1558         else
1559                 flags = PKT_RX_IP_CKSUM_GOOD;
1560
1561         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1562         if (unlikely(status != PP2_DESC_ERR_OK))
1563                 flags |= PKT_RX_L4_CKSUM_BAD;
1564         else
1565                 flags |= PKT_RX_L4_CKSUM_GOOD;
1566
1567         return flags;
1568 }
1569
1570 /**
1571  * DPDK callback for receive.
1572  *
1573  * @param rxq
1574  *   Generic pointer to the receive queue.
1575  * @param rx_pkts
1576  *   Array to store received packets.
1577  * @param nb_pkts
1578  *   Maximum number of packets in array.
1579  *
1580  * @return
1581  *   Number of packets successfully received.
1582  */
1583 static uint16_t
1584 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1585 {
1586         struct mrvl_rxq *q = rxq;
1587         struct pp2_ppio_desc descs[nb_pkts];
1588         struct pp2_bpool *bpool;
1589         int i, ret, rx_done = 0;
1590         int num;
1591         unsigned int core_id = rte_lcore_id();
1592
1593         if (unlikely(!q->priv->ppio))
1594                 return 0;
1595
1596         bpool = q->priv->bpool;
1597
1598         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1599                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1600         if (unlikely(ret < 0)) {
1601                 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1602                 return 0;
1603         }
1604         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1605
1606         for (i = 0; i < nb_pkts; i++) {
1607                 struct rte_mbuf *mbuf;
1608                 uint8_t l3_offset, l4_offset;
1609                 enum pp2_inq_desc_status status;
1610                 uint64_t addr;
1611
1612                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1613                         struct pp2_ppio_desc *pref_desc;
1614                         u64 pref_addr;
1615
1616                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1617                         pref_addr = cookie_addr_high |
1618                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
1619                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1620                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1621                 }
1622
1623                 addr = cookie_addr_high |
1624                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
1625                 mbuf = (struct rte_mbuf *)addr;
1626                 rte_pktmbuf_reset(mbuf);
1627
1628                 /* drop packet in case of mac, overrun or resource error */
1629                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1630                 if (unlikely(status != PP2_DESC_ERR_OK)) {
1631                         struct pp2_buff_inf binf = {
1632                                 .addr = rte_mbuf_data_iova_default(mbuf),
1633                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1634                         };
1635
1636                         pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
1637                         mrvl_port_bpool_size
1638                                 [bpool->pp2_id][bpool->id][core_id]++;
1639                         q->drop_mac++;
1640                         continue;
1641                 }
1642
1643                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1644                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1645                 mbuf->data_len = mbuf->pkt_len;
1646                 mbuf->port = q->port_id;
1647                 mbuf->packet_type =
1648                         mrvl_desc_to_packet_type_and_offset(&descs[i],
1649                                                             &l3_offset,
1650                                                             &l4_offset);
1651                 mbuf->l2_len = l3_offset;
1652                 mbuf->l3_len = l4_offset - l3_offset;
1653
1654                 if (likely(q->cksum_enabled))
1655                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1656
1657                 rx_pkts[rx_done++] = mbuf;
1658                 q->bytes_recv += mbuf->pkt_len;
1659         }
1660
1661         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1662                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1663
1664                 if (unlikely(num <= q->priv->bpool_min_size ||
1665                              (!rx_done && num < q->priv->bpool_init_size))) {
1666                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1667                         if (ret)
1668                                 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1669                 } else if (unlikely(num > q->priv->bpool_max_size)) {
1670                         int i;
1671                         int pkt_to_remove = num - q->priv->bpool_init_size;
1672                         struct rte_mbuf *mbuf;
1673                         struct pp2_buff_inf buff;
1674
1675                         RTE_LOG(DEBUG, PMD,
1676                                 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1677                                 bpool->pp2_id, q->priv->ppio->port_id,
1678                                 bpool->id, pkt_to_remove, num,
1679                                 q->priv->bpool_init_size);
1680
1681                         for (i = 0; i < pkt_to_remove; i++) {
1682                                 pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
1683                                 mbuf = (struct rte_mbuf *)
1684                                         (cookie_addr_high | buff.cookie);
1685                                 rte_pktmbuf_free(mbuf);
1686                         }
1687                         mrvl_port_bpool_size
1688                                 [bpool->pp2_id][bpool->id][core_id] -=
1689                                                                 pkt_to_remove;
1690                 }
1691                 rte_spinlock_unlock(&q->priv->lock);
1692         }
1693
1694         return rx_done;
1695 }
1696
1697 /**
1698  * Prepare offload information.
1699  *
1700  * @param ol_flags
1701  *   Offload flags.
1702  * @param packet_type
1703  *   Packet type bitfield.
1704  * @param l3_type
1705  *   Pointer to the pp2_ouq_l3_type structure.
1706  * @param l4_type
1707  *   Pointer to the pp2_outq_l4_type structure.
1708  * @param gen_l3_cksum
1709  *   Will be set to 1 in case l3 checksum is computed.
1710  * @param l4_cksum
1711  *   Will be set to 1 in case l4 checksum is computed.
1712  *
1713  * @return
1714  *   0 on success, negative error value otherwise.
1715  */
1716 static inline int
1717 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1718                         enum pp2_outq_l3_type *l3_type,
1719                         enum pp2_outq_l4_type *l4_type,
1720                         int *gen_l3_cksum,
1721                         int *gen_l4_cksum)
1722 {
1723         /*
1724          * Based on ol_flags prepare information
1725          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1726          * for offloading.
1727          */
1728         if (ol_flags & PKT_TX_IPV4) {
1729                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1730                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1731         } else if (ol_flags & PKT_TX_IPV6) {
1732                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1733                 /* no checksum for ipv6 header */
1734                 *gen_l3_cksum = 0;
1735         } else {
1736                 /* if something different then stop processing */
1737                 return -1;
1738         }
1739
1740         ol_flags &= PKT_TX_L4_MASK;
1741         if ((packet_type & RTE_PTYPE_L4_TCP) &&
1742             ol_flags == PKT_TX_TCP_CKSUM) {
1743                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1744                 *gen_l4_cksum = 1;
1745         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1746                    ol_flags == PKT_TX_UDP_CKSUM) {
1747                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1748                 *gen_l4_cksum = 1;
1749         } else {
1750                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1751                 /* no checksum for other type */
1752                 *gen_l4_cksum = 0;
1753         }
1754
1755         return 0;
1756 }
1757
1758 /**
1759  * Release already sent buffers to bpool (buffer-pool).
1760  *
1761  * @param ppio
1762  *   Pointer to the port structure.
1763  * @param hif
1764  *   Pointer to the MUSDK hardware interface.
1765  * @param sq
1766  *   Pointer to the shadow queue.
1767  * @param qid
1768  *   Queue id number.
1769  * @param force
1770  *   Force releasing packets.
1771  */
1772 static inline void
1773 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1774                        struct mrvl_shadow_txq *sq, int qid, int force)
1775 {
1776         struct buff_release_entry *entry;
1777         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1778         int i, core_id = rte_lcore_id();
1779
1780         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1781
1782         sq->num_to_release += nb_done;
1783
1784         if (likely(!force &&
1785                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1786                 return;
1787
1788         nb_done = sq->num_to_release;
1789         sq->num_to_release = 0;
1790
1791         for (i = 0; i < nb_done; i++) {
1792                 entry = &sq->ent[sq->tail + num];
1793                 if (unlikely(!entry->buff.addr)) {
1794                         RTE_LOG(ERR, PMD,
1795                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1796                                 sq->tail, (u64)entry->buff.cookie,
1797                                 (u64)entry->buff.addr);
1798                         skip_bufs = 1;
1799                         goto skip;
1800                 }
1801
1802                 if (unlikely(!entry->bpool)) {
1803                         struct rte_mbuf *mbuf;
1804
1805                         mbuf = (struct rte_mbuf *)
1806                                (cookie_addr_high | entry->buff.cookie);
1807                         rte_pktmbuf_free(mbuf);
1808                         skip_bufs = 1;
1809                         goto skip;
1810                 }
1811
1812                 mrvl_port_bpool_size
1813                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1814                 num++;
1815                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1816                         goto skip;
1817                 continue;
1818 skip:
1819                 if (likely(num))
1820                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1821                 num += skip_bufs;
1822                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1823                 sq->size -= num;
1824                 num = 0;
1825         }
1826
1827         if (likely(num)) {
1828                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1829                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1830                 sq->size -= num;
1831         }
1832 }
1833
1834 /**
1835  * DPDK callback for transmit.
1836  *
1837  * @param txq
1838  *   Generic pointer transmit queue.
1839  * @param tx_pkts
1840  *   Packets to transmit.
1841  * @param nb_pkts
1842  *   Number of packets in array.
1843  *
1844  * @return
1845  *   Number of packets successfully transmitted.
1846  */
1847 static uint16_t
1848 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1849 {
1850         struct mrvl_txq *q = txq;
1851         struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1852         struct pp2_hif *hif = hifs[rte_lcore_id()];
1853         struct pp2_ppio_desc descs[nb_pkts];
1854         int i, ret, bytes_sent = 0;
1855         uint16_t num, sq_free_size;
1856         uint64_t addr;
1857
1858         if (unlikely(!q->priv->ppio))
1859                 return 0;
1860
1861         if (sq->size)
1862                 mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
1863
1864         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1865         if (unlikely(nb_pkts > sq_free_size)) {
1866                 RTE_LOG(DEBUG, PMD,
1867                         "No room in shadow queue for %d packets! %d packets will be sent.\n",
1868                         nb_pkts, sq_free_size);
1869                 nb_pkts = sq_free_size;
1870         }
1871
1872         for (i = 0; i < nb_pkts; i++) {
1873                 struct rte_mbuf *mbuf = tx_pkts[i];
1874                 int gen_l3_cksum, gen_l4_cksum;
1875                 enum pp2_outq_l3_type l3_type;
1876                 enum pp2_outq_l4_type l4_type;
1877
1878                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1879                         struct rte_mbuf *pref_pkt_hdr;
1880
1881                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1882                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
1883                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
1884                 }
1885
1886                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1887                 sq->ent[sq->head].buff.addr =
1888                         rte_mbuf_data_iova_default(mbuf);
1889                 sq->ent[sq->head].bpool =
1890                         (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1891                          NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1892                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1893                 sq->size++;
1894
1895                 pp2_ppio_outq_desc_reset(&descs[i]);
1896                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1897                                                  rte_pktmbuf_iova(mbuf));
1898                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1899                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1900                                                rte_pktmbuf_pkt_len(mbuf));
1901
1902                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
1903                 /*
1904                  * in case unsupported ol_flags were passed
1905                  * do not update descriptor offload information
1906                  */
1907                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
1908                                               &l3_type, &l4_type, &gen_l3_cksum,
1909                                               &gen_l4_cksum);
1910                 if (unlikely(ret))
1911                         continue;
1912
1913                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
1914                                                   mbuf->l2_len,
1915                                                   mbuf->l2_len + mbuf->l3_len,
1916                                                   gen_l3_cksum, gen_l4_cksum);
1917         }
1918
1919         num = nb_pkts;
1920         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
1921         /* number of packets that were not sent */
1922         if (unlikely(num > nb_pkts)) {
1923                 for (i = nb_pkts; i < num; i++) {
1924                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
1925                                 MRVL_PP2_TX_SHADOWQ_MASK;
1926                         addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
1927                         bytes_sent -=
1928                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
1929                 }
1930                 sq->size -= num - nb_pkts;
1931         }
1932
1933         q->bytes_sent += bytes_sent;
1934
1935         return nb_pkts;
1936 }
1937
1938 /**
1939  * Initialize packet processor.
1940  *
1941  * @return
1942  *   0 on success, negative error value otherwise.
1943  */
1944 static int
1945 mrvl_init_pp2(void)
1946 {
1947         struct pp2_init_params init_params;
1948
1949         memset(&init_params, 0, sizeof(init_params));
1950         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
1951         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
1952         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
1953
1954         return pp2_init(&init_params);
1955 }
1956
1957 /**
1958  * Deinitialize packet processor.
1959  *
1960  * @return
1961  *   0 on success, negative error value otherwise.
1962  */
1963 static void
1964 mrvl_deinit_pp2(void)
1965 {
1966         pp2_deinit();
1967 }
1968
1969 /**
1970  * Create private device structure.
1971  *
1972  * @param dev_name
1973  *   Pointer to the port name passed in the initialization parameters.
1974  *
1975  * @return
1976  *   Pointer to the newly allocated private device structure.
1977  */
1978 static struct mrvl_priv *
1979 mrvl_priv_create(const char *dev_name)
1980 {
1981         struct pp2_bpool_params bpool_params;
1982         char match[MRVL_MATCH_LEN];
1983         struct mrvl_priv *priv;
1984         int ret, bpool_bit;
1985
1986         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
1987         if (!priv)
1988                 return NULL;
1989
1990         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
1991                                        &priv->pp_id, &priv->ppio_id);
1992         if (ret)
1993                 goto out_free_priv;
1994
1995         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
1996                                      PP2_BPOOL_NUM_POOLS);
1997         if (bpool_bit < 0)
1998                 goto out_free_priv;
1999         priv->bpool_bit = bpool_bit;
2000
2001         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2002                  priv->bpool_bit);
2003         memset(&bpool_params, 0, sizeof(bpool_params));
2004         bpool_params.match = match;
2005         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2006         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2007         if (ret)
2008                 goto out_clear_bpool_bit;
2009
2010         priv->ppio_params.type = PP2_PPIO_T_NIC;
2011         rte_spinlock_init(&priv->lock);
2012
2013         return priv;
2014 out_clear_bpool_bit:
2015         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2016 out_free_priv:
2017         rte_free(priv);
2018         return NULL;
2019 }
2020
2021 /**
2022  * Create device representing Ethernet port.
2023  *
2024  * @param name
2025  *   Pointer to the port's name.
2026  *
2027  * @return
2028  *   0 on success, negative error value otherwise.
2029  */
2030 static int
2031 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2032 {
2033         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2034         struct rte_eth_dev *eth_dev;
2035         struct mrvl_priv *priv;
2036         struct ifreq req;
2037
2038         eth_dev = rte_eth_dev_allocate(name);
2039         if (!eth_dev)
2040                 return -ENOMEM;
2041
2042         priv = mrvl_priv_create(name);
2043         if (!priv) {
2044                 ret = -ENOMEM;
2045                 goto out_free_dev;
2046         }
2047
2048         eth_dev->data->mac_addrs =
2049                 rte_zmalloc("mac_addrs",
2050                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2051         if (!eth_dev->data->mac_addrs) {
2052                 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2053                 ret = -ENOMEM;
2054                 goto out_free_priv;
2055         }
2056
2057         memset(&req, 0, sizeof(req));
2058         strcpy(req.ifr_name, name);
2059         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2060         if (ret)
2061                 goto out_free_mac;
2062
2063         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2064                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2065
2066         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2067         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2068         eth_dev->data->dev_private = priv;
2069         eth_dev->device = &vdev->device;
2070         eth_dev->dev_ops = &mrvl_ops;
2071
2072         return 0;
2073 out_free_mac:
2074         rte_free(eth_dev->data->mac_addrs);
2075 out_free_dev:
2076         rte_eth_dev_release_port(eth_dev);
2077 out_free_priv:
2078         rte_free(priv);
2079
2080         return ret;
2081 }
2082
2083 /**
2084  * Cleanup previously created device representing Ethernet port.
2085  *
2086  * @param name
2087  *   Pointer to the port name.
2088  */
2089 static void
2090 mrvl_eth_dev_destroy(const char *name)
2091 {
2092         struct rte_eth_dev *eth_dev;
2093         struct mrvl_priv *priv;
2094
2095         eth_dev = rte_eth_dev_allocated(name);
2096         if (!eth_dev)
2097                 return;
2098
2099         priv = eth_dev->data->dev_private;
2100         pp2_bpool_deinit(priv->bpool);
2101         rte_free(priv);
2102         rte_free(eth_dev->data->mac_addrs);
2103         rte_eth_dev_release_port(eth_dev);
2104 }
2105
2106 /**
2107  * Callback used by rte_kvargs_process() during argument parsing.
2108  *
2109  * @param key
2110  *   Pointer to the parsed key (unused).
2111  * @param value
2112  *   Pointer to the parsed value.
2113  * @param extra_args
2114  *   Pointer to the extra arguments which contains address of the
2115  *   table of pointers to parsed interface names.
2116  *
2117  * @return
2118  *   Always 0.
2119  */
2120 static int
2121 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2122                  void *extra_args)
2123 {
2124         const char **ifnames = extra_args;
2125
2126         ifnames[mrvl_ports_nb++] = value;
2127
2128         return 0;
2129 }
2130
2131 /**
2132  * Initialize per-lcore MUSDK hardware interfaces (hifs).
2133  *
2134  * @return
2135  *   0 on success, negative error value otherwise.
2136  */
2137 static int
2138 mrvl_init_hifs(void)
2139 {
2140         struct pp2_hif_params params;
2141         char match[MRVL_MATCH_LEN];
2142         int i, ret;
2143
2144         RTE_LCORE_FOREACH(i) {
2145                 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
2146                 if (ret < 0)
2147                         return ret;
2148
2149                 snprintf(match, sizeof(match), "hif-%d", ret);
2150                 memset(&params, 0, sizeof(params));
2151                 params.match = match;
2152                 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
2153                 ret = pp2_hif_init(&params, &hifs[i]);
2154                 if (ret) {
2155                         RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
2156                         return ret;
2157                 }
2158         }
2159
2160         return 0;
2161 }
2162
2163 /**
2164  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2165  */
2166 static void
2167 mrvl_deinit_hifs(void)
2168 {
2169         int i;
2170
2171         RTE_LCORE_FOREACH(i) {
2172                 if (hifs[i])
2173                         pp2_hif_deinit(hifs[i]);
2174         }
2175 }
2176
2177 static void mrvl_set_first_last_cores(int core_id)
2178 {
2179         if (core_id < mrvl_lcore_first)
2180                 mrvl_lcore_first = core_id;
2181
2182         if (core_id > mrvl_lcore_last)
2183                 mrvl_lcore_last = core_id;
2184 }
2185
2186 /**
2187  * DPDK callback to register the virtual device.
2188  *
2189  * @param vdev
2190  *   Pointer to the virtual device.
2191  *
2192  * @return
2193  *   0 on success, negative error value otherwise.
2194  */
2195 static int
2196 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2197 {
2198         struct rte_kvargs *kvlist;
2199         const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
2200         int ret = -EINVAL;
2201         uint32_t i, ifnum, cfgnum, core_id;
2202         const char *params;
2203
2204         params = rte_vdev_device_args(vdev);
2205         if (!params)
2206                 return -EINVAL;
2207
2208         kvlist = rte_kvargs_parse(params, valid_args);
2209         if (!kvlist)
2210                 return -EINVAL;
2211
2212         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2213         if (ifnum > RTE_DIM(ifnames))
2214                 goto out_free_kvlist;
2215
2216         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2217                            mrvl_get_ifnames, &ifnames);
2218
2219         cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2220         if (cfgnum > 1) {
2221                 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2222                 goto out_free_kvlist;
2223         } else if (cfgnum == 1) {
2224                 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2225                                    mrvl_get_qoscfg, &mrvl_qos_cfg);
2226         }
2227
2228         /*
2229          * ret == -EEXIST is correct, it means DMA
2230          * has been already initialized (by another PMD).
2231          */
2232         ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2233         if (ret < 0) {
2234                 if (ret != -EEXIST)
2235                         goto out_free_kvlist;
2236                 else
2237                         RTE_LOG(INFO, PMD,
2238                                 "DMA memory has been already initialized by a different driver.\n");
2239         }
2240
2241         ret = mrvl_init_pp2();
2242         if (ret) {
2243                 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2244                 goto out_deinit_dma;
2245         }
2246
2247         ret = mrvl_init_hifs();
2248         if (ret)
2249                 goto out_deinit_hifs;
2250
2251         for (i = 0; i < ifnum; i++) {
2252                 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]);
2253                 ret = mrvl_eth_dev_create(vdev, ifnames[i]);
2254                 if (ret)
2255                         goto out_cleanup;
2256         }
2257
2258         rte_kvargs_free(kvlist);
2259
2260         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2261
2262         mrvl_lcore_first = RTE_MAX_LCORE;
2263         mrvl_lcore_last = 0;
2264
2265         RTE_LCORE_FOREACH(core_id) {
2266                 mrvl_set_first_last_cores(core_id);
2267         }
2268
2269         return 0;
2270 out_cleanup:
2271         for (; i > 0; i--)
2272                 mrvl_eth_dev_destroy(ifnames[i]);
2273 out_deinit_hifs:
2274         mrvl_deinit_hifs();
2275         mrvl_deinit_pp2();
2276 out_deinit_dma:
2277         mv_sys_dma_mem_destroy();
2278 out_free_kvlist:
2279         rte_kvargs_free(kvlist);
2280
2281         return ret;
2282 }
2283
2284 /**
2285  * DPDK callback to remove virtual device.
2286  *
2287  * @param vdev
2288  *   Pointer to the removed virtual device.
2289  *
2290  * @return
2291  *   0 on success, negative error value otherwise.
2292  */
2293 static int
2294 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2295 {
2296         int i;
2297         const char *name;
2298
2299         name = rte_vdev_device_name(vdev);
2300         if (!name)
2301                 return -EINVAL;
2302
2303         RTE_LOG(INFO, PMD, "Removing %s\n", name);
2304
2305         for (i = 0; i < rte_eth_dev_count(); i++) {
2306                 char ifname[RTE_ETH_NAME_MAX_LEN];
2307
2308                 rte_eth_dev_get_name_by_port(i, ifname);
2309                 mrvl_eth_dev_destroy(ifname);
2310         }
2311
2312         mrvl_deinit_hifs();
2313         mrvl_deinit_pp2();
2314         mv_sys_dma_mem_destroy();
2315
2316         return 0;
2317 }
2318
2319 static struct rte_vdev_driver pmd_mrvl_drv = {
2320         .probe = rte_pmd_mrvl_probe,
2321         .remove = rte_pmd_mrvl_remove,
2322 };
2323
2324 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2325 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);