drivers/net/mvpp2/mrvl_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Marvell International Ltd.
   3  * Copyright(c) 2017 Semihalf.
   4  * All rights reserved.
   5  */
   6
   7 #include <rte_ethdev_driver.h>
   8 #include <rte_kvargs.h>
   9 #include <rte_log.h>
  10 #include <rte_malloc.h>
  11 #include <rte_bus_vdev.h>
  12
  13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  14  * we'll declare only one version.
  15  *
  16  * Note that it is not used in this PMD anyway.
  17  */
  18 #ifdef container_of
  19 #undef container_of
  20 #endif
  21
  22 #include <fcntl.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/sockios.h>
  25 #include <net/if.h>
  26 #include <net/if_arp.h>
  27 #include <sys/ioctl.h>
  28 #include <sys/socket.h>
  29 #include <sys/stat.h>
  30 #include <sys/types.h>
  31
  32 #include "mrvl_ethdev.h"
  33 #include "mrvl_qos.h"
  34
  35 /* bitmask with reserved hifs */
  36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  37 /* bitmask with reserved bpools */
  38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  39 /* bitmask with reserved kernel RSS tables */
  40 #define MRVL_MUSDK_RSS_RESERVED 0x01
  41 /* maximum number of available hifs */
  42 #define MRVL_MUSDK_HIFS_MAX 9
  43
  44 /* prefetch shift */
  45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  46
  47 /* TCAM has 25 entries reserved for uc/mc filter entries */
  48 #define MRVL_MAC_ADDRS_MAX 25
  49 #define MRVL_MATCH_LEN 16
  50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  51 /* Maximum allowable packet size */
  52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  53
  54 #define MRVL_IFACE_NAME_ARG "iface"
  55 #define MRVL_CFG_ARG "cfg"
  56
  57 #define MRVL_BURST_SIZE 64
  58
  59 #define MRVL_ARP_LENGTH 28
  60
  61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  62
  63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  64 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  65
  66 /* Memory size (in bytes) for MUSDK dma buffers */
  67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
  68
  69 /** Port Rx offload capabilities */
  70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
  71                           DEV_RX_OFFLOAD_JUMBO_FRAME | \
  72                           DEV_RX_OFFLOAD_CRC_STRIP | \
  73                           DEV_RX_OFFLOAD_CHECKSUM)
  74
  75 /** Port Tx offloads capabilities */
  76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
  77                           DEV_TX_OFFLOAD_UDP_CKSUM | \
  78                           DEV_TX_OFFLOAD_TCP_CKSUM)
  79
  80 static const char * const valid_args[] = {
  81         MRVL_IFACE_NAME_ARG,
  82         MRVL_CFG_ARG,
  83         NULL
  84 };
  85
  86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
  87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
  88 static int used_bpools[PP2_NUM_PKT_PROC] = {
  89         MRVL_MUSDK_BPOOLS_RESERVED,
  90         MRVL_MUSDK_BPOOLS_RESERVED
  91 };
  92
  93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
  94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
  95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
  96
  97 int mrvl_logtype;
  98
  99 struct mrvl_ifnames {
 100         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
 101         int idx;
 102 };
 103
 104 /*
 105  * To use buffer harvesting based on loopback port shadow queue structure
 106  * was introduced for buffers information bookkeeping.
 107  *
 108  * Before sending the packet, related buffer information (pp2_buff_inf) is
 109  * stored in shadow queue. After packet is transmitted no longer used
 110  * packet buffer is released back to it's original hardware pool,
 111  * on condition it originated from interface.
 112  * In case it  was generated by application itself i.e: mbuf->port field is
 113  * 0xff then its released to software mempool.
 114  */
 115 struct mrvl_shadow_txq {
 116         int head;           /* write index - used when sending buffers */
 117         int tail;           /* read index - used when releasing buffers */
 118         u16 size;           /* queue occupied size */
 119         u16 num_to_release; /* number of buffers sent, that can be released */
 120         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 121 };
 122
 123 struct mrvl_rxq {
 124         struct mrvl_priv *priv;
 125         struct rte_mempool *mp;
 126         int queue_id;
 127         int port_id;
 128         int cksum_enabled;
 129         uint64_t bytes_recv;
 130         uint64_t drop_mac;
 131 };
 132
 133 struct mrvl_txq {
 134         struct mrvl_priv *priv;
 135         int queue_id;
 136         int port_id;
 137         uint64_t bytes_sent;
 138         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 139         int tx_deferred_start;
 140 };
 141
 142 static int mrvl_lcore_first;
 143 static int mrvl_lcore_last;
 144 static int mrvl_dev_num;
 145
 146 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 147 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 148                         struct pp2_hif *hif, unsigned int core_id,
 149                         struct mrvl_shadow_txq *sq, int qid, int force);
 150
 151 #define MRVL_XSTATS_TBL_ENTRY(name) { \
 152         #name, offsetof(struct pp2_ppio_statistics, name),      \
 153         sizeof(((struct pp2_ppio_statistics *)0)->name)         \
 154 }
 155
 156 /* Table with xstats data */
 157 static struct {
 158         const char *name;
 159         unsigned int offset;
 160         unsigned int size;
 161 } mrvl_xstats_tbl[] = {
 162         MRVL_XSTATS_TBL_ENTRY(rx_bytes),
 163         MRVL_XSTATS_TBL_ENTRY(rx_packets),
 164         MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
 165         MRVL_XSTATS_TBL_ENTRY(rx_errors),
 166         MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
 167         MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
 168         MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
 169         MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
 170         MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
 171         MRVL_XSTATS_TBL_ENTRY(tx_bytes),
 172         MRVL_XSTATS_TBL_ENTRY(tx_packets),
 173         MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
 174         MRVL_XSTATS_TBL_ENTRY(tx_errors)
 175 };
 176
 177 static inline int
 178 mrvl_get_bpool_size(int pp2_id, int pool_id)
 179 {
 180         int i;
 181         int size = 0;
 182
 183         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 184                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 185
 186         return size;
 187 }
 188
 189 static inline int
 190 mrvl_reserve_bit(int *bitmap, int max)
 191 {
 192         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 193
 194         if (n >= max)
 195                 return -1;
 196
 197         *bitmap |= 1 << n;
 198
 199         return n;
 200 }
 201
 202 static int
 203 mrvl_init_hif(int core_id)
 204 {
 205         struct pp2_hif_params params;
 206         char match[MRVL_MATCH_LEN];
 207         int ret;
 208
 209         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 210         if (ret < 0) {
 211                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 212                 return ret;
 213         }
 214
 215         snprintf(match, sizeof(match), "hif-%d", ret);
 216         memset(&params, 0, sizeof(params));
 217         params.match = match;
 218         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 219         ret = pp2_hif_init(&params, &hifs[core_id]);
 220         if (ret) {
 221                 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
 222                 return ret;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static inline struct pp2_hif*
 229 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 230 {
 231         int ret;
 232
 233         if (likely(hifs[core_id] != NULL))
 234                 return hifs[core_id];
 235
 236         rte_spinlock_lock(&priv->lock);
 237
 238         ret = mrvl_init_hif(core_id);
 239         if (ret < 0) {
 240                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 241                 goto out;
 242         }
 243
 244         if (core_id < mrvl_lcore_first)
 245                 mrvl_lcore_first = core_id;
 246
 247         if (core_id > mrvl_lcore_last)
 248                 mrvl_lcore_last = core_id;
 249 out:
 250         rte_spinlock_unlock(&priv->lock);
 251
 252         return hifs[core_id];
 253 }
 254
 255 /**
 256  * Configure rss based on dpdk rss configuration.
 257  *
 258  * @param priv
 259  *   Pointer to private structure.
 260  * @param rss_conf
 261  *   Pointer to RSS configuration.
 262  *
 263  * @return
 264  *   0 on success, negative error value otherwise.
 265  */
 266 static int
 267 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 268 {
 269         if (rss_conf->rss_key)
 270                 MRVL_LOG(WARNING, "Changing hash key is not supported");
 271
 272         if (rss_conf->rss_hf == 0) {
 273                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 274         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 275                 priv->ppio_params.inqs_params.hash_type =
 276                         PP2_PPIO_HASH_T_2_TUPLE;
 277         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 278                 priv->ppio_params.inqs_params.hash_type =
 279                         PP2_PPIO_HASH_T_5_TUPLE;
 280                 priv->rss_hf_tcp = 1;
 281         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 282                 priv->ppio_params.inqs_params.hash_type =
 283                         PP2_PPIO_HASH_T_5_TUPLE;
 284                 priv->rss_hf_tcp = 0;
 285         } else {
 286                 return -EINVAL;
 287         }
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * Ethernet device configuration.
 294  *
 295  * Prepare the driver for a given number of TX and RX queues and
 296  * configure RSS.
 297  *
 298  * @param dev
 299  *   Pointer to Ethernet device structure.
 300  *
 301  * @return
 302  *   0 on success, negative error value otherwise.
 303  */
 304 static int
 305 mrvl_dev_configure(struct rte_eth_dev *dev)
 306 {
 307         struct mrvl_priv *priv = dev->data->dev_private;
 308         int ret;
 309
 310         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 311             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 312                 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
 313                         dev->data->dev_conf.rxmode.mq_mode);
 314                 return -EINVAL;
 315         }
 316
 317         if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
 318                 MRVL_LOG(INFO,
 319                         "L2 CRC stripping is always enabled in hw");
 320                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
 321         }
 322
 323         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 324                 MRVL_LOG(INFO, "Split headers not supported");
 325                 return -EINVAL;
 326         }
 327
 328         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 329                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 330                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 331
 332         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 333                                   dev->data->nb_rx_queues);
 334         if (ret < 0)
 335                 return ret;
 336
 337         ret = mrvl_configure_txqs(priv, dev->data->port_id,
 338                                   dev->data->nb_tx_queues);
 339         if (ret < 0)
 340                 return ret;
 341
 342         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 343         priv->ppio_params.maintain_stats = 1;
 344         priv->nb_rx_queues = dev->data->nb_rx_queues;
 345
 346         if (dev->data->nb_rx_queues == 1 &&
 347             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 348                 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
 349                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 350
 351                 return 0;
 352         }
 353
 354         return mrvl_configure_rss(priv,
 355                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 356 }
 357
 358 /**
 359  * DPDK callback to change the MTU.
 360  *
 361  * Setting the MTU affects hardware MRU (packets larger than the MRU
 362  * will be dropped).
 363  *
 364  * @param dev
 365  *   Pointer to Ethernet device structure.
 366  * @param mtu
 367  *   New MTU.
 368  *
 369  * @return
 370  *   0 on success, negative error value otherwise.
 371  */
 372 static int
 373 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 374 {
 375         struct mrvl_priv *priv = dev->data->dev_private;
 376         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 377         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 378         int ret;
 379
 380         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 381                 return -EINVAL;
 382
 383         if (!priv->ppio)
 384                 return 0;
 385
 386         ret = pp2_ppio_set_mru(priv->ppio, mru);
 387         if (ret)
 388                 return ret;
 389
 390         return pp2_ppio_set_mtu(priv->ppio, mtu);
 391 }
 392
 393 /**
 394  * DPDK callback to bring the link up.
 395  *
 396  * @param dev
 397  *   Pointer to Ethernet device structure.
 398  *
 399  * @return
 400  *   0 on success, negative error value otherwise.
 401  */
 402 static int
 403 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 404 {
 405         struct mrvl_priv *priv = dev->data->dev_private;
 406         int ret;
 407
 408         if (!priv->ppio)
 409                 return -EPERM;
 410
 411         ret = pp2_ppio_enable(priv->ppio);
 412         if (ret)
 413                 return ret;
 414
 415         /*
 416          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 417          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 418          * PP2_TRAFFIC_INGRESS_EGRESS.
 419          *
 420          * Set mtu to default DPDK value here.
 421          */
 422         ret = mrvl_mtu_set(dev, dev->data->mtu);
 423         if (ret)
 424                 pp2_ppio_disable(priv->ppio);
 425
 426         return ret;
 427 }
 428
 429 /**
 430  * DPDK callback to bring the link down.
 431  *
 432  * @param dev
 433  *   Pointer to Ethernet device structure.
 434  *
 435  * @return
 436  *   0 on success, negative error value otherwise.
 437  */
 438 static int
 439 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 440 {
 441         struct mrvl_priv *priv = dev->data->dev_private;
 442
 443         if (!priv->ppio)
 444                 return -EPERM;
 445
 446         return pp2_ppio_disable(priv->ppio);
 447 }
 448
 449 /**
 450  * DPDK callback to start tx queue.
 451  *
 452  * @param dev
 453  *   Pointer to Ethernet device structure.
 454  * @param queue_id
 455  *   Transmit queue index.
 456  *
 457  * @return
 458  *   0 on success, negative error value otherwise.
 459  */
 460 static int
 461 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
 462 {
 463         struct mrvl_priv *priv = dev->data->dev_private;
 464         int ret;
 465
 466         if (!priv)
 467                 return -EPERM;
 468
 469         /* passing 1 enables given tx queue */
 470         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
 471         if (ret) {
 472                 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
 473                 return ret;
 474         }
 475
 476         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 477
 478         return 0;
 479 }
 480
 481 /**
 482  * DPDK callback to stop tx queue.
 483  *
 484  * @param dev
 485  *   Pointer to Ethernet device structure.
 486  * @param queue_id
 487  *   Transmit queue index.
 488  *
 489  * @return
 490  *   0 on success, negative error value otherwise.
 491  */
 492 static int
 493 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
 494 {
 495         struct mrvl_priv *priv = dev->data->dev_private;
 496         int ret;
 497
 498         if (!priv->ppio)
 499                 return -EPERM;
 500
 501         /* passing 0 disables given tx queue */
 502         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
 503         if (ret) {
 504                 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
 505                 return ret;
 506         }
 507
 508         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 509
 510         return 0;
 511 }
 512
 513 /**
 514  * DPDK callback to start the device.
 515  *
 516  * @param dev
 517  *   Pointer to Ethernet device structure.
 518  *
 519  * @return
 520  *   0 on success, negative errno value on failure.
 521  */
 522 static int
 523 mrvl_dev_start(struct rte_eth_dev *dev)
 524 {
 525         struct mrvl_priv *priv = dev->data->dev_private;
 526         char match[MRVL_MATCH_LEN];
 527         int ret = 0, i, def_init_size;
 528
 529         snprintf(match, sizeof(match), "ppio-%d:%d",
 530                  priv->pp_id, priv->ppio_id);
 531         priv->ppio_params.match = match;
 532
 533         /*
 534          * Calculate the minimum bpool size for refill feature as follows:
 535          * 2 default burst sizes multiply by number of rx queues.
 536          * If the bpool size will be below this value, new buffers will
 537          * be added to the pool.
 538          */
 539         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 540
 541         /* In case initial bpool size configured in queues setup is
 542          * smaller than minimum size add more buffers
 543          */
 544         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 545         if (priv->bpool_init_size < def_init_size) {
 546                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 547
 548                 priv->bpool_init_size += buffs_to_add;
 549                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 550                 if (ret)
 551                         MRVL_LOG(ERR, "Failed to add buffers to bpool");
 552         }
 553
 554         /*
 555          * Calculate the maximum bpool size for refill feature as follows:
 556          * maximum number of descriptors in rx queue multiply by number
 557          * of rx queues plus minimum bpool size.
 558          * In case the bpool size will exceed this value, superfluous buffers
 559          * will be removed
 560          */
 561         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 562                                 priv->bpool_min_size;
 563
 564         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 565         if (ret) {
 566                 MRVL_LOG(ERR, "Failed to init ppio");
 567                 return ret;
 568         }
 569
 570         /*
 571          * In case there are some some stale uc/mc mac addresses flush them
 572          * here. It cannot be done during mrvl_dev_close() as port information
 573          * is already gone at that point (due to pp2_ppio_deinit() in
 574          * mrvl_dev_stop()).
 575          */
 576         if (!priv->uc_mc_flushed) {
 577                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 578                 if (ret) {
 579                         MRVL_LOG(ERR,
 580                                 "Failed to flush uc/mc filter list");
 581                         goto out;
 582                 }
 583                 priv->uc_mc_flushed = 1;
 584         }
 585
 586         if (!priv->vlan_flushed) {
 587                 ret = pp2_ppio_flush_vlan(priv->ppio);
 588                 if (ret) {
 589                         MRVL_LOG(ERR, "Failed to flush vlan list");
 590                         /*
 591                          * TODO
 592                          * once pp2_ppio_flush_vlan() is supported jump to out
 593                          * goto out;
 594                          */
 595                 }
 596                 priv->vlan_flushed = 1;
 597         }
 598
 599         /* For default QoS config, don't start classifier. */
 600         if (mrvl_qos_cfg) {
 601                 ret = mrvl_start_qos_mapping(priv);
 602                 if (ret) {
 603                         MRVL_LOG(ERR, "Failed to setup QoS mapping");
 604                         goto out;
 605                 }
 606         }
 607
 608         ret = mrvl_dev_set_link_up(dev);
 609         if (ret) {
 610                 MRVL_LOG(ERR, "Failed to set link up");
 611                 goto out;
 612         }
 613
 614         /* start tx queues */
 615         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 616                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 617
 618                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
 619
 620                 if (!txq->tx_deferred_start)
 621                         continue;
 622
 623                 /*
 624                  * All txqs are started by default. Stop them
 625                  * so that tx_deferred_start works as expected.
 626                  */
 627                 ret = mrvl_tx_queue_stop(dev, i);
 628                 if (ret)
 629                         goto out;
 630         }
 631
 632         return 0;
 633 out:
 634         MRVL_LOG(ERR, "Failed to start device");
 635         pp2_ppio_deinit(priv->ppio);
 636         return ret;
 637 }
 638
 639 /**
 640  * Flush receive queues.
 641  *
 642  * @param dev
 643  *   Pointer to Ethernet device structure.
 644  */
 645 static void
 646 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 647 {
 648         int i;
 649
 650         MRVL_LOG(INFO, "Flushing rx queues");
 651         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 652                 int ret, num;
 653
 654                 do {
 655                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 656                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 657
 658                         num = MRVL_PP2_RXD_MAX;
 659                         ret = pp2_ppio_recv(q->priv->ppio,
 660                                             q->priv->rxq_map[q->queue_id].tc,
 661                                             q->priv->rxq_map[q->queue_id].inq,
 662                                             descs, (uint16_t *)&num);
 663                 } while (ret == 0 && num);
 664         }
 665 }
 666
 667 /**
 668  * Flush transmit shadow queues.
 669  *
 670  * @param dev
 671  *   Pointer to Ethernet device structure.
 672  */
 673 static void
 674 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 675 {
 676         int i, j;
 677         struct mrvl_txq *txq;
 678
 679         MRVL_LOG(INFO, "Flushing tx shadow queues");
 680         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 681                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
 682
 683                 for (j = 0; j < RTE_MAX_LCORE; j++) {
 684                         struct mrvl_shadow_txq *sq;
 685
 686                         if (!hifs[j])
 687                                 continue;
 688
 689                         sq = &txq->shadow_txqs[j];
 690                         mrvl_free_sent_buffers(txq->priv->ppio,
 691                                 hifs[j], j, sq, txq->queue_id, 1);
 692                         while (sq->tail != sq->head) {
 693                                 uint64_t addr = cookie_addr_high |
 694                                         sq->ent[sq->tail].buff.cookie;
 695                                 rte_pktmbuf_free(
 696                                         (struct rte_mbuf *)addr);
 697                                 sq->tail = (sq->tail + 1) &
 698                                             MRVL_PP2_TX_SHADOWQ_MASK;
 699                         }
 700                         memset(sq, 0, sizeof(*sq));
 701                 }
 702         }
 703 }
 704
 705 /**
 706  * Flush hardware bpool (buffer-pool).
 707  *
 708  * @param dev
 709  *   Pointer to Ethernet device structure.
 710  */
 711 static void
 712 mrvl_flush_bpool(struct rte_eth_dev *dev)
 713 {
 714         struct mrvl_priv *priv = dev->data->dev_private;
 715         struct pp2_hif *hif;
 716         uint32_t num;
 717         int ret;
 718         unsigned int core_id = rte_lcore_id();
 719
 720         if (core_id == LCORE_ID_ANY)
 721                 core_id = 0;
 722
 723         hif = mrvl_get_hif(priv, core_id);
 724
 725         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 726         if (ret) {
 727                 MRVL_LOG(ERR, "Failed to get bpool buffers number");
 728                 return;
 729         }
 730
 731         while (num--) {
 732                 struct pp2_buff_inf inf;
 733                 uint64_t addr;
 734
 735                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
 736                 if (ret)
 737                         break;
 738
 739                 addr = cookie_addr_high | inf.cookie;
 740                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 741         }
 742 }
 743
 744 /**
 745  * DPDK callback to stop the device.
 746  *
 747  * @param dev
 748  *   Pointer to Ethernet device structure.
 749  */
 750 static void
 751 mrvl_dev_stop(struct rte_eth_dev *dev)
 752 {
 753         struct mrvl_priv *priv = dev->data->dev_private;
 754
 755         mrvl_dev_set_link_down(dev);
 756         mrvl_flush_rx_queues(dev);
 757         mrvl_flush_tx_shadow_queues(dev);
 758         if (priv->cls_tbl) {
 759                 pp2_cls_tbl_deinit(priv->cls_tbl);
 760                 priv->cls_tbl = NULL;
 761         }
 762         if (priv->qos_tbl) {
 763                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 764                 priv->qos_tbl = NULL;
 765         }
 766         if (priv->ppio)
 767                 pp2_ppio_deinit(priv->ppio);
 768         priv->ppio = NULL;
 769
 770         /* policer must be released after ppio deinitialization */
 771         if (priv->policer) {
 772                 pp2_cls_plcr_deinit(priv->policer);
 773                 priv->policer = NULL;
 774         }
 775 }
 776
 777 /**
 778  * DPDK callback to close the device.
 779  *
 780  * @param dev
 781  *   Pointer to Ethernet device structure.
 782  */
 783 static void
 784 mrvl_dev_close(struct rte_eth_dev *dev)
 785 {
 786         struct mrvl_priv *priv = dev->data->dev_private;
 787         size_t i;
 788
 789         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 790                 struct pp2_ppio_tc_params *tc_params =
 791                         &priv->ppio_params.inqs_params.tcs_params[i];
 792
 793                 if (tc_params->inqs_params) {
 794                         rte_free(tc_params->inqs_params);
 795                         tc_params->inqs_params = NULL;
 796                 }
 797         }
 798
 799         mrvl_flush_bpool(dev);
 800 }
 801
 802 /**
 803  * DPDK callback to retrieve physical link information.
 804  *
 805  * @param dev
 806  *   Pointer to Ethernet device structure.
 807  * @param wait_to_complete
 808  *   Wait for request completion (ignored).
 809  *
 810  * @return
 811  *   0 on success, negative error value otherwise.
 812  */
 813 static int
 814 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 815 {
 816         /*
 817          * TODO
 818          * once MUSDK provides necessary API use it here
 819          */
 820         struct mrvl_priv *priv = dev->data->dev_private;
 821         struct ethtool_cmd edata;
 822         struct ifreq req;
 823         int ret, fd, link_up;
 824
 825         if (!priv->ppio)
 826                 return -EPERM;
 827
 828         edata.cmd = ETHTOOL_GSET;
 829
 830         strcpy(req.ifr_name, dev->data->name);
 831         req.ifr_data = (void *)&edata;
 832
 833         fd = socket(AF_INET, SOCK_DGRAM, 0);
 834         if (fd == -1)
 835                 return -EFAULT;
 836
 837         ret = ioctl(fd, SIOCETHTOOL, &req);
 838         if (ret == -1) {
 839                 close(fd);
 840                 return -EFAULT;
 841         }
 842
 843         close(fd);
 844
 845         switch (ethtool_cmd_speed(&edata)) {
 846         case SPEED_10:
 847                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 848                 break;
 849         case SPEED_100:
 850                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 851                 break;
 852         case SPEED_1000:
 853                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 854                 break;
 855         case SPEED_10000:
 856                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 857                 break;
 858         default:
 859                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 860         }
 861
 862         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 863                                                          ETH_LINK_HALF_DUPLEX;
 864         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 865                                                            ETH_LINK_FIXED;
 866         pp2_ppio_get_link_state(priv->ppio, &link_up);
 867         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
 868
 869         return 0;
 870 }
 871
 872 /**
 873  * DPDK callback to enable promiscuous mode.
 874  *
 875  * @param dev
 876  *   Pointer to Ethernet device structure.
 877  */
 878 static void
 879 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 880 {
 881         struct mrvl_priv *priv = dev->data->dev_private;
 882         int ret;
 883
 884         if (!priv->ppio)
 885                 return;
 886
 887         if (priv->isolated)
 888                 return;
 889
 890         ret = pp2_ppio_set_promisc(priv->ppio, 1);
 891         if (ret)
 892                 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
 893 }
 894
 895 /**
 896  * DPDK callback to enable allmulti mode.
 897  *
 898  * @param dev
 899  *   Pointer to Ethernet device structure.
 900  */
 901 static void
 902 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 903 {
 904         struct mrvl_priv *priv = dev->data->dev_private;
 905         int ret;
 906
 907         if (!priv->ppio)
 908                 return;
 909
 910         if (priv->isolated)
 911                 return;
 912
 913         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 914         if (ret)
 915                 MRVL_LOG(ERR, "Failed enable all-multicast mode");
 916 }
 917
 918 /**
 919  * DPDK callback to disable promiscuous mode.
 920  *
 921  * @param dev
 922  *   Pointer to Ethernet device structure.
 923  */
 924 static void
 925 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 926 {
 927         struct mrvl_priv *priv = dev->data->dev_private;
 928         int ret;
 929
 930         if (!priv->ppio)
 931                 return;
 932
 933         ret = pp2_ppio_set_promisc(priv->ppio, 0);
 934         if (ret)
 935                 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
 936 }
 937
 938 /**
 939  * DPDK callback to disable allmulticast mode.
 940  *
 941  * @param dev
 942  *   Pointer to Ethernet device structure.
 943  */
 944 static void
 945 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 946 {
 947         struct mrvl_priv *priv = dev->data->dev_private;
 948         int ret;
 949
 950         if (!priv->ppio)
 951                 return;
 952
 953         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 954         if (ret)
 955                 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
 956 }
 957
 958 /**
 959  * DPDK callback to remove a MAC address.
 960  *
 961  * @param dev
 962  *   Pointer to Ethernet device structure.
 963  * @param index
 964  *   MAC address index.
 965  */
 966 static void
 967 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 968 {
 969         struct mrvl_priv *priv = dev->data->dev_private;
 970         char buf[ETHER_ADDR_FMT_SIZE];
 971         int ret;
 972
 973         if (!priv->ppio)
 974                 return;
 975
 976         if (priv->isolated)
 977                 return;
 978
 979         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 980                                        dev->data->mac_addrs[index].addr_bytes);
 981         if (ret) {
 982                 ether_format_addr(buf, sizeof(buf),
 983                                   &dev->data->mac_addrs[index]);
 984                 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
 985         }
 986 }
 987
 988 /**
 989  * DPDK callback to add a MAC address.
 990  *
 991  * @param dev
 992  *   Pointer to Ethernet device structure.
 993  * @param mac_addr
 994  *   MAC address to register.
 995  * @param index
 996  *   MAC address index.
 997  * @param vmdq
 998  *   VMDq pool index to associate address with (unused).
 999  *
1000  * @return
1001  *   0 on success, negative error value otherwise.
1002  */
1003 static int
1004 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1005                   uint32_t index, uint32_t vmdq __rte_unused)
1006 {
1007         struct mrvl_priv *priv = dev->data->dev_private;
1008         char buf[ETHER_ADDR_FMT_SIZE];
1009         int ret;
1010
1011         if (priv->isolated)
1012                 return -ENOTSUP;
1013
1014         if (index == 0)
1015                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1016                 return -1;
1017
1018         if (!priv->ppio)
1019                 return 0;
1020
1021         /*
1022          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1023          * parameter uc_filter_max. Maximum number of mc addresses is then
1024          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1025          * 21 respectively.
1026          *
1027          * If more than uc_filter_max uc addresses were added to filter list
1028          * then NIC will switch to promiscuous mode automatically.
1029          *
1030          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1031          * were added to filter list then NIC will switch to all-multicast mode
1032          * automatically.
1033          */
1034         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1035         if (ret) {
1036                 ether_format_addr(buf, sizeof(buf), mac_addr);
1037                 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1038                 return -1;
1039         }
1040
1041         return 0;
1042 }
1043
1044 /**
1045  * DPDK callback to set the primary MAC address.
1046  *
1047  * @param dev
1048  *   Pointer to Ethernet device structure.
1049  * @param mac_addr
1050  *   MAC address to register.
1051  *
1052  * @return
1053  *   0 on success, negative error value otherwise.
1054  */
1055 static int
1056 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1057 {
1058         struct mrvl_priv *priv = dev->data->dev_private;
1059         int ret;
1060
1061         if (!priv->ppio)
1062                 return 0;
1063
1064         if (priv->isolated)
1065                 return -ENOTSUP;
1066
1067         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1068         if (ret) {
1069                 char buf[ETHER_ADDR_FMT_SIZE];
1070                 ether_format_addr(buf, sizeof(buf), mac_addr);
1071                 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1072         }
1073
1074         return ret;
1075 }
1076
1077 /**
1078  * DPDK callback to get device statistics.
1079  *
1080  * @param dev
1081  *   Pointer to Ethernet device structure.
1082  * @param stats
1083  *   Stats structure output buffer.
1084  *
1085  * @return
1086  *   0 on success, negative error value otherwise.
1087  */
1088 static int
1089 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1090 {
1091         struct mrvl_priv *priv = dev->data->dev_private;
1092         struct pp2_ppio_statistics ppio_stats;
1093         uint64_t drop_mac = 0;
1094         unsigned int i, idx, ret;
1095
1096         if (!priv->ppio)
1097                 return -EPERM;
1098
1099         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1100                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1101                 struct pp2_ppio_inq_statistics rx_stats;
1102
1103                 if (!rxq)
1104                         continue;
1105
1106                 idx = rxq->queue_id;
1107                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1108                         MRVL_LOG(ERR,
1109                                 "rx queue %d stats out of range (0 - %d)",
1110                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1111                         continue;
1112                 }
1113
1114                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1115                                                   priv->rxq_map[idx].tc,
1116                                                   priv->rxq_map[idx].inq,
1117                                                   &rx_stats, 0);
1118                 if (unlikely(ret)) {
1119                         MRVL_LOG(ERR,
1120                                 "Failed to update rx queue %d stats", idx);
1121                         break;
1122                 }
1123
1124                 stats->q_ibytes[idx] = rxq->bytes_recv;
1125                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1126                 stats->q_errors[idx] = rx_stats.drop_early +
1127                                        rx_stats.drop_fullq +
1128                                        rx_stats.drop_bm +
1129                                        rxq->drop_mac;
1130                 stats->ibytes += rxq->bytes_recv;
1131                 drop_mac += rxq->drop_mac;
1132         }
1133
1134         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1135                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1136                 struct pp2_ppio_outq_statistics tx_stats;
1137
1138                 if (!txq)
1139                         continue;
1140
1141                 idx = txq->queue_id;
1142                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1143                         MRVL_LOG(ERR,
1144                                 "tx queue %d stats out of range (0 - %d)",
1145                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1146                 }
1147
1148                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1149                                                    &tx_stats, 0);
1150                 if (unlikely(ret)) {
1151                         MRVL_LOG(ERR,
1152                                 "Failed to update tx queue %d stats", idx);
1153                         break;
1154                 }
1155
1156                 stats->q_opackets[idx] = tx_stats.deq_desc;
1157                 stats->q_obytes[idx] = txq->bytes_sent;
1158                 stats->obytes += txq->bytes_sent;
1159         }
1160
1161         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1162         if (unlikely(ret)) {
1163                 MRVL_LOG(ERR, "Failed to update port statistics");
1164                 return ret;
1165         }
1166
1167         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1168         stats->opackets += ppio_stats.tx_packets;
1169         stats->imissed += ppio_stats.rx_fullq_dropped +
1170                           ppio_stats.rx_bm_dropped +
1171                           ppio_stats.rx_early_dropped +
1172                           ppio_stats.rx_fifo_dropped +
1173                           ppio_stats.rx_cls_dropped;
1174         stats->ierrors = drop_mac;
1175
1176         return 0;
1177 }
1178
1179 /**
1180  * DPDK callback to clear device statistics.
1181  *
1182  * @param dev
1183  *   Pointer to Ethernet device structure.
1184  */
1185 static void
1186 mrvl_stats_reset(struct rte_eth_dev *dev)
1187 {
1188         struct mrvl_priv *priv = dev->data->dev_private;
1189         int i;
1190
1191         if (!priv->ppio)
1192                 return;
1193
1194         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1195                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1196
1197                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1198                                             priv->rxq_map[i].inq, NULL, 1);
1199                 rxq->bytes_recv = 0;
1200                 rxq->drop_mac = 0;
1201         }
1202
1203         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1204                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1205
1206                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1207                 txq->bytes_sent = 0;
1208         }
1209
1210         pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1211 }
1212
1213 /**
1214  * DPDK callback to get extended statistics.
1215  *
1216  * @param dev
1217  *   Pointer to Ethernet device structure.
1218  * @param stats
1219  *   Pointer to xstats table.
1220  * @param n
1221  *   Number of entries in xstats table.
1222  * @return
1223  *   Negative value on error, number of read xstats otherwise.
1224  */
1225 static int
1226 mrvl_xstats_get(struct rte_eth_dev *dev,
1227                 struct rte_eth_xstat *stats, unsigned int n)
1228 {
1229         struct mrvl_priv *priv = dev->data->dev_private;
1230         struct pp2_ppio_statistics ppio_stats;
1231         unsigned int i;
1232
1233         if (!stats)
1234                 return 0;
1235
1236         pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1237         for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1238                 uint64_t val;
1239
1240                 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1241                         val = *(uint32_t *)((uint8_t *)&ppio_stats +
1242                                             mrvl_xstats_tbl[i].offset);
1243                 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1244                         val = *(uint64_t *)((uint8_t *)&ppio_stats +
1245                                             mrvl_xstats_tbl[i].offset);
1246                 else
1247                         return -EINVAL;
1248
1249                 stats[i].id = i;
1250                 stats[i].value = val;
1251         }
1252
1253         return n;
1254 }
1255
1256 /**
1257  * DPDK callback to reset extended statistics.
1258  *
1259  * @param dev
1260  *   Pointer to Ethernet device structure.
1261  */
1262 static void
1263 mrvl_xstats_reset(struct rte_eth_dev *dev)
1264 {
1265         mrvl_stats_reset(dev);
1266 }
1267
1268 /**
1269  * DPDK callback to get extended statistics names.
1270  *
1271  * @param dev (unused)
1272  *   Pointer to Ethernet device structure.
1273  * @param xstats_names
1274  *   Pointer to xstats names table.
1275  * @param size
1276  *   Size of the xstats names table.
1277  * @return
1278  *   Number of read names.
1279  */
1280 static int
1281 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1282                       struct rte_eth_xstat_name *xstats_names,
1283                       unsigned int size)
1284 {
1285         unsigned int i;
1286
1287         if (!xstats_names)
1288                 return RTE_DIM(mrvl_xstats_tbl);
1289
1290         for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1291                 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1292                          mrvl_xstats_tbl[i].name);
1293
1294         return size;
1295 }
1296
1297 /**
1298  * DPDK callback to get information about the device.
1299  *
1300  * @param dev
1301  *   Pointer to Ethernet device structure (unused).
1302  * @param info
1303  *   Info structure output buffer.
1304  */
1305 static void
1306 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1307                    struct rte_eth_dev_info *info)
1308 {
1309         info->speed_capa = ETH_LINK_SPEED_10M |
1310                            ETH_LINK_SPEED_100M |
1311                            ETH_LINK_SPEED_1G |
1312                            ETH_LINK_SPEED_10G;
1313
1314         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1315         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1316         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1317
1318         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1319         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1320         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1321
1322         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1323         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1324         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1325
1326         info->rx_offload_capa = MRVL_RX_OFFLOADS;
1327         info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1328
1329         info->tx_offload_capa = MRVL_TX_OFFLOADS;
1330         info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1331
1332         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1333                                        ETH_RSS_NONFRAG_IPV4_TCP |
1334                                        ETH_RSS_NONFRAG_IPV4_UDP;
1335
1336         /* By default packets are dropped if no descriptors are available */
1337         info->default_rxconf.rx_drop_en = 1;
1338         info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1339
1340         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1341 }
1342
1343 /**
1344  * Return supported packet types.
1345  *
1346  * @param dev
1347  *   Pointer to Ethernet device structure (unused).
1348  *
1349  * @return
1350  *   Const pointer to the table with supported packet types.
1351  */
1352 static const uint32_t *
1353 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1354 {
1355         static const uint32_t ptypes[] = {
1356                 RTE_PTYPE_L2_ETHER,
1357                 RTE_PTYPE_L3_IPV4,
1358                 RTE_PTYPE_L3_IPV4_EXT,
1359                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1360                 RTE_PTYPE_L3_IPV6,
1361                 RTE_PTYPE_L3_IPV6_EXT,
1362                 RTE_PTYPE_L2_ETHER_ARP,
1363                 RTE_PTYPE_L4_TCP,
1364                 RTE_PTYPE_L4_UDP
1365         };
1366
1367         return ptypes;
1368 }
1369
1370 /**
1371  * DPDK callback to get information about specific receive queue.
1372  *
1373  * @param dev
1374  *   Pointer to Ethernet device structure.
1375  * @param rx_queue_id
1376  *   Receive queue index.
1377  * @param qinfo
1378  *   Receive queue information structure.
1379  */
1380 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1381                               struct rte_eth_rxq_info *qinfo)
1382 {
1383         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1384         struct mrvl_priv *priv = dev->data->dev_private;
1385         int inq = priv->rxq_map[rx_queue_id].inq;
1386         int tc = priv->rxq_map[rx_queue_id].tc;
1387         struct pp2_ppio_tc_params *tc_params =
1388                 &priv->ppio_params.inqs_params.tcs_params[tc];
1389
1390         qinfo->mp = q->mp;
1391         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1392 }
1393
1394 /**
1395  * DPDK callback to get information about specific transmit queue.
1396  *
1397  * @param dev
1398  *   Pointer to Ethernet device structure.
1399  * @param tx_queue_id
1400  *   Transmit queue index.
1401  * @param qinfo
1402  *   Transmit queue information structure.
1403  */
1404 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1405                               struct rte_eth_txq_info *qinfo)
1406 {
1407         struct mrvl_priv *priv = dev->data->dev_private;
1408         struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1409
1410         qinfo->nb_desc =
1411                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1412         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1413 }
1414
1415 /**
1416  * DPDK callback to Configure a VLAN filter.
1417  *
1418  * @param dev
1419  *   Pointer to Ethernet device structure.
1420  * @param vlan_id
1421  *   VLAN ID to filter.
1422  * @param on
1423  *   Toggle filter.
1424  *
1425  * @return
1426  *   0 on success, negative error value otherwise.
1427  */
1428 static int
1429 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1430 {
1431         struct mrvl_priv *priv = dev->data->dev_private;
1432
1433         if (!priv->ppio)
1434                 return -EPERM;
1435
1436         if (priv->isolated)
1437                 return -ENOTSUP;
1438
1439         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1440                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1441 }
1442
1443 /**
1444  * Release buffers to hardware bpool (buffer-pool)
1445  *
1446  * @param rxq
1447  *   Receive queue pointer.
1448  * @param num
1449  *   Number of buffers to release to bpool.
1450  *
1451  * @return
1452  *   0 on success, negative error value otherwise.
1453  */
1454 static int
1455 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1456 {
1457         struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1458         struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1459         int i, ret;
1460         unsigned int core_id;
1461         struct pp2_hif *hif;
1462         struct pp2_bpool *bpool;
1463
1464         core_id = rte_lcore_id();
1465         if (core_id == LCORE_ID_ANY)
1466                 core_id = 0;
1467
1468         hif = mrvl_get_hif(rxq->priv, core_id);
1469         if (!hif)
1470                 return -1;
1471
1472         bpool = rxq->priv->bpool;
1473
1474         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1475         if (ret)
1476                 return ret;
1477
1478         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1479                 cookie_addr_high =
1480                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1481
1482         for (i = 0; i < num; i++) {
1483                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1484                         != cookie_addr_high) {
1485                         MRVL_LOG(ERR,
1486                                 "mbuf virtual addr high 0x%lx out of range",
1487                                 (uint64_t)mbufs[i] >> 32);
1488                         goto out;
1489                 }
1490
1491                 entries[i].buff.addr =
1492                         rte_mbuf_data_iova_default(mbufs[i]);
1493                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1494                 entries[i].bpool = bpool;
1495         }
1496
1497         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1498         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1499
1500         if (i != num)
1501                 goto out;
1502
1503         return 0;
1504 out:
1505         for (; i < num; i++)
1506                 rte_pktmbuf_free(mbufs[i]);
1507
1508         return -1;
1509 }
1510
1511 /**
1512  * DPDK callback to configure the receive queue.
1513  *
1514  * @param dev
1515  *   Pointer to Ethernet device structure.
1516  * @param idx
1517  *   RX queue index.
1518  * @param desc
1519  *   Number of descriptors to configure in queue.
1520  * @param socket
1521  *   NUMA socket on which memory must be allocated.
1522  * @param conf
1523  *   Thresholds parameters.
1524  * @param mp
1525  *   Memory pool for buffer allocations.
1526  *
1527  * @return
1528  *   0 on success, negative error value otherwise.
1529  */
1530 static int
1531 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1532                     unsigned int socket,
1533                     const struct rte_eth_rxconf *conf,
1534                     struct rte_mempool *mp)
1535 {
1536         struct mrvl_priv *priv = dev->data->dev_private;
1537         struct mrvl_rxq *rxq;
1538         uint32_t min_size,
1539                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1540         int ret, tc, inq;
1541         uint64_t offloads;
1542
1543         offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1544
1545         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1546                 /*
1547                  * Unknown TC mapping, mapping will not have a correct queue.
1548                  */
1549                 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1550                         idx, priv->ppio_id);
1551                 return -EFAULT;
1552         }
1553
1554         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1555                    MRVL_PKT_EFFEC_OFFS;
1556         if (min_size < max_rx_pkt_len) {
1557                 MRVL_LOG(ERR,
1558                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.",
1559                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1560                         MRVL_PKT_EFFEC_OFFS,
1561                         max_rx_pkt_len);
1562                 return -EINVAL;
1563         }
1564
1565         if (dev->data->rx_queues[idx]) {
1566                 rte_free(dev->data->rx_queues[idx]);
1567                 dev->data->rx_queues[idx] = NULL;
1568         }
1569
1570         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1571         if (!rxq)
1572                 return -ENOMEM;
1573
1574         rxq->priv = priv;
1575         rxq->mp = mp;
1576         rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1577         rxq->queue_id = idx;
1578         rxq->port_id = dev->data->port_id;
1579         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1580
1581         tc = priv->rxq_map[rxq->queue_id].tc,
1582         inq = priv->rxq_map[rxq->queue_id].inq;
1583         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1584                 desc;
1585
1586         ret = mrvl_fill_bpool(rxq, desc);
1587         if (ret) {
1588                 rte_free(rxq);
1589                 return ret;
1590         }
1591
1592         priv->bpool_init_size += desc;
1593
1594         dev->data->rx_queues[idx] = rxq;
1595
1596         return 0;
1597 }
1598
1599 /**
1600  * DPDK callback to release the receive queue.
1601  *
1602  * @param rxq
1603  *   Generic receive queue pointer.
1604  */
1605 static void
1606 mrvl_rx_queue_release(void *rxq)
1607 {
1608         struct mrvl_rxq *q = rxq;
1609         struct pp2_ppio_tc_params *tc_params;
1610         int i, num, tc, inq;
1611         struct pp2_hif *hif;
1612         unsigned int core_id = rte_lcore_id();
1613
1614         if (core_id == LCORE_ID_ANY)
1615                 core_id = 0;
1616
1617         hif = mrvl_get_hif(q->priv, core_id);
1618
1619         if (!q || !hif)
1620                 return;
1621
1622         tc = q->priv->rxq_map[q->queue_id].tc;
1623         inq = q->priv->rxq_map[q->queue_id].inq;
1624         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1625         num = tc_params->inqs_params[inq].size;
1626         for (i = 0; i < num; i++) {
1627                 struct pp2_buff_inf inf;
1628                 uint64_t addr;
1629
1630                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1631                 addr = cookie_addr_high | inf.cookie;
1632                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1633         }
1634
1635         rte_free(q);
1636 }
1637
1638 /**
1639  * DPDK callback to configure the transmit queue.
1640  *
1641  * @param dev
1642  *   Pointer to Ethernet device structure.
1643  * @param idx
1644  *   Transmit queue index.
1645  * @param desc
1646  *   Number of descriptors to configure in the queue.
1647  * @param socket
1648  *   NUMA socket on which memory must be allocated.
1649  * @param conf
1650  *   Tx queue configuration parameters.
1651  *
1652  * @return
1653  *   0 on success, negative error value otherwise.
1654  */
1655 static int
1656 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1657                     unsigned int socket,
1658                     const struct rte_eth_txconf *conf)
1659 {
1660         struct mrvl_priv *priv = dev->data->dev_private;
1661         struct mrvl_txq *txq;
1662
1663         if (dev->data->tx_queues[idx]) {
1664                 rte_free(dev->data->tx_queues[idx]);
1665                 dev->data->tx_queues[idx] = NULL;
1666         }
1667
1668         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1669         if (!txq)
1670                 return -ENOMEM;
1671
1672         txq->priv = priv;
1673         txq->queue_id = idx;
1674         txq->port_id = dev->data->port_id;
1675         txq->tx_deferred_start = conf->tx_deferred_start;
1676         dev->data->tx_queues[idx] = txq;
1677
1678         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1679
1680         return 0;
1681 }
1682
1683 /**
1684  * DPDK callback to release the transmit queue.
1685  *
1686  * @param txq
1687  *   Generic transmit queue pointer.
1688  */
1689 static void
1690 mrvl_tx_queue_release(void *txq)
1691 {
1692         struct mrvl_txq *q = txq;
1693
1694         if (!q)
1695                 return;
1696
1697         rte_free(q);
1698 }
1699
1700 /**
1701  * DPDK callback to get flow control configuration.
1702  *
1703  * @param dev
1704  *  Pointer to Ethernet device structure.
1705  * @param fc_conf
1706  *  Pointer to the flow control configuration.
1707  *
1708  * @return
1709  *  0 on success, negative error value otherwise.
1710  */
1711 static int
1712 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1713 {
1714         struct mrvl_priv *priv = dev->data->dev_private;
1715         int ret, en;
1716
1717         if (!priv)
1718                 return -EPERM;
1719
1720         ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1721         if (ret) {
1722                 MRVL_LOG(ERR, "Failed to read rx pause state");
1723                 return ret;
1724         }
1725
1726         fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1727
1728         return 0;
1729 }
1730
1731 /**
1732  * DPDK callback to set flow control configuration.
1733  *
1734  * @param dev
1735  *  Pointer to Ethernet device structure.
1736  * @param fc_conf
1737  *  Pointer to the flow control configuration.
1738  *
1739  * @return
1740  *  0 on success, negative error value otherwise.
1741  */
1742 static int
1743 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1744 {
1745         struct mrvl_priv *priv = dev->data->dev_private;
1746
1747         if (!priv)
1748                 return -EPERM;
1749
1750         if (fc_conf->high_water ||
1751             fc_conf->low_water ||
1752             fc_conf->pause_time ||
1753             fc_conf->mac_ctrl_frame_fwd ||
1754             fc_conf->autoneg) {
1755                 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1756
1757                 return -EINVAL;
1758         }
1759
1760         if (fc_conf->mode == RTE_FC_NONE ||
1761             fc_conf->mode == RTE_FC_RX_PAUSE) {
1762                 int ret, en;
1763
1764                 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1765                 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1766                 if (ret)
1767                         MRVL_LOG(ERR,
1768                                 "Failed to change flowctrl on RX side");
1769
1770                 return ret;
1771         }
1772
1773         return 0;
1774 }
1775
1776 /**
1777  * Update RSS hash configuration
1778  *
1779  * @param dev
1780  *   Pointer to Ethernet device structure.
1781  * @param rss_conf
1782  *   Pointer to RSS configuration.
1783  *
1784  * @return
1785  *   0 on success, negative error value otherwise.
1786  */
1787 static int
1788 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1789                      struct rte_eth_rss_conf *rss_conf)
1790 {
1791         struct mrvl_priv *priv = dev->data->dev_private;
1792
1793         if (priv->isolated)
1794                 return -ENOTSUP;
1795
1796         return mrvl_configure_rss(priv, rss_conf);
1797 }
1798
1799 /**
1800  * DPDK callback to get RSS hash configuration.
1801  *
1802  * @param dev
1803  *   Pointer to Ethernet device structure.
1804  * @rss_conf
1805  *   Pointer to RSS configuration.
1806  *
1807  * @return
1808  *   Always 0.
1809  */
1810 static int
1811 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1812                        struct rte_eth_rss_conf *rss_conf)
1813 {
1814         struct mrvl_priv *priv = dev->data->dev_private;
1815         enum pp2_ppio_hash_type hash_type =
1816                 priv->ppio_params.inqs_params.hash_type;
1817
1818         rss_conf->rss_key = NULL;
1819
1820         if (hash_type == PP2_PPIO_HASH_T_NONE)
1821                 rss_conf->rss_hf = 0;
1822         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1823                 rss_conf->rss_hf = ETH_RSS_IPV4;
1824         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1825                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1826         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1827                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1828
1829         return 0;
1830 }
1831
1832 /**
1833  * DPDK callback to get rte_flow callbacks.
1834  *
1835  * @param dev
1836  *   Pointer to the device structure.
1837  * @param filer_type
1838  *   Flow filter type.
1839  * @param filter_op
1840  *   Flow filter operation.
1841  * @param arg
1842  *   Pointer to pass the flow ops.
1843  *
1844  * @return
1845  *   0 on success, negative error value otherwise.
1846  */
1847 static int
1848 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1849                      enum rte_filter_type filter_type,
1850                      enum rte_filter_op filter_op, void *arg)
1851 {
1852         switch (filter_type) {
1853         case RTE_ETH_FILTER_GENERIC:
1854                 if (filter_op != RTE_ETH_FILTER_GET)
1855                         return -EINVAL;
1856                 *(const void **)arg = &mrvl_flow_ops;
1857                 return 0;
1858         default:
1859                 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1860                                 filter_type);
1861                 return -EINVAL;
1862         }
1863 }
1864
1865 static const struct eth_dev_ops mrvl_ops = {
1866         .dev_configure = mrvl_dev_configure,
1867         .dev_start = mrvl_dev_start,
1868         .dev_stop = mrvl_dev_stop,
1869         .dev_set_link_up = mrvl_dev_set_link_up,
1870         .dev_set_link_down = mrvl_dev_set_link_down,
1871         .dev_close = mrvl_dev_close,
1872         .link_update = mrvl_link_update,
1873         .promiscuous_enable = mrvl_promiscuous_enable,
1874         .allmulticast_enable = mrvl_allmulticast_enable,
1875         .promiscuous_disable = mrvl_promiscuous_disable,
1876         .allmulticast_disable = mrvl_allmulticast_disable,
1877         .mac_addr_remove = mrvl_mac_addr_remove,
1878         .mac_addr_add = mrvl_mac_addr_add,
1879         .mac_addr_set = mrvl_mac_addr_set,
1880         .mtu_set = mrvl_mtu_set,
1881         .stats_get = mrvl_stats_get,
1882         .stats_reset = mrvl_stats_reset,
1883         .xstats_get = mrvl_xstats_get,
1884         .xstats_reset = mrvl_xstats_reset,
1885         .xstats_get_names = mrvl_xstats_get_names,
1886         .dev_infos_get = mrvl_dev_infos_get,
1887         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1888         .rxq_info_get = mrvl_rxq_info_get,
1889         .txq_info_get = mrvl_txq_info_get,
1890         .vlan_filter_set = mrvl_vlan_filter_set,
1891         .tx_queue_start = mrvl_tx_queue_start,
1892         .tx_queue_stop = mrvl_tx_queue_stop,
1893         .rx_queue_setup = mrvl_rx_queue_setup,
1894         .rx_queue_release = mrvl_rx_queue_release,
1895         .tx_queue_setup = mrvl_tx_queue_setup,
1896         .tx_queue_release = mrvl_tx_queue_release,
1897         .flow_ctrl_get = mrvl_flow_ctrl_get,
1898         .flow_ctrl_set = mrvl_flow_ctrl_set,
1899         .rss_hash_update = mrvl_rss_hash_update,
1900         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1901         .filter_ctrl = mrvl_eth_filter_ctrl,
1902 };
1903
1904 /**
1905  * Return packet type information and l3/l4 offsets.
1906  *
1907  * @param desc
1908  *   Pointer to the received packet descriptor.
1909  * @param l3_offset
1910  *   l3 packet offset.
1911  * @param l4_offset
1912  *   l4 packet offset.
1913  *
1914  * @return
1915  *   Packet type information.
1916  */
1917 static inline uint64_t
1918 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1919                                     uint8_t *l3_offset, uint8_t *l4_offset)
1920 {
1921         enum pp2_inq_l3_type l3_type;
1922         enum pp2_inq_l4_type l4_type;
1923         uint64_t packet_type;
1924
1925         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1926         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1927
1928         packet_type = RTE_PTYPE_L2_ETHER;
1929
1930         switch (l3_type) {
1931         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1932                 packet_type |= RTE_PTYPE_L3_IPV4;
1933                 break;
1934         case PP2_INQ_L3_TYPE_IPV4_OK:
1935                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1936                 break;
1937         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1938                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1939                 break;
1940         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1941                 packet_type |= RTE_PTYPE_L3_IPV6;
1942                 break;
1943         case PP2_INQ_L3_TYPE_IPV6_EXT:
1944                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1945                 break;
1946         case PP2_INQ_L3_TYPE_ARP:
1947                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1948                 /*
1949                  * In case of ARP l4_offset is set to wrong value.
1950                  * Set it to proper one so that later on mbuf->l3_len can be
1951                  * calculated subtracting l4_offset and l3_offset.
1952                  */
1953                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1954                 break;
1955         default:
1956                 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
1957                 break;
1958         }
1959
1960         switch (l4_type) {
1961         case PP2_INQ_L4_TYPE_TCP:
1962                 packet_type |= RTE_PTYPE_L4_TCP;
1963                 break;
1964         case PP2_INQ_L4_TYPE_UDP:
1965                 packet_type |= RTE_PTYPE_L4_UDP;
1966                 break;
1967         default:
1968                 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
1969                 break;
1970         }
1971
1972         return packet_type;
1973 }
1974
1975 /**
1976  * Get offload information from the received packet descriptor.
1977  *
1978  * @param desc
1979  *   Pointer to the received packet descriptor.
1980  *
1981  * @return
1982  *   Mbuf offload flags.
1983  */
1984 static inline uint64_t
1985 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1986 {
1987         uint64_t flags;
1988         enum pp2_inq_desc_status status;
1989
1990         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1991         if (unlikely(status != PP2_DESC_ERR_OK))
1992                 flags = PKT_RX_IP_CKSUM_BAD;
1993         else
1994                 flags = PKT_RX_IP_CKSUM_GOOD;
1995
1996         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1997         if (unlikely(status != PP2_DESC_ERR_OK))
1998                 flags |= PKT_RX_L4_CKSUM_BAD;
1999         else
2000                 flags |= PKT_RX_L4_CKSUM_GOOD;
2001
2002         return flags;
2003 }
2004
2005 /**
2006  * DPDK callback for receive.
2007  *
2008  * @param rxq
2009  *   Generic pointer to the receive queue.
2010  * @param rx_pkts
2011  *   Array to store received packets.
2012  * @param nb_pkts
2013  *   Maximum number of packets in array.
2014  *
2015  * @return
2016  *   Number of packets successfully received.
2017  */
2018 static uint16_t
2019 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2020 {
2021         struct mrvl_rxq *q = rxq;
2022         struct pp2_ppio_desc descs[nb_pkts];
2023         struct pp2_bpool *bpool;
2024         int i, ret, rx_done = 0;
2025         int num;
2026         struct pp2_hif *hif;
2027         unsigned int core_id = rte_lcore_id();
2028
2029         hif = mrvl_get_hif(q->priv, core_id);
2030
2031         if (unlikely(!q->priv->ppio || !hif))
2032                 return 0;
2033
2034         bpool = q->priv->bpool;
2035
2036         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2037                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2038         if (unlikely(ret < 0)) {
2039                 MRVL_LOG(ERR, "Failed to receive packets");
2040                 return 0;
2041         }
2042         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2043
2044         for (i = 0; i < nb_pkts; i++) {
2045                 struct rte_mbuf *mbuf;
2046                 uint8_t l3_offset, l4_offset;
2047                 enum pp2_inq_desc_status status;
2048                 uint64_t addr;
2049
2050                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2051                         struct pp2_ppio_desc *pref_desc;
2052                         u64 pref_addr;
2053
2054                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2055                         pref_addr = cookie_addr_high |
2056                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
2057                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2058                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2059                 }
2060
2061                 addr = cookie_addr_high |
2062                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
2063                 mbuf = (struct rte_mbuf *)addr;
2064                 rte_pktmbuf_reset(mbuf);
2065
2066                 /* drop packet in case of mac, overrun or resource error */
2067                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2068                 if (unlikely(status != PP2_DESC_ERR_OK)) {
2069                         struct pp2_buff_inf binf = {
2070                                 .addr = rte_mbuf_data_iova_default(mbuf),
2071                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2072                         };
2073
2074                         pp2_bpool_put_buff(hif, bpool, &binf);
2075                         mrvl_port_bpool_size
2076                                 [bpool->pp2_id][bpool->id][core_id]++;
2077                         q->drop_mac++;
2078                         continue;
2079                 }
2080
2081                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2082                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2083                 mbuf->data_len = mbuf->pkt_len;
2084                 mbuf->port = q->port_id;
2085                 mbuf->packet_type =
2086                         mrvl_desc_to_packet_type_and_offset(&descs[i],
2087                                                             &l3_offset,
2088                                                             &l4_offset);
2089                 mbuf->l2_len = l3_offset;
2090                 mbuf->l3_len = l4_offset - l3_offset;
2091
2092                 if (likely(q->cksum_enabled))
2093                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2094
2095                 rx_pkts[rx_done++] = mbuf;
2096                 q->bytes_recv += mbuf->pkt_len;
2097         }
2098
2099         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2100                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2101
2102                 if (unlikely(num <= q->priv->bpool_min_size ||
2103                              (!rx_done && num < q->priv->bpool_init_size))) {
2104                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2105                         if (ret)
2106                                 MRVL_LOG(ERR, "Failed to fill bpool");
2107                 } else if (unlikely(num > q->priv->bpool_max_size)) {
2108                         int i;
2109                         int pkt_to_remove = num - q->priv->bpool_init_size;
2110                         struct rte_mbuf *mbuf;
2111                         struct pp2_buff_inf buff;
2112
2113                         MRVL_LOG(DEBUG,
2114                                 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2115                                 bpool->pp2_id, q->priv->ppio->port_id,
2116                                 bpool->id, pkt_to_remove, num,
2117                                 q->priv->bpool_init_size);
2118
2119                         for (i = 0; i < pkt_to_remove; i++) {
2120                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2121                                 if (ret)
2122                                         break;
2123                                 mbuf = (struct rte_mbuf *)
2124                                         (cookie_addr_high | buff.cookie);
2125                                 rte_pktmbuf_free(mbuf);
2126                         }
2127                         mrvl_port_bpool_size
2128                                 [bpool->pp2_id][bpool->id][core_id] -= i;
2129                 }
2130                 rte_spinlock_unlock(&q->priv->lock);
2131         }
2132
2133         return rx_done;
2134 }
2135
2136 /**
2137  * Prepare offload information.
2138  *
2139  * @param ol_flags
2140  *   Offload flags.
2141  * @param packet_type
2142  *   Packet type bitfield.
2143  * @param l3_type
2144  *   Pointer to the pp2_ouq_l3_type structure.
2145  * @param l4_type
2146  *   Pointer to the pp2_outq_l4_type structure.
2147  * @param gen_l3_cksum
2148  *   Will be set to 1 in case l3 checksum is computed.
2149  * @param l4_cksum
2150  *   Will be set to 1 in case l4 checksum is computed.
2151  *
2152  * @return
2153  *   0 on success, negative error value otherwise.
2154  */
2155 static inline int
2156 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2157                         enum pp2_outq_l3_type *l3_type,
2158                         enum pp2_outq_l4_type *l4_type,
2159                         int *gen_l3_cksum,
2160                         int *gen_l4_cksum)
2161 {
2162         /*
2163          * Based on ol_flags prepare information
2164          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2165          * for offloading.
2166          */
2167         if (ol_flags & PKT_TX_IPV4) {
2168                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2169                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2170         } else if (ol_flags & PKT_TX_IPV6) {
2171                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2172                 /* no checksum for ipv6 header */
2173                 *gen_l3_cksum = 0;
2174         } else {
2175                 /* if something different then stop processing */
2176                 return -1;
2177         }
2178
2179         ol_flags &= PKT_TX_L4_MASK;
2180         if ((packet_type & RTE_PTYPE_L4_TCP) &&
2181             ol_flags == PKT_TX_TCP_CKSUM) {
2182                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2183                 *gen_l4_cksum = 1;
2184         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2185                    ol_flags == PKT_TX_UDP_CKSUM) {
2186                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2187                 *gen_l4_cksum = 1;
2188         } else {
2189                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2190                 /* no checksum for other type */
2191                 *gen_l4_cksum = 0;
2192         }
2193
2194         return 0;
2195 }
2196
2197 /**
2198  * Release already sent buffers to bpool (buffer-pool).
2199  *
2200  * @param ppio
2201  *   Pointer to the port structure.
2202  * @param hif
2203  *   Pointer to the MUSDK hardware interface.
2204  * @param sq
2205  *   Pointer to the shadow queue.
2206  * @param qid
2207  *   Queue id number.
2208  * @param force
2209  *   Force releasing packets.
2210  */
2211 static inline void
2212 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2213                        unsigned int core_id, struct mrvl_shadow_txq *sq,
2214                        int qid, int force)
2215 {
2216         struct buff_release_entry *entry;
2217         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2218         int i;
2219
2220         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2221
2222         sq->num_to_release += nb_done;
2223
2224         if (likely(!force &&
2225                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2226                 return;
2227
2228         nb_done = sq->num_to_release;
2229         sq->num_to_release = 0;
2230
2231         for (i = 0; i < nb_done; i++) {
2232                 entry = &sq->ent[sq->tail + num];
2233                 if (unlikely(!entry->buff.addr)) {
2234                         MRVL_LOG(ERR,
2235                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2236                                 sq->tail, (u64)entry->buff.cookie,
2237                                 (u64)entry->buff.addr);
2238                         skip_bufs = 1;
2239                         goto skip;
2240                 }
2241
2242                 if (unlikely(!entry->bpool)) {
2243                         struct rte_mbuf *mbuf;
2244
2245                         mbuf = (struct rte_mbuf *)
2246                                (cookie_addr_high | entry->buff.cookie);
2247                         rte_pktmbuf_free(mbuf);
2248                         skip_bufs = 1;
2249                         goto skip;
2250                 }
2251
2252                 mrvl_port_bpool_size
2253                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2254                 num++;
2255                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2256                         goto skip;
2257                 continue;
2258 skip:
2259                 if (likely(num))
2260                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2261                 num += skip_bufs;
2262                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2263                 sq->size -= num;
2264                 num = 0;
2265                 skip_bufs = 0;
2266         }
2267
2268         if (likely(num)) {
2269                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2270                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2271                 sq->size -= num;
2272         }
2273 }
2274
2275 /**
2276  * DPDK callback for transmit.
2277  *
2278  * @param txq
2279  *   Generic pointer transmit queue.
2280  * @param tx_pkts
2281  *   Packets to transmit.
2282  * @param nb_pkts
2283  *   Number of packets in array.
2284  *
2285  * @return
2286  *   Number of packets successfully transmitted.
2287  */
2288 static uint16_t
2289 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2290 {
2291         struct mrvl_txq *q = txq;
2292         struct mrvl_shadow_txq *sq;
2293         struct pp2_hif *hif;
2294         struct pp2_ppio_desc descs[nb_pkts];
2295         unsigned int core_id = rte_lcore_id();
2296         int i, ret, bytes_sent = 0;
2297         uint16_t num, sq_free_size;
2298         uint64_t addr;
2299
2300         hif = mrvl_get_hif(q->priv, core_id);
2301         sq = &q->shadow_txqs[core_id];
2302
2303         if (unlikely(!q->priv->ppio || !hif))
2304                 return 0;
2305
2306         if (sq->size)
2307                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2308                                        sq, q->queue_id, 0);
2309
2310         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2311         if (unlikely(nb_pkts > sq_free_size)) {
2312                 MRVL_LOG(DEBUG,
2313                         "No room in shadow queue for %d packets! %d packets will be sent.",
2314                         nb_pkts, sq_free_size);
2315                 nb_pkts = sq_free_size;
2316         }
2317
2318         for (i = 0; i < nb_pkts; i++) {
2319                 struct rte_mbuf *mbuf = tx_pkts[i];
2320                 int gen_l3_cksum, gen_l4_cksum;
2321                 enum pp2_outq_l3_type l3_type;
2322                 enum pp2_outq_l4_type l4_type;
2323
2324                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2325                         struct rte_mbuf *pref_pkt_hdr;
2326
2327                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2328                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2329                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2330                 }
2331
2332                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2333                 sq->ent[sq->head].buff.addr =
2334                         rte_mbuf_data_iova_default(mbuf);
2335                 sq->ent[sq->head].bpool =
2336                         (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2337                          mbuf->refcnt > 1)) ? NULL :
2338                          mrvl_port_to_bpool_lookup[mbuf->port];
2339                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2340                 sq->size++;
2341
2342                 pp2_ppio_outq_desc_reset(&descs[i]);
2343                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2344                                                  rte_pktmbuf_iova(mbuf));
2345                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2346                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2347                                                rte_pktmbuf_pkt_len(mbuf));
2348
2349                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2350                 /*
2351                  * in case unsupported ol_flags were passed
2352                  * do not update descriptor offload information
2353                  */
2354                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2355                                               &l3_type, &l4_type, &gen_l3_cksum,
2356                                               &gen_l4_cksum);
2357                 if (unlikely(ret))
2358                         continue;
2359
2360                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2361                                                   mbuf->l2_len,
2362                                                   mbuf->l2_len + mbuf->l3_len,
2363                                                   gen_l3_cksum, gen_l4_cksum);
2364         }
2365
2366         num = nb_pkts;
2367         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2368         /* number of packets that were not sent */
2369         if (unlikely(num > nb_pkts)) {
2370                 for (i = nb_pkts; i < num; i++) {
2371                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2372                                 MRVL_PP2_TX_SHADOWQ_MASK;
2373                         addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2374                         bytes_sent -=
2375                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2376                 }
2377                 sq->size -= num - nb_pkts;
2378         }
2379
2380         q->bytes_sent += bytes_sent;
2381
2382         return nb_pkts;
2383 }
2384
2385 /**
2386  * Initialize packet processor.
2387  *
2388  * @return
2389  *   0 on success, negative error value otherwise.
2390  */
2391 static int
2392 mrvl_init_pp2(void)
2393 {
2394         struct pp2_init_params init_params;
2395
2396         memset(&init_params, 0, sizeof(init_params));
2397         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2398         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2399         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2400
2401         return pp2_init(&init_params);
2402 }
2403
2404 /**
2405  * Deinitialize packet processor.
2406  *
2407  * @return
2408  *   0 on success, negative error value otherwise.
2409  */
2410 static void
2411 mrvl_deinit_pp2(void)
2412 {
2413         pp2_deinit();
2414 }
2415
2416 /**
2417  * Create private device structure.
2418  *
2419  * @param dev_name
2420  *   Pointer to the port name passed in the initialization parameters.
2421  *
2422  * @return
2423  *   Pointer to the newly allocated private device structure.
2424  */
2425 static struct mrvl_priv *
2426 mrvl_priv_create(const char *dev_name)
2427 {
2428         struct pp2_bpool_params bpool_params;
2429         char match[MRVL_MATCH_LEN];
2430         struct mrvl_priv *priv;
2431         int ret, bpool_bit;
2432
2433         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2434         if (!priv)
2435                 return NULL;
2436
2437         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2438                                        &priv->pp_id, &priv->ppio_id);
2439         if (ret)
2440                 goto out_free_priv;
2441
2442         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2443                                      PP2_BPOOL_NUM_POOLS);
2444         if (bpool_bit < 0)
2445                 goto out_free_priv;
2446         priv->bpool_bit = bpool_bit;
2447
2448         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2449                  priv->bpool_bit);
2450         memset(&bpool_params, 0, sizeof(bpool_params));
2451         bpool_params.match = match;
2452         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2453         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2454         if (ret)
2455                 goto out_clear_bpool_bit;
2456
2457         priv->ppio_params.type = PP2_PPIO_T_NIC;
2458         rte_spinlock_init(&priv->lock);
2459
2460         return priv;
2461 out_clear_bpool_bit:
2462         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2463 out_free_priv:
2464         rte_free(priv);
2465         return NULL;
2466 }
2467
2468 /**
2469  * Create device representing Ethernet port.
2470  *
2471  * @param name
2472  *   Pointer to the port's name.
2473  *
2474  * @return
2475  *   0 on success, negative error value otherwise.
2476  */
2477 static int
2478 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2479 {
2480         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2481         struct rte_eth_dev *eth_dev;
2482         struct mrvl_priv *priv;
2483         struct ifreq req;
2484
2485         eth_dev = rte_eth_dev_allocate(name);
2486         if (!eth_dev)
2487                 return -ENOMEM;
2488
2489         priv = mrvl_priv_create(name);
2490         if (!priv) {
2491                 ret = -ENOMEM;
2492                 goto out_free_dev;
2493         }
2494
2495         eth_dev->data->mac_addrs =
2496                 rte_zmalloc("mac_addrs",
2497                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2498         if (!eth_dev->data->mac_addrs) {
2499                 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2500                 ret = -ENOMEM;
2501                 goto out_free_priv;
2502         }
2503
2504         memset(&req, 0, sizeof(req));
2505         strcpy(req.ifr_name, name);
2506         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2507         if (ret)
2508                 goto out_free_mac;
2509
2510         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2511                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2512
2513         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2514         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2515         eth_dev->data->kdrv = RTE_KDRV_NONE;
2516         eth_dev->data->dev_private = priv;
2517         eth_dev->device = &vdev->device;
2518         eth_dev->dev_ops = &mrvl_ops;
2519
2520         rte_eth_dev_probing_finish(eth_dev);
2521         return 0;
2522 out_free_mac:
2523         rte_free(eth_dev->data->mac_addrs);
2524 out_free_dev:
2525         rte_eth_dev_release_port(eth_dev);
2526 out_free_priv:
2527         rte_free(priv);
2528
2529         return ret;
2530 }
2531
2532 /**
2533  * Cleanup previously created device representing Ethernet port.
2534  *
2535  * @param name
2536  *   Pointer to the port name.
2537  */
2538 static void
2539 mrvl_eth_dev_destroy(const char *name)
2540 {
2541         struct rte_eth_dev *eth_dev;
2542         struct mrvl_priv *priv;
2543
2544         eth_dev = rte_eth_dev_allocated(name);
2545         if (!eth_dev)
2546                 return;
2547
2548         priv = eth_dev->data->dev_private;
2549         pp2_bpool_deinit(priv->bpool);
2550         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2551         rte_free(priv);
2552         rte_free(eth_dev->data->mac_addrs);
2553         rte_eth_dev_release_port(eth_dev);
2554 }
2555
2556 /**
2557  * Callback used by rte_kvargs_process() during argument parsing.
2558  *
2559  * @param key
2560  *   Pointer to the parsed key (unused).
2561  * @param value
2562  *   Pointer to the parsed value.
2563  * @param extra_args
2564  *   Pointer to the extra arguments which contains address of the
2565  *   table of pointers to parsed interface names.
2566  *
2567  * @return
2568  *   Always 0.
2569  */
2570 static int
2571 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2572                  void *extra_args)
2573 {
2574         struct mrvl_ifnames *ifnames = extra_args;
2575
2576         ifnames->names[ifnames->idx++] = value;
2577
2578         return 0;
2579 }
2580
2581 /**
2582  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2583  */
2584 static void
2585 mrvl_deinit_hifs(void)
2586 {
2587         int i;
2588
2589         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2590                 if (hifs[i])
2591                         pp2_hif_deinit(hifs[i]);
2592         }
2593         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2594         memset(hifs, 0, sizeof(hifs));
2595 }
2596
2597 /**
2598  * DPDK callback to register the virtual device.
2599  *
2600  * @param vdev
2601  *   Pointer to the virtual device.
2602  *
2603  * @return
2604  *   0 on success, negative error value otherwise.
2605  */
2606 static int
2607 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2608 {
2609         struct rte_kvargs *kvlist;
2610         struct mrvl_ifnames ifnames;
2611         int ret = -EINVAL;
2612         uint32_t i, ifnum, cfgnum;
2613         const char *params;
2614
2615         params = rte_vdev_device_args(vdev);
2616         if (!params)
2617                 return -EINVAL;
2618
2619         kvlist = rte_kvargs_parse(params, valid_args);
2620         if (!kvlist)
2621                 return -EINVAL;
2622
2623         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2624         if (ifnum > RTE_DIM(ifnames.names))
2625                 goto out_free_kvlist;
2626
2627         ifnames.idx = 0;
2628         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2629                            mrvl_get_ifnames, &ifnames);
2630
2631
2632         /*
2633          * The below system initialization should be done only once,
2634          * on the first provided configuration file
2635          */
2636         if (!mrvl_qos_cfg) {
2637                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2638                 MRVL_LOG(INFO, "Parsing config file!");
2639                 if (cfgnum > 1) {
2640                         MRVL_LOG(ERR, "Cannot handle more than one config file!");
2641                         goto out_free_kvlist;
2642                 } else if (cfgnum == 1) {
2643                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2644                                            mrvl_get_qoscfg, &mrvl_qos_cfg);
2645                 }
2646         }
2647
2648         if (mrvl_dev_num)
2649                 goto init_devices;
2650
2651         MRVL_LOG(INFO, "Perform MUSDK initializations");
2652         /*
2653          * ret == -EEXIST is correct, it means DMA
2654          * has been already initialized (by another PMD).
2655          */
2656         ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2657         if (ret < 0) {
2658                 if (ret != -EEXIST)
2659                         goto out_free_kvlist;
2660                 else
2661                         MRVL_LOG(INFO,
2662                                 "DMA memory has been already initialized by a different driver.");
2663         }
2664
2665         ret = mrvl_init_pp2();
2666         if (ret) {
2667                 MRVL_LOG(ERR, "Failed to init PP!");
2668                 goto out_deinit_dma;
2669         }
2670
2671         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2672         memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2673
2674         mrvl_lcore_first = RTE_MAX_LCORE;
2675         mrvl_lcore_last = 0;
2676
2677 init_devices:
2678         for (i = 0; i < ifnum; i++) {
2679                 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2680                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2681                 if (ret)
2682                         goto out_cleanup;
2683         }
2684         mrvl_dev_num += ifnum;
2685
2686         rte_kvargs_free(kvlist);
2687
2688         return 0;
2689 out_cleanup:
2690         for (; i > 0; i--)
2691                 mrvl_eth_dev_destroy(ifnames.names[i]);
2692
2693         if (mrvl_dev_num == 0)
2694                 mrvl_deinit_pp2();
2695 out_deinit_dma:
2696         if (mrvl_dev_num == 0)
2697                 mv_sys_dma_mem_destroy();
2698 out_free_kvlist:
2699         rte_kvargs_free(kvlist);
2700
2701         return ret;
2702 }
2703
2704 /**
2705  * DPDK callback to remove virtual device.
2706  *
2707  * @param vdev
2708  *   Pointer to the removed virtual device.
2709  *
2710  * @return
2711  *   0 on success, negative error value otherwise.
2712  */
2713 static int
2714 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2715 {
2716         int i;
2717         const char *name;
2718
2719         name = rte_vdev_device_name(vdev);
2720         if (!name)
2721                 return -EINVAL;
2722
2723         MRVL_LOG(INFO, "Removing %s", name);
2724
2725         RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2726                 char ifname[RTE_ETH_NAME_MAX_LEN];
2727
2728                 rte_eth_dev_get_name_by_port(i, ifname);
2729                 mrvl_eth_dev_destroy(ifname);
2730                 mrvl_dev_num--;
2731         }
2732
2733         if (mrvl_dev_num == 0) {
2734                 MRVL_LOG(INFO, "Perform MUSDK deinit");
2735                 mrvl_deinit_hifs();
2736                 mrvl_deinit_pp2();
2737                 mv_sys_dma_mem_destroy();
2738         }
2739
2740         return 0;
2741 }
2742
2743 static struct rte_vdev_driver pmd_mrvl_drv = {
2744         .probe = rte_pmd_mrvl_probe,
2745         .remove = rte_pmd_mrvl_remove,
2746 };
2747
2748 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2749 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
2750
2751 RTE_INIT(mrvl_init_log);
2752 static void
2753 mrvl_init_log(void)
2754 {
2755         mrvl_logtype = rte_log_register("pmd.net.mvpp2");
2756         if (mrvl_logtype >= 0)
2757                 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);
2758 }