2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
48 #include <sys/socket.h>
55 #include <rte_byteorder.h>
56 #include <rte_common.h>
58 #include <rte_debug.h>
59 #include <rte_ethdev.h>
61 #include <rte_ether.h>
62 #include <rte_malloc.h>
63 #include <rte_memzone.h>
64 #include <rte_mempool.h>
65 #include <rte_version.h>
66 #include <rte_string_fns.h>
67 #include <rte_alarm.h>
69 #include "nfp_net_pmd.h"
70 #include "nfp_net_logs.h"
71 #include "nfp_net_ctrl.h"
74 static void nfp_net_close(struct rte_eth_dev *dev);
75 static int nfp_net_configure(struct rte_eth_dev *dev);
76 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
78 static void nfp_net_dev_interrupt_delayed_handler(void *param);
79 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
80 static void nfp_net_infos_get(struct rte_eth_dev *dev,
81 struct rte_eth_dev_info *dev_info);
82 static int nfp_net_init(struct rte_eth_dev *eth_dev);
83 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
84 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
85 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
86 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
87 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
89 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
91 static void nfp_net_rx_queue_release(void *rxq);
92 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
93 uint16_t nb_desc, unsigned int socket_id,
94 const struct rte_eth_rxconf *rx_conf,
95 struct rte_mempool *mp);
96 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
97 static void nfp_net_tx_queue_release(void *txq);
98 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
99 uint16_t nb_desc, unsigned int socket_id,
100 const struct rte_eth_txconf *tx_conf);
101 static int nfp_net_start(struct rte_eth_dev *dev);
102 static void nfp_net_stats_get(struct rte_eth_dev *dev,
103 struct rte_eth_stats *stats);
104 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
105 static void nfp_net_stop(struct rte_eth_dev *dev);
106 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
110 * The offset of the queue controller queues in the PCIe Target. These
111 * happen to be at the same offset on the NFP6000 and the NFP3200 so
112 * we use a single macro here.
114 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
116 /* Maximum value which can be added to a queue with one transaction */
117 #define NFP_QCP_MAX_ADD 0x7f
119 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
120 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
122 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
124 NFP_QCP_READ_PTR = 0,
129 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
130 * @q: Base address for queue structure
131 * @ptr: Add to the Read or Write pointer
132 * @val: Value to add to the queue pointer
134 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
137 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
141 if (ptr == NFP_QCP_READ_PTR)
142 off = NFP_QCP_QUEUE_ADD_RPTR;
144 off = NFP_QCP_QUEUE_ADD_WPTR;
146 while (val > NFP_QCP_MAX_ADD) {
147 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
148 val -= NFP_QCP_MAX_ADD;
151 nn_writel(rte_cpu_to_le_32(val), q + off);
155 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
156 * @q: Base address for queue structure
157 * @ptr: Read or Write pointer
159 static inline uint32_t
160 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
165 if (ptr == NFP_QCP_READ_PTR)
166 off = NFP_QCP_QUEUE_STS_LO;
168 off = NFP_QCP_QUEUE_STS_HI;
170 val = rte_cpu_to_le_32(nn_readl(q + off));
172 if (ptr == NFP_QCP_READ_PTR)
173 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
175 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
179 * Functions to read/write from/to Config BAR
180 * Performs any endian conversion necessary.
182 static inline uint8_t
183 nn_cfg_readb(struct nfp_net_hw *hw, int off)
185 return nn_readb(hw->ctrl_bar + off);
189 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
191 nn_writeb(val, hw->ctrl_bar + off);
194 static inline uint32_t
195 nn_cfg_readl(struct nfp_net_hw *hw, int off)
197 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
201 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
203 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
206 static inline uint64_t
207 nn_cfg_readq(struct nfp_net_hw *hw, int off)
209 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
213 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
215 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
218 /* Creating memzone for hardware rings. */
219 static const struct rte_memzone *
220 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
221 uint16_t queue_id, uint32_t ring_size, int socket_id)
223 char z_name[RTE_MEMZONE_NAMESIZE];
224 const struct rte_memzone *mz;
226 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
227 dev->driver->pci_drv.name,
228 ring_name, dev->data->port_id, queue_id);
230 mz = rte_memzone_lookup(z_name);
234 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
239 * Atomically reads link status information from global structure rte_eth_dev.
242 * - Pointer to the structure rte_eth_dev to read from.
243 * - Pointer to the buffer to be saved with the link status.
246 * - On success, zero.
247 * - On failure, negative value.
250 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
251 struct rte_eth_link *link)
253 struct rte_eth_link *dst = link;
254 struct rte_eth_link *src = &dev->data->dev_link;
256 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
257 *(uint64_t *)src) == 0)
264 * Atomically writes the link status information into global
265 * structure rte_eth_dev.
268 * - Pointer to the structure rte_eth_dev to read from.
269 * - Pointer to the buffer to be saved with the link status.
272 * - On success, zero.
273 * - On failure, negative value.
276 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
277 struct rte_eth_link *link)
279 struct rte_eth_link *dst = &dev->data->dev_link;
280 struct rte_eth_link *src = link;
282 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
283 *(uint64_t *)src) == 0)
290 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
294 if (rxq->rxbufs == NULL)
297 for (i = 0; i < rxq->rx_count; i++) {
298 if (rxq->rxbufs[i].mbuf) {
299 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
300 rxq->rxbufs[i].mbuf = NULL;
306 nfp_net_rx_queue_release(void *rx_queue)
308 struct nfp_net_rxq *rxq = rx_queue;
311 nfp_net_rx_queue_release_mbufs(rxq);
312 rte_free(rxq->rxbufs);
318 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
320 nfp_net_rx_queue_release_mbufs(rxq);
327 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
331 if (txq->txbufs == NULL)
334 for (i = 0; i < txq->tx_count; i++) {
335 if (txq->txbufs[i].mbuf) {
336 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
337 txq->txbufs[i].mbuf = NULL;
343 nfp_net_tx_queue_release(void *tx_queue)
345 struct nfp_net_txq *txq = tx_queue;
348 nfp_net_tx_queue_release_mbufs(txq);
349 rte_free(txq->txbufs);
355 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
357 nfp_net_tx_queue_release_mbufs(txq);
364 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
368 struct timespec wait;
370 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
373 if (hw->qcp_cfg == NULL)
374 rte_panic("Bad configuration queue pointer\n");
376 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
379 wait.tv_nsec = 1000000;
381 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
383 /* Poll update field, waiting for NFP to ack the config */
384 for (cnt = 0; ; cnt++) {
385 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
388 if (new & NFP_NET_CFG_UPDATE_ERR) {
389 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
392 if (cnt >= NFP_NET_POLL_TIMEOUT) {
393 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
394 " %dms\n", update, cnt);
395 rte_panic("Exiting\n");
397 nanosleep(&wait, 0); /* waiting for a 1ms */
399 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
404 * Reconfigure the NIC
405 * @nn: device to reconfigure
406 * @ctrl: The value for the ctrl field in the BAR config
407 * @update: The value for the update field in the BAR config
409 * Write the update word to the BAR and ping the reconfig queue. Then poll
410 * until the firmware has acknowledged the update by zeroing the update word.
413 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
417 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
420 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
421 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
425 err = __nfp_net_reconfig(hw, update);
431 * Reconfig errors imply situations where they can be handled.
432 * Otherwise, rte_panic is called inside __nfp_net_reconfig
434 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
440 * Configure an Ethernet device. This function must be invoked first
441 * before any other function in the Ethernet API. This function can
442 * also be re-invoked when a device is in the stopped state.
445 nfp_net_configure(struct rte_eth_dev *dev)
447 struct rte_eth_conf *dev_conf;
448 struct rte_eth_rxmode *rxmode;
449 struct rte_eth_txmode *txmode;
450 uint32_t new_ctrl = 0;
452 struct nfp_net_hw *hw;
454 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
457 * A DPDK app sends info about how many queues to use and how
458 * those queues need to be configured. This is used by the
459 * DPDK core and it makes sure no more queues than those
460 * advertised by the driver are requested. This function is
461 * called after that internal process
464 PMD_INIT_LOG(DEBUG, "Configure\n");
466 dev_conf = &dev->data->dev_conf;
467 rxmode = &dev_conf->rxmode;
468 txmode = &dev_conf->txmode;
470 /* Checking TX mode */
471 if (txmode->mq_mode) {
472 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
476 /* Checking RX mode */
477 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
478 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
479 update = NFP_NET_CFG_UPDATE_RSS;
480 new_ctrl = NFP_NET_CFG_CTRL_RSS;
482 PMD_INIT_LOG(INFO, "RSS not supported\n");
487 if (rxmode->split_hdr_size) {
488 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
492 if (rxmode->hw_ip_checksum) {
493 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
494 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
496 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
501 if (rxmode->hw_vlan_filter) {
502 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
506 if (rxmode->hw_vlan_strip) {
507 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
508 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
510 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
515 if (rxmode->hw_vlan_extend) {
516 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
520 /* Supporting VLAN insertion by default */
521 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
522 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
524 if (rxmode->jumbo_frame)
525 /* this is handled in rte_eth_dev_configure */
527 if (rxmode->hw_strip_crc) {
528 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
532 if (rxmode->enable_scatter) {
533 PMD_INIT_LOG(INFO, "Scatter not supported\n");
540 update |= NFP_NET_CFG_UPDATE_GEN;
542 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
543 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
552 nfp_net_enable_queues(struct rte_eth_dev *dev)
554 struct nfp_net_hw *hw;
555 uint64_t enabled_queues = 0;
558 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
560 /* Enabling the required TX queues in the device */
561 for (i = 0; i < dev->data->nb_tx_queues; i++)
562 enabled_queues |= (1 << i);
564 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
568 /* Enabling the required RX queues in the device */
569 for (i = 0; i < dev->data->nb_rx_queues; i++)
570 enabled_queues |= (1 << i);
572 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
576 nfp_net_disable_queues(struct rte_eth_dev *dev)
578 struct nfp_net_hw *hw;
579 uint32_t new_ctrl, update = 0;
581 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
583 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
584 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
586 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
587 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
588 NFP_NET_CFG_UPDATE_MSIX;
590 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
591 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
593 /* If an error when reconfig we avoid to change hw state */
594 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
601 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
605 for (i = 0; i < dev->data->nb_rx_queues; i++) {
606 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
613 nfp_net_params_setup(struct nfp_net_hw *hw)
615 uint32_t *mac_address;
617 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
618 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
620 /* A MAC address is 8 bytes long */
621 mac_address = (uint32_t *)(hw->mac_addr);
623 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
624 rte_cpu_to_be_32(*mac_address));
625 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
626 rte_cpu_to_be_32(*(mac_address + 4)));
630 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
632 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
636 nfp_net_start(struct rte_eth_dev *dev)
638 uint32_t new_ctrl, update = 0;
639 struct nfp_net_hw *hw;
642 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
644 PMD_INIT_LOG(DEBUG, "Start\n");
646 /* Disabling queues just in case... */
647 nfp_net_disable_queues(dev);
649 /* Writing configuration parameters in the device */
650 nfp_net_params_setup(hw);
652 /* Enabling the required queues in the device */
653 nfp_net_enable_queues(dev);
656 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
657 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
659 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
660 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
662 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
663 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
667 * Allocating rte mbuffs for configured rx queues.
668 * This requires queues being enabled before
670 if (nfp_net_rx_freelist_setup(dev) < 0) {
681 * An error returned by this function should mean the app
682 * exiting and then the system releasing all the memory
683 * allocated even memory coming from hugepages.
685 * The device could be enabled at this point with some queues
686 * ready for getting packets. This is true if the call to
687 * nfp_net_rx_freelist_setup() succeeds for some queues but
688 * fails for subsequent queues.
690 * This should make the app exiting but better if we tell the
693 nfp_net_disable_queues(dev);
698 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
700 nfp_net_stop(struct rte_eth_dev *dev)
704 PMD_INIT_LOG(DEBUG, "Stop\n");
706 nfp_net_disable_queues(dev);
709 for (i = 0; i < dev->data->nb_tx_queues; i++) {
710 nfp_net_reset_tx_queue(
711 (struct nfp_net_txq *)dev->data->tx_queues[i]);
714 for (i = 0; i < dev->data->nb_rx_queues; i++) {
715 nfp_net_reset_rx_queue(
716 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
720 /* Reset and stop device. The device can not be restarted. */
722 nfp_net_close(struct rte_eth_dev *dev)
724 struct nfp_net_hw *hw;
726 PMD_INIT_LOG(DEBUG, "Close\n");
728 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
731 * We assume that the DPDK application is stopping all the
732 * threads/queues before calling the device close function.
737 rte_intr_disable(&dev->pci_dev->intr_handle);
738 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
741 * The ixgbe PMD driver disables the pcie master on the
742 * device. The i40e does not...
747 nfp_net_promisc_enable(struct rte_eth_dev *dev)
749 uint32_t new_ctrl, update = 0;
750 struct nfp_net_hw *hw;
752 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
754 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
756 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
757 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
761 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
762 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
766 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
767 update = NFP_NET_CFG_UPDATE_GEN;
770 * DPDK sets promiscuous mode on just after this call assuming
771 * it can not fail ...
773 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
780 nfp_net_promisc_disable(struct rte_eth_dev *dev)
782 uint32_t new_ctrl, update = 0;
783 struct nfp_net_hw *hw;
785 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
787 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
788 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
792 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
793 update = NFP_NET_CFG_UPDATE_GEN;
796 * DPDK sets promiscuous mode off just before this call
797 * assuming it can not fail ...
799 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
806 * return 0 means link status changed, -1 means not changed
808 * Wait to complete is needed as it can take up to 9 seconds to get the Link
812 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
814 struct nfp_net_hw *hw;
815 struct rte_eth_link link, old;
816 uint32_t nn_link_status;
818 PMD_DRV_LOG(DEBUG, "Link update\n");
820 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
822 memset(&old, 0, sizeof(old));
823 nfp_net_dev_atomic_read_link_status(dev, &old);
825 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
827 memset(&link, 0, sizeof(struct rte_eth_link));
829 if (nn_link_status & NFP_NET_CFG_STS_LINK)
830 link.link_status = 1;
832 link.link_duplex = ETH_LINK_FULL_DUPLEX;
833 /* Other cards can limit the tx and rx rate per VF */
834 link.link_speed = ETH_LINK_SPEED_40G;
836 if (old.link_status != link.link_status) {
837 nfp_net_dev_atomic_write_link_status(dev, &link);
838 if (link.link_status)
839 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
841 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
849 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
852 struct nfp_net_hw *hw;
853 struct rte_eth_stats nfp_dev_stats;
855 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
857 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
859 /* reading per RX ring stats */
860 for (i = 0; i < dev->data->nb_rx_queues; i++) {
861 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
864 nfp_dev_stats.q_ipackets[i] =
865 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
867 nfp_dev_stats.q_ipackets[i] -=
868 hw->eth_stats_base.q_ipackets[i];
870 nfp_dev_stats.q_ibytes[i] =
871 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
873 nfp_dev_stats.q_ibytes[i] -=
874 hw->eth_stats_base.q_ibytes[i];
877 /* reading per TX ring stats */
878 for (i = 0; i < dev->data->nb_tx_queues; i++) {
879 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
882 nfp_dev_stats.q_opackets[i] =
883 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
885 nfp_dev_stats.q_opackets[i] -=
886 hw->eth_stats_base.q_opackets[i];
888 nfp_dev_stats.q_obytes[i] =
889 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
891 nfp_dev_stats.q_obytes[i] -=
892 hw->eth_stats_base.q_obytes[i];
895 nfp_dev_stats.ipackets =
896 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
898 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
900 nfp_dev_stats.ibytes =
901 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
903 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
905 nfp_dev_stats.opackets =
906 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
908 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
910 nfp_dev_stats.obytes =
911 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
913 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
915 nfp_dev_stats.imcasts =
916 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
918 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
920 /* reading general device stats */
921 nfp_dev_stats.ierrors =
922 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
924 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
926 nfp_dev_stats.oerrors =
927 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
929 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
931 /* Multicast frames received */
932 nfp_dev_stats.imcasts =
933 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
935 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
937 /* RX ring mbuf allocation failures */
938 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
940 nfp_dev_stats.imissed =
941 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
943 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
946 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
950 nfp_net_stats_reset(struct rte_eth_dev *dev)
953 struct nfp_net_hw *hw;
955 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 * hw->eth_stats_base records the per counter starting point.
962 /* reading per RX ring stats */
963 for (i = 0; i < dev->data->nb_rx_queues; i++) {
964 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
967 hw->eth_stats_base.q_ipackets[i] =
968 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
970 hw->eth_stats_base.q_ibytes[i] =
971 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
974 /* reading per TX ring stats */
975 for (i = 0; i < dev->data->nb_tx_queues; i++) {
976 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
979 hw->eth_stats_base.q_opackets[i] =
980 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
982 hw->eth_stats_base.q_obytes[i] =
983 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
986 hw->eth_stats_base.ipackets =
987 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
989 hw->eth_stats_base.ibytes =
990 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
992 hw->eth_stats_base.opackets =
993 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
995 hw->eth_stats_base.obytes =
996 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
998 hw->eth_stats_base.imcasts =
999 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
1001 /* reading general device stats */
1002 hw->eth_stats_base.ierrors =
1003 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1005 hw->eth_stats_base.oerrors =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1008 /* Multicast frames received */
1009 hw->eth_stats_base.imcasts =
1010 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
1012 /* RX ring mbuf allocation failures */
1013 dev->data->rx_mbuf_alloc_failed = 0;
1015 hw->eth_stats_base.imissed =
1016 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1020 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1022 struct nfp_net_hw *hw;
1024 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026 dev_info->driver_name = dev->driver->pci_drv.name;
1027 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1028 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1029 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1030 dev_info->max_rx_pktlen = hw->mtu;
1031 /* Next should change when PF support is implemented */
1032 dev_info->max_mac_addrs = 1;
1034 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1035 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1037 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1038 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1039 DEV_RX_OFFLOAD_UDP_CKSUM |
1040 DEV_RX_OFFLOAD_TCP_CKSUM;
1042 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1043 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1045 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1046 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1047 DEV_RX_OFFLOAD_UDP_CKSUM |
1048 DEV_RX_OFFLOAD_TCP_CKSUM;
1050 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1052 .pthresh = DEFAULT_RX_PTHRESH,
1053 .hthresh = DEFAULT_RX_HTHRESH,
1054 .wthresh = DEFAULT_RX_WTHRESH,
1056 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1060 dev_info->default_txconf = (struct rte_eth_txconf) {
1062 .pthresh = DEFAULT_TX_PTHRESH,
1063 .hthresh = DEFAULT_TX_HTHRESH,
1064 .wthresh = DEFAULT_TX_WTHRESH,
1066 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1067 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1068 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1069 ETH_TXQ_FLAGS_NOOFFLOADS,
1072 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1073 #if RTE_VER_MAJOR == 2 && RTE_VER_MINOR >= 1
1074 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1079 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1081 struct nfp_net_rxq *rxq;
1082 struct nfp_net_rx_desc *rxds;
1086 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1089 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1093 idx = rxq->rd_p % rxq->rx_count;
1094 rxds = &rxq->rxds[idx];
1099 * Other PMDs are just checking the DD bit in intervals of 4
1100 * descriptors and counting all four if the first has the DD
1101 * bit on. Of course, this is not accurate but can be good for
1102 * perfomance. But ideally that should be done in descriptors
1103 * chunks belonging to the same cache line
1106 while (count < rxq->rx_count) {
1107 rxds = &rxq->rxds[idx];
1108 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1115 if ((idx) == rxq->rx_count)
1123 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1125 struct rte_eth_link link;
1127 memset(&link, 0, sizeof(link));
1128 nfp_net_dev_atomic_read_link_status(dev, &link);
1129 if (link.link_status)
1130 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1131 (int)(dev->data->port_id), (unsigned)link.link_speed,
1132 link.link_duplex == ETH_LINK_FULL_DUPLEX
1133 ? "full-duplex" : "half-duplex");
1135 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1136 (int)(dev->data->port_id));
1138 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1139 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1140 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1143 /* Interrupt configuration and handling */
1146 * nfp_net_irq_unmask - Unmask an interrupt
1148 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1149 * clear the ICR for the entry.
1152 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1154 struct nfp_net_hw *hw;
1156 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1159 /* If MSI-X auto-masking is used, clear the entry */
1161 rte_intr_enable(&dev->pci_dev->intr_handle);
1163 /* Make sure all updates are written before un-masking */
1165 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1166 NFP_NET_CFG_ICR_UNMASKED);
1171 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1175 struct rte_eth_link link;
1176 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1178 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1180 /* get the link status */
1181 memset(&link, 0, sizeof(link));
1182 nfp_net_dev_atomic_read_link_status(dev, &link);
1184 nfp_net_link_update(dev, 0);
1187 if (!link.link_status) {
1188 /* handle it 1 sec later, wait it being stable */
1189 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1190 /* likely to down */
1192 /* handle it 4 sec later, wait it being stable */
1193 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1196 if (rte_eal_alarm_set(timeout * 1000,
1197 nfp_net_dev_interrupt_delayed_handler,
1199 RTE_LOG(ERR, PMD, "Error setting alarm");
1201 nfp_net_irq_unmask(dev);
1206 * Interrupt handler which shall be registered for alarm callback for delayed
1207 * handling specific interrupt to wait for the stable nic state. As the NIC
1208 * interrupt state is not stable for nfp after link is just down, it needs
1209 * to wait 4 seconds to get the stable status.
1211 * @param handle Pointer to interrupt handle.
1212 * @param param The address of parameter (struct rte_eth_dev *)
1217 nfp_net_dev_interrupt_delayed_handler(void *param)
1219 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1221 nfp_net_link_update(dev, 0);
1222 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1224 nfp_net_dev_link_status_print(dev);
1227 nfp_net_irq_unmask(dev);
1231 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1233 struct nfp_net_hw *hw;
1235 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237 /* check that mtu is within the allowed range */
1238 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1241 /* switch to jumbo mode if needed */
1242 if ((uint32_t)mtu > ETHER_MAX_LEN)
1243 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1245 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1247 /* update max frame size */
1248 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1250 /* writing to configuration space */
1251 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1259 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1260 uint16_t queue_idx, uint16_t nb_desc,
1261 unsigned int socket_id,
1262 const struct rte_eth_rxconf *rx_conf,
1263 struct rte_mempool *mp)
1265 const struct rte_memzone *tz;
1266 struct nfp_net_rxq *rxq;
1267 struct nfp_net_hw *hw;
1269 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271 PMD_INIT_FUNC_TRACE();
1273 /* Validating number of descriptors */
1274 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1275 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1276 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1277 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1282 * Free memory prior to re-allocation if needed. This is the case after
1283 * calling nfp_net_stop
1285 if (dev->data->rx_queues[queue_idx]) {
1286 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1287 dev->data->rx_queues[queue_idx] = NULL;
1290 /* Allocating rx queue data structure */
1291 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1292 RTE_CACHE_LINE_SIZE, socket_id);
1296 /* Hw queues mapping based on firmware confifguration */
1297 rxq->qidx = queue_idx;
1298 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1299 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1300 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1301 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1304 * Tracking mbuf size for detecting a potential mbuf overflow due to
1308 rxq->mbuf_size = rxq->mem_pool->elt_size;
1309 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1310 hw->flbufsz = rxq->mbuf_size;
1312 rxq->rx_count = nb_desc;
1313 rxq->port_id = dev->data->port_id;
1314 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1315 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1317 rxq->drop_en = rx_conf->rx_drop_en;
1320 * Allocate RX ring hardware descriptors. A memzone large enough to
1321 * handle the maximum ring size is allocated in order to allow for
1322 * resizing in later calls to the queue setup function.
1324 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1325 sizeof(struct nfp_net_rx_desc) *
1326 NFP_NET_MAX_RX_DESC, socket_id);
1329 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1330 nfp_net_rx_queue_release(rxq);
1334 /* Saving physical and virtual addresses for the RX ring */
1335 rxq->dma = (uint64_t)tz->phys_addr;
1336 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1338 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1339 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1340 sizeof(*rxq->rxbufs) * nb_desc,
1341 RTE_CACHE_LINE_SIZE, socket_id);
1342 if (rxq->rxbufs == NULL) {
1343 nfp_net_rx_queue_release(rxq);
1347 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1348 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1350 nfp_net_reset_rx_queue(rxq);
1352 dev->data->rx_queues[queue_idx] = rxq;
1356 * Telling the HW about the physical address of the RX ring and number
1357 * of descriptors in log2 format
1359 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1360 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1366 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1368 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1372 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1375 for (i = 0; i < rxq->rx_count; i++) {
1376 struct nfp_net_rx_desc *rxd;
1377 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1380 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1381 (unsigned)rxq->qidx);
1385 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1387 rxd = &rxq->rxds[i];
1389 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1390 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1392 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1397 /* Make sure all writes are flushed before telling the hardware */
1400 /* Not advertising the whole ring as the firmware gets confused if so */
1401 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1404 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1410 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1411 uint16_t nb_desc, unsigned int socket_id,
1412 const struct rte_eth_txconf *tx_conf)
1414 const struct rte_memzone *tz;
1415 struct nfp_net_txq *txq;
1416 uint16_t tx_free_thresh;
1417 struct nfp_net_hw *hw;
1419 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421 PMD_INIT_FUNC_TRACE();
1423 /* Validating number of descriptors */
1424 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1425 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1426 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1427 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1431 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1432 tx_conf->tx_free_thresh :
1433 DEFAULT_TX_FREE_THRESH);
1435 if (tx_free_thresh > (nb_desc)) {
1437 "tx_free_thresh must be less than the number of TX "
1438 "descriptors. (tx_free_thresh=%u port=%d "
1439 "queue=%d)\n", (unsigned int)tx_free_thresh,
1440 (int)dev->data->port_id, (int)queue_idx);
1445 * Free memory prior to re-allocation if needed. This is the case after
1446 * calling nfp_net_stop
1448 if (dev->data->tx_queues[queue_idx]) {
1449 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1451 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1452 dev->data->tx_queues[queue_idx] = NULL;
1455 /* Allocating tx queue data structure */
1456 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1457 RTE_CACHE_LINE_SIZE, socket_id);
1459 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1464 * Allocate TX ring hardware descriptors. A memzone large enough to
1465 * handle the maximum ring size is allocated in order to allow for
1466 * resizing in later calls to the queue setup function.
1468 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1469 sizeof(struct nfp_net_tx_desc) *
1470 NFP_NET_MAX_TX_DESC, socket_id);
1472 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1473 nfp_net_tx_queue_release(txq);
1477 txq->tx_count = nb_desc;
1479 txq->tx_free_thresh = tx_free_thresh;
1480 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1481 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1482 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1484 /* queue mapping based on firmware configuration */
1485 txq->qidx = queue_idx;
1486 txq->tx_qcidx = queue_idx * hw->stride_tx;
1487 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1489 txq->port_id = dev->data->port_id;
1490 txq->txq_flags = tx_conf->txq_flags;
1492 /* Saving physical and virtual addresses for the TX ring */
1493 txq->dma = (uint64_t)tz->phys_addr;
1494 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1496 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1497 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1498 sizeof(*txq->txbufs) * nb_desc,
1499 RTE_CACHE_LINE_SIZE, socket_id);
1500 if (txq->txbufs == NULL) {
1501 nfp_net_tx_queue_release(txq);
1504 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1505 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1507 nfp_net_reset_tx_queue(txq);
1509 dev->data->tx_queues[queue_idx] = txq;
1513 * Telling the HW about the physical address of the TX ring and number
1514 * of descriptors in log2 format
1516 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1517 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1522 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1524 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1525 struct rte_mbuf *mb)
1528 struct nfp_net_hw *hw = txq->hw;
1530 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1533 ol_flags = mb->ol_flags;
1535 /* IPv6 does not need checksum */
1536 if (ol_flags & PKT_TX_IP_CKSUM)
1537 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1539 switch (ol_flags & PKT_TX_L4_MASK) {
1540 case PKT_TX_UDP_CKSUM:
1541 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1543 case PKT_TX_TCP_CKSUM:
1544 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1548 txd->flags |= PCIE_DESC_TX_CSUM;
1551 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1553 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1554 struct rte_mbuf *mb)
1556 struct nfp_net_hw *hw = rxq->hw;
1558 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1561 /* If IPv4 and IP checksum error, fail */
1562 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1563 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1564 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1566 /* If neither UDP nor TCP return */
1567 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1568 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1571 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1572 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1573 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1575 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1576 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1577 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1580 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1581 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1584 * nfp_net_set_hash - Set mbuf hash data
1586 * The RSS hash and hash-type are pre-pended to the packet data.
1587 * Extract and decode it and set the mbuf fields.
1590 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1591 struct rte_mbuf *mbuf)
1595 struct nfp_net_hw *hw = rxq->hw;
1597 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1600 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1603 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1604 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1607 * hash type is sharing the same word with input port info
1612 mbuf->hash.rss = hash;
1613 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1615 switch (hash_type) {
1616 case NFP_NET_RSS_IPV4:
1617 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1619 case NFP_NET_RSS_IPV6:
1620 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1622 case NFP_NET_RSS_IPV6_EX:
1623 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1626 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1630 /* nfp_net_check_port - Set mbuf in_port field */
1632 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1636 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1641 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1642 mbuf->data_off - 8));
1645 * hash type is sharing the same word with input port info
1649 port = (uint8_t)(port >> 8);
1654 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1656 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1659 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1664 * There are some decissions to take:
1665 * 1) How to check DD RX descriptors bit
1666 * 2) How and when to allocate new mbufs
1668 * Current implementation checks just one single DD bit each loop. As each
1669 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1670 * a single cache line instead. Tests with this change have not shown any
1671 * performance improvement but it requires further investigation. For example,
1672 * depending on which descriptor is next, the number of descriptors could be
1673 * less than 8 for just checking those in the same cache line. This implies
1674 * extra work which could be counterproductive by itself. Indeed, last firmware
1675 * changes are just doing this: writing several descriptors with the DD bit
1676 * for saving PCIe bandwidth and DMA operations from the NFP.
1678 * Mbuf allocation is done when a new packet is received. Then the descriptor
1679 * is automatically linked with the new mbuf and the old one is given to the
1680 * user. The main drawback with this design is mbuf allocation is heavier than
1681 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1682 * cache point of view it does not seem allocating the mbuf early on as we are
1683 * doing now have any benefit at all. Again, tests with this change have not
1684 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1685 * so looking at the implications of this type of allocation should be studied
1690 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1692 struct nfp_net_rxq *rxq;
1693 struct nfp_net_rx_desc *rxds;
1694 struct nfp_net_rx_buff *rxb;
1695 struct nfp_net_hw *hw;
1696 struct rte_mbuf *mb;
1697 struct rte_mbuf *new_mb;
1704 if (unlikely(rxq == NULL)) {
1706 * DPDK just checks the queue is lower than max queues
1707 * enabled. But the queue needs to be configured
1709 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1717 while (avail < nb_pkts) {
1718 idx = rxq->rd_p % rxq->rx_count;
1720 rxb = &rxq->rxbufs[idx];
1721 if (unlikely(rxb == NULL)) {
1722 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1727 * Memory barrier to ensure that we won't do other
1728 * reads before the DD bit.
1732 rxds = &rxq->rxds[idx];
1733 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1737 * We got a packet. Let's alloc a new mbuff for refilling the
1738 * free descriptor ring as soon as possible
1740 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1741 if (unlikely(new_mb == NULL)) {
1742 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1743 "queue_id=%u\n", (unsigned)rxq->port_id,
1744 (unsigned)rxq->qidx);
1745 nfp_net_mbuf_alloc_failed(rxq);
1752 * Grab the mbuff and refill the descriptor with the
1753 * previously allocated mbuff
1758 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1759 rxds->rxd.data_len, rxq->mbuf_size);
1761 /* Size of this segment */
1762 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1763 /* Size of the whole packet. We just support 1 segment */
1764 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1766 if (unlikely((mb->data_len + hw->rx_offset) >
1769 * This should not happen and the user has the
1770 * responsibility of avoiding it. But we have
1771 * to give some info about the error
1774 "mbuf overflow likely due to the RX offset.\n"
1775 "\t\tYour mbuf size should have extra space for"
1776 " RX offset=%u bytes.\n"
1777 "\t\tCurrently you just have %u bytes available"
1778 " but the received packet is %u bytes long",
1780 rxq->mbuf_size - hw->rx_offset,
1785 /* Filling the received mbuff with packet info */
1787 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1789 mb->data_off = RTE_PKTMBUF_HEADROOM +
1790 NFP_DESC_META_LEN(rxds);
1792 /* No scatter mode supported */
1796 /* Checking the RSS flag */
1797 nfp_net_set_hash(rxq, rxds, mb);
1799 /* Checking the checksum flag */
1800 nfp_net_rx_cksum(rxq, rxds, mb);
1802 /* Checking the port flag */
1803 nfp_net_check_port(rxds, mb);
1805 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1806 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1807 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1808 mb->ol_flags |= PKT_RX_VLAN_PKT;
1811 /* Adding the mbuff to the mbuff array passed by the app */
1812 rx_pkts[avail++] = mb;
1814 /* Now resetting and updating the descriptor */
1817 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1819 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1820 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1828 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1829 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1831 nb_hold += rxq->nb_rx_hold;
1834 * FL descriptors needs to be written before incrementing the
1835 * FL queue WR pointer
1838 if (nb_hold > rxq->rx_free_thresh) {
1839 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1840 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1841 (unsigned)nb_hold, (unsigned)avail);
1842 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1845 rxq->nb_rx_hold = nb_hold;
1851 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1853 * @txq: TX queue to work with
1854 * Returns number of descriptors freed
1857 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1862 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1863 " status\n", txq->qidx);
1865 /* Work out how many packets have been sent */
1866 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1868 if (qcp_rd_p == txq->qcp_rd_p) {
1869 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1870 "packets (%u, %u)\n", txq->qidx,
1871 qcp_rd_p, txq->qcp_rd_p);
1875 if (qcp_rd_p > txq->qcp_rd_p)
1876 todo = qcp_rd_p - txq->qcp_rd_p;
1878 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1880 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1881 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1886 txq->qcp_rd_p += todo;
1887 txq->qcp_rd_p %= txq->tx_count;
1893 /* Leaving always free descriptors for avoiding wrapping confusion */
1894 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1897 * nfp_net_txq_full - Check if the TX queue free descriptors
1898 * is below tx_free_threshold
1900 * @txq: TX queue to check
1902 * This function uses the host copy* of read/write pointers
1905 int nfp_net_txq_full(struct nfp_net_txq *txq)
1907 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1911 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1913 struct nfp_net_txq *txq;
1914 struct nfp_net_hw *hw;
1915 struct nfp_net_tx_desc *txds;
1916 struct rte_mbuf *pkt;
1918 int pkt_size, dma_size;
1919 uint16_t free_descs, issued_descs;
1920 struct rte_mbuf **lmbuf;
1925 txds = &txq->txds[txq->tail];
1927 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1928 txq->qidx, txq->tail, nb_pkts);
1930 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1931 nfp_net_tx_free_bufs(txq);
1933 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1934 if (unlikely(free_descs == 0))
1941 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1942 txq->qidx, nb_pkts);
1943 /* Sending packets */
1944 while ((i < nb_pkts) && free_descs) {
1945 /* Grabbing the mbuf linked to the current descriptor */
1946 lmbuf = &txq->txbufs[txq->tail].mbuf;
1947 /* Warming the cache for releasing the mbuf later on */
1948 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1950 pkt = *(tx_pkts + i);
1952 if (unlikely((pkt->nb_segs > 1) &&
1953 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1954 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1955 rte_panic("Multisegment packet unsupported\n");
1958 /* Checking if we have enough descriptors */
1959 if (unlikely(pkt->nb_segs > free_descs))
1963 * Checksum and VLAN flags just in the first descriptor for a
1964 * multisegment packet
1966 nfp_net_tx_cksum(txq, txds, pkt);
1968 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1969 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1970 txds->flags |= PCIE_DESC_TX_VLAN;
1971 txds->vlan = pkt->vlan_tci;
1974 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1975 rte_panic("TSO is not supported\n");
1978 * mbuf data_len is the data in one segment and pkt_len data
1979 * in the whole packet. When the packet is just one segment,
1980 * then data_len = pkt_len
1982 pkt_size = pkt->pkt_len;
1985 /* Releasing mbuf which was prefetched above */
1987 rte_pktmbuf_free_seg(*lmbuf);
1989 dma_size = pkt->data_len;
1990 dma_addr = RTE_MBUF_DATA_DMA_ADDR(pkt);
1991 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1992 "%" PRIx64 "\n", dma_addr);
1994 /* Filling descriptors fields */
1995 txds->dma_len = dma_size;
1996 txds->data_len = pkt->pkt_len;
1997 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
1998 txds->dma_addr_lo = (dma_addr & 0xffffffff);
1999 ASSERT(free_descs > 0);
2003 * Linking mbuf with descriptor for being released
2004 * next time descriptor is used
2010 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2013 pkt_size -= dma_size;
2016 txds->offset_eop |= PCIE_DESC_TX_EOP;
2018 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2021 /* Referencing next free TX descriptor */
2022 txds = &txq->txds[txq->tail];
2029 /* Increment write pointers. Force memory write before we let HW know */
2031 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2037 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2039 uint32_t new_ctrl, update;
2040 struct nfp_net_hw *hw;
2042 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2046 (mask & ETH_VLAN_FILTER_OFFLOAD))
2047 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2048 " ETH_VLAN_FILTER_EXTEND");
2050 /* Enable vlan strip if it is not configured yet */
2051 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2052 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2053 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2055 /* Disable vlan strip just if it is configured */
2056 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2057 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2058 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2063 update = NFP_NET_CFG_UPDATE_GEN;
2065 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2068 hw->ctrl = new_ctrl;
2071 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2073 nfp_net_reta_update(struct rte_eth_dev *dev,
2074 struct rte_eth_rss_reta_entry64 *reta_conf,
2077 uint32_t reta, mask;
2081 struct nfp_net_hw *hw =
2082 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2087 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2088 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2089 "(%d) doesn't match the number hardware can supported "
2090 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2095 * Update Redirection Table. There are 128 8bit-entries which can be
2096 * manage as 32 32bit-entries
2098 for (i = 0; i < reta_size; i += 4) {
2099 /* Handling 4 RSS entries per loop */
2100 idx = i / RTE_RETA_GROUP_SIZE;
2101 shift = i % RTE_RETA_GROUP_SIZE;
2102 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2108 /* If all 4 entries were set, don't need read RETA register */
2110 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2112 for (j = 0; j < 4; j++) {
2113 if (!(mask & (0x1 << j)))
2116 /* Clearing the entry bits */
2117 reta &= ~(0xFF << (8 * j));
2118 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2120 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2123 update = NFP_NET_CFG_UPDATE_RSS;
2125 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2131 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2133 nfp_net_reta_query(struct rte_eth_dev *dev,
2134 struct rte_eth_rss_reta_entry64 *reta_conf,
2140 struct nfp_net_hw *hw;
2142 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2147 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2148 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2149 "(%d) doesn't match the number hardware can supported "
2150 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2155 * Reading Redirection Table. There are 128 8bit-entries which can be
2156 * manage as 32 32bit-entries
2158 for (i = 0; i < reta_size; i += 4) {
2159 /* Handling 4 RSS entries per loop */
2160 idx = i / RTE_RETA_GROUP_SIZE;
2161 shift = i % RTE_RETA_GROUP_SIZE;
2162 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2167 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2168 for (j = 0; j < 4; j++) {
2169 if (!(mask & (0x1 << j)))
2171 reta_conf->reta[shift + j] =
2172 (uint8_t)((reta >> (8 * j)) & 0xF);
2179 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2180 struct rte_eth_rss_conf *rss_conf)
2183 uint32_t cfg_rss_ctrl = 0;
2187 struct nfp_net_hw *hw;
2189 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191 rss_hf = rss_conf->rss_hf;
2193 /* Checking if RSS is enabled */
2194 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2195 if (rss_hf != 0) { /* Enable RSS? */
2196 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2199 return 0; /* Nothing to do */
2202 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2203 RTE_LOG(ERR, PMD, "hash key too long\n");
2207 if (rss_hf & ETH_RSS_IPV4)
2208 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2209 NFP_NET_CFG_RSS_IPV4_TCP |
2210 NFP_NET_CFG_RSS_IPV4_UDP;
2212 if (rss_hf & ETH_RSS_IPV6)
2213 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2214 NFP_NET_CFG_RSS_IPV6_TCP |
2215 NFP_NET_CFG_RSS_IPV6_UDP;
2217 /* configuring where to apply the RSS hash */
2218 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2220 /* Writing the key byte a byte */
2221 for (i = 0; i < rss_conf->rss_key_len; i++) {
2222 memcpy(&key, &rss_conf->rss_key[i], 1);
2223 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2226 /* Writing the key size */
2227 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2229 update = NFP_NET_CFG_UPDATE_RSS;
2231 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2238 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2239 struct rte_eth_rss_conf *rss_conf)
2242 uint32_t cfg_rss_ctrl;
2245 struct nfp_net_hw *hw;
2247 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2249 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2252 rss_hf = rss_conf->rss_hf;
2253 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2255 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2256 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2258 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2259 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2261 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2262 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2264 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2265 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2267 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2268 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2270 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2271 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2273 /* Reading the key size */
2274 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2276 /* Reading the key byte a byte */
2277 for (i = 0; i < rss_conf->rss_key_len; i++) {
2278 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2279 memcpy(&rss_conf->rss_key[i], &key, 1);
2285 /* Initialise and register driver with DPDK Application */
2286 static struct eth_dev_ops nfp_net_eth_dev_ops = {
2287 .dev_configure = nfp_net_configure,
2288 .dev_start = nfp_net_start,
2289 .dev_stop = nfp_net_stop,
2290 .dev_close = nfp_net_close,
2291 .promiscuous_enable = nfp_net_promisc_enable,
2292 .promiscuous_disable = nfp_net_promisc_disable,
2293 .link_update = nfp_net_link_update,
2294 .stats_get = nfp_net_stats_get,
2295 .stats_reset = nfp_net_stats_reset,
2296 .dev_infos_get = nfp_net_infos_get,
2297 .mtu_set = nfp_net_dev_mtu_set,
2298 .vlan_offload_set = nfp_net_vlan_offload_set,
2299 .reta_update = nfp_net_reta_update,
2300 .reta_query = nfp_net_reta_query,
2301 .rss_hash_update = nfp_net_rss_hash_update,
2302 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2303 .rx_queue_setup = nfp_net_rx_queue_setup,
2304 .rx_queue_release = nfp_net_rx_queue_release,
2305 .rx_queue_count = nfp_net_rx_queue_count,
2306 .tx_queue_setup = nfp_net_tx_queue_setup,
2307 .tx_queue_release = nfp_net_tx_queue_release,
2311 nfp_net_init(struct rte_eth_dev *eth_dev)
2313 struct rte_pci_device *pci_dev;
2314 struct nfp_net_hw *hw;
2316 uint32_t tx_bar_off, rx_bar_off;
2320 PMD_INIT_FUNC_TRACE();
2322 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2324 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2325 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2326 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2328 /* For secondary processes, the primary has done all the work */
2329 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2332 pci_dev = eth_dev->pci_dev;
2333 hw->device_id = pci_dev->id.device_id;
2334 hw->vendor_id = pci_dev->id.vendor_id;
2335 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2336 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2338 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2339 pci_dev->id.vendor_id, pci_dev->id.device_id,
2340 pci_dev->addr.domain, pci_dev->addr.bus,
2341 pci_dev->addr.devid, pci_dev->addr.function);
2343 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2344 if (hw->ctrl_bar == NULL) {
2346 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2349 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2350 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2352 /* Work out where in the BAR the queues start. */
2353 switch (pci_dev->id.device_id) {
2354 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2355 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2356 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2357 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2358 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2361 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2365 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2366 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2368 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2369 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2371 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2372 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2374 nfp_net_cfg_queue_setup(hw);
2376 /* Get some of the read-only fields from the config BAR */
2377 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2378 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2379 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2380 hw->mtu = hw->max_mtu;
2382 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2383 hw->rx_offset = NFP_NET_RX_OFFSET;
2385 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2387 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2388 hw->ver, hw->max_mtu);
2389 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2390 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2391 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2392 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2393 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2394 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2395 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2396 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2397 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2398 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2400 pci_dev = eth_dev->pci_dev;
2403 hw->stride_rx = stride;
2404 hw->stride_tx = stride;
2406 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2407 hw->max_rx_queues, hw->max_tx_queues);
2409 /* Allocating memory for mac addr */
2410 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2411 if (eth_dev->data->mac_addrs == NULL) {
2412 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2416 /* Using random mac addresses for VFs */
2417 eth_random_addr(&hw->mac_addr[0]);
2419 /* Copying mac address to DPDK eth_dev struct */
2420 ether_addr_copy(ð_dev->data->mac_addrs[0],
2421 (struct ether_addr *)hw->mac_addr);
2423 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2424 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2425 eth_dev->data->port_id, pci_dev->id.vendor_id,
2426 pci_dev->id.device_id,
2427 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2428 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2430 /* Registering LSC interrupt handler */
2431 rte_intr_callback_register(&pci_dev->intr_handle,
2432 nfp_net_dev_interrupt_handler,
2435 /* enable uio intr after callback register */
2436 rte_intr_enable(&pci_dev->intr_handle);
2438 /* Telling the firmware about the LSC interrupt entry */
2439 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2441 /* Recording current stats counters values */
2442 nfp_net_stats_reset(eth_dev);
2447 static struct rte_pci_id pci_id_nfp_net_map[] = {
2449 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2450 .device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,
2451 .subsystem_vendor_id = PCI_ANY_ID,
2452 .subsystem_device_id = PCI_ANY_ID,
2455 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2456 .device_id = PCI_DEVICE_ID_NFP6000_VF_NIC,
2457 .subsystem_vendor_id = PCI_ANY_ID,
2458 .subsystem_device_id = PCI_ANY_ID,
2465 static struct eth_driver rte_nfp_net_pmd = {
2467 .name = "rte_nfp_net_pmd",
2468 .id_table = pci_id_nfp_net_map,
2469 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2471 .eth_dev_init = nfp_net_init,
2472 .dev_private_size = sizeof(struct nfp_net_adapter),
2476 nfp_net_pmd_init(const char *name __rte_unused,
2477 const char *params __rte_unused)
2479 PMD_INIT_FUNC_TRACE();
2480 PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2481 NFP_NET_PMD_VERSION);
2483 rte_eth_driver_register(&rte_nfp_net_pmd);
2487 static struct rte_driver rte_nfp_net_driver = {
2489 .init = nfp_net_pmd_init,
2492 PMD_REGISTER_DRIVER(rte_nfp_net_driver);
2496 * c-file-style: "Linux"
2497 * indent-tabs-mode: t