drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57 #include <rte_service_component.h>
  58
  59 #include "nfpcore/nfp_cpp.h"
  60 #include "nfpcore/nfp_nffw.h"
  61 #include "nfpcore/nfp_hwinfo.h"
  62 #include "nfpcore/nfp_mip.h"
  63 #include "nfpcore/nfp_rtsym.h"
  64 #include "nfpcore/nfp_nsp.h"
  65
  66 #include "nfp_net_pmd.h"
  67 #include "nfp_net_logs.h"
  68 #include "nfp_net_ctrl.h"
  69
  70 #include <sys/types.h>
  71 #include <sys/socket.h>
  72 #include <sys/un.h>
  73 #include <unistd.h>
  74 #include <stdio.h>
  75 #include <sys/ioctl.h>
  76 #include <errno.h>
  77
  78 /* Prototypes */
  79 static void nfp_net_close(struct rte_eth_dev *dev);
  80 static int nfp_net_configure(struct rte_eth_dev *dev);
  81 static void nfp_net_dev_interrupt_handler(void *param);
  82 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  83 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  84 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  85                               struct rte_eth_dev_info *dev_info);
  86 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  87 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  88 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  89 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  90 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  91 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  92                                        uint16_t queue_idx);
  93 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  94                                   uint16_t nb_pkts);
  95 static void nfp_net_rx_queue_release(void *rxq);
  96 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  97                                   uint16_t nb_desc, unsigned int socket_id,
  98                                   const struct rte_eth_rxconf *rx_conf,
  99                                   struct rte_mempool *mp);
 100 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
 101 static void nfp_net_tx_queue_release(void *txq);
 102 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 103                                   uint16_t nb_desc, unsigned int socket_id,
 104                                   const struct rte_eth_txconf *tx_conf);
 105 static int nfp_net_start(struct rte_eth_dev *dev);
 106 static int nfp_net_stats_get(struct rte_eth_dev *dev,
 107                               struct rte_eth_stats *stats);
 108 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 109 static void nfp_net_stop(struct rte_eth_dev *dev);
 110 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 111                                   uint16_t nb_pkts);
 112
 113 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 114 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 115                                    struct rte_eth_rss_conf *rss_conf);
 116 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 117                     struct rte_eth_rss_reta_entry64 *reta_conf,
 118                     uint16_t reta_size);
 119 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 120                         struct rte_eth_rss_conf *rss_conf);
 121 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 122                              struct ether_addr *mac_addr);
 123
 124 /* The offset of the queue controller queues in the PCIe Target */
 125 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 126
 127 /* Maximum value which can be added to a queue with one transaction */
 128 #define NFP_QCP_MAX_ADD 0x7f
 129
 130 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 131         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 132
 133 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 134 enum nfp_qcp_ptr {
 135         NFP_QCP_READ_PTR = 0,
 136         NFP_QCP_WRITE_PTR
 137 };
 138
 139 /*
 140  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 141  * @q: Base address for queue structure
 142  * @ptr: Add to the Read or Write pointer
 143  * @val: Value to add to the queue pointer
 144  *
 145  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 146  */
 147 static inline void
 148 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 149 {
 150         uint32_t off;
 151
 152         if (ptr == NFP_QCP_READ_PTR)
 153                 off = NFP_QCP_QUEUE_ADD_RPTR;
 154         else
 155                 off = NFP_QCP_QUEUE_ADD_WPTR;
 156
 157         while (val > NFP_QCP_MAX_ADD) {
 158                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 159                 val -= NFP_QCP_MAX_ADD;
 160         }
 161
 162         nn_writel(rte_cpu_to_le_32(val), q + off);
 163 }
 164
 165 /*
 166  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 167  * @q:  Base address for queue structure
 168  * @ptr: Read or Write pointer
 169  */
 170 static inline uint32_t
 171 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 172 {
 173         uint32_t off;
 174         uint32_t val;
 175
 176         if (ptr == NFP_QCP_READ_PTR)
 177                 off = NFP_QCP_QUEUE_STS_LO;
 178         else
 179                 off = NFP_QCP_QUEUE_STS_HI;
 180
 181         val = rte_cpu_to_le_32(nn_readl(q + off));
 182
 183         if (ptr == NFP_QCP_READ_PTR)
 184                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 185         else
 186                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 187 }
 188
 189 /*
 190  * Functions to read/write from/to Config BAR
 191  * Performs any endian conversion necessary.
 192  */
 193 static inline uint8_t
 194 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 195 {
 196         return nn_readb(hw->ctrl_bar + off);
 197 }
 198
 199 static inline void
 200 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 201 {
 202         nn_writeb(val, hw->ctrl_bar + off);
 203 }
 204
 205 static inline uint32_t
 206 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 207 {
 208         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 209 }
 210
 211 static inline void
 212 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 213 {
 214         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 215 }
 216
 217 static inline uint64_t
 218 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 219 {
 220         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 221 }
 222
 223 static inline void
 224 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 225 {
 226         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 227 }
 228
 229 static void
 230 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 231 {
 232         unsigned i;
 233
 234         if (rxq->rxbufs == NULL)
 235                 return;
 236
 237         for (i = 0; i < rxq->rx_count; i++) {
 238                 if (rxq->rxbufs[i].mbuf) {
 239                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 240                         rxq->rxbufs[i].mbuf = NULL;
 241                 }
 242         }
 243 }
 244
 245 static void
 246 nfp_net_rx_queue_release(void *rx_queue)
 247 {
 248         struct nfp_net_rxq *rxq = rx_queue;
 249
 250         if (rxq) {
 251                 nfp_net_rx_queue_release_mbufs(rxq);
 252                 rte_free(rxq->rxbufs);
 253                 rte_free(rxq);
 254         }
 255 }
 256
 257 static void
 258 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 259 {
 260         nfp_net_rx_queue_release_mbufs(rxq);
 261         rxq->rd_p = 0;
 262         rxq->nb_rx_hold = 0;
 263 }
 264
 265 static void
 266 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 267 {
 268         unsigned i;
 269
 270         if (txq->txbufs == NULL)
 271                 return;
 272
 273         for (i = 0; i < txq->tx_count; i++) {
 274                 if (txq->txbufs[i].mbuf) {
 275                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 276                         txq->txbufs[i].mbuf = NULL;
 277                 }
 278         }
 279 }
 280
 281 static void
 282 nfp_net_tx_queue_release(void *tx_queue)
 283 {
 284         struct nfp_net_txq *txq = tx_queue;
 285
 286         if (txq) {
 287                 nfp_net_tx_queue_release_mbufs(txq);
 288                 rte_free(txq->txbufs);
 289                 rte_free(txq);
 290         }
 291 }
 292
 293 static void
 294 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 295 {
 296         nfp_net_tx_queue_release_mbufs(txq);
 297         txq->wr_p = 0;
 298         txq->rd_p = 0;
 299 }
 300
 301 static int
 302 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 303 {
 304         int cnt;
 305         uint32_t new;
 306         struct timespec wait;
 307
 308         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 309                     hw->qcp_cfg);
 310
 311         if (hw->qcp_cfg == NULL)
 312                 rte_panic("Bad configuration queue pointer\n");
 313
 314         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 315
 316         wait.tv_sec = 0;
 317         wait.tv_nsec = 1000000;
 318
 319         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 320
 321         /* Poll update field, waiting for NFP to ack the config */
 322         for (cnt = 0; ; cnt++) {
 323                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 324                 if (new == 0)
 325                         break;
 326                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 327                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 328                         return -1;
 329                 }
 330                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 331                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 332                                           " %dms", update, cnt);
 333                         rte_panic("Exiting\n");
 334                 }
 335                 nanosleep(&wait, 0); /* waiting for a 1ms */
 336         }
 337         PMD_DRV_LOG(DEBUG, "Ack DONE");
 338         return 0;
 339 }
 340
 341 /*
 342  * Reconfigure the NIC
 343  * @nn:    device to reconfigure
 344  * @ctrl:    The value for the ctrl field in the BAR config
 345  * @update:  The value for the update field in the BAR config
 346  *
 347  * Write the update word to the BAR and ping the reconfig queue. Then poll
 348  * until the firmware has acknowledged the update by zeroing the update word.
 349  */
 350 static int
 351 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 352 {
 353         uint32_t err;
 354
 355         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 356                     ctrl, update);
 357
 358         rte_spinlock_lock(&hw->reconfig_lock);
 359
 360         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 361         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 362
 363         rte_wmb();
 364
 365         err = __nfp_net_reconfig(hw, update);
 366
 367         rte_spinlock_unlock(&hw->reconfig_lock);
 368
 369         if (!err)
 370                 return 0;
 371
 372         /*
 373          * Reconfig errors imply situations where they can be handled.
 374          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 375          */
 376         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 377                      ctrl, update);
 378         return -EIO;
 379 }
 380
 381 /*
 382  * Configure an Ethernet device. This function must be invoked first
 383  * before any other function in the Ethernet API. This function can
 384  * also be re-invoked when a device is in the stopped state.
 385  */
 386 static int
 387 nfp_net_configure(struct rte_eth_dev *dev)
 388 {
 389         struct rte_eth_conf *dev_conf;
 390         struct rte_eth_rxmode *rxmode;
 391         struct rte_eth_txmode *txmode;
 392         struct nfp_net_hw *hw;
 393
 394         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 395
 396         /*
 397          * A DPDK app sends info about how many queues to use and how
 398          * those queues need to be configured. This is used by the
 399          * DPDK core and it makes sure no more queues than those
 400          * advertised by the driver are requested. This function is
 401          * called after that internal process
 402          */
 403
 404         PMD_INIT_LOG(DEBUG, "Configure");
 405
 406         dev_conf = &dev->data->dev_conf;
 407         rxmode = &dev_conf->rxmode;
 408         txmode = &dev_conf->txmode;
 409
 410         /* Checking TX mode */
 411         if (txmode->mq_mode) {
 412                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 413                 return -EINVAL;
 414         }
 415
 416         /* Checking RX mode */
 417         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 418             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 419                 PMD_INIT_LOG(INFO, "RSS not supported");
 420                 return -EINVAL;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static void
 427 nfp_net_enable_queues(struct rte_eth_dev *dev)
 428 {
 429         struct nfp_net_hw *hw;
 430         uint64_t enabled_queues = 0;
 431         int i;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         /* Enabling the required TX queues in the device */
 436         for (i = 0; i < dev->data->nb_tx_queues; i++)
 437                 enabled_queues |= (1 << i);
 438
 439         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 440
 441         enabled_queues = 0;
 442
 443         /* Enabling the required RX queues in the device */
 444         for (i = 0; i < dev->data->nb_rx_queues; i++)
 445                 enabled_queues |= (1 << i);
 446
 447         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 448 }
 449
 450 static void
 451 nfp_net_disable_queues(struct rte_eth_dev *dev)
 452 {
 453         struct nfp_net_hw *hw;
 454         uint32_t new_ctrl, update = 0;
 455
 456         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 457
 458         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 459         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 460
 461         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 462         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 463                  NFP_NET_CFG_UPDATE_MSIX;
 464
 465         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 466                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 467
 468         /* If an error when reconfig we avoid to change hw state */
 469         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 470                 return;
 471
 472         hw->ctrl = new_ctrl;
 473 }
 474
 475 static int
 476 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 477 {
 478         int i;
 479
 480         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 481                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 482                         return -1;
 483         }
 484         return 0;
 485 }
 486
 487 static void
 488 nfp_net_params_setup(struct nfp_net_hw *hw)
 489 {
 490         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 491         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 492 }
 493
 494 static void
 495 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 496 {
 497         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 498 }
 499
 500 #define ETH_ADDR_LEN    6
 501
 502 static void
 503 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 504 {
 505         int i;
 506
 507         for (i = 0; i < ETH_ADDR_LEN; i++)
 508                 dst[i] = src[i];
 509 }
 510
 511 static int
 512 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 513 {
 514         struct nfp_eth_table *nfp_eth_table;
 515
 516         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 517         /*
 518          * hw points to port0 private data. We need hw now pointing to
 519          * right port.
 520          */
 521         hw += port;
 522         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 523                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 524
 525         free(nfp_eth_table);
 526         return 0;
 527 }
 528
 529 static void
 530 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 531 {
 532         uint32_t tmp;
 533
 534         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 535         memcpy(&hw->mac_addr[0], &tmp, 4);
 536
 537         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 538         memcpy(&hw->mac_addr[4], &tmp, 2);
 539 }
 540
 541 static void
 542 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 543 {
 544         uint32_t mac0 = *(uint32_t *)mac;
 545         uint16_t mac1;
 546
 547         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 548
 549         mac += 4;
 550         mac1 = *(uint16_t *)mac;
 551         nn_writew(rte_cpu_to_be_16(mac1),
 552                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 553 }
 554
 555 int
 556 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 557 {
 558         struct nfp_net_hw *hw;
 559         uint32_t update, ctrl;
 560
 561         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 563             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 564                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 565                                   " port enabled");
 566                 return -EBUSY;
 567         }
 568
 569         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 570             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 571                 return -EBUSY;
 572
 573         /* Writing new MAC to the specific port BAR address */
 574         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 575
 576         /* Signal the NIC about the change */
 577         update = NFP_NET_CFG_UPDATE_MACADDR;
 578         ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
 579         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 580                 PMD_INIT_LOG(INFO, "MAC address update failed");
 581                 return -EIO;
 582         }
 583         return 0;
 584 }
 585
 586 static int
 587 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 588                            struct rte_intr_handle *intr_handle)
 589 {
 590         struct nfp_net_hw *hw;
 591         int i;
 592
 593         if (!intr_handle->intr_vec) {
 594                 intr_handle->intr_vec =
 595                         rte_zmalloc("intr_vec",
 596                                     dev->data->nb_rx_queues * sizeof(int), 0);
 597                 if (!intr_handle->intr_vec) {
 598                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 599                                      " intr_vec", dev->data->nb_rx_queues);
 600                         return -ENOMEM;
 601                 }
 602         }
 603
 604         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 605
 606         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 607                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 608                 /* UIO just supports one queue and no LSC*/
 609                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 610                 intr_handle->intr_vec[0] = 0;
 611         } else {
 612                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 613                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 614                         /*
 615                          * The first msix vector is reserved for non
 616                          * efd interrupts
 617                         */
 618                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 619                         intr_handle->intr_vec[i] = i + 1;
 620                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 621                                             intr_handle->intr_vec[i]);
 622                 }
 623         }
 624
 625         /* Avoiding TX interrupts */
 626         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 627         return 0;
 628 }
 629
 630 static uint32_t
 631 nfp_check_offloads(struct rte_eth_dev *dev)
 632 {
 633         struct nfp_net_hw *hw;
 634         struct rte_eth_conf *dev_conf;
 635         struct rte_eth_rxmode *rxmode;
 636         struct rte_eth_txmode *txmode;
 637         uint32_t ctrl = 0;
 638
 639         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         dev_conf = &dev->data->dev_conf;
 642         rxmode = &dev_conf->rxmode;
 643         txmode = &dev_conf->txmode;
 644
 645         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 646                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 647                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 648         }
 649
 650         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 651                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 652                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 653         }
 654
 655         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 656                 hw->mtu = rxmode->max_rx_pkt_len;
 657
 658         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 659                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 660
 661         /* L2 broadcast */
 662         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 663                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 664
 665         /* L2 multicast */
 666         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 667                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 668
 669         /* TX checksum offload */
 670         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 671             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 672             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 673                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 674
 675         /* LSO offload */
 676         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 677                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 678                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 679                 else
 680                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 681         }
 682
 683         /* RX gather */
 684         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 685                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 686
 687         return ctrl;
 688 }
 689
 690 static int
 691 nfp_net_start(struct rte_eth_dev *dev)
 692 {
 693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 695         uint32_t new_ctrl, update = 0;
 696         struct nfp_net_hw *hw;
 697         struct rte_eth_conf *dev_conf;
 698         struct rte_eth_rxmode *rxmode;
 699         uint32_t intr_vector;
 700         int ret;
 701
 702         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 703
 704         PMD_INIT_LOG(DEBUG, "Start");
 705
 706         /* Disabling queues just in case... */
 707         nfp_net_disable_queues(dev);
 708
 709         /* Enabling the required queues in the device */
 710         nfp_net_enable_queues(dev);
 711
 712         /* check and configure queue intr-vector mapping */
 713         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 714                 if (hw->pf_multiport_enabled) {
 715                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 716                                           "with NFP multiport PF");
 717                                 return -EINVAL;
 718                 }
 719                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 720                         /*
 721                          * Better not to share LSC with RX interrupts.
 722                          * Unregistering LSC interrupt handler
 723                          */
 724                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 725                                 nfp_net_dev_interrupt_handler, (void *)dev);
 726
 727                         if (dev->data->nb_rx_queues > 1) {
 728                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 729                                              "supports 1 queue with UIO");
 730                                 return -EIO;
 731                         }
 732                 }
 733                 intr_vector = dev->data->nb_rx_queues;
 734                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 735                         return -1;
 736
 737                 nfp_configure_rx_interrupt(dev, intr_handle);
 738                 update = NFP_NET_CFG_UPDATE_MSIX;
 739         }
 740
 741         rte_intr_enable(intr_handle);
 742
 743         new_ctrl = nfp_check_offloads(dev);
 744
 745         /* Writing configuration parameters in the device */
 746         nfp_net_params_setup(hw);
 747
 748         dev_conf = &dev->data->dev_conf;
 749         rxmode = &dev_conf->rxmode;
 750
 751         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 752                 nfp_net_rss_config_default(dev);
 753                 update |= NFP_NET_CFG_UPDATE_RSS;
 754                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 755         }
 756
 757         /* Enable device */
 758         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 759
 760         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 761
 762         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 763                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 764
 765         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 766         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 767                 return -EIO;
 768
 769         /*
 770          * Allocating rte mbuffs for configured rx queues.
 771          * This requires queues being enabled before
 772          */
 773         if (nfp_net_rx_freelist_setup(dev) < 0) {
 774                 ret = -ENOMEM;
 775                 goto error;
 776         }
 777
 778         if (hw->is_pf) {
 779                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 780                         /* Configure the physical port up */
 781                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 782                 else
 783                         nfp_eth_set_configured(dev->process_private,
 784                                                hw->pf_port_idx, 1);
 785         }
 786
 787         hw->ctrl = new_ctrl;
 788
 789         return 0;
 790
 791 error:
 792         /*
 793          * An error returned by this function should mean the app
 794          * exiting and then the system releasing all the memory
 795          * allocated even memory coming from hugepages.
 796          *
 797          * The device could be enabled at this point with some queues
 798          * ready for getting packets. This is true if the call to
 799          * nfp_net_rx_freelist_setup() succeeds for some queues but
 800          * fails for subsequent queues.
 801          *
 802          * This should make the app exiting but better if we tell the
 803          * device first.
 804          */
 805         nfp_net_disable_queues(dev);
 806
 807         return ret;
 808 }
 809
 810 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 811 static void
 812 nfp_net_stop(struct rte_eth_dev *dev)
 813 {
 814         int i;
 815         struct nfp_net_hw *hw;
 816
 817         PMD_INIT_LOG(DEBUG, "Stop");
 818
 819         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 820
 821         nfp_net_disable_queues(dev);
 822
 823         /* Clear queues */
 824         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 825                 nfp_net_reset_tx_queue(
 826                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 827         }
 828
 829         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 830                 nfp_net_reset_rx_queue(
 831                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 832         }
 833
 834         if (hw->is_pf) {
 835                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 836                         /* Configure the physical port down */
 837                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 838                 else
 839                         nfp_eth_set_configured(dev->process_private,
 840                                                hw->pf_port_idx, 0);
 841         }
 842 }
 843
 844 /* Reset and stop device. The device can not be restarted. */
 845 static void
 846 nfp_net_close(struct rte_eth_dev *dev)
 847 {
 848         struct nfp_net_hw *hw;
 849         struct rte_pci_device *pci_dev;
 850         int i;
 851
 852         PMD_INIT_LOG(DEBUG, "Close");
 853
 854         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 855         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 856
 857         /*
 858          * We assume that the DPDK application is stopping all the
 859          * threads/queues before calling the device close function.
 860          */
 861
 862         nfp_net_disable_queues(dev);
 863
 864         /* Clear queues */
 865         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 866                 nfp_net_reset_tx_queue(
 867                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 868         }
 869
 870         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 871                 nfp_net_reset_rx_queue(
 872                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 873         }
 874
 875         rte_intr_disable(&pci_dev->intr_handle);
 876         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 877
 878         /* unregister callback func from eal lib */
 879         rte_intr_callback_unregister(&pci_dev->intr_handle,
 880                                      nfp_net_dev_interrupt_handler,
 881                                      (void *)dev);
 882
 883         /*
 884          * The ixgbe PMD driver disables the pcie master on the
 885          * device. The i40e does not...
 886          */
 887 }
 888
 889 static void
 890 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 891 {
 892         uint32_t new_ctrl, update = 0;
 893         struct nfp_net_hw *hw;
 894
 895         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 896
 897         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 898
 899         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 900                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 901                 return;
 902         }
 903
 904         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 905                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 906                 return;
 907         }
 908
 909         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 910         update = NFP_NET_CFG_UPDATE_GEN;
 911
 912         /*
 913          * DPDK sets promiscuous mode on just after this call assuming
 914          * it can not fail ...
 915          */
 916         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 917                 return;
 918
 919         hw->ctrl = new_ctrl;
 920 }
 921
 922 static void
 923 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 924 {
 925         uint32_t new_ctrl, update = 0;
 926         struct nfp_net_hw *hw;
 927
 928         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929
 930         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 931                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 932                 return;
 933         }
 934
 935         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 936         update = NFP_NET_CFG_UPDATE_GEN;
 937
 938         /*
 939          * DPDK sets promiscuous mode off just before this call
 940          * assuming it can not fail ...
 941          */
 942         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 943                 return;
 944
 945         hw->ctrl = new_ctrl;
 946 }
 947
 948 /*
 949  * return 0 means link status changed, -1 means not changed
 950  *
 951  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 952  * status.
 953  */
 954 static int
 955 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 956 {
 957         struct nfp_net_hw *hw;
 958         struct rte_eth_link link;
 959         uint32_t nn_link_status;
 960         int ret;
 961
 962         static const uint32_t ls_to_ethtool[] = {
 963                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 964                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 965                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 966                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 967                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 968                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 969                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 970                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 971         };
 972
 973         PMD_DRV_LOG(DEBUG, "Link update");
 974
 975         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 976
 977         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 978
 979         memset(&link, 0, sizeof(struct rte_eth_link));
 980
 981         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 982                 link.link_status = ETH_LINK_UP;
 983
 984         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 985
 986         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 987                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 988
 989         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 990                 link.link_speed = ETH_SPEED_NUM_NONE;
 991         else
 992                 link.link_speed = ls_to_ethtool[nn_link_status];
 993
 994         ret = rte_eth_linkstatus_set(dev, &link);
 995         if (ret == 0) {
 996                 if (link.link_status)
 997                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 998                 else
 999                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1000         }
1001         return ret;
1002 }
1003
1004 static int
1005 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1006 {
1007         int i;
1008         struct nfp_net_hw *hw;
1009         struct rte_eth_stats nfp_dev_stats;
1010
1011         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1012
1013         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1014
1015         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1016
1017         /* reading per RX ring stats */
1018         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1019                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1020                         break;
1021
1022                 nfp_dev_stats.q_ipackets[i] =
1023                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1024
1025                 nfp_dev_stats.q_ipackets[i] -=
1026                         hw->eth_stats_base.q_ipackets[i];
1027
1028                 nfp_dev_stats.q_ibytes[i] =
1029                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1030
1031                 nfp_dev_stats.q_ibytes[i] -=
1032                         hw->eth_stats_base.q_ibytes[i];
1033         }
1034
1035         /* reading per TX ring stats */
1036         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1037                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1038                         break;
1039
1040                 nfp_dev_stats.q_opackets[i] =
1041                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1042
1043                 nfp_dev_stats.q_opackets[i] -=
1044                         hw->eth_stats_base.q_opackets[i];
1045
1046                 nfp_dev_stats.q_obytes[i] =
1047                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1048
1049                 nfp_dev_stats.q_obytes[i] -=
1050                         hw->eth_stats_base.q_obytes[i];
1051         }
1052
1053         nfp_dev_stats.ipackets =
1054                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1055
1056         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1057
1058         nfp_dev_stats.ibytes =
1059                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1060
1061         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1062
1063         nfp_dev_stats.opackets =
1064                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1065
1066         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1067
1068         nfp_dev_stats.obytes =
1069                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1070
1071         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1072
1073         /* reading general device stats */
1074         nfp_dev_stats.ierrors =
1075                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1076
1077         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1078
1079         nfp_dev_stats.oerrors =
1080                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1081
1082         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1083
1084         /* RX ring mbuf allocation failures */
1085         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1086
1087         nfp_dev_stats.imissed =
1088                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1089
1090         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1091
1092         if (stats) {
1093                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1094                 return 0;
1095         }
1096         return -EINVAL;
1097 }
1098
1099 static void
1100 nfp_net_stats_reset(struct rte_eth_dev *dev)
1101 {
1102         int i;
1103         struct nfp_net_hw *hw;
1104
1105         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1106
1107         /*
1108          * hw->eth_stats_base records the per counter starting point.
1109          * Lets update it now
1110          */
1111
1112         /* reading per RX ring stats */
1113         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1114                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1115                         break;
1116
1117                 hw->eth_stats_base.q_ipackets[i] =
1118                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1119
1120                 hw->eth_stats_base.q_ibytes[i] =
1121                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1122         }
1123
1124         /* reading per TX ring stats */
1125         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1126                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1127                         break;
1128
1129                 hw->eth_stats_base.q_opackets[i] =
1130                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1131
1132                 hw->eth_stats_base.q_obytes[i] =
1133                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1134         }
1135
1136         hw->eth_stats_base.ipackets =
1137                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1138
1139         hw->eth_stats_base.ibytes =
1140                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1141
1142         hw->eth_stats_base.opackets =
1143                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1144
1145         hw->eth_stats_base.obytes =
1146                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1147
1148         /* reading general device stats */
1149         hw->eth_stats_base.ierrors =
1150                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1151
1152         hw->eth_stats_base.oerrors =
1153                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1154
1155         /* RX ring mbuf allocation failures */
1156         dev->data->rx_mbuf_alloc_failed = 0;
1157
1158         hw->eth_stats_base.imissed =
1159                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1160 }
1161
1162 static void
1163 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1164 {
1165         struct nfp_net_hw *hw;
1166
1167         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168
1169         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1170         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1171         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1172         dev_info->max_rx_pktlen = hw->max_mtu;
1173         /* Next should change when PF support is implemented */
1174         dev_info->max_mac_addrs = 1;
1175
1176         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1177                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1178
1179         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1180                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1181                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1182                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1183
1184         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1185
1186         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1187                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1188
1189         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1190                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1191                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1192                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1193
1194         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1195                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1196
1197         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1198                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1199
1200         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1201                 .rx_thresh = {
1202                         .pthresh = DEFAULT_RX_PTHRESH,
1203                         .hthresh = DEFAULT_RX_HTHRESH,
1204                         .wthresh = DEFAULT_RX_WTHRESH,
1205                 },
1206                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1207                 .rx_drop_en = 0,
1208         };
1209
1210         dev_info->default_txconf = (struct rte_eth_txconf) {
1211                 .tx_thresh = {
1212                         .pthresh = DEFAULT_TX_PTHRESH,
1213                         .hthresh = DEFAULT_TX_HTHRESH,
1214                         .wthresh = DEFAULT_TX_WTHRESH,
1215                 },
1216                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1217                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1218         };
1219
1220         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1221                                            ETH_RSS_NONFRAG_IPV4_TCP |
1222                                            ETH_RSS_NONFRAG_IPV4_UDP |
1223                                            ETH_RSS_IPV6 |
1224                                            ETH_RSS_NONFRAG_IPV6_TCP |
1225                                            ETH_RSS_NONFRAG_IPV6_UDP;
1226
1227         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1228         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1229
1230         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1231                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1232                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1233 }
1234
1235 static const uint32_t *
1236 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1237 {
1238         static const uint32_t ptypes[] = {
1239                 /* refers to nfp_net_set_hash() */
1240                 RTE_PTYPE_INNER_L3_IPV4,
1241                 RTE_PTYPE_INNER_L3_IPV6,
1242                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1243                 RTE_PTYPE_INNER_L4_MASK,
1244                 RTE_PTYPE_UNKNOWN
1245         };
1246
1247         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1248                 return ptypes;
1249         return NULL;
1250 }
1251
1252 static uint32_t
1253 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1254 {
1255         struct nfp_net_rxq *rxq;
1256         struct nfp_net_rx_desc *rxds;
1257         uint32_t idx;
1258         uint32_t count;
1259
1260         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1261
1262         idx = rxq->rd_p;
1263
1264         count = 0;
1265
1266         /*
1267          * Other PMDs are just checking the DD bit in intervals of 4
1268          * descriptors and counting all four if the first has the DD
1269          * bit on. Of course, this is not accurate but can be good for
1270          * performance. But ideally that should be done in descriptors
1271          * chunks belonging to the same cache line
1272          */
1273
1274         while (count < rxq->rx_count) {
1275                 rxds = &rxq->rxds[idx];
1276                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1277                         break;
1278
1279                 count++;
1280                 idx++;
1281
1282                 /* Wrapping? */
1283                 if ((idx) == rxq->rx_count)
1284                         idx = 0;
1285         }
1286
1287         return count;
1288 }
1289
1290 static int
1291 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1292 {
1293         struct rte_pci_device *pci_dev;
1294         struct nfp_net_hw *hw;
1295         int base = 0;
1296
1297         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1299
1300         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1301                 base = 1;
1302
1303         /* Make sure all updates are written before un-masking */
1304         rte_wmb();
1305         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1306                       NFP_NET_CFG_ICR_UNMASKED);
1307         return 0;
1308 }
1309
1310 static int
1311 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1312 {
1313         struct rte_pci_device *pci_dev;
1314         struct nfp_net_hw *hw;
1315         int base = 0;
1316
1317         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1319
1320         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1321                 base = 1;
1322
1323         /* Make sure all updates are written before un-masking */
1324         rte_wmb();
1325         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1326         return 0;
1327 }
1328
1329 static void
1330 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1331 {
1332         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1333         struct rte_eth_link link;
1334
1335         rte_eth_linkstatus_get(dev, &link);
1336         if (link.link_status)
1337                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1338                             dev->data->port_id, link.link_speed,
1339                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1340                             ? "full-duplex" : "half-duplex");
1341         else
1342                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1343                             dev->data->port_id);
1344
1345         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1346                 pci_dev->addr.domain, pci_dev->addr.bus,
1347                 pci_dev->addr.devid, pci_dev->addr.function);
1348 }
1349
1350 /* Interrupt configuration and handling */
1351
1352 /*
1353  * nfp_net_irq_unmask - Unmask an interrupt
1354  *
1355  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1356  * clear the ICR for the entry.
1357  */
1358 static void
1359 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1360 {
1361         struct nfp_net_hw *hw;
1362         struct rte_pci_device *pci_dev;
1363
1364         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1366
1367         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1368                 /* If MSI-X auto-masking is used, clear the entry */
1369                 rte_wmb();
1370                 rte_intr_enable(&pci_dev->intr_handle);
1371         } else {
1372                 /* Make sure all updates are written before un-masking */
1373                 rte_wmb();
1374                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1375                               NFP_NET_CFG_ICR_UNMASKED);
1376         }
1377 }
1378
1379 static void
1380 nfp_net_dev_interrupt_handler(void *param)
1381 {
1382         int64_t timeout;
1383         struct rte_eth_link link;
1384         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1385
1386         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1387
1388         rte_eth_linkstatus_get(dev, &link);
1389
1390         nfp_net_link_update(dev, 0);
1391
1392         /* likely to up */
1393         if (!link.link_status) {
1394                 /* handle it 1 sec later, wait it being stable */
1395                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1396                 /* likely to down */
1397         } else {
1398                 /* handle it 4 sec later, wait it being stable */
1399                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1400         }
1401
1402         if (rte_eal_alarm_set(timeout * 1000,
1403                               nfp_net_dev_interrupt_delayed_handler,
1404                               (void *)dev) < 0) {
1405                 PMD_INIT_LOG(ERR, "Error setting alarm");
1406                 /* Unmasking */
1407                 nfp_net_irq_unmask(dev);
1408         }
1409 }
1410
1411 /*
1412  * Interrupt handler which shall be registered for alarm callback for delayed
1413  * handling specific interrupt to wait for the stable nic state. As the NIC
1414  * interrupt state is not stable for nfp after link is just down, it needs
1415  * to wait 4 seconds to get the stable status.
1416  *
1417  * @param handle   Pointer to interrupt handle.
1418  * @param param    The address of parameter (struct rte_eth_dev *)
1419  *
1420  * @return  void
1421  */
1422 static void
1423 nfp_net_dev_interrupt_delayed_handler(void *param)
1424 {
1425         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1426
1427         nfp_net_link_update(dev, 0);
1428         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1429
1430         nfp_net_dev_link_status_print(dev);
1431
1432         /* Unmasking */
1433         nfp_net_irq_unmask(dev);
1434 }
1435
1436 static int
1437 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1438 {
1439         struct nfp_net_hw *hw;
1440
1441         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442
1443         /* check that mtu is within the allowed range */
1444         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1445                 return -EINVAL;
1446
1447         /* mtu setting is forbidden if port is started */
1448         if (dev->data->dev_started) {
1449                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1450                             dev->data->port_id);
1451                 return -EBUSY;
1452         }
1453
1454         /* switch to jumbo mode if needed */
1455         if ((uint32_t)mtu > ETHER_MAX_LEN)
1456                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1457         else
1458                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1459
1460         /* update max frame size */
1461         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1462
1463         /* writing to configuration space */
1464         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1465
1466         hw->mtu = mtu;
1467
1468         return 0;
1469 }
1470
1471 static int
1472 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1473                        uint16_t queue_idx, uint16_t nb_desc,
1474                        unsigned int socket_id,
1475                        const struct rte_eth_rxconf *rx_conf,
1476                        struct rte_mempool *mp)
1477 {
1478         const struct rte_memzone *tz;
1479         struct nfp_net_rxq *rxq;
1480         struct nfp_net_hw *hw;
1481
1482         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483
1484         PMD_INIT_FUNC_TRACE();
1485
1486         /* Validating number of descriptors */
1487         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1488             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1489             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1490                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1491                 return -EINVAL;
1492         }
1493
1494         /*
1495          * Free memory prior to re-allocation if needed. This is the case after
1496          * calling nfp_net_stop
1497          */
1498         if (dev->data->rx_queues[queue_idx]) {
1499                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1500                 dev->data->rx_queues[queue_idx] = NULL;
1501         }
1502
1503         /* Allocating rx queue data structure */
1504         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1505                                  RTE_CACHE_LINE_SIZE, socket_id);
1506         if (rxq == NULL)
1507                 return -ENOMEM;
1508
1509         /* Hw queues mapping based on firmware confifguration */
1510         rxq->qidx = queue_idx;
1511         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1512         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1513         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1514         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1515
1516         /*
1517          * Tracking mbuf size for detecting a potential mbuf overflow due to
1518          * RX offset
1519          */
1520         rxq->mem_pool = mp;
1521         rxq->mbuf_size = rxq->mem_pool->elt_size;
1522         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1523         hw->flbufsz = rxq->mbuf_size;
1524
1525         rxq->rx_count = nb_desc;
1526         rxq->port_id = dev->data->port_id;
1527         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1528         rxq->drop_en = rx_conf->rx_drop_en;
1529
1530         /*
1531          * Allocate RX ring hardware descriptors. A memzone large enough to
1532          * handle the maximum ring size is allocated in order to allow for
1533          * resizing in later calls to the queue setup function.
1534          */
1535         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1536                                    sizeof(struct nfp_net_rx_desc) *
1537                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1538                                    socket_id);
1539
1540         if (tz == NULL) {
1541                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1542                 nfp_net_rx_queue_release(rxq);
1543                 return -ENOMEM;
1544         }
1545
1546         /* Saving physical and virtual addresses for the RX ring */
1547         rxq->dma = (uint64_t)tz->iova;
1548         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1549
1550         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1551         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1552                                          sizeof(*rxq->rxbufs) * nb_desc,
1553                                          RTE_CACHE_LINE_SIZE, socket_id);
1554         if (rxq->rxbufs == NULL) {
1555                 nfp_net_rx_queue_release(rxq);
1556                 return -ENOMEM;
1557         }
1558
1559         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1560                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1561
1562         nfp_net_reset_rx_queue(rxq);
1563
1564         dev->data->rx_queues[queue_idx] = rxq;
1565         rxq->hw = hw;
1566
1567         /*
1568          * Telling the HW about the physical address of the RX ring and number
1569          * of descriptors in log2 format
1570          */
1571         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1572         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1573
1574         return 0;
1575 }
1576
1577 static int
1578 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1579 {
1580         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1581         uint64_t dma_addr;
1582         unsigned i;
1583
1584         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1585                    rxq->rx_count);
1586
1587         for (i = 0; i < rxq->rx_count; i++) {
1588                 struct nfp_net_rx_desc *rxd;
1589                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1590
1591                 if (mbuf == NULL) {
1592                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1593                                 (unsigned)rxq->qidx);
1594                         return -ENOMEM;
1595                 }
1596
1597                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1598
1599                 rxd = &rxq->rxds[i];
1600                 rxd->fld.dd = 0;
1601                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1602                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1603                 rxe[i].mbuf = mbuf;
1604                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1605         }
1606
1607         /* Make sure all writes are flushed before telling the hardware */
1608         rte_wmb();
1609
1610         /* Not advertising the whole ring as the firmware gets confused if so */
1611         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1612                    rxq->rx_count - 1);
1613
1614         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1615
1616         return 0;
1617 }
1618
1619 static int
1620 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1621                        uint16_t nb_desc, unsigned int socket_id,
1622                        const struct rte_eth_txconf *tx_conf)
1623 {
1624         const struct rte_memzone *tz;
1625         struct nfp_net_txq *txq;
1626         uint16_t tx_free_thresh;
1627         struct nfp_net_hw *hw;
1628
1629         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630
1631         PMD_INIT_FUNC_TRACE();
1632
1633         /* Validating number of descriptors */
1634         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1635             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1636             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1637                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1638                 return -EINVAL;
1639         }
1640
1641         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1642                                     tx_conf->tx_free_thresh :
1643                                     DEFAULT_TX_FREE_THRESH);
1644
1645         if (tx_free_thresh > (nb_desc)) {
1646                 PMD_DRV_LOG(ERR,
1647                         "tx_free_thresh must be less than the number of TX "
1648                         "descriptors. (tx_free_thresh=%u port=%d "
1649                         "queue=%d)", (unsigned int)tx_free_thresh,
1650                         dev->data->port_id, (int)queue_idx);
1651                 return -(EINVAL);
1652         }
1653
1654         /*
1655          * Free memory prior to re-allocation if needed. This is the case after
1656          * calling nfp_net_stop
1657          */
1658         if (dev->data->tx_queues[queue_idx]) {
1659                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1660                            queue_idx);
1661                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1662                 dev->data->tx_queues[queue_idx] = NULL;
1663         }
1664
1665         /* Allocating tx queue data structure */
1666         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1667                                  RTE_CACHE_LINE_SIZE, socket_id);
1668         if (txq == NULL) {
1669                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1670                 return -ENOMEM;
1671         }
1672
1673         /*
1674          * Allocate TX ring hardware descriptors. A memzone large enough to
1675          * handle the maximum ring size is allocated in order to allow for
1676          * resizing in later calls to the queue setup function.
1677          */
1678         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1679                                    sizeof(struct nfp_net_tx_desc) *
1680                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1681                                    socket_id);
1682         if (tz == NULL) {
1683                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1684                 nfp_net_tx_queue_release(txq);
1685                 return -ENOMEM;
1686         }
1687
1688         txq->tx_count = nb_desc;
1689         txq->tx_free_thresh = tx_free_thresh;
1690         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1691         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1692         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1693
1694         /* queue mapping based on firmware configuration */
1695         txq->qidx = queue_idx;
1696         txq->tx_qcidx = queue_idx * hw->stride_tx;
1697         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1698
1699         txq->port_id = dev->data->port_id;
1700
1701         /* Saving physical and virtual addresses for the TX ring */
1702         txq->dma = (uint64_t)tz->iova;
1703         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1704
1705         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1706         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1707                                          sizeof(*txq->txbufs) * nb_desc,
1708                                          RTE_CACHE_LINE_SIZE, socket_id);
1709         if (txq->txbufs == NULL) {
1710                 nfp_net_tx_queue_release(txq);
1711                 return -ENOMEM;
1712         }
1713         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1714                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1715
1716         nfp_net_reset_tx_queue(txq);
1717
1718         dev->data->tx_queues[queue_idx] = txq;
1719         txq->hw = hw;
1720
1721         /*
1722          * Telling the HW about the physical address of the TX ring and number
1723          * of descriptors in log2 format
1724          */
1725         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1726         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1727
1728         return 0;
1729 }
1730
1731 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1732 static inline void
1733 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1734                struct rte_mbuf *mb)
1735 {
1736         uint64_t ol_flags;
1737         struct nfp_net_hw *hw = txq->hw;
1738
1739         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1740                 goto clean_txd;
1741
1742         ol_flags = mb->ol_flags;
1743
1744         if (!(ol_flags & PKT_TX_TCP_SEG))
1745                 goto clean_txd;
1746
1747         txd->l3_offset = mb->l2_len;
1748         txd->l4_offset = mb->l2_len + mb->l3_len;
1749         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1750         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1751         txd->flags = PCIE_DESC_TX_LSO;
1752         return;
1753
1754 clean_txd:
1755         txd->flags = 0;
1756         txd->l3_offset = 0;
1757         txd->l4_offset = 0;
1758         txd->lso_hdrlen = 0;
1759         txd->mss = 0;
1760 }
1761
1762 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1763 static inline void
1764 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1765                  struct rte_mbuf *mb)
1766 {
1767         uint64_t ol_flags;
1768         struct nfp_net_hw *hw = txq->hw;
1769
1770         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1771                 return;
1772
1773         ol_flags = mb->ol_flags;
1774
1775         /* IPv6 does not need checksum */
1776         if (ol_flags & PKT_TX_IP_CKSUM)
1777                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1778
1779         switch (ol_flags & PKT_TX_L4_MASK) {
1780         case PKT_TX_UDP_CKSUM:
1781                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1782                 break;
1783         case PKT_TX_TCP_CKSUM:
1784                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1785                 break;
1786         }
1787
1788         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1789                 txd->flags |= PCIE_DESC_TX_CSUM;
1790 }
1791
1792 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1793 static inline void
1794 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1795                  struct rte_mbuf *mb)
1796 {
1797         struct nfp_net_hw *hw = rxq->hw;
1798
1799         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1800                 return;
1801
1802         /* If IPv4 and IP checksum error, fail */
1803         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1804             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1805                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1806         else
1807                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1808
1809         /* If neither UDP nor TCP return */
1810         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1811             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1812                 return;
1813
1814         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1815                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1816         else
1817                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1818 }
1819
1820 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1821 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1822
1823 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1824
1825 /*
1826  * nfp_net_set_hash - Set mbuf hash data
1827  *
1828  * The RSS hash and hash-type are pre-pended to the packet data.
1829  * Extract and decode it and set the mbuf fields.
1830  */
1831 static inline void
1832 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1833                  struct rte_mbuf *mbuf)
1834 {
1835         struct nfp_net_hw *hw = rxq->hw;
1836         uint8_t *meta_offset;
1837         uint32_t meta_info;
1838         uint32_t hash = 0;
1839         uint32_t hash_type = 0;
1840
1841         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1842                 return;
1843
1844         /* this is true for new firmwares */
1845         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1846             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1847              NFP_DESC_META_LEN(rxd))) {
1848                 /*
1849                  * new metadata api:
1850                  * <----  32 bit  ----->
1851                  * m    field type word
1852                  * e     data field #2
1853                  * t     data field #1
1854                  * a     data field #0
1855                  * ====================
1856                  *    packet data
1857                  *
1858                  * Field type word contains up to 8 4bit field types
1859                  * A 4bit field type refers to a data field word
1860                  * A data field word can have several 4bit field types
1861                  */
1862                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1863                 meta_offset -= NFP_DESC_META_LEN(rxd);
1864                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1865                 meta_offset += 4;
1866                 /* NFP PMD just supports metadata for hashing */
1867                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1868                 case NFP_NET_META_HASH:
1869                         /* next field type is about the hash type */
1870                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1871                         /* hash value is in the data field */
1872                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1873                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1874                         break;
1875                 default:
1876                         /* Unsupported metadata can be a performance issue */
1877                         return;
1878                 }
1879         } else {
1880                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1881                         return;
1882
1883                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1884                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1885         }
1886
1887         mbuf->hash.rss = hash;
1888         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1889
1890         switch (hash_type) {
1891         case NFP_NET_RSS_IPV4:
1892                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1893                 break;
1894         case NFP_NET_RSS_IPV6:
1895                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1896                 break;
1897         case NFP_NET_RSS_IPV6_EX:
1898                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1899                 break;
1900         case NFP_NET_RSS_IPV4_TCP:
1901                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1902                 break;
1903         case NFP_NET_RSS_IPV6_TCP:
1904                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1905                 break;
1906         case NFP_NET_RSS_IPV4_UDP:
1907                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1908                 break;
1909         case NFP_NET_RSS_IPV6_UDP:
1910                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1911                 break;
1912         default:
1913                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1914         }
1915 }
1916
1917 static inline void
1918 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1919 {
1920         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1921 }
1922
1923 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1924
1925 /*
1926  * RX path design:
1927  *
1928  * There are some decissions to take:
1929  * 1) How to check DD RX descriptors bit
1930  * 2) How and when to allocate new mbufs
1931  *
1932  * Current implementation checks just one single DD bit each loop. As each
1933  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1934  * a single cache line instead. Tests with this change have not shown any
1935  * performance improvement but it requires further investigation. For example,
1936  * depending on which descriptor is next, the number of descriptors could be
1937  * less than 8 for just checking those in the same cache line. This implies
1938  * extra work which could be counterproductive by itself. Indeed, last firmware
1939  * changes are just doing this: writing several descriptors with the DD bit
1940  * for saving PCIe bandwidth and DMA operations from the NFP.
1941  *
1942  * Mbuf allocation is done when a new packet is received. Then the descriptor
1943  * is automatically linked with the new mbuf and the old one is given to the
1944  * user. The main drawback with this design is mbuf allocation is heavier than
1945  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1946  * cache point of view it does not seem allocating the mbuf early on as we are
1947  * doing now have any benefit at all. Again, tests with this change have not
1948  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1949  * so looking at the implications of this type of allocation should be studied
1950  * deeply
1951  */
1952
1953 static uint16_t
1954 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1955 {
1956         struct nfp_net_rxq *rxq;
1957         struct nfp_net_rx_desc *rxds;
1958         struct nfp_net_rx_buff *rxb;
1959         struct nfp_net_hw *hw;
1960         struct rte_mbuf *mb;
1961         struct rte_mbuf *new_mb;
1962         uint16_t nb_hold;
1963         uint64_t dma_addr;
1964         int avail;
1965
1966         rxq = rx_queue;
1967         if (unlikely(rxq == NULL)) {
1968                 /*
1969                  * DPDK just checks the queue is lower than max queues
1970                  * enabled. But the queue needs to be configured
1971                  */
1972                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1973                 return -EINVAL;
1974         }
1975
1976         hw = rxq->hw;
1977         avail = 0;
1978         nb_hold = 0;
1979
1980         while (avail < nb_pkts) {
1981                 rxb = &rxq->rxbufs[rxq->rd_p];
1982                 if (unlikely(rxb == NULL)) {
1983                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1984                         break;
1985                 }
1986
1987                 rxds = &rxq->rxds[rxq->rd_p];
1988                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1989                         break;
1990
1991                 /*
1992                  * Memory barrier to ensure that we won't do other
1993                  * reads before the DD bit.
1994                  */
1995                 rte_rmb();
1996
1997                 /*
1998                  * We got a packet. Let's alloc a new mbuff for refilling the
1999                  * free descriptor ring as soon as possible
2000                  */
2001                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2002                 if (unlikely(new_mb == NULL)) {
2003                         RTE_LOG_DP(DEBUG, PMD,
2004                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2005                                 rxq->port_id, (unsigned int)rxq->qidx);
2006                         nfp_net_mbuf_alloc_failed(rxq);
2007                         break;
2008                 }
2009
2010                 nb_hold++;
2011
2012                 /*
2013                  * Grab the mbuff and refill the descriptor with the
2014                  * previously allocated mbuff
2015                  */
2016                 mb = rxb->mbuf;
2017                 rxb->mbuf = new_mb;
2018
2019                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2020                            rxds->rxd.data_len, rxq->mbuf_size);
2021
2022                 /* Size of this segment */
2023                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2024                 /* Size of the whole packet. We just support 1 segment */
2025                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2026
2027                 if (unlikely((mb->data_len + hw->rx_offset) >
2028                              rxq->mbuf_size)) {
2029                         /*
2030                          * This should not happen and the user has the
2031                          * responsibility of avoiding it. But we have
2032                          * to give some info about the error
2033                          */
2034                         RTE_LOG_DP(ERR, PMD,
2035                                 "mbuf overflow likely due to the RX offset.\n"
2036                                 "\t\tYour mbuf size should have extra space for"
2037                                 " RX offset=%u bytes.\n"
2038                                 "\t\tCurrently you just have %u bytes available"
2039                                 " but the received packet is %u bytes long",
2040                                 hw->rx_offset,
2041                                 rxq->mbuf_size - hw->rx_offset,
2042                                 mb->data_len);
2043                         return -EINVAL;
2044                 }
2045
2046                 /* Filling the received mbuff with packet info */
2047                 if (hw->rx_offset)
2048                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2049                 else
2050                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2051                                        NFP_DESC_META_LEN(rxds);
2052
2053                 /* No scatter mode supported */
2054                 mb->nb_segs = 1;
2055                 mb->next = NULL;
2056
2057                 mb->port = rxq->port_id;
2058
2059                 /* Checking the RSS flag */
2060                 nfp_net_set_hash(rxq, rxds, mb);
2061
2062                 /* Checking the checksum flag */
2063                 nfp_net_rx_cksum(rxq, rxds, mb);
2064
2065                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2066                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2067                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2068                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2069                 }
2070
2071                 /* Adding the mbuff to the mbuff array passed by the app */
2072                 rx_pkts[avail++] = mb;
2073
2074                 /* Now resetting and updating the descriptor */
2075                 rxds->vals[0] = 0;
2076                 rxds->vals[1] = 0;
2077                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2078                 rxds->fld.dd = 0;
2079                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2080                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2081
2082                 rxq->rd_p++;
2083                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2084                         rxq->rd_p = 0;
2085         }
2086
2087         if (nb_hold == 0)
2088                 return nb_hold;
2089
2090         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2091                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2092
2093         nb_hold += rxq->nb_rx_hold;
2094
2095         /*
2096          * FL descriptors needs to be written before incrementing the
2097          * FL queue WR pointer
2098          */
2099         rte_wmb();
2100         if (nb_hold > rxq->rx_free_thresh) {
2101                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2102                            rxq->port_id, (unsigned int)rxq->qidx,
2103                            (unsigned)nb_hold, (unsigned)avail);
2104                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2105                 nb_hold = 0;
2106         }
2107         rxq->nb_rx_hold = nb_hold;
2108
2109         return avail;
2110 }
2111
2112 /*
2113  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2114  * status
2115  * @txq: TX queue to work with
2116  * Returns number of descriptors freed
2117  */
2118 int
2119 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2120 {
2121         uint32_t qcp_rd_p;
2122         int todo;
2123
2124         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2125                    " status", txq->qidx);
2126
2127         /* Work out how many packets have been sent */
2128         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2129
2130         if (qcp_rd_p == txq->rd_p) {
2131                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2132                            "packets (%u, %u)", txq->qidx,
2133                            qcp_rd_p, txq->rd_p);
2134                 return 0;
2135         }
2136
2137         if (qcp_rd_p > txq->rd_p)
2138                 todo = qcp_rd_p - txq->rd_p;
2139         else
2140                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2141
2142         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2143                    qcp_rd_p, txq->rd_p, txq->rd_p);
2144
2145         if (todo == 0)
2146                 return todo;
2147
2148         txq->rd_p += todo;
2149         if (unlikely(txq->rd_p >= txq->tx_count))
2150                 txq->rd_p -= txq->tx_count;
2151
2152         return todo;
2153 }
2154
2155 /* Leaving always free descriptors for avoiding wrapping confusion */
2156 static inline
2157 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2158 {
2159         if (txq->wr_p >= txq->rd_p)
2160                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2161         else
2162                 return txq->rd_p - txq->wr_p - 8;
2163 }
2164
2165 /*
2166  * nfp_net_txq_full - Check if the TX queue free descriptors
2167  * is below tx_free_threshold
2168  *
2169  * @txq: TX queue to check
2170  *
2171  * This function uses the host copy* of read/write pointers
2172  */
2173 static inline
2174 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2175 {
2176         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2177 }
2178
2179 static uint16_t
2180 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2181 {
2182         struct nfp_net_txq *txq;
2183         struct nfp_net_hw *hw;
2184         struct nfp_net_tx_desc *txds, txd;
2185         struct rte_mbuf *pkt;
2186         uint64_t dma_addr;
2187         int pkt_size, dma_size;
2188         uint16_t free_descs, issued_descs;
2189         struct rte_mbuf **lmbuf;
2190         int i;
2191
2192         txq = tx_queue;
2193         hw = txq->hw;
2194         txds = &txq->txds[txq->wr_p];
2195
2196         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2197                    txq->qidx, txq->wr_p, nb_pkts);
2198
2199         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2200                 nfp_net_tx_free_bufs(txq);
2201
2202         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2203         if (unlikely(free_descs == 0))
2204                 return 0;
2205
2206         pkt = *tx_pkts;
2207
2208         i = 0;
2209         issued_descs = 0;
2210         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2211                    txq->qidx, nb_pkts);
2212         /* Sending packets */
2213         while ((i < nb_pkts) && free_descs) {
2214                 /* Grabbing the mbuf linked to the current descriptor */
2215                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2216                 /* Warming the cache for releasing the mbuf later on */
2217                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2218
2219                 pkt = *(tx_pkts + i);
2220
2221                 if (unlikely((pkt->nb_segs > 1) &&
2222                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2223                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2224                         rte_panic("Multisegment packet unsupported\n");
2225                 }
2226
2227                 /* Checking if we have enough descriptors */
2228                 if (unlikely(pkt->nb_segs > free_descs))
2229                         goto xmit_end;
2230
2231                 /*
2232                  * Checksum and VLAN flags just in the first descriptor for a
2233                  * multisegment packet, but TSO info needs to be in all of them.
2234                  */
2235                 txd.data_len = pkt->pkt_len;
2236                 nfp_net_tx_tso(txq, &txd, pkt);
2237                 nfp_net_tx_cksum(txq, &txd, pkt);
2238
2239                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2240                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2241                         txd.flags |= PCIE_DESC_TX_VLAN;
2242                         txd.vlan = pkt->vlan_tci;
2243                 }
2244
2245                 /*
2246                  * mbuf data_len is the data in one segment and pkt_len data
2247                  * in the whole packet. When the packet is just one segment,
2248                  * then data_len = pkt_len
2249                  */
2250                 pkt_size = pkt->pkt_len;
2251
2252                 while (pkt) {
2253                         /* Copying TSO, VLAN and cksum info */
2254                         *txds = txd;
2255
2256                         /* Releasing mbuf used by this descriptor previously*/
2257                         if (*lmbuf)
2258                                 rte_pktmbuf_free_seg(*lmbuf);
2259
2260                         /*
2261                          * Linking mbuf with descriptor for being released
2262                          * next time descriptor is used
2263                          */
2264                         *lmbuf = pkt;
2265
2266                         dma_size = pkt->data_len;
2267                         dma_addr = rte_mbuf_data_iova(pkt);
2268                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2269                                    "%" PRIx64 "", dma_addr);
2270
2271                         /* Filling descriptors fields */
2272                         txds->dma_len = dma_size;
2273                         txds->data_len = txd.data_len;
2274                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2275                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2276                         ASSERT(free_descs > 0);
2277                         free_descs--;
2278
2279                         txq->wr_p++;
2280                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2281                                 txq->wr_p = 0;
2282
2283                         pkt_size -= dma_size;
2284
2285                         /*
2286                          * Making the EOP, packets with just one segment
2287                          * the priority
2288                          */
2289                         if (likely(!pkt_size))
2290                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2291                         else
2292                                 txds->offset_eop = 0;
2293
2294                         pkt = pkt->next;
2295                         /* Referencing next free TX descriptor */
2296                         txds = &txq->txds[txq->wr_p];
2297                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2298                         issued_descs++;
2299                 }
2300                 i++;
2301         }
2302
2303 xmit_end:
2304         /* Increment write pointers. Force memory write before we let HW know */
2305         rte_wmb();
2306         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2307
2308         return i;
2309 }
2310
2311 static int
2312 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2313 {
2314         uint32_t new_ctrl, update;
2315         struct nfp_net_hw *hw;
2316         int ret;
2317
2318         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2319         new_ctrl = 0;
2320
2321         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2322             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2323                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2324                         " ETH_VLAN_EXTEND_OFFLOAD");
2325
2326         /* Enable vlan strip if it is not configured yet */
2327         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2328             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2329                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2330
2331         /* Disable vlan strip just if it is configured */
2332         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2333             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2334                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2335
2336         if (new_ctrl == 0)
2337                 return 0;
2338
2339         update = NFP_NET_CFG_UPDATE_GEN;
2340
2341         ret = nfp_net_reconfig(hw, new_ctrl, update);
2342         if (!ret)
2343                 hw->ctrl = new_ctrl;
2344
2345         return ret;
2346 }
2347
2348 static int
2349 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2350                     struct rte_eth_rss_reta_entry64 *reta_conf,
2351                     uint16_t reta_size)
2352 {
2353         uint32_t reta, mask;
2354         int i, j;
2355         int idx, shift;
2356         struct nfp_net_hw *hw =
2357                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358
2359         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2360                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2361                         "(%d) doesn't match the number hardware can supported "
2362                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2363                 return -EINVAL;
2364         }
2365
2366         /*
2367          * Update Redirection Table. There are 128 8bit-entries which can be
2368          * manage as 32 32bit-entries
2369          */
2370         for (i = 0; i < reta_size; i += 4) {
2371                 /* Handling 4 RSS entries per loop */
2372                 idx = i / RTE_RETA_GROUP_SIZE;
2373                 shift = i % RTE_RETA_GROUP_SIZE;
2374                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2375
2376                 if (!mask)
2377                         continue;
2378
2379                 reta = 0;
2380                 /* If all 4 entries were set, don't need read RETA register */
2381                 if (mask != 0xF)
2382                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2383
2384                 for (j = 0; j < 4; j++) {
2385                         if (!(mask & (0x1 << j)))
2386                                 continue;
2387                         if (mask != 0xF)
2388                                 /* Clearing the entry bits */
2389                                 reta &= ~(0xFF << (8 * j));
2390                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2391                 }
2392                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2393                               reta);
2394         }
2395         return 0;
2396 }
2397
2398 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2399 static int
2400 nfp_net_reta_update(struct rte_eth_dev *dev,
2401                     struct rte_eth_rss_reta_entry64 *reta_conf,
2402                     uint16_t reta_size)
2403 {
2404         struct nfp_net_hw *hw =
2405                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         uint32_t update;
2407         int ret;
2408
2409         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2410                 return -EINVAL;
2411
2412         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2413         if (ret != 0)
2414                 return ret;
2415
2416         update = NFP_NET_CFG_UPDATE_RSS;
2417
2418         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2419                 return -EIO;
2420
2421         return 0;
2422 }
2423
2424  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2425 static int
2426 nfp_net_reta_query(struct rte_eth_dev *dev,
2427                    struct rte_eth_rss_reta_entry64 *reta_conf,
2428                    uint16_t reta_size)
2429 {
2430         uint8_t i, j, mask;
2431         int idx, shift;
2432         uint32_t reta;
2433         struct nfp_net_hw *hw;
2434
2435         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436
2437         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2438                 return -EINVAL;
2439
2440         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2441                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2442                         "(%d) doesn't match the number hardware can supported "
2443                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2444                 return -EINVAL;
2445         }
2446
2447         /*
2448          * Reading Redirection Table. There are 128 8bit-entries which can be
2449          * manage as 32 32bit-entries
2450          */
2451         for (i = 0; i < reta_size; i += 4) {
2452                 /* Handling 4 RSS entries per loop */
2453                 idx = i / RTE_RETA_GROUP_SIZE;
2454                 shift = i % RTE_RETA_GROUP_SIZE;
2455                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2456
2457                 if (!mask)
2458                         continue;
2459
2460                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2461                                     shift);
2462                 for (j = 0; j < 4; j++) {
2463                         if (!(mask & (0x1 << j)))
2464                                 continue;
2465                         reta_conf->reta[shift + j] =
2466                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2467                 }
2468         }
2469         return 0;
2470 }
2471
2472 static int
2473 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2474                         struct rte_eth_rss_conf *rss_conf)
2475 {
2476         struct nfp_net_hw *hw;
2477         uint64_t rss_hf;
2478         uint32_t cfg_rss_ctrl = 0;
2479         uint8_t key;
2480         int i;
2481
2482         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483
2484         /* Writing the key byte a byte */
2485         for (i = 0; i < rss_conf->rss_key_len; i++) {
2486                 memcpy(&key, &rss_conf->rss_key[i], 1);
2487                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2488         }
2489
2490         rss_hf = rss_conf->rss_hf;
2491
2492         if (rss_hf & ETH_RSS_IPV4)
2493                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2494
2495         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2496                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2497
2498         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2499                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2500
2501         if (rss_hf & ETH_RSS_IPV6)
2502                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2503
2504         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2505                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2506
2507         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2508                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2509
2510         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2511         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2512
2513         /* configuring where to apply the RSS hash */
2514         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2515
2516         /* Writing the key size */
2517         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2518
2519         return 0;
2520 }
2521
2522 static int
2523 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2524                         struct rte_eth_rss_conf *rss_conf)
2525 {
2526         uint32_t update;
2527         uint64_t rss_hf;
2528         struct nfp_net_hw *hw;
2529
2530         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531
2532         rss_hf = rss_conf->rss_hf;
2533
2534         /* Checking if RSS is enabled */
2535         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2536                 if (rss_hf != 0) { /* Enable RSS? */
2537                         PMD_DRV_LOG(ERR, "RSS unsupported");
2538                         return -EINVAL;
2539                 }
2540                 return 0; /* Nothing to do */
2541         }
2542
2543         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2544                 PMD_DRV_LOG(ERR, "hash key too long");
2545                 return -EINVAL;
2546         }
2547
2548         nfp_net_rss_hash_write(dev, rss_conf);
2549
2550         update = NFP_NET_CFG_UPDATE_RSS;
2551
2552         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2553                 return -EIO;
2554
2555         return 0;
2556 }
2557
2558 static int
2559 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2560                           struct rte_eth_rss_conf *rss_conf)
2561 {
2562         uint64_t rss_hf;
2563         uint32_t cfg_rss_ctrl;
2564         uint8_t key;
2565         int i;
2566         struct nfp_net_hw *hw;
2567
2568         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569
2570         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2571                 return -EINVAL;
2572
2573         rss_hf = rss_conf->rss_hf;
2574         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2575
2576         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2577                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2578
2579         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2580                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2581
2582         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2583                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2584
2585         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2586                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2587
2588         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2589                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2590
2591         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2592                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2593
2594         /* Reading the key size */
2595         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2596
2597         /* Reading the key byte a byte */
2598         for (i = 0; i < rss_conf->rss_key_len; i++) {
2599                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2600                 memcpy(&rss_conf->rss_key[i], &key, 1);
2601         }
2602
2603         return 0;
2604 }
2605
2606 static int
2607 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2608 {
2609         struct rte_eth_conf *dev_conf;
2610         struct rte_eth_rss_conf rss_conf;
2611         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2612         uint16_t rx_queues = dev->data->nb_rx_queues;
2613         uint16_t queue;
2614         int i, j, ret;
2615
2616         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2617                 rx_queues);
2618
2619         nfp_reta_conf[0].mask = ~0x0;
2620         nfp_reta_conf[1].mask = ~0x0;
2621
2622         queue = 0;
2623         for (i = 0; i < 0x40; i += 8) {
2624                 for (j = i; j < (i + 8); j++) {
2625                         nfp_reta_conf[0].reta[j] = queue;
2626                         nfp_reta_conf[1].reta[j] = queue++;
2627                         queue %= rx_queues;
2628                 }
2629         }
2630         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2631         if (ret != 0)
2632                 return ret;
2633
2634         dev_conf = &dev->data->dev_conf;
2635         if (!dev_conf) {
2636                 PMD_DRV_LOG(INFO, "wrong rss conf");
2637                 return -EINVAL;
2638         }
2639         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2640
2641         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2642
2643         return ret;
2644 }
2645
2646
2647 /* Initialise and register driver with DPDK Application */
2648 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2649         .dev_configure          = nfp_net_configure,
2650         .dev_start              = nfp_net_start,
2651         .dev_stop               = nfp_net_stop,
2652         .dev_close              = nfp_net_close,
2653         .promiscuous_enable     = nfp_net_promisc_enable,
2654         .promiscuous_disable    = nfp_net_promisc_disable,
2655         .link_update            = nfp_net_link_update,
2656         .stats_get              = nfp_net_stats_get,
2657         .stats_reset            = nfp_net_stats_reset,
2658         .dev_infos_get          = nfp_net_infos_get,
2659         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2660         .mtu_set                = nfp_net_dev_mtu_set,
2661         .mac_addr_set           = nfp_set_mac_addr,
2662         .vlan_offload_set       = nfp_net_vlan_offload_set,
2663         .reta_update            = nfp_net_reta_update,
2664         .reta_query             = nfp_net_reta_query,
2665         .rss_hash_update        = nfp_net_rss_hash_update,
2666         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2667         .rx_queue_setup         = nfp_net_rx_queue_setup,
2668         .rx_queue_release       = nfp_net_rx_queue_release,
2669         .rx_queue_count         = nfp_net_rx_queue_count,
2670         .tx_queue_setup         = nfp_net_tx_queue_setup,
2671         .tx_queue_release       = nfp_net_tx_queue_release,
2672         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2673         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2674 };
2675
2676 /*
2677  * All eth_dev created got its private data, but before nfp_net_init, that
2678  * private data is referencing private data for all the PF ports. This is due
2679  * to how the vNIC bars are mapped based on first port, so all ports need info
2680  * about port 0 private data. Inside nfp_net_init the private data pointer is
2681  * changed to the right address for each port once the bars have been mapped.
2682  *
2683  * This functions helps to find out which port and therefore which offset
2684  * inside the private data array to use.
2685  */
2686 static int
2687 get_pf_port_number(char *name)
2688 {
2689         char *pf_str = name;
2690         int size = 0;
2691
2692         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2693                 pf_str++;
2694
2695         if (size == 30)
2696                 /*
2697                  * This should not happen at all and it would mean major
2698                  * implementation fault.
2699                  */
2700                 rte_panic("nfp_net: problem with pf device name\n");
2701
2702         /* Expecting _portX with X within [0,7] */
2703         pf_str += 5;
2704
2705         return (int)strtol(pf_str, NULL, 10);
2706 }
2707
2708 static int
2709 nfp_net_init(struct rte_eth_dev *eth_dev)
2710 {
2711         struct rte_pci_device *pci_dev;
2712         struct nfp_net_hw *hw, *hwport0;
2713
2714         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2715         uint32_t start_q;
2716         int stride = 4;
2717         int port = 0;
2718         int err;
2719
2720         PMD_INIT_FUNC_TRACE();
2721
2722         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2723
2724         /* NFP can not handle DMA addresses requiring more than 40 bits */
2725         if (rte_mem_check_dma_mask(40)) {
2726                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2727                                    pci_dev->device.name);
2728                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2729                 return -ENODEV;
2730         };
2731
2732         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2733             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2734                 port = get_pf_port_number(eth_dev->data->name);
2735                 if (port < 0 || port > 7) {
2736                         PMD_DRV_LOG(ERR, "Port value is wrong");
2737                         return -ENODEV;
2738                 }
2739
2740                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2741
2742                 /* This points to port 0 private data */
2743                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2744
2745                 /* This points to the specific port private data */
2746                 hw = &hwport0[port];
2747         } else {
2748                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2749                 hwport0 = 0;
2750         }
2751
2752         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2753         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2754         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2755
2756         /* For secondary processes, the primary has done all the work */
2757         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2758                 return 0;
2759
2760         rte_eth_copy_pci_info(eth_dev, pci_dev);
2761
2762         hw->device_id = pci_dev->id.device_id;
2763         hw->vendor_id = pci_dev->id.vendor_id;
2764         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2765         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2766
2767         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2768                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2769                      pci_dev->addr.domain, pci_dev->addr.bus,
2770                      pci_dev->addr.devid, pci_dev->addr.function);
2771
2772         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2773         if (hw->ctrl_bar == NULL) {
2774                 PMD_DRV_LOG(ERR,
2775                         "hw->ctrl_bar is NULL. BAR0 not configured");
2776                 return -ENODEV;
2777         }
2778
2779         if (hw->is_pf && port == 0) {
2780                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2781                                              hw->total_ports * 32768,
2782                                              &hw->ctrl_area);
2783                 if (!hw->ctrl_bar) {
2784                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2785                         return -EIO;
2786                 }
2787
2788                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2789         }
2790
2791         if (port > 0) {
2792                 if (!hwport0->ctrl_bar)
2793                         return -ENODEV;
2794
2795                 /* address based on port0 offset */
2796                 hw->ctrl_bar = hwport0->ctrl_bar +
2797                                (port * NFP_PF_CSR_SLICE_SIZE);
2798         }
2799
2800         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2801
2802         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2803         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2804
2805         /* Work out where in the BAR the queues start. */
2806         switch (pci_dev->id.device_id) {
2807         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2808         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2809         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2810                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2811                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2812                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2813                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2814                 break;
2815         default:
2816                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2817                 err = -ENODEV;
2818                 goto dev_err_ctrl_map;
2819         }
2820
2821         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2822         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2823
2824         if (hw->is_pf && port == 0) {
2825                 /* configure access to tx/rx vNIC BARs */
2826                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2827                                                       NFP_PCIE_QUEUE(0),
2828                                                       NFP_QCP_QUEUE_AREA_SZ,
2829                                                       &hw->hwqueues_area);
2830
2831                 if (!hwport0->hw_queues) {
2832                         printf("nfp_rtsym_map fails for net.qc");
2833                         err = -EIO;
2834                         goto dev_err_ctrl_map;
2835                 }
2836
2837                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2838                                     hwport0->hw_queues);
2839         }
2840
2841         if (hw->is_pf) {
2842                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2843                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2844                 eth_dev->data->dev_private = hw;
2845         } else {
2846                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2847                              tx_bar_off;
2848                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2849                              rx_bar_off;
2850         }
2851
2852         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2853                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2854
2855         nfp_net_cfg_queue_setup(hw);
2856
2857         /* Get some of the read-only fields from the config BAR */
2858         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2859         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2860         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2861         hw->mtu = ETHER_MTU;
2862
2863         /* VLAN insertion is incompatible with LSOv2 */
2864         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2865                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2866
2867         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2868                 hw->rx_offset = NFP_NET_RX_OFFSET;
2869         else
2870                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2871
2872         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2873                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2874                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2875
2876         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2877                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2878                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2879                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2880                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2881                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2882                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2883                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2884                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2885                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2886                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2887                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2888                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2889                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2890                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2891
2892         hw->ctrl = 0;
2893
2894         hw->stride_rx = stride;
2895         hw->stride_tx = stride;
2896
2897         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2898                      hw->max_rx_queues, hw->max_tx_queues);
2899
2900         /* Initializing spinlock for reconfigs */
2901         rte_spinlock_init(&hw->reconfig_lock);
2902
2903         /* Allocating memory for mac addr */
2904         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2905         if (eth_dev->data->mac_addrs == NULL) {
2906                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2907                 err = -ENOMEM;
2908                 goto dev_err_queues_map;
2909         }
2910
2911         if (hw->is_pf) {
2912                 nfp_net_pf_read_mac(hwport0, port);
2913                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2914         } else {
2915                 nfp_net_vf_read_mac(hw);
2916         }
2917
2918         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2919                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2920                                    port);
2921                 /* Using random mac addresses for VFs */
2922                 eth_random_addr(&hw->mac_addr[0]);
2923                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2924         }
2925
2926         /* Copying mac address to DPDK eth_dev struct */
2927         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2928                         &eth_dev->data->mac_addrs[0]);
2929
2930         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2931                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2932
2933         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2934                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2935                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2936                      pci_dev->id.device_id,
2937                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2938                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2939
2940         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2941                 /* Registering LSC interrupt handler */
2942                 rte_intr_callback_register(&pci_dev->intr_handle,
2943                                            nfp_net_dev_interrupt_handler,
2944                                            (void *)eth_dev);
2945                 /* Telling the firmware about the LSC interrupt entry */
2946                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2947                 /* Recording current stats counters values */
2948                 nfp_net_stats_reset(eth_dev);
2949         }
2950
2951         return 0;
2952
2953 dev_err_queues_map:
2954                 nfp_cpp_area_free(hw->hwqueues_area);
2955 dev_err_ctrl_map:
2956                 nfp_cpp_area_free(hw->ctrl_area);
2957
2958         return err;
2959 }
2960
2961 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
2962
2963 /*
2964  * Serving a write request to NFP from host programs. The request
2965  * sends the write size and the CPP target. The bridge makes use
2966  * of CPP interface handler configured by the PMD setup.
2967  */
2968 static int
2969 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
2970 {
2971         struct nfp_cpp_area *area;
2972         off_t offset, nfp_offset;
2973         uint32_t cpp_id, pos, len;
2974         uint32_t tmpbuf[16];
2975         size_t count, curlen, totlen = 0;
2976         int err = 0;
2977
2978         PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
2979                 sizeof(off_t), sizeof(size_t));
2980
2981         /* Reading the count param */
2982         err = recv(sockfd, &count, sizeof(off_t), 0);
2983         if (err != sizeof(off_t))
2984                 return -EINVAL;
2985
2986         curlen = count;
2987
2988         /* Reading the offset param */
2989         err = recv(sockfd, &offset, sizeof(off_t), 0);
2990         if (err != sizeof(off_t))
2991                 return -EINVAL;
2992
2993         /* Obtain target's CPP ID and offset in target */
2994         cpp_id = (offset >> 40) << 8;
2995         nfp_offset = offset & ((1ull << 40) - 1);
2996
2997         PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
2998                 offset);
2999         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3000                 cpp_id, nfp_offset);
3001
3002         /* Adjust length if not aligned */
3003         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3004             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3005                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3006                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3007         }
3008
3009         while (count > 0) {
3010                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3011                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3012                                                     nfp_offset, curlen);
3013                 if (!area) {
3014                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3015                         return -EIO;
3016                 }
3017
3018                 /* mapping the target */
3019                 err = nfp_cpp_area_acquire(area);
3020                 if (err < 0) {
3021                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3022                         nfp_cpp_area_free(area);
3023                         return -EIO;
3024                 }
3025
3026                 for (pos = 0; pos < curlen; pos += len) {
3027                         len = curlen - pos;
3028                         if (len > sizeof(tmpbuf))
3029                                 len = sizeof(tmpbuf);
3030
3031                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %lu\n", __func__,
3032                                            len, count);
3033                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3034                         if (err != (int)len) {
3035                                 RTE_LOG(ERR, PMD,
3036                                         "%s: error when receiving, %d of %lu\n",
3037                                         __func__, err, count);
3038                                 nfp_cpp_area_release(area);
3039                                 nfp_cpp_area_free(area);
3040                                 return -EIO;
3041                         }
3042                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3043                         if (err < 0) {
3044                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3045                                 nfp_cpp_area_release(area);
3046                                 nfp_cpp_area_free(area);
3047                                 return -EIO;
3048                         }
3049                 }
3050
3051                 nfp_offset += pos;
3052                 totlen += pos;
3053                 nfp_cpp_area_release(area);
3054                 nfp_cpp_area_free(area);
3055
3056                 count -= pos;
3057                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3058                          NFP_CPP_MEMIO_BOUNDARY : count;
3059         }
3060
3061         return 0;
3062 }
3063
3064 /*
3065  * Serving a read request to NFP from host programs. The request
3066  * sends the read size and the CPP target. The bridge makes use
3067  * of CPP interface handler configured by the PMD setup. The read
3068  * data is sent to the requester using the same socket.
3069  */
3070 static int
3071 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3072 {
3073         struct nfp_cpp_area *area;
3074         off_t offset, nfp_offset;
3075         uint32_t cpp_id, pos, len;
3076         uint32_t tmpbuf[16];
3077         size_t count, curlen, totlen = 0;
3078         int err = 0;
3079
3080         PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3081                 sizeof(off_t), sizeof(size_t));
3082
3083         /* Reading the count param */
3084         err = recv(sockfd, &count, sizeof(off_t), 0);
3085         if (err != sizeof(off_t))
3086                 return -EINVAL;
3087
3088         curlen = count;
3089
3090         /* Reading the offset param */
3091         err = recv(sockfd, &offset, sizeof(off_t), 0);
3092         if (err != sizeof(off_t))
3093                 return -EINVAL;
3094
3095         /* Obtain target's CPP ID and offset in target */
3096         cpp_id = (offset >> 40) << 8;
3097         nfp_offset = offset & ((1ull << 40) - 1);
3098
3099         PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3100                            offset);
3101         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3102                            cpp_id, nfp_offset);
3103
3104         /* Adjust length if not aligned */
3105         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3106             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3107                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3108                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3109         }
3110
3111         while (count > 0) {
3112                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3113                                                     nfp_offset, curlen);
3114                 if (!area) {
3115                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3116                         return -EIO;
3117                 }
3118
3119                 err = nfp_cpp_area_acquire(area);
3120                 if (err < 0) {
3121                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3122                         nfp_cpp_area_free(area);
3123                         return -EIO;
3124                 }
3125
3126                 for (pos = 0; pos < curlen; pos += len) {
3127                         len = curlen - pos;
3128                         if (len > sizeof(tmpbuf))
3129                                 len = sizeof(tmpbuf);
3130
3131                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3132                         if (err < 0) {
3133                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3134                                 nfp_cpp_area_release(area);
3135                                 nfp_cpp_area_free(area);
3136                                 return -EIO;
3137                         }
3138                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %lu\n", __func__,
3139                                            len, count);
3140
3141                         err = send(sockfd, tmpbuf, len, 0);
3142                         if (err != (int)len) {
3143                                 RTE_LOG(ERR, PMD,
3144                                         "%s: error when sending: %d of %lu\n",
3145                                         __func__, err, count);
3146                                 nfp_cpp_area_release(area);
3147                                 nfp_cpp_area_free(area);
3148                                 return -EIO;
3149                         }
3150                 }
3151
3152                 nfp_offset += pos;
3153                 totlen += pos;
3154                 nfp_cpp_area_release(area);
3155                 nfp_cpp_area_free(area);
3156
3157                 count -= pos;
3158                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3159                         NFP_CPP_MEMIO_BOUNDARY : count;
3160         }
3161         return 0;
3162 }
3163
3164 #define NFP_IOCTL 'n'
3165 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3166 /*
3167  * Serving a ioctl command from host NFP tools. This usually goes to
3168  * a kernel driver char driver but it is not available when the PF is
3169  * bound to the PMD. Currently just one ioctl command is served and it
3170  * does not require any CPP access at all.
3171  */
3172 static int
3173 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3174 {
3175         uint32_t cmd, ident_size, tmp;
3176         int err;
3177
3178         /* Reading now the IOCTL command */
3179         err = recv(sockfd, &cmd, 4, 0);
3180         if (err != 4) {
3181                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3182                 return -EIO;
3183         }
3184
3185         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3186         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3187                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3188                 return -EINVAL;
3189         }
3190
3191         err = recv(sockfd, &ident_size, 4, 0);
3192         if (err != 4) {
3193                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3194                 return -EIO;
3195         }
3196
3197         tmp = nfp_cpp_model(cpp);
3198
3199         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3200
3201         err = send(sockfd, &tmp, 4, 0);
3202         if (err != 4) {
3203                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3204                 return -EIO;
3205         }
3206
3207         tmp = cpp->interface;
3208
3209         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3210
3211         err = send(sockfd, &tmp, 4, 0);
3212         if (err != 4) {
3213                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3214                 return -EIO;
3215         }
3216
3217         return 0;
3218 }
3219
3220 #define NFP_BRIDGE_OP_READ      20
3221 #define NFP_BRIDGE_OP_WRITE     30
3222 #define NFP_BRIDGE_OP_IOCTL     40
3223
3224 /*
3225  * This is the code to be executed by a service core. The CPP bridge interface
3226  * is based on a unix socket and requests usually received by a kernel char
3227  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3228  * can be executed with a wrapper library and LD_LIBRARY being completely
3229  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3230  * accesses.
3231  */
3232 static int32_t
3233 nfp_cpp_bridge_service_func(void *args)
3234 {
3235         struct sockaddr address;
3236         struct nfp_cpp *cpp = args;
3237         int sockfd, datafd, op, ret;
3238
3239         unlink("/tmp/nfp_cpp");
3240         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3241         if (sockfd < 0) {
3242                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3243                         __func__);
3244                 return -EIO;
3245         }
3246
3247         memset(&address, 0, sizeof(struct sockaddr));
3248
3249         address.sa_family = AF_UNIX;
3250         strcpy(address.sa_data, "/tmp/nfp_cpp");
3251
3252         ret = bind(sockfd, (const struct sockaddr *)&address,
3253                    sizeof(struct sockaddr));
3254         if (ret < 0) {
3255                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3256                                   __func__, errno);
3257                 return ret;
3258         }
3259
3260         ret = listen(sockfd, 20);
3261         if (ret < 0) {
3262                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3263                                   __func__, errno);
3264                 return ret;
3265         }
3266
3267         for (;;) {
3268                 datafd = accept(sockfd, NULL, NULL);
3269                 if (datafd < 0) {
3270                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3271                                           __func__, errno);
3272                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3273                         return -EIO;
3274                 }
3275
3276                 while (1) {
3277                         ret = recv(datafd, &op, 4, 0);
3278                         if (ret <= 0) {
3279                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3280                                                    __func__);
3281                                 break;
3282                         }
3283
3284                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3285
3286                         if (op == NFP_BRIDGE_OP_READ)
3287                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3288
3289                         if (op == NFP_BRIDGE_OP_WRITE)
3290                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3291
3292                         if (op == NFP_BRIDGE_OP_IOCTL)
3293                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3294
3295                         if (op == 0)
3296                                 break;
3297                 }
3298                 close(datafd);
3299         }
3300         close(sockfd);
3301
3302         return 0;
3303 }
3304
3305 static int
3306 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3307                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3308                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3309 {
3310         struct rte_eth_dev *eth_dev;
3311         struct nfp_net_hw *hw = NULL;
3312         char *port_name;
3313         struct rte_service_spec service;
3314         int retval;
3315
3316         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3317         if (!port_name)
3318                 return -ENOMEM;
3319
3320         if (ports > 1)
3321                 sprintf(port_name, "%s_port%d", dev->device.name, port);
3322         else
3323                 sprintf(port_name, "%s", dev->device.name);
3324
3325
3326         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3327                 eth_dev = rte_eth_dev_allocate(port_name);
3328                 if (!eth_dev) {
3329                         rte_free(port_name);
3330                         return -ENODEV;
3331                 }
3332                 if (port == 0) {
3333                         *priv = rte_zmalloc(port_name,
3334                                             sizeof(struct nfp_net_adapter) *
3335                                             ports, RTE_CACHE_LINE_SIZE);
3336                         if (!*priv) {
3337                                 rte_free(port_name);
3338                                 rte_eth_dev_release_port(eth_dev);
3339                                 return -ENOMEM;
3340                         }
3341                 }
3342                 eth_dev->data->dev_private = *priv;
3343
3344                 /*
3345                  * dev_private pointing to port0 dev_private because we need
3346                  * to configure vNIC bars based on port0 at nfp_net_init.
3347                  * Then dev_private is adjusted per port.
3348                  */
3349                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3350                 hw->cpp = cpp;
3351                 hw->hwinfo = hwinfo;
3352                 hw->sym_tbl = sym_tbl;
3353                 hw->pf_port_idx = phys_port;
3354                 hw->is_pf = 1;
3355                 if (ports > 1)
3356                         hw->pf_multiport_enabled = 1;
3357
3358                 hw->total_ports = ports;
3359         } else {
3360                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3361                 if (!eth_dev) {
3362                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3363                                 "ethdev doesn't exist");
3364                         rte_free(port_name);
3365                         return -ENODEV;
3366                 }
3367                 eth_dev->process_private = cpp;
3368         }
3369
3370         eth_dev->device = &dev->device;
3371         rte_eth_copy_pci_info(eth_dev, dev);
3372
3373         retval = nfp_net_init(eth_dev);
3374
3375         if (retval) {
3376                 retval = -ENODEV;
3377                 goto probe_failed;
3378         } else {
3379                 rte_eth_dev_probing_finish(eth_dev);
3380         }
3381
3382         rte_free(port_name);
3383
3384         if (port == 0) {
3385                 /*
3386                  * The rte_service needs to be created just once per PMD.
3387                  * And the cpp handler needs to be linked to the service.
3388                  * Secondary processes will be used for debugging DPDK apps
3389                  * when requiring to use the CPP interface for accessing NFP
3390                  * components. And the cpp handler for secondary processes is
3391                  * available at this point.
3392                  */
3393                 memset(&service, 0, sizeof(struct rte_service_spec));
3394                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3395                 service.callback = nfp_cpp_bridge_service_func;
3396                 service.callback_userdata = (void *)cpp;
3397
3398                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3399
3400                 if (rte_service_component_register(&service,
3401                                                    &hw->nfp_cpp_service_id))
3402                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3403                 else
3404                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3405         }
3406
3407         return retval;
3408
3409 probe_failed:
3410         rte_free(port_name);
3411         /* free ports private data if primary process */
3412         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3413                 rte_free(eth_dev->data->dev_private);
3414
3415         rte_eth_dev_release_port(eth_dev);
3416
3417         return retval;
3418 }
3419
3420 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3421
3422 static int
3423 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3424 {
3425         struct nfp_cpp *cpp = nsp->cpp;
3426         int fw_f;
3427         char *fw_buf;
3428         char fw_name[125];
3429         char serial[40];
3430         struct stat file_stat;
3431         off_t fsize, bytes;
3432
3433         /* Looking for firmware file in order of priority */
3434
3435         /* First try to find a firmware image specific for this device */
3436         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3437                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3438                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3439                 cpp->interface & 0xff);
3440
3441         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3442
3443         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3444         fw_f = open(fw_name, O_RDONLY);
3445         if (fw_f > 0)
3446                 goto read_fw;
3447
3448         /* Then try the PCI name */
3449         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3450
3451         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3452         fw_f = open(fw_name, O_RDONLY);
3453         if (fw_f > 0)
3454                 goto read_fw;
3455
3456         /* Finally try the card type and media */
3457         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3458         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3459         fw_f = open(fw_name, O_RDONLY);
3460         if (fw_f < 0) {
3461                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3462                 return -ENOENT;
3463         }
3464
3465 read_fw:
3466         if (fstat(fw_f, &file_stat) < 0) {
3467                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3468                 close(fw_f);
3469                 return -ENOENT;
3470         }
3471
3472         fsize = file_stat.st_size;
3473         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3474                             fw_name, (uint64_t)fsize);
3475
3476         fw_buf = malloc((size_t)fsize);
3477         if (!fw_buf) {
3478                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3479                 close(fw_f);
3480                 return -ENOMEM;
3481         }
3482         memset(fw_buf, 0, fsize);
3483
3484         bytes = read(fw_f, fw_buf, fsize);
3485         if (bytes != fsize) {
3486                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3487                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3488                                    (uint64_t)bytes, (uint64_t)fsize);
3489                 free(fw_buf);
3490                 close(fw_f);
3491                 return -EIO;
3492         }
3493
3494         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3495         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3496         PMD_DRV_LOG(INFO, "Done");
3497
3498         free(fw_buf);
3499         close(fw_f);
3500
3501         return 0;
3502 }
3503
3504 static int
3505 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3506              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3507 {
3508         struct nfp_nsp *nsp;
3509         const char *nfp_fw_model;
3510         char card_desc[100];
3511         int err = 0;
3512
3513         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3514
3515         if (nfp_fw_model) {
3516                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3517         } else {
3518                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3519                 return -EIO;
3520         }
3521
3522         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3523                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3524                        nfp_eth_table->count);
3525                 return -EIO;
3526         }
3527
3528         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3529                            nfp_eth_table->count);
3530
3531         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3532
3533         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3534                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3535
3536         nsp = nfp_nsp_open(cpp);
3537         if (!nsp) {
3538                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3539                 return -EIO;
3540         }
3541
3542         nfp_nsp_device_soft_reset(nsp);
3543         err = nfp_fw_upload(dev, nsp, card_desc);
3544
3545         nfp_nsp_close(nsp);
3546         return err;
3547 }
3548
3549 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3550                             struct rte_pci_device *dev)
3551 {
3552         struct nfp_cpp *cpp;
3553         struct nfp_hwinfo *hwinfo;
3554         struct nfp_rtsym_table *sym_tbl;
3555         struct nfp_eth_table *nfp_eth_table = NULL;
3556         int total_ports;
3557         void *priv = 0;
3558         int ret = -ENODEV;
3559         int err;
3560         int i;
3561
3562         if (!dev)
3563                 return ret;
3564
3565         /*
3566          * When device bound to UIO, the device could be used, by mistake,
3567          * by two DPDK apps, and the UIO driver does not avoid it. This
3568          * could lead to a serious problem when configuring the NFP CPP
3569          * interface. Here we avoid this telling to the CPP init code to
3570          * use a lock file if UIO is being used.
3571          */
3572         if (dev->kdrv == RTE_KDRV_VFIO)
3573                 cpp = nfp_cpp_from_device_name(dev, 0);
3574         else
3575                 cpp = nfp_cpp_from_device_name(dev, 1);
3576
3577         if (!cpp) {
3578                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3579                 ret = -EIO;
3580                 goto error;
3581         }
3582
3583         hwinfo = nfp_hwinfo_read(cpp);
3584         if (!hwinfo) {
3585                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3586                 return -EIO;
3587         }
3588
3589         nfp_eth_table = nfp_eth_read_ports(cpp);
3590         if (!nfp_eth_table) {
3591                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3592                 return -EIO;
3593         }
3594
3595         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3596                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3597                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3598                         ret = -EIO;
3599                         goto error;
3600                 }
3601         }
3602
3603         /* Now the symbol table should be there */
3604         sym_tbl = nfp_rtsym_table_read(cpp);
3605         if (!sym_tbl) {
3606                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3607                                 " symbol table");
3608                 ret = -EIO;
3609                 goto error;
3610         }
3611
3612         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3613         if (total_ports != (int)nfp_eth_table->count) {
3614                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3615                 ret = -EIO;
3616                 goto error;
3617         }
3618         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3619
3620         if (total_ports <= 0 || total_ports > 8) {
3621                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3622                 ret = -ENODEV;
3623                 goto error;
3624         }
3625
3626         for (i = 0; i < total_ports; i++) {
3627                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3628                                         nfp_eth_table->ports[i].index,
3629                                         sym_tbl, &priv);
3630                 if (ret)
3631                         break;
3632         }
3633
3634 error:
3635         free(nfp_eth_table);
3636         return ret;
3637 }
3638
3639 int nfp_logtype_init;
3640 int nfp_logtype_driver;
3641
3642 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3643         {
3644                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3645                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3646         },
3647         {
3648                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3649                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3650         },
3651         {
3652                 .vendor_id = 0,
3653         },
3654 };
3655
3656 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3657         {
3658                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3659                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3660         },
3661         {
3662                 .vendor_id = 0,
3663         },
3664 };
3665
3666 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3667         struct rte_pci_device *pci_dev)
3668 {
3669         return rte_eth_dev_pci_generic_probe(pci_dev,
3670                 sizeof(struct nfp_net_adapter), nfp_net_init);
3671 }
3672
3673 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3674 {
3675         struct rte_eth_dev *eth_dev;
3676         struct nfp_net_hw *hw, *hwport0;
3677         int port = 0;
3678
3679         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3680         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3681             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3682                 port = get_pf_port_number(eth_dev->data->name);
3683                 /*
3684                  * hotplug is not possible with multiport PF although freeing
3685                  * data structures can be done for first port.
3686                  */
3687                 if (port != 0)
3688                         return -ENOTSUP;
3689                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3690                 hw = &hwport0[port];
3691                 nfp_cpp_area_free(hw->ctrl_area);
3692                 nfp_cpp_area_free(hw->hwqueues_area);
3693                 free(hw->hwinfo);
3694                 free(hw->sym_tbl);
3695                 nfp_cpp_free(hw->cpp);
3696         } else {
3697                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3698         }
3699         /* hotplug is not possible with multiport PF */
3700         if (hw->pf_multiport_enabled)
3701                 return -ENOTSUP;
3702         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3703 }
3704
3705 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3706         .id_table = pci_id_nfp_pf_net_map,
3707         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3708                      RTE_PCI_DRV_IOVA_AS_VA,
3709         .probe = nfp_pf_pci_probe,
3710         .remove = eth_nfp_pci_remove,
3711 };
3712
3713 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3714         .id_table = pci_id_nfp_vf_net_map,
3715         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3716                      RTE_PCI_DRV_IOVA_AS_VA,
3717         .probe = eth_nfp_pci_probe,
3718         .remove = eth_nfp_pci_remove,
3719 };
3720
3721 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3722 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3723 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3724 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3725 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3726 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3727
3728 RTE_INIT(nfp_init_log)
3729 {
3730         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3731         if (nfp_logtype_init >= 0)
3732                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3733         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3734         if (nfp_logtype_driver >= 0)
3735                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3736 }
3737 /*
3738  * Local variables:
3739  * c-file-style: "Linux"
3740  * indent-tabs-mode: t
3741  * End:
3742  */