drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         /* Supporting VLAN insertion by default */
 492         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 493                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 494
 495         if (rxmode->jumbo_frame)
 496                 /* this is handled in rte_eth_dev_configure */
 497
 498         if (rxmode->hw_strip_crc) {
 499                 PMD_INIT_LOG(INFO, "strip CRC not supported");
 500                 return -EINVAL;
 501         }
 502
 503         if (rxmode->enable_scatter) {
 504                 PMD_INIT_LOG(INFO, "Scatter not supported");
 505                 return -EINVAL;
 506         }
 507
 508         if (!new_ctrl)
 509                 return 0;
 510
 511         update |= NFP_NET_CFG_UPDATE_GEN;
 512
 513         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 514         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 515                 return -EIO;
 516
 517         hw->ctrl = new_ctrl;
 518
 519         return 0;
 520 }
 521
 522 static void
 523 nfp_net_enable_queues(struct rte_eth_dev *dev)
 524 {
 525         struct nfp_net_hw *hw;
 526         uint64_t enabled_queues = 0;
 527         int i;
 528
 529         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 530
 531         /* Enabling the required TX queues in the device */
 532         for (i = 0; i < dev->data->nb_tx_queues; i++)
 533                 enabled_queues |= (1 << i);
 534
 535         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 536
 537         enabled_queues = 0;
 538
 539         /* Enabling the required RX queues in the device */
 540         for (i = 0; i < dev->data->nb_rx_queues; i++)
 541                 enabled_queues |= (1 << i);
 542
 543         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 544 }
 545
 546 static void
 547 nfp_net_disable_queues(struct rte_eth_dev *dev)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t new_ctrl, update = 0;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553
 554         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 555         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 556
 557         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 558         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 559                  NFP_NET_CFG_UPDATE_MSIX;
 560
 561         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 562                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 563
 564         /* If an error when reconfig we avoid to change hw state */
 565         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 566                 return;
 567
 568         hw->ctrl = new_ctrl;
 569 }
 570
 571 static int
 572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 573 {
 574         int i;
 575
 576         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 577                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 578                         return -1;
 579         }
 580         return 0;
 581 }
 582
 583 static void
 584 nfp_net_params_setup(struct nfp_net_hw *hw)
 585 {
 586         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 587         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 588 }
 589
 590 static void
 591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 592 {
 593         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 594 }
 595
 596 #define ETH_ADDR_LEN    6
 597
 598 static void
 599 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
 600 {
 601         int i;
 602
 603         for (i = 0; i < ETH_ADDR_LEN; i++)
 604                 dst[ETH_ADDR_LEN - i - 1] = src[i];
 605 }
 606
 607 static int
 608 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 609 {
 610         union eth_table_entry *entry;
 611         int idx, i;
 612
 613         idx = port;
 614         entry = hw->eth_table;
 615
 616         /* Reading NFP ethernet table obtained before */
 617         for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
 618                 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
 619                         /* port not in use */
 620                         entry++;
 621                         continue;
 622                 }
 623                 if (idx == 0)
 624                         break;
 625                 idx--;
 626                 entry++;
 627         }
 628
 629         if (i == NSP_ETH_MAX_COUNT)
 630                 return -EINVAL;
 631
 632         /*
 633          * hw points to port0 private data. We need hw now pointing to
 634          * right port.
 635          */
 636         hw += port;
 637         nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
 638                                  (uint8_t *)&entry->mac_addr);
 639
 640         return 0;
 641 }
 642
 643 static void
 644 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 645 {
 646         uint32_t tmp;
 647
 648         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 649         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 650
 651         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 652         memcpy(&hw->mac_addr[4], &tmp, 2);
 653 }
 654
 655 static void
 656 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 657 {
 658         uint32_t mac0 = *(uint32_t *)mac;
 659         uint16_t mac1;
 660
 661         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 662
 663         mac += 4;
 664         mac1 = *(uint16_t *)mac;
 665         nn_writew(rte_cpu_to_be_16(mac1),
 666                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 667 }
 668
 669 static int
 670 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 671                            struct rte_intr_handle *intr_handle)
 672 {
 673         struct nfp_net_hw *hw;
 674         int i;
 675
 676         if (!intr_handle->intr_vec) {
 677                 intr_handle->intr_vec =
 678                         rte_zmalloc("intr_vec",
 679                                     dev->data->nb_rx_queues * sizeof(int), 0);
 680                 if (!intr_handle->intr_vec) {
 681                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 682                                      " intr_vec", dev->data->nb_rx_queues);
 683                         return -ENOMEM;
 684                 }
 685         }
 686
 687         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 688
 689         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 690                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 691                 /* UIO just supports one queue and no LSC*/
 692                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 693                 intr_handle->intr_vec[0] = 0;
 694         } else {
 695                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 696                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 697                         /*
 698                          * The first msix vector is reserved for non
 699                          * efd interrupts
 700                         */
 701                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 702                         intr_handle->intr_vec[i] = i + 1;
 703                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 704                                             intr_handle->intr_vec[i]);
 705                 }
 706         }
 707
 708         /* Avoiding TX interrupts */
 709         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 710         return 0;
 711 }
 712
 713 static int
 714 nfp_net_start(struct rte_eth_dev *dev)
 715 {
 716         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 717         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 718         uint32_t new_ctrl, update = 0;
 719         struct nfp_net_hw *hw;
 720         uint32_t intr_vector;
 721         int ret;
 722
 723         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 724
 725         PMD_INIT_LOG(DEBUG, "Start");
 726
 727         /* Disabling queues just in case... */
 728         nfp_net_disable_queues(dev);
 729
 730         /* Writing configuration parameters in the device */
 731         nfp_net_params_setup(hw);
 732
 733         /* Enabling the required queues in the device */
 734         nfp_net_enable_queues(dev);
 735
 736         /* check and configure queue intr-vector mapping */
 737         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 738                 if (hw->pf_multiport_enabled) {
 739                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 740                                           "with NFP multiport PF");
 741                                 return -EINVAL;
 742                 }
 743                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 744                         /*
 745                          * Better not to share LSC with RX interrupts.
 746                          * Unregistering LSC interrupt handler
 747                          */
 748                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 749                                 nfp_net_dev_interrupt_handler, (void *)dev);
 750
 751                         if (dev->data->nb_rx_queues > 1) {
 752                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 753                                              "supports 1 queue with UIO");
 754                                 return -EIO;
 755                         }
 756                 }
 757                 intr_vector = dev->data->nb_rx_queues;
 758                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 759                         return -1;
 760
 761                 nfp_configure_rx_interrupt(dev, intr_handle);
 762                 update = NFP_NET_CFG_UPDATE_MSIX;
 763         }
 764
 765         rte_intr_enable(intr_handle);
 766
 767         /* Enable device */
 768         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 769
 770         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 771
 772         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 773                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 774
 775         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 776         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 777                 return -EIO;
 778
 779         /*
 780          * Allocating rte mbuffs for configured rx queues.
 781          * This requires queues being enabled before
 782          */
 783         if (nfp_net_rx_freelist_setup(dev) < 0) {
 784                 ret = -ENOMEM;
 785                 goto error;
 786         }
 787
 788         if (hw->is_pf)
 789                 /* Configure the physical port up */
 790                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 791
 792         hw->ctrl = new_ctrl;
 793
 794         return 0;
 795
 796 error:
 797         /*
 798          * An error returned by this function should mean the app
 799          * exiting and then the system releasing all the memory
 800          * allocated even memory coming from hugepages.
 801          *
 802          * The device could be enabled at this point with some queues
 803          * ready for getting packets. This is true if the call to
 804          * nfp_net_rx_freelist_setup() succeeds for some queues but
 805          * fails for subsequent queues.
 806          *
 807          * This should make the app exiting but better if we tell the
 808          * device first.
 809          */
 810         nfp_net_disable_queues(dev);
 811
 812         return ret;
 813 }
 814
 815 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 816 static void
 817 nfp_net_stop(struct rte_eth_dev *dev)
 818 {
 819         int i;
 820         struct nfp_net_hw *hw;
 821
 822         PMD_INIT_LOG(DEBUG, "Stop");
 823
 824         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 825
 826         nfp_net_disable_queues(dev);
 827
 828         /* Clear queues */
 829         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 830                 nfp_net_reset_tx_queue(
 831                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 832         }
 833
 834         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 835                 nfp_net_reset_rx_queue(
 836                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 837         }
 838
 839         if (hw->is_pf)
 840                 /* Configure the physical port down */
 841                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 842 }
 843
 844 /* Reset and stop device. The device can not be restarted. */
 845 static void
 846 nfp_net_close(struct rte_eth_dev *dev)
 847 {
 848         struct nfp_net_hw *hw;
 849         struct rte_pci_device *pci_dev;
 850         int i;
 851
 852         PMD_INIT_LOG(DEBUG, "Close");
 853
 854         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 855         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 856
 857         /*
 858          * We assume that the DPDK application is stopping all the
 859          * threads/queues before calling the device close function.
 860          */
 861
 862         nfp_net_disable_queues(dev);
 863
 864         /* Clear queues */
 865         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 866                 nfp_net_reset_tx_queue(
 867                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 868         }
 869
 870         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 871                 nfp_net_reset_rx_queue(
 872                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 873         }
 874
 875         rte_intr_disable(&pci_dev->intr_handle);
 876         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 877
 878         /* unregister callback func from eal lib */
 879         rte_intr_callback_unregister(&pci_dev->intr_handle,
 880                                      nfp_net_dev_interrupt_handler,
 881                                      (void *)dev);
 882
 883         /*
 884          * The ixgbe PMD driver disables the pcie master on the
 885          * device. The i40e does not...
 886          */
 887 }
 888
 889 static void
 890 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 891 {
 892         uint32_t new_ctrl, update = 0;
 893         struct nfp_net_hw *hw;
 894
 895         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 896
 897         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 898
 899         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 900                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 901                 return;
 902         }
 903
 904         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 905                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 906                 return;
 907         }
 908
 909         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 910         update = NFP_NET_CFG_UPDATE_GEN;
 911
 912         /*
 913          * DPDK sets promiscuous mode on just after this call assuming
 914          * it can not fail ...
 915          */
 916         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 917                 return;
 918
 919         hw->ctrl = new_ctrl;
 920 }
 921
 922 static void
 923 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 924 {
 925         uint32_t new_ctrl, update = 0;
 926         struct nfp_net_hw *hw;
 927
 928         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929
 930         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 931                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 932                 return;
 933         }
 934
 935         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 936         update = NFP_NET_CFG_UPDATE_GEN;
 937
 938         /*
 939          * DPDK sets promiscuous mode off just before this call
 940          * assuming it can not fail ...
 941          */
 942         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 943                 return;
 944
 945         hw->ctrl = new_ctrl;
 946 }
 947
 948 /*
 949  * return 0 means link status changed, -1 means not changed
 950  *
 951  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 952  * status.
 953  */
 954 static int
 955 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 956 {
 957         struct nfp_net_hw *hw;
 958         struct rte_eth_link link, old;
 959         uint32_t nn_link_status;
 960
 961         static const uint32_t ls_to_ethtool[] = {
 962                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 963                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 964                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 965                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 966                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 967                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 968                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 969                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 970         };
 971
 972         PMD_DRV_LOG(DEBUG, "Link update\n");
 973
 974         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 975
 976         memset(&old, 0, sizeof(old));
 977         nfp_net_dev_atomic_read_link_status(dev, &old);
 978
 979         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 980
 981         memset(&link, 0, sizeof(struct rte_eth_link));
 982
 983         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 984                 link.link_status = ETH_LINK_UP;
 985
 986         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 987
 988         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 989                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 990
 991         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 992                 link.link_speed = ETH_SPEED_NUM_NONE;
 993         else
 994                 link.link_speed = ls_to_ethtool[nn_link_status];
 995
 996         if (old.link_status != link.link_status) {
 997                 nfp_net_dev_atomic_write_link_status(dev, &link);
 998                 if (link.link_status)
 999                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1000                 else
1001                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1002                 return 0;
1003         }
1004
1005         return -1;
1006 }
1007
1008 static void
1009 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1010 {
1011         int i;
1012         struct nfp_net_hw *hw;
1013         struct rte_eth_stats nfp_dev_stats;
1014
1015         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1016
1017         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1018
1019         /* reading per RX ring stats */
1020         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1021                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1022                         break;
1023
1024                 nfp_dev_stats.q_ipackets[i] =
1025                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1026
1027                 nfp_dev_stats.q_ipackets[i] -=
1028                         hw->eth_stats_base.q_ipackets[i];
1029
1030                 nfp_dev_stats.q_ibytes[i] =
1031                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1032
1033                 nfp_dev_stats.q_ibytes[i] -=
1034                         hw->eth_stats_base.q_ibytes[i];
1035         }
1036
1037         /* reading per TX ring stats */
1038         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1039                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1040                         break;
1041
1042                 nfp_dev_stats.q_opackets[i] =
1043                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1044
1045                 nfp_dev_stats.q_opackets[i] -=
1046                         hw->eth_stats_base.q_opackets[i];
1047
1048                 nfp_dev_stats.q_obytes[i] =
1049                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1050
1051                 nfp_dev_stats.q_obytes[i] -=
1052                         hw->eth_stats_base.q_obytes[i];
1053         }
1054
1055         nfp_dev_stats.ipackets =
1056                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1057
1058         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1059
1060         nfp_dev_stats.ibytes =
1061                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1062
1063         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1064
1065         nfp_dev_stats.opackets =
1066                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1067
1068         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1069
1070         nfp_dev_stats.obytes =
1071                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1072
1073         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1074
1075         /* reading general device stats */
1076         nfp_dev_stats.ierrors =
1077                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1078
1079         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1080
1081         nfp_dev_stats.oerrors =
1082                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1083
1084         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1085
1086         /* RX ring mbuf allocation failures */
1087         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1088
1089         nfp_dev_stats.imissed =
1090                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1091
1092         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1093
1094         if (stats)
1095                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1096 }
1097
1098 static void
1099 nfp_net_stats_reset(struct rte_eth_dev *dev)
1100 {
1101         int i;
1102         struct nfp_net_hw *hw;
1103
1104         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105
1106         /*
1107          * hw->eth_stats_base records the per counter starting point.
1108          * Lets update it now
1109          */
1110
1111         /* reading per RX ring stats */
1112         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1113                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1114                         break;
1115
1116                 hw->eth_stats_base.q_ipackets[i] =
1117                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1118
1119                 hw->eth_stats_base.q_ibytes[i] =
1120                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1121         }
1122
1123         /* reading per TX ring stats */
1124         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1125                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1126                         break;
1127
1128                 hw->eth_stats_base.q_opackets[i] =
1129                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1130
1131                 hw->eth_stats_base.q_obytes[i] =
1132                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1133         }
1134
1135         hw->eth_stats_base.ipackets =
1136                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1137
1138         hw->eth_stats_base.ibytes =
1139                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1140
1141         hw->eth_stats_base.opackets =
1142                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1143
1144         hw->eth_stats_base.obytes =
1145                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1146
1147         /* reading general device stats */
1148         hw->eth_stats_base.ierrors =
1149                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1150
1151         hw->eth_stats_base.oerrors =
1152                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1153
1154         /* RX ring mbuf allocation failures */
1155         dev->data->rx_mbuf_alloc_failed = 0;
1156
1157         hw->eth_stats_base.imissed =
1158                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1159 }
1160
1161 static void
1162 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1163 {
1164         struct nfp_net_hw *hw;
1165
1166         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167
1168         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1169         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1170         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1171         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1172         dev_info->max_rx_pktlen = hw->mtu;
1173         /* Next should change when PF support is implemented */
1174         dev_info->max_mac_addrs = 1;
1175
1176         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1177                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1178
1179         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1180                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1181                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1182                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1183
1184         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1185                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1186
1187         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1188                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1189                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1190                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1191
1192         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1193                 .rx_thresh = {
1194                         .pthresh = DEFAULT_RX_PTHRESH,
1195                         .hthresh = DEFAULT_RX_HTHRESH,
1196                         .wthresh = DEFAULT_RX_WTHRESH,
1197                 },
1198                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1199                 .rx_drop_en = 0,
1200         };
1201
1202         dev_info->default_txconf = (struct rte_eth_txconf) {
1203                 .tx_thresh = {
1204                         .pthresh = DEFAULT_TX_PTHRESH,
1205                         .hthresh = DEFAULT_TX_HTHRESH,
1206                         .wthresh = DEFAULT_TX_WTHRESH,
1207                 },
1208                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1209                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1210                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1211                              ETH_TXQ_FLAGS_NOOFFLOADS,
1212         };
1213
1214         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1215                                            ETH_RSS_NONFRAG_IPV4_UDP |
1216                                            ETH_RSS_NONFRAG_IPV6_TCP |
1217                                            ETH_RSS_NONFRAG_IPV6_UDP;
1218
1219         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1220         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1221
1222         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1223                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1224                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1225
1226         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1227                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1228 }
1229
1230 static const uint32_t *
1231 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1232 {
1233         static const uint32_t ptypes[] = {
1234                 /* refers to nfp_net_set_hash() */
1235                 RTE_PTYPE_INNER_L3_IPV4,
1236                 RTE_PTYPE_INNER_L3_IPV6,
1237                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1238                 RTE_PTYPE_INNER_L4_MASK,
1239                 RTE_PTYPE_UNKNOWN
1240         };
1241
1242         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1243                 return ptypes;
1244         return NULL;
1245 }
1246
1247 static uint32_t
1248 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1249 {
1250         struct nfp_net_rxq *rxq;
1251         struct nfp_net_rx_desc *rxds;
1252         uint32_t idx;
1253         uint32_t count;
1254
1255         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1256
1257         idx = rxq->rd_p;
1258
1259         count = 0;
1260
1261         /*
1262          * Other PMDs are just checking the DD bit in intervals of 4
1263          * descriptors and counting all four if the first has the DD
1264          * bit on. Of course, this is not accurate but can be good for
1265          * performance. But ideally that should be done in descriptors
1266          * chunks belonging to the same cache line
1267          */
1268
1269         while (count < rxq->rx_count) {
1270                 rxds = &rxq->rxds[idx];
1271                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1272                         break;
1273
1274                 count++;
1275                 idx++;
1276
1277                 /* Wrapping? */
1278                 if ((idx) == rxq->rx_count)
1279                         idx = 0;
1280         }
1281
1282         return count;
1283 }
1284
1285 static int
1286 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1287 {
1288         struct rte_pci_device *pci_dev;
1289         struct nfp_net_hw *hw;
1290         int base = 0;
1291
1292         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1294
1295         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1296                 base = 1;
1297
1298         /* Make sure all updates are written before un-masking */
1299         rte_wmb();
1300         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1301                       NFP_NET_CFG_ICR_UNMASKED);
1302         return 0;
1303 }
1304
1305 static int
1306 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1307 {
1308         struct rte_pci_device *pci_dev;
1309         struct nfp_net_hw *hw;
1310         int base = 0;
1311
1312         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1314
1315         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1316                 base = 1;
1317
1318         /* Make sure all updates are written before un-masking */
1319         rte_wmb();
1320         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1321         return 0;
1322 }
1323
1324 static void
1325 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1326 {
1327         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1328         struct rte_eth_link link;
1329
1330         memset(&link, 0, sizeof(link));
1331         nfp_net_dev_atomic_read_link_status(dev, &link);
1332         if (link.link_status)
1333                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1334                         (int)(dev->data->port_id), (unsigned)link.link_speed,
1335                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1336                         ? "full-duplex" : "half-duplex");
1337         else
1338                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1339                         (int)(dev->data->port_id));
1340
1341         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1342                 pci_dev->addr.domain, pci_dev->addr.bus,
1343                 pci_dev->addr.devid, pci_dev->addr.function);
1344 }
1345
1346 /* Interrupt configuration and handling */
1347
1348 /*
1349  * nfp_net_irq_unmask - Unmask an interrupt
1350  *
1351  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1352  * clear the ICR for the entry.
1353  */
1354 static void
1355 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1356 {
1357         struct nfp_net_hw *hw;
1358         struct rte_pci_device *pci_dev;
1359
1360         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1362
1363         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1364                 /* If MSI-X auto-masking is used, clear the entry */
1365                 rte_wmb();
1366                 rte_intr_enable(&pci_dev->intr_handle);
1367         } else {
1368                 /* Make sure all updates are written before un-masking */
1369                 rte_wmb();
1370                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1371                               NFP_NET_CFG_ICR_UNMASKED);
1372         }
1373 }
1374
1375 static void
1376 nfp_net_dev_interrupt_handler(void *param)
1377 {
1378         int64_t timeout;
1379         struct rte_eth_link link;
1380         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1381
1382         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1383
1384         /* get the link status */
1385         memset(&link, 0, sizeof(link));
1386         nfp_net_dev_atomic_read_link_status(dev, &link);
1387
1388         nfp_net_link_update(dev, 0);
1389
1390         /* likely to up */
1391         if (!link.link_status) {
1392                 /* handle it 1 sec later, wait it being stable */
1393                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1394                 /* likely to down */
1395         } else {
1396                 /* handle it 4 sec later, wait it being stable */
1397                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1398         }
1399
1400         if (rte_eal_alarm_set(timeout * 1000,
1401                               nfp_net_dev_interrupt_delayed_handler,
1402                               (void *)dev) < 0) {
1403                 RTE_LOG(ERR, PMD, "Error setting alarm");
1404                 /* Unmasking */
1405                 nfp_net_irq_unmask(dev);
1406         }
1407 }
1408
1409 /*
1410  * Interrupt handler which shall be registered for alarm callback for delayed
1411  * handling specific interrupt to wait for the stable nic state. As the NIC
1412  * interrupt state is not stable for nfp after link is just down, it needs
1413  * to wait 4 seconds to get the stable status.
1414  *
1415  * @param handle   Pointer to interrupt handle.
1416  * @param param    The address of parameter (struct rte_eth_dev *)
1417  *
1418  * @return  void
1419  */
1420 static void
1421 nfp_net_dev_interrupt_delayed_handler(void *param)
1422 {
1423         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1424
1425         nfp_net_link_update(dev, 0);
1426         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1427
1428         nfp_net_dev_link_status_print(dev);
1429
1430         /* Unmasking */
1431         nfp_net_irq_unmask(dev);
1432 }
1433
1434 static int
1435 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1436 {
1437         struct nfp_net_hw *hw;
1438
1439         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440
1441         /* check that mtu is within the allowed range */
1442         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1443                 return -EINVAL;
1444
1445         /* switch to jumbo mode if needed */
1446         if ((uint32_t)mtu > ETHER_MAX_LEN)
1447                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1448         else
1449                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1450
1451         /* update max frame size */
1452         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1453
1454         /* writing to configuration space */
1455         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1456
1457         hw->mtu = mtu;
1458
1459         return 0;
1460 }
1461
1462 static int
1463 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1464                        uint16_t queue_idx, uint16_t nb_desc,
1465                        unsigned int socket_id,
1466                        const struct rte_eth_rxconf *rx_conf,
1467                        struct rte_mempool *mp)
1468 {
1469         const struct rte_memzone *tz;
1470         struct nfp_net_rxq *rxq;
1471         struct nfp_net_hw *hw;
1472
1473         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1474
1475         PMD_INIT_FUNC_TRACE();
1476
1477         /* Validating number of descriptors */
1478         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1479             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1480             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1481                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1482                 return -EINVAL;
1483         }
1484
1485         /*
1486          * Free memory prior to re-allocation if needed. This is the case after
1487          * calling nfp_net_stop
1488          */
1489         if (dev->data->rx_queues[queue_idx]) {
1490                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1491                 dev->data->rx_queues[queue_idx] = NULL;
1492         }
1493
1494         /* Allocating rx queue data structure */
1495         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1496                                  RTE_CACHE_LINE_SIZE, socket_id);
1497         if (rxq == NULL)
1498                 return -ENOMEM;
1499
1500         /* Hw queues mapping based on firmware confifguration */
1501         rxq->qidx = queue_idx;
1502         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1503         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1504         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1505         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1506
1507         /*
1508          * Tracking mbuf size for detecting a potential mbuf overflow due to
1509          * RX offset
1510          */
1511         rxq->mem_pool = mp;
1512         rxq->mbuf_size = rxq->mem_pool->elt_size;
1513         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1514         hw->flbufsz = rxq->mbuf_size;
1515
1516         rxq->rx_count = nb_desc;
1517         rxq->port_id = dev->data->port_id;
1518         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1519         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1520                                   : ETHER_CRC_LEN);
1521         rxq->drop_en = rx_conf->rx_drop_en;
1522
1523         /*
1524          * Allocate RX ring hardware descriptors. A memzone large enough to
1525          * handle the maximum ring size is allocated in order to allow for
1526          * resizing in later calls to the queue setup function.
1527          */
1528         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1529                                    sizeof(struct nfp_net_rx_desc) *
1530                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1531                                    socket_id);
1532
1533         if (tz == NULL) {
1534                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1535                 nfp_net_rx_queue_release(rxq);
1536                 return -ENOMEM;
1537         }
1538
1539         /* Saving physical and virtual addresses for the RX ring */
1540         rxq->dma = (uint64_t)tz->phys_addr;
1541         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1542
1543         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1544         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1545                                          sizeof(*rxq->rxbufs) * nb_desc,
1546                                          RTE_CACHE_LINE_SIZE, socket_id);
1547         if (rxq->rxbufs == NULL) {
1548                 nfp_net_rx_queue_release(rxq);
1549                 return -ENOMEM;
1550         }
1551
1552         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1553                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1554
1555         nfp_net_reset_rx_queue(rxq);
1556
1557         dev->data->rx_queues[queue_idx] = rxq;
1558         rxq->hw = hw;
1559
1560         /*
1561          * Telling the HW about the physical address of the RX ring and number
1562          * of descriptors in log2 format
1563          */
1564         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1565         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1566
1567         return 0;
1568 }
1569
1570 static int
1571 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1572 {
1573         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1574         uint64_t dma_addr;
1575         unsigned i;
1576
1577         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1578                    rxq->rx_count);
1579
1580         for (i = 0; i < rxq->rx_count; i++) {
1581                 struct nfp_net_rx_desc *rxd;
1582                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1583
1584                 if (mbuf == NULL) {
1585                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1586                                 (unsigned)rxq->qidx);
1587                         return -ENOMEM;
1588                 }
1589
1590                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1591
1592                 rxd = &rxq->rxds[i];
1593                 rxd->fld.dd = 0;
1594                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1595                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1596                 rxe[i].mbuf = mbuf;
1597                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1598         }
1599
1600         /* Make sure all writes are flushed before telling the hardware */
1601         rte_wmb();
1602
1603         /* Not advertising the whole ring as the firmware gets confused if so */
1604         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1605                    rxq->rx_count - 1);
1606
1607         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1608
1609         return 0;
1610 }
1611
1612 static int
1613 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1614                        uint16_t nb_desc, unsigned int socket_id,
1615                        const struct rte_eth_txconf *tx_conf)
1616 {
1617         const struct rte_memzone *tz;
1618         struct nfp_net_txq *txq;
1619         uint16_t tx_free_thresh;
1620         struct nfp_net_hw *hw;
1621
1622         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623
1624         PMD_INIT_FUNC_TRACE();
1625
1626         /* Validating number of descriptors */
1627         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1628             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1629             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1630                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1631                 return -EINVAL;
1632         }
1633
1634         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1635                                     tx_conf->tx_free_thresh :
1636                                     DEFAULT_TX_FREE_THRESH);
1637
1638         if (tx_free_thresh > (nb_desc)) {
1639                 RTE_LOG(ERR, PMD,
1640                         "tx_free_thresh must be less than the number of TX "
1641                         "descriptors. (tx_free_thresh=%u port=%d "
1642                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1643                         (int)dev->data->port_id, (int)queue_idx);
1644                 return -(EINVAL);
1645         }
1646
1647         /*
1648          * Free memory prior to re-allocation if needed. This is the case after
1649          * calling nfp_net_stop
1650          */
1651         if (dev->data->tx_queues[queue_idx]) {
1652                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1653                            queue_idx);
1654                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1655                 dev->data->tx_queues[queue_idx] = NULL;
1656         }
1657
1658         /* Allocating tx queue data structure */
1659         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1660                                  RTE_CACHE_LINE_SIZE, socket_id);
1661         if (txq == NULL) {
1662                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1663                 return -ENOMEM;
1664         }
1665
1666         /*
1667          * Allocate TX ring hardware descriptors. A memzone large enough to
1668          * handle the maximum ring size is allocated in order to allow for
1669          * resizing in later calls to the queue setup function.
1670          */
1671         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1672                                    sizeof(struct nfp_net_tx_desc) *
1673                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1674                                    socket_id);
1675         if (tz == NULL) {
1676                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1677                 nfp_net_tx_queue_release(txq);
1678                 return -ENOMEM;
1679         }
1680
1681         txq->tx_count = nb_desc;
1682         txq->tx_free_thresh = tx_free_thresh;
1683         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1684         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1685         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1686
1687         /* queue mapping based on firmware configuration */
1688         txq->qidx = queue_idx;
1689         txq->tx_qcidx = queue_idx * hw->stride_tx;
1690         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1691
1692         txq->port_id = dev->data->port_id;
1693         txq->txq_flags = tx_conf->txq_flags;
1694
1695         /* Saving physical and virtual addresses for the TX ring */
1696         txq->dma = (uint64_t)tz->phys_addr;
1697         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1698
1699         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1700         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1701                                          sizeof(*txq->txbufs) * nb_desc,
1702                                          RTE_CACHE_LINE_SIZE, socket_id);
1703         if (txq->txbufs == NULL) {
1704                 nfp_net_tx_queue_release(txq);
1705                 return -ENOMEM;
1706         }
1707         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1708                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1709
1710         nfp_net_reset_tx_queue(txq);
1711
1712         dev->data->tx_queues[queue_idx] = txq;
1713         txq->hw = hw;
1714
1715         /*
1716          * Telling the HW about the physical address of the TX ring and number
1717          * of descriptors in log2 format
1718          */
1719         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1720         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1721
1722         return 0;
1723 }
1724
1725 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1726 static inline void
1727 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1728                struct rte_mbuf *mb)
1729 {
1730         uint64_t ol_flags;
1731         struct nfp_net_hw *hw = txq->hw;
1732
1733         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1734                 goto clean_txd;
1735
1736         ol_flags = mb->ol_flags;
1737
1738         if (!(ol_flags & PKT_TX_TCP_SEG))
1739                 goto clean_txd;
1740
1741         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1742         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1743         txd->flags = PCIE_DESC_TX_LSO;
1744         return;
1745
1746 clean_txd:
1747         txd->flags = 0;
1748         txd->l4_offset = 0;
1749         txd->lso = 0;
1750 }
1751
1752 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1753 static inline void
1754 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1755                  struct rte_mbuf *mb)
1756 {
1757         uint64_t ol_flags;
1758         struct nfp_net_hw *hw = txq->hw;
1759
1760         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1761                 return;
1762
1763         ol_flags = mb->ol_flags;
1764
1765         /* IPv6 does not need checksum */
1766         if (ol_flags & PKT_TX_IP_CKSUM)
1767                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1768
1769         switch (ol_flags & PKT_TX_L4_MASK) {
1770         case PKT_TX_UDP_CKSUM:
1771                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1772                 break;
1773         case PKT_TX_TCP_CKSUM:
1774                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1775                 break;
1776         }
1777
1778         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1779                 txd->flags |= PCIE_DESC_TX_CSUM;
1780 }
1781
1782 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1783 static inline void
1784 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1785                  struct rte_mbuf *mb)
1786 {
1787         struct nfp_net_hw *hw = rxq->hw;
1788
1789         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1790                 return;
1791
1792         /* If IPv4 and IP checksum error, fail */
1793         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1794             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1795                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1796
1797         /* If neither UDP nor TCP return */
1798         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1799             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1800                 return;
1801
1802         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1803             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1804                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1805
1806         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1807             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1808                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1809 }
1810
1811 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1812 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1813
1814 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1815
1816 /*
1817  * nfp_net_set_hash - Set mbuf hash data
1818  *
1819  * The RSS hash and hash-type are pre-pended to the packet data.
1820  * Extract and decode it and set the mbuf fields.
1821  */
1822 static inline void
1823 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1824                  struct rte_mbuf *mbuf)
1825 {
1826         struct nfp_net_hw *hw = rxq->hw;
1827         uint8_t *meta_offset;
1828         uint32_t meta_info;
1829         uint32_t hash = 0;
1830         uint32_t hash_type = 0;
1831
1832         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1833                 return;
1834
1835         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1836                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1837                         return;
1838
1839                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1840                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1841
1842         } else if (NFP_DESC_META_LEN(rxd)) {
1843                 /*
1844                  * new metadata api:
1845                  * <----  32 bit  ----->
1846                  * m    field type word
1847                  * e     data field #2
1848                  * t     data field #1
1849                  * a     data field #0
1850                  * ====================
1851                  *    packet data
1852                  *
1853                  * Field type word contains up to 8 4bit field types
1854                  * A 4bit field type refers to a data field word
1855                  * A data field word can have several 4bit field types
1856                  */
1857                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1858                 meta_offset -= NFP_DESC_META_LEN(rxd);
1859                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1860                 meta_offset += 4;
1861                 /* NFP PMD just supports metadata for hashing */
1862                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1863                 case NFP_NET_META_HASH:
1864                         /* next field type is about the hash type */
1865                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1866                         /* hash value is in the data field */
1867                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1868                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1869                         break;
1870                 default:
1871                         /* Unsupported metadata can be a performance issue */
1872                         return;
1873                 }
1874         } else {
1875                 return;
1876         }
1877
1878         mbuf->hash.rss = hash;
1879         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1880
1881         switch (hash_type) {
1882         case NFP_NET_RSS_IPV4:
1883                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1884                 break;
1885         case NFP_NET_RSS_IPV6:
1886                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1887                 break;
1888         case NFP_NET_RSS_IPV6_EX:
1889                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1890                 break;
1891         default:
1892                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1893         }
1894 }
1895
1896 static inline void
1897 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1898 {
1899         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1900 }
1901
1902 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1903
1904 /*
1905  * RX path design:
1906  *
1907  * There are some decissions to take:
1908  * 1) How to check DD RX descriptors bit
1909  * 2) How and when to allocate new mbufs
1910  *
1911  * Current implementation checks just one single DD bit each loop. As each
1912  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1913  * a single cache line instead. Tests with this change have not shown any
1914  * performance improvement but it requires further investigation. For example,
1915  * depending on which descriptor is next, the number of descriptors could be
1916  * less than 8 for just checking those in the same cache line. This implies
1917  * extra work which could be counterproductive by itself. Indeed, last firmware
1918  * changes are just doing this: writing several descriptors with the DD bit
1919  * for saving PCIe bandwidth and DMA operations from the NFP.
1920  *
1921  * Mbuf allocation is done when a new packet is received. Then the descriptor
1922  * is automatically linked with the new mbuf and the old one is given to the
1923  * user. The main drawback with this design is mbuf allocation is heavier than
1924  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1925  * cache point of view it does not seem allocating the mbuf early on as we are
1926  * doing now have any benefit at all. Again, tests with this change have not
1927  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1928  * so looking at the implications of this type of allocation should be studied
1929  * deeply
1930  */
1931
1932 static uint16_t
1933 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1934 {
1935         struct nfp_net_rxq *rxq;
1936         struct nfp_net_rx_desc *rxds;
1937         struct nfp_net_rx_buff *rxb;
1938         struct nfp_net_hw *hw;
1939         struct rte_mbuf *mb;
1940         struct rte_mbuf *new_mb;
1941         uint16_t nb_hold;
1942         uint64_t dma_addr;
1943         int avail;
1944
1945         rxq = rx_queue;
1946         if (unlikely(rxq == NULL)) {
1947                 /*
1948                  * DPDK just checks the queue is lower than max queues
1949                  * enabled. But the queue needs to be configured
1950                  */
1951                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1952                 return -EINVAL;
1953         }
1954
1955         hw = rxq->hw;
1956         avail = 0;
1957         nb_hold = 0;
1958
1959         while (avail < nb_pkts) {
1960                 rxb = &rxq->rxbufs[rxq->rd_p];
1961                 if (unlikely(rxb == NULL)) {
1962                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1963                         break;
1964                 }
1965
1966                 /*
1967                  * Memory barrier to ensure that we won't do other
1968                  * reads before the DD bit.
1969                  */
1970                 rte_rmb();
1971
1972                 rxds = &rxq->rxds[rxq->rd_p];
1973                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1974                         break;
1975
1976                 /*
1977                  * We got a packet. Let's alloc a new mbuff for refilling the
1978                  * free descriptor ring as soon as possible
1979                  */
1980                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1981                 if (unlikely(new_mb == NULL)) {
1982                         RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1983                                 "queue_id=%u\n", (unsigned)rxq->port_id,
1984                                 (unsigned)rxq->qidx);
1985                         nfp_net_mbuf_alloc_failed(rxq);
1986                         break;
1987                 }
1988
1989                 nb_hold++;
1990
1991                 /*
1992                  * Grab the mbuff and refill the descriptor with the
1993                  * previously allocated mbuff
1994                  */
1995                 mb = rxb->mbuf;
1996                 rxb->mbuf = new_mb;
1997
1998                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1999                            rxds->rxd.data_len, rxq->mbuf_size);
2000
2001                 /* Size of this segment */
2002                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2003                 /* Size of the whole packet. We just support 1 segment */
2004                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2005
2006                 if (unlikely((mb->data_len + hw->rx_offset) >
2007                              rxq->mbuf_size)) {
2008                         /*
2009                          * This should not happen and the user has the
2010                          * responsibility of avoiding it. But we have
2011                          * to give some info about the error
2012                          */
2013                         RTE_LOG_DP(ERR, PMD,
2014                                 "mbuf overflow likely due to the RX offset.\n"
2015                                 "\t\tYour mbuf size should have extra space for"
2016                                 " RX offset=%u bytes.\n"
2017                                 "\t\tCurrently you just have %u bytes available"
2018                                 " but the received packet is %u bytes long",
2019                                 hw->rx_offset,
2020                                 rxq->mbuf_size - hw->rx_offset,
2021                                 mb->data_len);
2022                         return -EINVAL;
2023                 }
2024
2025                 /* Filling the received mbuff with packet info */
2026                 if (hw->rx_offset)
2027                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2028                 else
2029                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2030                                        NFP_DESC_META_LEN(rxds);
2031
2032                 /* No scatter mode supported */
2033                 mb->nb_segs = 1;
2034                 mb->next = NULL;
2035
2036                 /* Checking the RSS flag */
2037                 nfp_net_set_hash(rxq, rxds, mb);
2038
2039                 /* Checking the checksum flag */
2040                 nfp_net_rx_cksum(rxq, rxds, mb);
2041
2042                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2043                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2044                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2045                         mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
2046                 }
2047
2048                 /* Adding the mbuff to the mbuff array passed by the app */
2049                 rx_pkts[avail++] = mb;
2050
2051                 /* Now resetting and updating the descriptor */
2052                 rxds->vals[0] = 0;
2053                 rxds->vals[1] = 0;
2054                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2055                 rxds->fld.dd = 0;
2056                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2057                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2058
2059                 rxq->rd_p++;
2060                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2061                         rxq->rd_p = 0;
2062         }
2063
2064         if (nb_hold == 0)
2065                 return nb_hold;
2066
2067         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2068                    (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
2069
2070         nb_hold += rxq->nb_rx_hold;
2071
2072         /*
2073          * FL descriptors needs to be written before incrementing the
2074          * FL queue WR pointer
2075          */
2076         rte_wmb();
2077         if (nb_hold > rxq->rx_free_thresh) {
2078                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2079                            (unsigned)rxq->port_id, (unsigned)rxq->qidx,
2080                            (unsigned)nb_hold, (unsigned)avail);
2081                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2082                 nb_hold = 0;
2083         }
2084         rxq->nb_rx_hold = nb_hold;
2085
2086         return avail;
2087 }
2088
2089 /*
2090  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2091  * status
2092  * @txq: TX queue to work with
2093  * Returns number of descriptors freed
2094  */
2095 int
2096 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2097 {
2098         uint32_t qcp_rd_p;
2099         int todo;
2100
2101         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2102                    " status\n", txq->qidx);
2103
2104         /* Work out how many packets have been sent */
2105         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2106
2107         if (qcp_rd_p == txq->rd_p) {
2108                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2109                            "packets (%u, %u)\n", txq->qidx,
2110                            qcp_rd_p, txq->rd_p);
2111                 return 0;
2112         }
2113
2114         if (qcp_rd_p > txq->rd_p)
2115                 todo = qcp_rd_p - txq->rd_p;
2116         else
2117                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2118
2119         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2120                    qcp_rd_p, txq->rd_p, txq->rd_p);
2121
2122         if (todo == 0)
2123                 return todo;
2124
2125         txq->rd_p += todo;
2126         if (unlikely(txq->rd_p >= txq->tx_count))
2127                 txq->rd_p -= txq->tx_count;
2128
2129         return todo;
2130 }
2131
2132 /* Leaving always free descriptors for avoiding wrapping confusion */
2133 static inline
2134 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2135 {
2136         if (txq->wr_p >= txq->rd_p)
2137                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2138         else
2139                 return txq->rd_p - txq->wr_p - 8;
2140 }
2141
2142 /*
2143  * nfp_net_txq_full - Check if the TX queue free descriptors
2144  * is below tx_free_threshold
2145  *
2146  * @txq: TX queue to check
2147  *
2148  * This function uses the host copy* of read/write pointers
2149  */
2150 static inline
2151 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2152 {
2153         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2154 }
2155
2156 static uint16_t
2157 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2158 {
2159         struct nfp_net_txq *txq;
2160         struct nfp_net_hw *hw;
2161         struct nfp_net_tx_desc *txds, txd;
2162         struct rte_mbuf *pkt;
2163         uint64_t dma_addr;
2164         int pkt_size, dma_size;
2165         uint16_t free_descs, issued_descs;
2166         struct rte_mbuf **lmbuf;
2167         int i;
2168
2169         txq = tx_queue;
2170         hw = txq->hw;
2171         txds = &txq->txds[txq->wr_p];
2172
2173         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2174                    txq->qidx, txq->wr_p, nb_pkts);
2175
2176         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2177                 nfp_net_tx_free_bufs(txq);
2178
2179         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2180         if (unlikely(free_descs == 0))
2181                 return 0;
2182
2183         pkt = *tx_pkts;
2184
2185         i = 0;
2186         issued_descs = 0;
2187         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2188                    txq->qidx, nb_pkts);
2189         /* Sending packets */
2190         while ((i < nb_pkts) && free_descs) {
2191                 /* Grabbing the mbuf linked to the current descriptor */
2192                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2193                 /* Warming the cache for releasing the mbuf later on */
2194                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2195
2196                 pkt = *(tx_pkts + i);
2197
2198                 if (unlikely((pkt->nb_segs > 1) &&
2199                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2200                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2201                         rte_panic("Multisegment packet unsupported\n");
2202                 }
2203
2204                 /* Checking if we have enough descriptors */
2205                 if (unlikely(pkt->nb_segs > free_descs))
2206                         goto xmit_end;
2207
2208                 /*
2209                  * Checksum and VLAN flags just in the first descriptor for a
2210                  * multisegment packet, but TSO info needs to be in all of them.
2211                  */
2212                 txd.data_len = pkt->pkt_len;
2213                 nfp_net_tx_tso(txq, &txd, pkt);
2214                 nfp_net_tx_cksum(txq, &txd, pkt);
2215
2216                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2217                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2218                         txd.flags |= PCIE_DESC_TX_VLAN;
2219                         txd.vlan = pkt->vlan_tci;
2220                 }
2221
2222                 /*
2223                  * mbuf data_len is the data in one segment and pkt_len data
2224                  * in the whole packet. When the packet is just one segment,
2225                  * then data_len = pkt_len
2226                  */
2227                 pkt_size = pkt->pkt_len;
2228
2229                 while (pkt) {
2230                         /* Copying TSO, VLAN and cksum info */
2231                         *txds = txd;
2232
2233                         /* Releasing mbuf used by this descriptor previously*/
2234                         if (*lmbuf)
2235                                 rte_pktmbuf_free_seg(*lmbuf);
2236
2237                         /*
2238                          * Linking mbuf with descriptor for being released
2239                          * next time descriptor is used
2240                          */
2241                         *lmbuf = pkt;
2242
2243                         dma_size = pkt->data_len;
2244                         dma_addr = rte_mbuf_data_dma_addr(pkt);
2245                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2246                                    "%" PRIx64 "\n", dma_addr);
2247
2248                         /* Filling descriptors fields */
2249                         txds->dma_len = dma_size;
2250                         txds->data_len = txd.data_len;
2251                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2252                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2253                         ASSERT(free_descs > 0);
2254                         free_descs--;
2255
2256                         txq->wr_p++;
2257                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2258                                 txq->wr_p = 0;
2259
2260                         pkt_size -= dma_size;
2261                         if (!pkt_size)
2262                                 /* End of packet */
2263                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2264                         else
2265                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2266
2267                         pkt = pkt->next;
2268                         /* Referencing next free TX descriptor */
2269                         txds = &txq->txds[txq->wr_p];
2270                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2271                         issued_descs++;
2272                 }
2273                 i++;
2274         }
2275
2276 xmit_end:
2277         /* Increment write pointers. Force memory write before we let HW know */
2278         rte_wmb();
2279         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2280
2281         return i;
2282 }
2283
2284 static void
2285 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2286 {
2287         uint32_t new_ctrl, update;
2288         struct nfp_net_hw *hw;
2289
2290         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         new_ctrl = 0;
2292
2293         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2294             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2295                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2296                         " ETH_VLAN_EXTEND_OFFLOAD");
2297
2298         /* Enable vlan strip if it is not configured yet */
2299         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2300             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2301                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2302
2303         /* Disable vlan strip just if it is configured */
2304         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2305             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2306                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2307
2308         if (new_ctrl == 0)
2309                 return;
2310
2311         update = NFP_NET_CFG_UPDATE_GEN;
2312
2313         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2314                 return;
2315
2316         hw->ctrl = new_ctrl;
2317 }
2318
2319 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2320 static int
2321 nfp_net_reta_update(struct rte_eth_dev *dev,
2322                     struct rte_eth_rss_reta_entry64 *reta_conf,
2323                     uint16_t reta_size)
2324 {
2325         uint32_t reta, mask;
2326         int i, j;
2327         int idx, shift;
2328         uint32_t update;
2329         struct nfp_net_hw *hw =
2330                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331
2332         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2333                 return -EINVAL;
2334
2335         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2336                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2337                         "(%d) doesn't match the number hardware can supported "
2338                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2339                 return -EINVAL;
2340         }
2341
2342         /*
2343          * Update Redirection Table. There are 128 8bit-entries which can be
2344          * manage as 32 32bit-entries
2345          */
2346         for (i = 0; i < reta_size; i += 4) {
2347                 /* Handling 4 RSS entries per loop */
2348                 idx = i / RTE_RETA_GROUP_SIZE;
2349                 shift = i % RTE_RETA_GROUP_SIZE;
2350                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2351
2352                 if (!mask)
2353                         continue;
2354
2355                 reta = 0;
2356                 /* If all 4 entries were set, don't need read RETA register */
2357                 if (mask != 0xF)
2358                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2359
2360                 for (j = 0; j < 4; j++) {
2361                         if (!(mask & (0x1 << j)))
2362                                 continue;
2363                         if (mask != 0xF)
2364                                 /* Clearing the entry bits */
2365                                 reta &= ~(0xFF << (8 * j));
2366                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2367                 }
2368                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2369                               reta);
2370         }
2371
2372         update = NFP_NET_CFG_UPDATE_RSS;
2373
2374         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2375                 return -EIO;
2376
2377         return 0;
2378 }
2379
2380  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2381 static int
2382 nfp_net_reta_query(struct rte_eth_dev *dev,
2383                    struct rte_eth_rss_reta_entry64 *reta_conf,
2384                    uint16_t reta_size)
2385 {
2386         uint8_t i, j, mask;
2387         int idx, shift;
2388         uint32_t reta;
2389         struct nfp_net_hw *hw;
2390
2391         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392
2393         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2394                 return -EINVAL;
2395
2396         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2397                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2398                         "(%d) doesn't match the number hardware can supported "
2399                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2400                 return -EINVAL;
2401         }
2402
2403         /*
2404          * Reading Redirection Table. There are 128 8bit-entries which can be
2405          * manage as 32 32bit-entries
2406          */
2407         for (i = 0; i < reta_size; i += 4) {
2408                 /* Handling 4 RSS entries per loop */
2409                 idx = i / RTE_RETA_GROUP_SIZE;
2410                 shift = i % RTE_RETA_GROUP_SIZE;
2411                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2412
2413                 if (!mask)
2414                         continue;
2415
2416                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2417                                     shift);
2418                 for (j = 0; j < 4; j++) {
2419                         if (!(mask & (0x1 << j)))
2420                                 continue;
2421                         reta_conf->reta[shift + j] =
2422                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2423                 }
2424         }
2425         return 0;
2426 }
2427
2428 static int
2429 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2430                         struct rte_eth_rss_conf *rss_conf)
2431 {
2432         uint32_t update;
2433         uint32_t cfg_rss_ctrl = 0;
2434         uint8_t key;
2435         uint64_t rss_hf;
2436         int i;
2437         struct nfp_net_hw *hw;
2438
2439         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440
2441         rss_hf = rss_conf->rss_hf;
2442
2443         /* Checking if RSS is enabled */
2444         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2445                 if (rss_hf != 0) { /* Enable RSS? */
2446                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2447                         return -EINVAL;
2448                 }
2449                 return 0; /* Nothing to do */
2450         }
2451
2452         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2453                 RTE_LOG(ERR, PMD, "hash key too long\n");
2454                 return -EINVAL;
2455         }
2456
2457         if (rss_hf & ETH_RSS_IPV4)
2458                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2459                                 NFP_NET_CFG_RSS_IPV4_TCP |
2460                                 NFP_NET_CFG_RSS_IPV4_UDP;
2461
2462         if (rss_hf & ETH_RSS_IPV6)
2463                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2464                                 NFP_NET_CFG_RSS_IPV6_TCP |
2465                                 NFP_NET_CFG_RSS_IPV6_UDP;
2466
2467         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2468         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2469
2470         /* configuring where to apply the RSS hash */
2471         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2472
2473         /* Writing the key byte a byte */
2474         for (i = 0; i < rss_conf->rss_key_len; i++) {
2475                 memcpy(&key, &rss_conf->rss_key[i], 1);
2476                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2477         }
2478
2479         /* Writing the key size */
2480         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2481
2482         update = NFP_NET_CFG_UPDATE_RSS;
2483
2484         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2485                 return -EIO;
2486
2487         return 0;
2488 }
2489
2490 static int
2491 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2492                           struct rte_eth_rss_conf *rss_conf)
2493 {
2494         uint64_t rss_hf;
2495         uint32_t cfg_rss_ctrl;
2496         uint8_t key;
2497         int i;
2498         struct nfp_net_hw *hw;
2499
2500         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501
2502         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2503                 return -EINVAL;
2504
2505         rss_hf = rss_conf->rss_hf;
2506         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2507
2508         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2509                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2510
2511         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2512                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2513
2514         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2515                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2516
2517         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2518                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2519
2520         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2521                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2522
2523         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2524                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2525
2526         /* Reading the key size */
2527         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2528
2529         /* Reading the key byte a byte */
2530         for (i = 0; i < rss_conf->rss_key_len; i++) {
2531                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2532                 memcpy(&rss_conf->rss_key[i], &key, 1);
2533         }
2534
2535         return 0;
2536 }
2537
2538 /* Initialise and register driver with DPDK Application */
2539 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2540         .dev_configure          = nfp_net_configure,
2541         .dev_start              = nfp_net_start,
2542         .dev_stop               = nfp_net_stop,
2543         .dev_close              = nfp_net_close,
2544         .promiscuous_enable     = nfp_net_promisc_enable,
2545         .promiscuous_disable    = nfp_net_promisc_disable,
2546         .link_update            = nfp_net_link_update,
2547         .stats_get              = nfp_net_stats_get,
2548         .stats_reset            = nfp_net_stats_reset,
2549         .dev_infos_get          = nfp_net_infos_get,
2550         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2551         .mtu_set                = nfp_net_dev_mtu_set,
2552         .vlan_offload_set       = nfp_net_vlan_offload_set,
2553         .reta_update            = nfp_net_reta_update,
2554         .reta_query             = nfp_net_reta_query,
2555         .rss_hash_update        = nfp_net_rss_hash_update,
2556         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2557         .rx_queue_setup         = nfp_net_rx_queue_setup,
2558         .rx_queue_release       = nfp_net_rx_queue_release,
2559         .rx_queue_count         = nfp_net_rx_queue_count,
2560         .tx_queue_setup         = nfp_net_tx_queue_setup,
2561         .tx_queue_release       = nfp_net_tx_queue_release,
2562         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2563         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2564 };
2565
2566 /*
2567  * All eth_dev created got its private data, but before nfp_net_init, that
2568  * private data is referencing private data for all the PF ports. This is due
2569  * to how the vNIC bars are mapped based on first port, so all ports need info
2570  * about port 0 private data. Inside nfp_net_init the private data pointer is
2571  * changed to the right address for each port once the bars have been mapped.
2572  *
2573  * This functions helps to find out which port and therefore which offset
2574  * inside the private data array to use.
2575  */
2576 static int
2577 get_pf_port_number(char *name)
2578 {
2579         char *pf_str = name;
2580         int size = 0;
2581
2582         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2583                 pf_str++;
2584
2585         if (size == 30)
2586                 /*
2587                  * This should not happen at all and it would mean major
2588                  * implementation fault.
2589                  */
2590                 rte_panic("nfp_net: problem with pf device name\n");
2591
2592         /* Expecting _portX with X within [0,7] */
2593         pf_str += 5;
2594
2595         return (int)strtol(pf_str, NULL, 10);
2596 }
2597
2598 static int
2599 nfp_net_init(struct rte_eth_dev *eth_dev)
2600 {
2601         struct rte_pci_device *pci_dev;
2602         struct nfp_net_hw *hw, *hwport0;
2603
2604         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2605         uint32_t start_q;
2606         int stride = 4;
2607
2608         nspu_desc_t *nspu_desc = NULL;
2609         uint64_t bar_offset;
2610         int port = 0;
2611
2612         PMD_INIT_FUNC_TRACE();
2613
2614         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2615
2616         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2617             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2618                 port = get_pf_port_number(eth_dev->data->name);
2619                 if (port < 0 || port > 7) {
2620                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2621                         return -ENODEV;
2622                 }
2623
2624                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2625
2626                 /* This points to port 0 private data */
2627                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2628
2629                 /* This points to the specific port private data */
2630                 hw = &hwport0[port];
2631                 hw->pf_port_idx = port;
2632         } else {
2633                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2634                 hwport0 = 0;
2635         }
2636
2637         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2638         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2639         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2640
2641         /* For secondary processes, the primary has done all the work */
2642         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2643                 return 0;
2644
2645         rte_eth_copy_pci_info(eth_dev, pci_dev);
2646         /* hotplug is not possible with multiport PF */
2647         if (!hw->pf_multiport_enabled)
2648                 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2649
2650         hw->device_id = pci_dev->id.device_id;
2651         hw->vendor_id = pci_dev->id.vendor_id;
2652         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2653         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2654
2655         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2656                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2657                      pci_dev->addr.domain, pci_dev->addr.bus,
2658                      pci_dev->addr.devid, pci_dev->addr.function);
2659
2660         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2661         if (hw->ctrl_bar == NULL) {
2662                 RTE_LOG(ERR, PMD,
2663                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2664                 return -ENODEV;
2665         }
2666
2667         if (hw->is_pf && port == 0) {
2668                 nspu_desc = hw->nspu_desc;
2669
2670                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2671                         /*
2672                          * A firmware should be there after PF probe so this
2673                          * should not happen.
2674                          */
2675                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2676                         return -ENODEV;
2677                 }
2678
2679                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2680                 hw->ctrl_bar += bar_offset;
2681                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2682         }
2683
2684         if (port > 0) {
2685                 if (!hwport0->ctrl_bar)
2686                         return -ENODEV;
2687
2688                 /* address based on port0 offset */
2689                 hw->ctrl_bar = hwport0->ctrl_bar +
2690                                (port * NFP_PF_CSR_SLICE_SIZE);
2691         }
2692
2693         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2694
2695         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2696         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2697
2698         /* Work out where in the BAR the queues start. */
2699         switch (pci_dev->id.device_id) {
2700         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2701         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2702         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2703                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2704                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2705                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2706                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2707                 break;
2708         default:
2709                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2710                 return -ENODEV;
2711         }
2712
2713         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2714         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2715
2716         if (hw->is_pf && port == 0) {
2717                 /* configure access to tx/rx vNIC BARs */
2718                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2719                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2720                                     bar_offset);
2721                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2722
2723                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2724                 hwport0->hw_queues += bar_offset;
2725
2726                 /* Lets seize the chance to read eth table from hw */
2727                 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2728                         return -ENODEV;
2729         }
2730
2731         if (hw->is_pf) {
2732                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2733                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2734                 eth_dev->data->dev_private = hw;
2735         } else {
2736                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2737                              tx_bar_off;
2738                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2739                              rx_bar_off;
2740         }
2741
2742         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2743                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2744
2745         nfp_net_cfg_queue_setup(hw);
2746
2747         /* Get some of the read-only fields from the config BAR */
2748         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2749         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2750         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2751         hw->mtu = hw->max_mtu;
2752
2753         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2754                 hw->rx_offset = NFP_NET_RX_OFFSET;
2755         else
2756                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2757
2758         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2759                      hw->ver, hw->max_mtu);
2760         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2761                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2762                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2763                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2764                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2765                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2766                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2767                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2768                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2769                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2770
2771         hw->ctrl = 0;
2772
2773         hw->stride_rx = stride;
2774         hw->stride_tx = stride;
2775
2776         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2777                      hw->max_rx_queues, hw->max_tx_queues);
2778
2779         /* Initializing spinlock for reconfigs */
2780         rte_spinlock_init(&hw->reconfig_lock);
2781
2782         /* Allocating memory for mac addr */
2783         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2784         if (eth_dev->data->mac_addrs == NULL) {
2785                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2786                 return -ENOMEM;
2787         }
2788
2789         if (hw->is_pf)
2790                 nfp_net_pf_read_mac(hwport0, port);
2791         else
2792                 nfp_net_vf_read_mac(hw);
2793
2794         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2795                 /* Using random mac addresses for VFs */
2796                 eth_random_addr(&hw->mac_addr[0]);
2797                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2798         }
2799
2800         /* Copying mac address to DPDK eth_dev struct */
2801         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2802                         &eth_dev->data->mac_addrs[0]);
2803
2804         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2805                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2806                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2807                      pci_dev->id.device_id,
2808                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2809                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2810
2811         /* Registering LSC interrupt handler */
2812         rte_intr_callback_register(&pci_dev->intr_handle,
2813                                    nfp_net_dev_interrupt_handler,
2814                                    (void *)eth_dev);
2815
2816         /* Telling the firmware about the LSC interrupt entry */
2817         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2818
2819         /* Recording current stats counters values */
2820         nfp_net_stats_reset(eth_dev);
2821
2822         return 0;
2823 }
2824
2825 static int
2826 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2827                   nfpu_desc_t *nfpu_desc, void **priv)
2828 {
2829         struct rte_eth_dev *eth_dev;
2830         struct nfp_net_hw *hw;
2831         char *port_name;
2832         int ret;
2833
2834         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2835         if (!port_name)
2836                 return -ENOMEM;
2837
2838         if (ports > 1)
2839                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2840         else
2841                 sprintf(port_name, "%s", dev->device.name);
2842
2843         eth_dev = rte_eth_dev_allocate(port_name);
2844         if (!eth_dev)
2845                 return -ENOMEM;
2846
2847         if (port == 0) {
2848                 *priv = rte_zmalloc(port_name,
2849                                     sizeof(struct nfp_net_adapter) * ports,
2850                                     RTE_CACHE_LINE_SIZE);
2851                 if (!*priv) {
2852                         rte_eth_dev_release_port(eth_dev);
2853                         return -ENOMEM;
2854                 }
2855         }
2856
2857         eth_dev->data->dev_private = *priv;
2858
2859         /*
2860          * dev_private pointing to port0 dev_private because we need
2861          * to configure vNIC bars based on port0 at nfp_net_init.
2862          * Then dev_private is adjusted per port.
2863          */
2864         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2865         hw->nspu_desc = nfpu_desc->nspu;
2866         hw->nfpu_desc = nfpu_desc;
2867         hw->is_pf = 1;
2868         if (ports > 1)
2869                 hw->pf_multiport_enabled = 1;
2870
2871         eth_dev->device = &dev->device;
2872         rte_eth_copy_pci_info(eth_dev, dev);
2873
2874         ret = nfp_net_init(eth_dev);
2875
2876         if (ret)
2877                 rte_eth_dev_release_port(eth_dev);
2878
2879         rte_free(port_name);
2880
2881         return ret;
2882 }
2883
2884 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2885                             struct rte_pci_device *dev)
2886 {
2887         nfpu_desc_t *nfpu_desc;
2888         nspu_desc_t *nspu_desc;
2889         uint64_t offset_symbol;
2890         uint8_t *bar_offset;
2891         int major, minor;
2892         int total_ports;
2893         void *priv = 0;
2894         int ret = -ENODEV;
2895         int i;
2896
2897         if (!dev)
2898                 return ret;
2899
2900         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2901         if (!nfpu_desc)
2902                 return -ENOMEM;
2903
2904         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2905                 RTE_LOG(ERR, PMD,
2906                         "nfpu_open failed\n");
2907                 goto nfpu_error;
2908         }
2909
2910         nspu_desc = nfpu_desc->nspu;
2911
2912
2913         /* Check NSP ABI version */
2914         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2915                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2916                 goto error;
2917         }
2918         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2919
2920         if ((major == 0) && (minor < 20)) {
2921                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2922                 goto error;
2923         }
2924
2925         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2926                                &offset_symbol);
2927         if (ret)
2928                 goto error;
2929
2930         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2931         bar_offset += offset_symbol;
2932         total_ports = (uint32_t)*bar_offset;
2933         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2934
2935         if (total_ports <= 0 || total_ports > 8) {
2936                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2937                 ret = -ENODEV;
2938                 goto error;
2939         }
2940
2941         for (i = 0; i < total_ports; i++) {
2942                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2943                 if (ret)
2944                         goto error;
2945         }
2946
2947         return 0;
2948
2949 error:
2950         nfpu_close(nfpu_desc);
2951 nfpu_error:
2952         rte_free(nfpu_desc);
2953
2954         return ret;
2955 }
2956
2957 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2958         {
2959                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2960                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2961         },
2962         {
2963                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2964                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2965         },
2966         {
2967                 .vendor_id = 0,
2968         },
2969 };
2970
2971 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2972         {
2973                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2974                                PCI_DEVICE_ID_NFP6000_VF_NIC)
2975         },
2976         {
2977                 .vendor_id = 0,
2978         },
2979 };
2980
2981 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2982         struct rte_pci_device *pci_dev)
2983 {
2984         return rte_eth_dev_pci_generic_probe(pci_dev,
2985                 sizeof(struct nfp_net_adapter), nfp_net_init);
2986 }
2987
2988 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2989 {
2990         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2991 }
2992
2993 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
2994         .id_table = pci_id_nfp_pf_net_map,
2995         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2996         .probe = nfp_pf_pci_probe,
2997         .remove = eth_nfp_pci_remove,
2998 };
2999
3000 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3001         .id_table = pci_id_nfp_vf_net_map,
3002         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3003         .probe = eth_nfp_pci_probe,
3004         .remove = eth_nfp_pci_remove,
3005 };
3006
3007 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3008 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3009 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3010 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3011 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3012 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3013
3014 /*
3015  * Local variables:
3016  * c-file-style: "Linux"
3017  * indent-tabs-mode: t
3018  * End:
3019  */