drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         /* Supporting VLAN insertion by default */
 492         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 493                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 494
 495         if (rxmode->jumbo_frame)
 496                 /* this is handled in rte_eth_dev_configure */
 497
 498         if (rxmode->hw_strip_crc) {
 499                 PMD_INIT_LOG(INFO, "strip CRC not supported");
 500                 return -EINVAL;
 501         }
 502
 503         if (rxmode->enable_scatter) {
 504                 PMD_INIT_LOG(INFO, "Scatter not supported");
 505                 return -EINVAL;
 506         }
 507
 508         if (!new_ctrl)
 509                 return 0;
 510
 511         update |= NFP_NET_CFG_UPDATE_GEN;
 512
 513         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 514         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 515                 return -EIO;
 516
 517         hw->ctrl = new_ctrl;
 518
 519         return 0;
 520 }
 521
 522 static void
 523 nfp_net_enable_queues(struct rte_eth_dev *dev)
 524 {
 525         struct nfp_net_hw *hw;
 526         uint64_t enabled_queues = 0;
 527         int i;
 528
 529         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 530
 531         /* Enabling the required TX queues in the device */
 532         for (i = 0; i < dev->data->nb_tx_queues; i++)
 533                 enabled_queues |= (1 << i);
 534
 535         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 536
 537         enabled_queues = 0;
 538
 539         /* Enabling the required RX queues in the device */
 540         for (i = 0; i < dev->data->nb_rx_queues; i++)
 541                 enabled_queues |= (1 << i);
 542
 543         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 544 }
 545
 546 static void
 547 nfp_net_disable_queues(struct rte_eth_dev *dev)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t new_ctrl, update = 0;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553
 554         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 555         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 556
 557         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 558         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 559                  NFP_NET_CFG_UPDATE_MSIX;
 560
 561         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 562                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 563
 564         /* If an error when reconfig we avoid to change hw state */
 565         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 566                 return;
 567
 568         hw->ctrl = new_ctrl;
 569 }
 570
 571 static int
 572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 573 {
 574         int i;
 575
 576         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 577                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 578                         return -1;
 579         }
 580         return 0;
 581 }
 582
 583 static void
 584 nfp_net_params_setup(struct nfp_net_hw *hw)
 585 {
 586         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 587         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 588 }
 589
 590 static void
 591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 592 {
 593         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 594 }
 595
 596 static void nfp_net_read_mac(struct nfp_net_hw *hw)
 597 {
 598         uint32_t tmp;
 599
 600         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 601         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 602
 603         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 604         memcpy(&hw->mac_addr[4], &tmp, 2);
 605 }
 606
 607 static void
 608 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 609 {
 610         uint32_t mac0 = *(uint32_t *)mac;
 611         uint16_t mac1;
 612
 613         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 614
 615         mac += 4;
 616         mac1 = *(uint16_t *)mac;
 617         nn_writew(rte_cpu_to_be_16(mac1),
 618                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 619 }
 620
 621 static int
 622 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 623                            struct rte_intr_handle *intr_handle)
 624 {
 625         struct nfp_net_hw *hw;
 626         int i;
 627
 628         if (!intr_handle->intr_vec) {
 629                 intr_handle->intr_vec =
 630                         rte_zmalloc("intr_vec",
 631                                     dev->data->nb_rx_queues * sizeof(int), 0);
 632                 if (!intr_handle->intr_vec) {
 633                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 634                                      " intr_vec", dev->data->nb_rx_queues);
 635                         return -ENOMEM;
 636                 }
 637         }
 638
 639         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 642                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 643                 /* UIO just supports one queue and no LSC*/
 644                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 645                 intr_handle->intr_vec[0] = 0;
 646         } else {
 647                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 648                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 649                         /*
 650                          * The first msix vector is reserved for non
 651                          * efd interrupts
 652                         */
 653                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 654                         intr_handle->intr_vec[i] = i + 1;
 655                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 656                                             intr_handle->intr_vec[i]);
 657                 }
 658         }
 659
 660         /* Avoiding TX interrupts */
 661         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 662         return 0;
 663 }
 664
 665 static int
 666 nfp_net_start(struct rte_eth_dev *dev)
 667 {
 668         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 669         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 670         uint32_t new_ctrl, update = 0;
 671         struct nfp_net_hw *hw;
 672         uint32_t intr_vector;
 673         int ret;
 674
 675         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 676
 677         PMD_INIT_LOG(DEBUG, "Start");
 678
 679         /* Disabling queues just in case... */
 680         nfp_net_disable_queues(dev);
 681
 682         /* Writing configuration parameters in the device */
 683         nfp_net_params_setup(hw);
 684
 685         /* Enabling the required queues in the device */
 686         nfp_net_enable_queues(dev);
 687
 688         /* check and configure queue intr-vector mapping */
 689         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 690                 if (hw->pf_multiport_enabled) {
 691                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 692                                           "with NFP multiport PF");
 693                                 return -EINVAL;
 694                 }
 695                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 696                         /*
 697                          * Better not to share LSC with RX interrupts.
 698                          * Unregistering LSC interrupt handler
 699                          */
 700                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 701                                 nfp_net_dev_interrupt_handler, (void *)dev);
 702
 703                         if (dev->data->nb_rx_queues > 1) {
 704                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 705                                              "supports 1 queue with UIO");
 706                                 return -EIO;
 707                         }
 708                 }
 709                 intr_vector = dev->data->nb_rx_queues;
 710                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 711                         return -1;
 712
 713                 nfp_configure_rx_interrupt(dev, intr_handle);
 714                 update = NFP_NET_CFG_UPDATE_MSIX;
 715         }
 716
 717         rte_intr_enable(intr_handle);
 718
 719         /* Enable device */
 720         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 721
 722         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 723
 724         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 725                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 726
 727         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 728         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 729                 return -EIO;
 730
 731         /*
 732          * Allocating rte mbuffs for configured rx queues.
 733          * This requires queues being enabled before
 734          */
 735         if (nfp_net_rx_freelist_setup(dev) < 0) {
 736                 ret = -ENOMEM;
 737                 goto error;
 738         }
 739
 740         if (hw->is_pf)
 741                 /* Configure the physical port up */
 742                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 743
 744         hw->ctrl = new_ctrl;
 745
 746         return 0;
 747
 748 error:
 749         /*
 750          * An error returned by this function should mean the app
 751          * exiting and then the system releasing all the memory
 752          * allocated even memory coming from hugepages.
 753          *
 754          * The device could be enabled at this point with some queues
 755          * ready for getting packets. This is true if the call to
 756          * nfp_net_rx_freelist_setup() succeeds for some queues but
 757          * fails for subsequent queues.
 758          *
 759          * This should make the app exiting but better if we tell the
 760          * device first.
 761          */
 762         nfp_net_disable_queues(dev);
 763
 764         return ret;
 765 }
 766
 767 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 768 static void
 769 nfp_net_stop(struct rte_eth_dev *dev)
 770 {
 771         int i;
 772         struct nfp_net_hw *hw;
 773
 774         PMD_INIT_LOG(DEBUG, "Stop");
 775
 776         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 777
 778         nfp_net_disable_queues(dev);
 779
 780         /* Clear queues */
 781         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 782                 nfp_net_reset_tx_queue(
 783                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 784         }
 785
 786         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 787                 nfp_net_reset_rx_queue(
 788                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 789         }
 790
 791         if (hw->is_pf)
 792                 /* Configure the physical port down */
 793                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 794 }
 795
 796 /* Reset and stop device. The device can not be restarted. */
 797 static void
 798 nfp_net_close(struct rte_eth_dev *dev)
 799 {
 800         struct nfp_net_hw *hw;
 801         struct rte_pci_device *pci_dev;
 802         int i;
 803
 804         PMD_INIT_LOG(DEBUG, "Close");
 805
 806         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 807         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 808
 809         /*
 810          * We assume that the DPDK application is stopping all the
 811          * threads/queues before calling the device close function.
 812          */
 813
 814         nfp_net_disable_queues(dev);
 815
 816         /* Clear queues */
 817         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 818                 nfp_net_reset_tx_queue(
 819                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 820         }
 821
 822         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 823                 nfp_net_reset_rx_queue(
 824                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 825         }
 826
 827         rte_intr_disable(&pci_dev->intr_handle);
 828         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 829
 830         /* unregister callback func from eal lib */
 831         rte_intr_callback_unregister(&pci_dev->intr_handle,
 832                                      nfp_net_dev_interrupt_handler,
 833                                      (void *)dev);
 834
 835         /*
 836          * The ixgbe PMD driver disables the pcie master on the
 837          * device. The i40e does not...
 838          */
 839 }
 840
 841 static void
 842 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 843 {
 844         uint32_t new_ctrl, update = 0;
 845         struct nfp_net_hw *hw;
 846
 847         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 848
 849         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850
 851         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 852                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 853                 return;
 854         }
 855
 856         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 857                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 858                 return;
 859         }
 860
 861         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 862         update = NFP_NET_CFG_UPDATE_GEN;
 863
 864         /*
 865          * DPDK sets promiscuous mode on just after this call assuming
 866          * it can not fail ...
 867          */
 868         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 869                 return;
 870
 871         hw->ctrl = new_ctrl;
 872 }
 873
 874 static void
 875 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 876 {
 877         uint32_t new_ctrl, update = 0;
 878         struct nfp_net_hw *hw;
 879
 880         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 881
 882         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 883                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 884                 return;
 885         }
 886
 887         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 888         update = NFP_NET_CFG_UPDATE_GEN;
 889
 890         /*
 891          * DPDK sets promiscuous mode off just before this call
 892          * assuming it can not fail ...
 893          */
 894         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 895                 return;
 896
 897         hw->ctrl = new_ctrl;
 898 }
 899
 900 /*
 901  * return 0 means link status changed, -1 means not changed
 902  *
 903  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 904  * status.
 905  */
 906 static int
 907 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 908 {
 909         struct nfp_net_hw *hw;
 910         struct rte_eth_link link, old;
 911         uint32_t nn_link_status;
 912
 913         static const uint32_t ls_to_ethtool[] = {
 914                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 915                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 916                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 917                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 918                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 919                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 920                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 921                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 922         };
 923
 924         PMD_DRV_LOG(DEBUG, "Link update\n");
 925
 926         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 927
 928         memset(&old, 0, sizeof(old));
 929         nfp_net_dev_atomic_read_link_status(dev, &old);
 930
 931         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 932
 933         memset(&link, 0, sizeof(struct rte_eth_link));
 934
 935         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 936                 link.link_status = ETH_LINK_UP;
 937
 938         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 939
 940         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 941                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 942
 943         if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
 944             ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
 945             (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
 946                 /* We really do not know the speed wil old firmware */
 947                 link.link_speed = ETH_SPEED_NUM_NONE;
 948         else {
 949                 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 950                         link.link_speed = ETH_SPEED_NUM_NONE;
 951                 else
 952                         link.link_speed = ls_to_ethtool[nn_link_status];
 953         }
 954
 955         if (old.link_status != link.link_status) {
 956                 nfp_net_dev_atomic_write_link_status(dev, &link);
 957                 if (link.link_status)
 958                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
 959                 else
 960                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
 961                 return 0;
 962         }
 963
 964         return -1;
 965 }
 966
 967 static void
 968 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 969 {
 970         int i;
 971         struct nfp_net_hw *hw;
 972         struct rte_eth_stats nfp_dev_stats;
 973
 974         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 975
 976         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
 977
 978         /* reading per RX ring stats */
 979         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 980                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 981                         break;
 982
 983                 nfp_dev_stats.q_ipackets[i] =
 984                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
 985
 986                 nfp_dev_stats.q_ipackets[i] -=
 987                         hw->eth_stats_base.q_ipackets[i];
 988
 989                 nfp_dev_stats.q_ibytes[i] =
 990                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
 991
 992                 nfp_dev_stats.q_ibytes[i] -=
 993                         hw->eth_stats_base.q_ibytes[i];
 994         }
 995
 996         /* reading per TX ring stats */
 997         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 998                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 999                         break;
1000
1001                 nfp_dev_stats.q_opackets[i] =
1002                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1003
1004                 nfp_dev_stats.q_opackets[i] -=
1005                         hw->eth_stats_base.q_opackets[i];
1006
1007                 nfp_dev_stats.q_obytes[i] =
1008                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1009
1010                 nfp_dev_stats.q_obytes[i] -=
1011                         hw->eth_stats_base.q_obytes[i];
1012         }
1013
1014         nfp_dev_stats.ipackets =
1015                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1016
1017         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1018
1019         nfp_dev_stats.ibytes =
1020                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1021
1022         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1023
1024         nfp_dev_stats.opackets =
1025                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1026
1027         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1028
1029         nfp_dev_stats.obytes =
1030                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1031
1032         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1033
1034         /* reading general device stats */
1035         nfp_dev_stats.ierrors =
1036                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1037
1038         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1039
1040         nfp_dev_stats.oerrors =
1041                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1042
1043         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1044
1045         /* RX ring mbuf allocation failures */
1046         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1047
1048         nfp_dev_stats.imissed =
1049                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1050
1051         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1052
1053         if (stats)
1054                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1055 }
1056
1057 static void
1058 nfp_net_stats_reset(struct rte_eth_dev *dev)
1059 {
1060         int i;
1061         struct nfp_net_hw *hw;
1062
1063         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064
1065         /*
1066          * hw->eth_stats_base records the per counter starting point.
1067          * Lets update it now
1068          */
1069
1070         /* reading per RX ring stats */
1071         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1072                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1073                         break;
1074
1075                 hw->eth_stats_base.q_ipackets[i] =
1076                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1077
1078                 hw->eth_stats_base.q_ibytes[i] =
1079                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1080         }
1081
1082         /* reading per TX ring stats */
1083         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1084                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1085                         break;
1086
1087                 hw->eth_stats_base.q_opackets[i] =
1088                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1089
1090                 hw->eth_stats_base.q_obytes[i] =
1091                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1092         }
1093
1094         hw->eth_stats_base.ipackets =
1095                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1096
1097         hw->eth_stats_base.ibytes =
1098                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1099
1100         hw->eth_stats_base.opackets =
1101                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1102
1103         hw->eth_stats_base.obytes =
1104                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1105
1106         /* reading general device stats */
1107         hw->eth_stats_base.ierrors =
1108                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1109
1110         hw->eth_stats_base.oerrors =
1111                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1112
1113         /* RX ring mbuf allocation failures */
1114         dev->data->rx_mbuf_alloc_failed = 0;
1115
1116         hw->eth_stats_base.imissed =
1117                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1118 }
1119
1120 static void
1121 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1122 {
1123         struct nfp_net_hw *hw;
1124
1125         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1126
1127         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1128         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1129         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1130         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1131         dev_info->max_rx_pktlen = hw->mtu;
1132         /* Next should change when PF support is implemented */
1133         dev_info->max_mac_addrs = 1;
1134
1135         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1136                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1137
1138         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1139                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1140                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1141                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1142
1143         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1144                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1145
1146         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1147                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1148                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1149                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1150
1151         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1152                 .rx_thresh = {
1153                         .pthresh = DEFAULT_RX_PTHRESH,
1154                         .hthresh = DEFAULT_RX_HTHRESH,
1155                         .wthresh = DEFAULT_RX_WTHRESH,
1156                 },
1157                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1158                 .rx_drop_en = 0,
1159         };
1160
1161         dev_info->default_txconf = (struct rte_eth_txconf) {
1162                 .tx_thresh = {
1163                         .pthresh = DEFAULT_TX_PTHRESH,
1164                         .hthresh = DEFAULT_TX_HTHRESH,
1165                         .wthresh = DEFAULT_TX_WTHRESH,
1166                 },
1167                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1168                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1169                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1170                              ETH_TXQ_FLAGS_NOOFFLOADS,
1171         };
1172
1173         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1174         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1175
1176         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1177                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1178                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1179
1180         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1181                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1182 }
1183
1184 static const uint32_t *
1185 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1186 {
1187         static const uint32_t ptypes[] = {
1188                 /* refers to nfp_net_set_hash() */
1189                 RTE_PTYPE_INNER_L3_IPV4,
1190                 RTE_PTYPE_INNER_L3_IPV6,
1191                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1192                 RTE_PTYPE_INNER_L4_MASK,
1193                 RTE_PTYPE_UNKNOWN
1194         };
1195
1196         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1197                 return ptypes;
1198         return NULL;
1199 }
1200
1201 static uint32_t
1202 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1203 {
1204         struct nfp_net_rxq *rxq;
1205         struct nfp_net_rx_desc *rxds;
1206         uint32_t idx;
1207         uint32_t count;
1208
1209         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1210
1211         idx = rxq->rd_p;
1212
1213         count = 0;
1214
1215         /*
1216          * Other PMDs are just checking the DD bit in intervals of 4
1217          * descriptors and counting all four if the first has the DD
1218          * bit on. Of course, this is not accurate but can be good for
1219          * performance. But ideally that should be done in descriptors
1220          * chunks belonging to the same cache line
1221          */
1222
1223         while (count < rxq->rx_count) {
1224                 rxds = &rxq->rxds[idx];
1225                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1226                         break;
1227
1228                 count++;
1229                 idx++;
1230
1231                 /* Wrapping? */
1232                 if ((idx) == rxq->rx_count)
1233                         idx = 0;
1234         }
1235
1236         return count;
1237 }
1238
1239 static int
1240 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1241 {
1242         struct rte_pci_device *pci_dev;
1243         struct nfp_net_hw *hw;
1244         int base = 0;
1245
1246         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1248
1249         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1250                 base = 1;
1251
1252         /* Make sure all updates are written before un-masking */
1253         rte_wmb();
1254         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1255                       NFP_NET_CFG_ICR_UNMASKED);
1256         return 0;
1257 }
1258
1259 static int
1260 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1261 {
1262         struct rte_pci_device *pci_dev;
1263         struct nfp_net_hw *hw;
1264         int base = 0;
1265
1266         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1267         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1268
1269         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1270                 base = 1;
1271
1272         /* Make sure all updates are written before un-masking */
1273         rte_wmb();
1274         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1275         return 0;
1276 }
1277
1278 static void
1279 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1280 {
1281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1282         struct rte_eth_link link;
1283
1284         memset(&link, 0, sizeof(link));
1285         nfp_net_dev_atomic_read_link_status(dev, &link);
1286         if (link.link_status)
1287                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1288                         (int)(dev->data->port_id), (unsigned)link.link_speed,
1289                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1290                         ? "full-duplex" : "half-duplex");
1291         else
1292                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1293                         (int)(dev->data->port_id));
1294
1295         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1296                 pci_dev->addr.domain, pci_dev->addr.bus,
1297                 pci_dev->addr.devid, pci_dev->addr.function);
1298 }
1299
1300 /* Interrupt configuration and handling */
1301
1302 /*
1303  * nfp_net_irq_unmask - Unmask an interrupt
1304  *
1305  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1306  * clear the ICR for the entry.
1307  */
1308 static void
1309 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1310 {
1311         struct nfp_net_hw *hw;
1312         struct rte_pci_device *pci_dev;
1313
1314         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1316
1317         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1318                 /* If MSI-X auto-masking is used, clear the entry */
1319                 rte_wmb();
1320                 rte_intr_enable(&pci_dev->intr_handle);
1321         } else {
1322                 /* Make sure all updates are written before un-masking */
1323                 rte_wmb();
1324                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1325                               NFP_NET_CFG_ICR_UNMASKED);
1326         }
1327 }
1328
1329 static void
1330 nfp_net_dev_interrupt_handler(void *param)
1331 {
1332         int64_t timeout;
1333         struct rte_eth_link link;
1334         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1335
1336         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1337
1338         /* get the link status */
1339         memset(&link, 0, sizeof(link));
1340         nfp_net_dev_atomic_read_link_status(dev, &link);
1341
1342         nfp_net_link_update(dev, 0);
1343
1344         /* likely to up */
1345         if (!link.link_status) {
1346                 /* handle it 1 sec later, wait it being stable */
1347                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1348                 /* likely to down */
1349         } else {
1350                 /* handle it 4 sec later, wait it being stable */
1351                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1352         }
1353
1354         if (rte_eal_alarm_set(timeout * 1000,
1355                               nfp_net_dev_interrupt_delayed_handler,
1356                               (void *)dev) < 0) {
1357                 RTE_LOG(ERR, PMD, "Error setting alarm");
1358                 /* Unmasking */
1359                 nfp_net_irq_unmask(dev);
1360         }
1361 }
1362
1363 /*
1364  * Interrupt handler which shall be registered for alarm callback for delayed
1365  * handling specific interrupt to wait for the stable nic state. As the NIC
1366  * interrupt state is not stable for nfp after link is just down, it needs
1367  * to wait 4 seconds to get the stable status.
1368  *
1369  * @param handle   Pointer to interrupt handle.
1370  * @param param    The address of parameter (struct rte_eth_dev *)
1371  *
1372  * @return  void
1373  */
1374 static void
1375 nfp_net_dev_interrupt_delayed_handler(void *param)
1376 {
1377         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1378
1379         nfp_net_link_update(dev, 0);
1380         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1381
1382         nfp_net_dev_link_status_print(dev);
1383
1384         /* Unmasking */
1385         nfp_net_irq_unmask(dev);
1386 }
1387
1388 static int
1389 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1390 {
1391         struct nfp_net_hw *hw;
1392
1393         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394
1395         /* check that mtu is within the allowed range */
1396         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1397                 return -EINVAL;
1398
1399         /* switch to jumbo mode if needed */
1400         if ((uint32_t)mtu > ETHER_MAX_LEN)
1401                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1402         else
1403                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1404
1405         /* update max frame size */
1406         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1407
1408         /* writing to configuration space */
1409         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1410
1411         hw->mtu = mtu;
1412
1413         return 0;
1414 }
1415
1416 static int
1417 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1418                        uint16_t queue_idx, uint16_t nb_desc,
1419                        unsigned int socket_id,
1420                        const struct rte_eth_rxconf *rx_conf,
1421                        struct rte_mempool *mp)
1422 {
1423         const struct rte_memzone *tz;
1424         struct nfp_net_rxq *rxq;
1425         struct nfp_net_hw *hw;
1426
1427         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428
1429         PMD_INIT_FUNC_TRACE();
1430
1431         /* Validating number of descriptors */
1432         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1433             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1434             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1435                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1436                 return -EINVAL;
1437         }
1438
1439         /*
1440          * Free memory prior to re-allocation if needed. This is the case after
1441          * calling nfp_net_stop
1442          */
1443         if (dev->data->rx_queues[queue_idx]) {
1444                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1445                 dev->data->rx_queues[queue_idx] = NULL;
1446         }
1447
1448         /* Allocating rx queue data structure */
1449         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1450                                  RTE_CACHE_LINE_SIZE, socket_id);
1451         if (rxq == NULL)
1452                 return -ENOMEM;
1453
1454         /* Hw queues mapping based on firmware confifguration */
1455         rxq->qidx = queue_idx;
1456         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1457         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1458         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1459         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1460
1461         /*
1462          * Tracking mbuf size for detecting a potential mbuf overflow due to
1463          * RX offset
1464          */
1465         rxq->mem_pool = mp;
1466         rxq->mbuf_size = rxq->mem_pool->elt_size;
1467         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1468         hw->flbufsz = rxq->mbuf_size;
1469
1470         rxq->rx_count = nb_desc;
1471         rxq->port_id = dev->data->port_id;
1472         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1473         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1474                                   : ETHER_CRC_LEN);
1475         rxq->drop_en = rx_conf->rx_drop_en;
1476
1477         /*
1478          * Allocate RX ring hardware descriptors. A memzone large enough to
1479          * handle the maximum ring size is allocated in order to allow for
1480          * resizing in later calls to the queue setup function.
1481          */
1482         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1483                                    sizeof(struct nfp_net_rx_desc) *
1484                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1485                                    socket_id);
1486
1487         if (tz == NULL) {
1488                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1489                 nfp_net_rx_queue_release(rxq);
1490                 return -ENOMEM;
1491         }
1492
1493         /* Saving physical and virtual addresses for the RX ring */
1494         rxq->dma = (uint64_t)tz->phys_addr;
1495         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1496
1497         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1498         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1499                                          sizeof(*rxq->rxbufs) * nb_desc,
1500                                          RTE_CACHE_LINE_SIZE, socket_id);
1501         if (rxq->rxbufs == NULL) {
1502                 nfp_net_rx_queue_release(rxq);
1503                 return -ENOMEM;
1504         }
1505
1506         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1507                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1508
1509         nfp_net_reset_rx_queue(rxq);
1510
1511         dev->data->rx_queues[queue_idx] = rxq;
1512         rxq->hw = hw;
1513
1514         /*
1515          * Telling the HW about the physical address of the RX ring and number
1516          * of descriptors in log2 format
1517          */
1518         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1519         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1520
1521         return 0;
1522 }
1523
1524 static int
1525 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1526 {
1527         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1528         uint64_t dma_addr;
1529         unsigned i;
1530
1531         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1532                    rxq->rx_count);
1533
1534         for (i = 0; i < rxq->rx_count; i++) {
1535                 struct nfp_net_rx_desc *rxd;
1536                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1537
1538                 if (mbuf == NULL) {
1539                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1540                                 (unsigned)rxq->qidx);
1541                         return -ENOMEM;
1542                 }
1543
1544                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1545
1546                 rxd = &rxq->rxds[i];
1547                 rxd->fld.dd = 0;
1548                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1549                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1550                 rxe[i].mbuf = mbuf;
1551                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1552         }
1553
1554         /* Make sure all writes are flushed before telling the hardware */
1555         rte_wmb();
1556
1557         /* Not advertising the whole ring as the firmware gets confused if so */
1558         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1559                    rxq->rx_count - 1);
1560
1561         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1562
1563         return 0;
1564 }
1565
1566 static int
1567 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1568                        uint16_t nb_desc, unsigned int socket_id,
1569                        const struct rte_eth_txconf *tx_conf)
1570 {
1571         const struct rte_memzone *tz;
1572         struct nfp_net_txq *txq;
1573         uint16_t tx_free_thresh;
1574         struct nfp_net_hw *hw;
1575
1576         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577
1578         PMD_INIT_FUNC_TRACE();
1579
1580         /* Validating number of descriptors */
1581         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1582             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1583             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1584                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1585                 return -EINVAL;
1586         }
1587
1588         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1589                                     tx_conf->tx_free_thresh :
1590                                     DEFAULT_TX_FREE_THRESH);
1591
1592         if (tx_free_thresh > (nb_desc)) {
1593                 RTE_LOG(ERR, PMD,
1594                         "tx_free_thresh must be less than the number of TX "
1595                         "descriptors. (tx_free_thresh=%u port=%d "
1596                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1597                         (int)dev->data->port_id, (int)queue_idx);
1598                 return -(EINVAL);
1599         }
1600
1601         /*
1602          * Free memory prior to re-allocation if needed. This is the case after
1603          * calling nfp_net_stop
1604          */
1605         if (dev->data->tx_queues[queue_idx]) {
1606                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1607                            queue_idx);
1608                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1609                 dev->data->tx_queues[queue_idx] = NULL;
1610         }
1611
1612         /* Allocating tx queue data structure */
1613         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1614                                  RTE_CACHE_LINE_SIZE, socket_id);
1615         if (txq == NULL) {
1616                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1617                 return -ENOMEM;
1618         }
1619
1620         /*
1621          * Allocate TX ring hardware descriptors. A memzone large enough to
1622          * handle the maximum ring size is allocated in order to allow for
1623          * resizing in later calls to the queue setup function.
1624          */
1625         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1626                                    sizeof(struct nfp_net_tx_desc) *
1627                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1628                                    socket_id);
1629         if (tz == NULL) {
1630                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1631                 nfp_net_tx_queue_release(txq);
1632                 return -ENOMEM;
1633         }
1634
1635         txq->tx_count = nb_desc;
1636         txq->tx_free_thresh = tx_free_thresh;
1637         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1638         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1639         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1640
1641         /* queue mapping based on firmware configuration */
1642         txq->qidx = queue_idx;
1643         txq->tx_qcidx = queue_idx * hw->stride_tx;
1644         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1645
1646         txq->port_id = dev->data->port_id;
1647         txq->txq_flags = tx_conf->txq_flags;
1648
1649         /* Saving physical and virtual addresses for the TX ring */
1650         txq->dma = (uint64_t)tz->phys_addr;
1651         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1652
1653         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1654         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1655                                          sizeof(*txq->txbufs) * nb_desc,
1656                                          RTE_CACHE_LINE_SIZE, socket_id);
1657         if (txq->txbufs == NULL) {
1658                 nfp_net_tx_queue_release(txq);
1659                 return -ENOMEM;
1660         }
1661         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1662                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1663
1664         nfp_net_reset_tx_queue(txq);
1665
1666         dev->data->tx_queues[queue_idx] = txq;
1667         txq->hw = hw;
1668
1669         /*
1670          * Telling the HW about the physical address of the TX ring and number
1671          * of descriptors in log2 format
1672          */
1673         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1674         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1675
1676         return 0;
1677 }
1678
1679 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1680 static inline void
1681 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1682                struct rte_mbuf *mb)
1683 {
1684         uint64_t ol_flags;
1685         struct nfp_net_hw *hw = txq->hw;
1686
1687         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1688                 goto clean_txd;
1689
1690         ol_flags = mb->ol_flags;
1691
1692         if (!(ol_flags & PKT_TX_TCP_SEG))
1693                 goto clean_txd;
1694
1695         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1696         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1697         txd->flags = PCIE_DESC_TX_LSO;
1698         return;
1699
1700 clean_txd:
1701         txd->flags = 0;
1702         txd->l4_offset = 0;
1703         txd->lso = 0;
1704 }
1705
1706 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1707 static inline void
1708 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1709                  struct rte_mbuf *mb)
1710 {
1711         uint64_t ol_flags;
1712         struct nfp_net_hw *hw = txq->hw;
1713
1714         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1715                 return;
1716
1717         ol_flags = mb->ol_flags;
1718
1719         /* IPv6 does not need checksum */
1720         if (ol_flags & PKT_TX_IP_CKSUM)
1721                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1722
1723         switch (ol_flags & PKT_TX_L4_MASK) {
1724         case PKT_TX_UDP_CKSUM:
1725                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1726                 break;
1727         case PKT_TX_TCP_CKSUM:
1728                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1729                 break;
1730         }
1731
1732         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1733                 txd->flags |= PCIE_DESC_TX_CSUM;
1734 }
1735
1736 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1737 static inline void
1738 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1739                  struct rte_mbuf *mb)
1740 {
1741         struct nfp_net_hw *hw = rxq->hw;
1742
1743         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1744                 return;
1745
1746         /* If IPv4 and IP checksum error, fail */
1747         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1748             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1749                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1750
1751         /* If neither UDP nor TCP return */
1752         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1753             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1754                 return;
1755
1756         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1757             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1758                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1759
1760         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1761             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1762                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1763 }
1764
1765 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1766 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1767
1768 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1769
1770 /*
1771  * nfp_net_set_hash - Set mbuf hash data
1772  *
1773  * The RSS hash and hash-type are pre-pended to the packet data.
1774  * Extract and decode it and set the mbuf fields.
1775  */
1776 static inline void
1777 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1778                  struct rte_mbuf *mbuf)
1779 {
1780         struct nfp_net_hw *hw = rxq->hw;
1781         uint8_t *meta_offset;
1782         uint32_t meta_info;
1783         uint32_t hash = 0;
1784         uint32_t hash_type = 0;
1785
1786         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1787                 return;
1788
1789         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1790                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1791                         return;
1792
1793                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1794                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1795
1796         } else if (NFP_DESC_META_LEN(rxd)) {
1797                 /*
1798                  * new metadata api:
1799                  * <----  32 bit  ----->
1800                  * m    field type word
1801                  * e     data field #2
1802                  * t     data field #1
1803                  * a     data field #0
1804                  * ====================
1805                  *    packet data
1806                  *
1807                  * Field type word contains up to 8 4bit field types
1808                  * A 4bit field type refers to a data field word
1809                  * A data field word can have several 4bit field types
1810                  */
1811                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1812                 meta_offset -= NFP_DESC_META_LEN(rxd);
1813                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1814                 meta_offset += 4;
1815                 /* NFP PMD just supports metadata for hashing */
1816                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1817                 case NFP_NET_META_HASH:
1818                         /* next field type is about the hash type */
1819                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1820                         /* hash value is in the data field */
1821                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1822                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1823                         break;
1824                 default:
1825                         /* Unsupported metadata can be a performance issue */
1826                         return;
1827                 }
1828         } else {
1829                 return;
1830         }
1831
1832         mbuf->hash.rss = hash;
1833         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1834
1835         switch (hash_type) {
1836         case NFP_NET_RSS_IPV4:
1837                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1838                 break;
1839         case NFP_NET_RSS_IPV6:
1840                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1841                 break;
1842         case NFP_NET_RSS_IPV6_EX:
1843                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1844                 break;
1845         default:
1846                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1847         }
1848 }
1849
1850 static inline void
1851 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1852 {
1853         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1854 }
1855
1856 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1857
1858 /*
1859  * RX path design:
1860  *
1861  * There are some decissions to take:
1862  * 1) How to check DD RX descriptors bit
1863  * 2) How and when to allocate new mbufs
1864  *
1865  * Current implementation checks just one single DD bit each loop. As each
1866  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1867  * a single cache line instead. Tests with this change have not shown any
1868  * performance improvement but it requires further investigation. For example,
1869  * depending on which descriptor is next, the number of descriptors could be
1870  * less than 8 for just checking those in the same cache line. This implies
1871  * extra work which could be counterproductive by itself. Indeed, last firmware
1872  * changes are just doing this: writing several descriptors with the DD bit
1873  * for saving PCIe bandwidth and DMA operations from the NFP.
1874  *
1875  * Mbuf allocation is done when a new packet is received. Then the descriptor
1876  * is automatically linked with the new mbuf and the old one is given to the
1877  * user. The main drawback with this design is mbuf allocation is heavier than
1878  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1879  * cache point of view it does not seem allocating the mbuf early on as we are
1880  * doing now have any benefit at all. Again, tests with this change have not
1881  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1882  * so looking at the implications of this type of allocation should be studied
1883  * deeply
1884  */
1885
1886 static uint16_t
1887 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1888 {
1889         struct nfp_net_rxq *rxq;
1890         struct nfp_net_rx_desc *rxds;
1891         struct nfp_net_rx_buff *rxb;
1892         struct nfp_net_hw *hw;
1893         struct rte_mbuf *mb;
1894         struct rte_mbuf *new_mb;
1895         uint16_t nb_hold;
1896         uint64_t dma_addr;
1897         int avail;
1898
1899         rxq = rx_queue;
1900         if (unlikely(rxq == NULL)) {
1901                 /*
1902                  * DPDK just checks the queue is lower than max queues
1903                  * enabled. But the queue needs to be configured
1904                  */
1905                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1906                 return -EINVAL;
1907         }
1908
1909         hw = rxq->hw;
1910         avail = 0;
1911         nb_hold = 0;
1912
1913         while (avail < nb_pkts) {
1914                 rxb = &rxq->rxbufs[rxq->rd_p];
1915                 if (unlikely(rxb == NULL)) {
1916                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1917                         break;
1918                 }
1919
1920                 /*
1921                  * Memory barrier to ensure that we won't do other
1922                  * reads before the DD bit.
1923                  */
1924                 rte_rmb();
1925
1926                 rxds = &rxq->rxds[rxq->rd_p];
1927                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1928                         break;
1929
1930                 /*
1931                  * We got a packet. Let's alloc a new mbuff for refilling the
1932                  * free descriptor ring as soon as possible
1933                  */
1934                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1935                 if (unlikely(new_mb == NULL)) {
1936                         RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1937                                 "queue_id=%u\n", (unsigned)rxq->port_id,
1938                                 (unsigned)rxq->qidx);
1939                         nfp_net_mbuf_alloc_failed(rxq);
1940                         break;
1941                 }
1942
1943                 nb_hold++;
1944
1945                 /*
1946                  * Grab the mbuff and refill the descriptor with the
1947                  * previously allocated mbuff
1948                  */
1949                 mb = rxb->mbuf;
1950                 rxb->mbuf = new_mb;
1951
1952                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1953                            rxds->rxd.data_len, rxq->mbuf_size);
1954
1955                 /* Size of this segment */
1956                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1957                 /* Size of the whole packet. We just support 1 segment */
1958                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1959
1960                 if (unlikely((mb->data_len + hw->rx_offset) >
1961                              rxq->mbuf_size)) {
1962                         /*
1963                          * This should not happen and the user has the
1964                          * responsibility of avoiding it. But we have
1965                          * to give some info about the error
1966                          */
1967                         RTE_LOG_DP(ERR, PMD,
1968                                 "mbuf overflow likely due to the RX offset.\n"
1969                                 "\t\tYour mbuf size should have extra space for"
1970                                 " RX offset=%u bytes.\n"
1971                                 "\t\tCurrently you just have %u bytes available"
1972                                 " but the received packet is %u bytes long",
1973                                 hw->rx_offset,
1974                                 rxq->mbuf_size - hw->rx_offset,
1975                                 mb->data_len);
1976                         return -EINVAL;
1977                 }
1978
1979                 /* Filling the received mbuff with packet info */
1980                 if (hw->rx_offset)
1981                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1982                 else
1983                         mb->data_off = RTE_PKTMBUF_HEADROOM +
1984                                        NFP_DESC_META_LEN(rxds);
1985
1986                 /* No scatter mode supported */
1987                 mb->nb_segs = 1;
1988                 mb->next = NULL;
1989
1990                 /* Checking the RSS flag */
1991                 nfp_net_set_hash(rxq, rxds, mb);
1992
1993                 /* Checking the checksum flag */
1994                 nfp_net_rx_cksum(rxq, rxds, mb);
1995
1996                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1997                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1998                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1999                         mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
2000                 }
2001
2002                 /* Adding the mbuff to the mbuff array passed by the app */
2003                 rx_pkts[avail++] = mb;
2004
2005                 /* Now resetting and updating the descriptor */
2006                 rxds->vals[0] = 0;
2007                 rxds->vals[1] = 0;
2008                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2009                 rxds->fld.dd = 0;
2010                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2011                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2012
2013                 rxq->rd_p++;
2014                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2015                         rxq->rd_p = 0;
2016         }
2017
2018         if (nb_hold == 0)
2019                 return nb_hold;
2020
2021         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2022                    (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
2023
2024         nb_hold += rxq->nb_rx_hold;
2025
2026         /*
2027          * FL descriptors needs to be written before incrementing the
2028          * FL queue WR pointer
2029          */
2030         rte_wmb();
2031         if (nb_hold > rxq->rx_free_thresh) {
2032                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2033                            (unsigned)rxq->port_id, (unsigned)rxq->qidx,
2034                            (unsigned)nb_hold, (unsigned)avail);
2035                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2036                 nb_hold = 0;
2037         }
2038         rxq->nb_rx_hold = nb_hold;
2039
2040         return avail;
2041 }
2042
2043 /*
2044  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2045  * status
2046  * @txq: TX queue to work with
2047  * Returns number of descriptors freed
2048  */
2049 int
2050 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2051 {
2052         uint32_t qcp_rd_p;
2053         int todo;
2054
2055         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2056                    " status\n", txq->qidx);
2057
2058         /* Work out how many packets have been sent */
2059         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2060
2061         if (qcp_rd_p == txq->rd_p) {
2062                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2063                            "packets (%u, %u)\n", txq->qidx,
2064                            qcp_rd_p, txq->rd_p);
2065                 return 0;
2066         }
2067
2068         if (qcp_rd_p > txq->rd_p)
2069                 todo = qcp_rd_p - txq->rd_p;
2070         else
2071                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2072
2073         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2074                    qcp_rd_p, txq->rd_p, txq->rd_p);
2075
2076         if (todo == 0)
2077                 return todo;
2078
2079         txq->rd_p += todo;
2080         if (unlikely(txq->rd_p >= txq->tx_count))
2081                 txq->rd_p -= txq->tx_count;
2082
2083         return todo;
2084 }
2085
2086 /* Leaving always free descriptors for avoiding wrapping confusion */
2087 static inline
2088 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2089 {
2090         if (txq->wr_p >= txq->rd_p)
2091                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2092         else
2093                 return txq->rd_p - txq->wr_p - 8;
2094 }
2095
2096 /*
2097  * nfp_net_txq_full - Check if the TX queue free descriptors
2098  * is below tx_free_threshold
2099  *
2100  * @txq: TX queue to check
2101  *
2102  * This function uses the host copy* of read/write pointers
2103  */
2104 static inline
2105 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2106 {
2107         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2108 }
2109
2110 static uint16_t
2111 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2112 {
2113         struct nfp_net_txq *txq;
2114         struct nfp_net_hw *hw;
2115         struct nfp_net_tx_desc *txds, txd;
2116         struct rte_mbuf *pkt;
2117         uint64_t dma_addr;
2118         int pkt_size, dma_size;
2119         uint16_t free_descs, issued_descs;
2120         struct rte_mbuf **lmbuf;
2121         int i;
2122
2123         txq = tx_queue;
2124         hw = txq->hw;
2125         txds = &txq->txds[txq->wr_p];
2126
2127         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2128                    txq->qidx, txq->wr_p, nb_pkts);
2129
2130         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2131                 nfp_net_tx_free_bufs(txq);
2132
2133         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2134         if (unlikely(free_descs == 0))
2135                 return 0;
2136
2137         pkt = *tx_pkts;
2138
2139         i = 0;
2140         issued_descs = 0;
2141         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2142                    txq->qidx, nb_pkts);
2143         /* Sending packets */
2144         while ((i < nb_pkts) && free_descs) {
2145                 /* Grabbing the mbuf linked to the current descriptor */
2146                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2147                 /* Warming the cache for releasing the mbuf later on */
2148                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2149
2150                 pkt = *(tx_pkts + i);
2151
2152                 if (unlikely((pkt->nb_segs > 1) &&
2153                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2154                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2155                         rte_panic("Multisegment packet unsupported\n");
2156                 }
2157
2158                 /* Checking if we have enough descriptors */
2159                 if (unlikely(pkt->nb_segs > free_descs))
2160                         goto xmit_end;
2161
2162                 /*
2163                  * Checksum and VLAN flags just in the first descriptor for a
2164                  * multisegment packet, but TSO info needs to be in all of them.
2165                  */
2166                 txd.data_len = pkt->pkt_len;
2167                 nfp_net_tx_tso(txq, &txd, pkt);
2168                 nfp_net_tx_cksum(txq, &txd, pkt);
2169
2170                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2171                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2172                         txd.flags |= PCIE_DESC_TX_VLAN;
2173                         txd.vlan = pkt->vlan_tci;
2174                 }
2175
2176                 /*
2177                  * mbuf data_len is the data in one segment and pkt_len data
2178                  * in the whole packet. When the packet is just one segment,
2179                  * then data_len = pkt_len
2180                  */
2181                 pkt_size = pkt->pkt_len;
2182
2183                 while (pkt) {
2184                         /* Copying TSO, VLAN and cksum info */
2185                         *txds = txd;
2186
2187                         /* Releasing mbuf used by this descriptor previously*/
2188                         if (*lmbuf)
2189                                 rte_pktmbuf_free_seg(*lmbuf);
2190
2191                         /*
2192                          * Linking mbuf with descriptor for being released
2193                          * next time descriptor is used
2194                          */
2195                         *lmbuf = pkt;
2196
2197                         dma_size = pkt->data_len;
2198                         dma_addr = rte_mbuf_data_dma_addr(pkt);
2199                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2200                                    "%" PRIx64 "\n", dma_addr);
2201
2202                         /* Filling descriptors fields */
2203                         txds->dma_len = dma_size;
2204                         txds->data_len = txd.data_len;
2205                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2206                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2207                         ASSERT(free_descs > 0);
2208                         free_descs--;
2209
2210                         txq->wr_p++;
2211                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2212                                 txq->wr_p = 0;
2213
2214                         pkt_size -= dma_size;
2215                         if (!pkt_size)
2216                                 /* End of packet */
2217                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2218                         else
2219                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2220
2221                         pkt = pkt->next;
2222                         /* Referencing next free TX descriptor */
2223                         txds = &txq->txds[txq->wr_p];
2224                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2225                         issued_descs++;
2226                 }
2227                 i++;
2228         }
2229
2230 xmit_end:
2231         /* Increment write pointers. Force memory write before we let HW know */
2232         rte_wmb();
2233         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2234
2235         return i;
2236 }
2237
2238 static void
2239 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2240 {
2241         uint32_t new_ctrl, update;
2242         struct nfp_net_hw *hw;
2243
2244         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245         new_ctrl = 0;
2246
2247         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2248             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2249                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2250                         " ETH_VLAN_EXTEND_OFFLOAD");
2251
2252         /* Enable vlan strip if it is not configured yet */
2253         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2254             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2255                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2256
2257         /* Disable vlan strip just if it is configured */
2258         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2259             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2260                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2261
2262         if (new_ctrl == 0)
2263                 return;
2264
2265         update = NFP_NET_CFG_UPDATE_GEN;
2266
2267         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2268                 return;
2269
2270         hw->ctrl = new_ctrl;
2271 }
2272
2273 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2274 static int
2275 nfp_net_reta_update(struct rte_eth_dev *dev,
2276                     struct rte_eth_rss_reta_entry64 *reta_conf,
2277                     uint16_t reta_size)
2278 {
2279         uint32_t reta, mask;
2280         int i, j;
2281         int idx, shift;
2282         uint32_t update;
2283         struct nfp_net_hw *hw =
2284                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285
2286         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2287                 return -EINVAL;
2288
2289         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2290                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2291                         "(%d) doesn't match the number hardware can supported "
2292                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2293                 return -EINVAL;
2294         }
2295
2296         /*
2297          * Update Redirection Table. There are 128 8bit-entries which can be
2298          * manage as 32 32bit-entries
2299          */
2300         for (i = 0; i < reta_size; i += 4) {
2301                 /* Handling 4 RSS entries per loop */
2302                 idx = i / RTE_RETA_GROUP_SIZE;
2303                 shift = i % RTE_RETA_GROUP_SIZE;
2304                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2305
2306                 if (!mask)
2307                         continue;
2308
2309                 reta = 0;
2310                 /* If all 4 entries were set, don't need read RETA register */
2311                 if (mask != 0xF)
2312                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2313
2314                 for (j = 0; j < 4; j++) {
2315                         if (!(mask & (0x1 << j)))
2316                                 continue;
2317                         if (mask != 0xF)
2318                                 /* Clearing the entry bits */
2319                                 reta &= ~(0xFF << (8 * j));
2320                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2321                 }
2322                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2323                               reta);
2324         }
2325
2326         update = NFP_NET_CFG_UPDATE_RSS;
2327
2328         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2329                 return -EIO;
2330
2331         return 0;
2332 }
2333
2334  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2335 static int
2336 nfp_net_reta_query(struct rte_eth_dev *dev,
2337                    struct rte_eth_rss_reta_entry64 *reta_conf,
2338                    uint16_t reta_size)
2339 {
2340         uint8_t i, j, mask;
2341         int idx, shift;
2342         uint32_t reta;
2343         struct nfp_net_hw *hw;
2344
2345         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346
2347         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2348                 return -EINVAL;
2349
2350         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2351                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2352                         "(%d) doesn't match the number hardware can supported "
2353                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2354                 return -EINVAL;
2355         }
2356
2357         /*
2358          * Reading Redirection Table. There are 128 8bit-entries which can be
2359          * manage as 32 32bit-entries
2360          */
2361         for (i = 0; i < reta_size; i += 4) {
2362                 /* Handling 4 RSS entries per loop */
2363                 idx = i / RTE_RETA_GROUP_SIZE;
2364                 shift = i % RTE_RETA_GROUP_SIZE;
2365                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2366
2367                 if (!mask)
2368                         continue;
2369
2370                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2371                                     shift);
2372                 for (j = 0; j < 4; j++) {
2373                         if (!(mask & (0x1 << j)))
2374                                 continue;
2375                         reta_conf->reta[shift + j] =
2376                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2377                 }
2378         }
2379         return 0;
2380 }
2381
2382 static int
2383 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2384                         struct rte_eth_rss_conf *rss_conf)
2385 {
2386         uint32_t update;
2387         uint32_t cfg_rss_ctrl = 0;
2388         uint8_t key;
2389         uint64_t rss_hf;
2390         int i;
2391         struct nfp_net_hw *hw;
2392
2393         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394
2395         rss_hf = rss_conf->rss_hf;
2396
2397         /* Checking if RSS is enabled */
2398         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2399                 if (rss_hf != 0) { /* Enable RSS? */
2400                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2401                         return -EINVAL;
2402                 }
2403                 return 0; /* Nothing to do */
2404         }
2405
2406         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2407                 RTE_LOG(ERR, PMD, "hash key too long\n");
2408                 return -EINVAL;
2409         }
2410
2411         if (rss_hf & ETH_RSS_IPV4)
2412                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2413                                 NFP_NET_CFG_RSS_IPV4_TCP |
2414                                 NFP_NET_CFG_RSS_IPV4_UDP;
2415
2416         if (rss_hf & ETH_RSS_IPV6)
2417                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2418                                 NFP_NET_CFG_RSS_IPV6_TCP |
2419                                 NFP_NET_CFG_RSS_IPV6_UDP;
2420
2421         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2422         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2423
2424         /* configuring where to apply the RSS hash */
2425         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2426
2427         /* Writing the key byte a byte */
2428         for (i = 0; i < rss_conf->rss_key_len; i++) {
2429                 memcpy(&key, &rss_conf->rss_key[i], 1);
2430                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2431         }
2432
2433         /* Writing the key size */
2434         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2435
2436         update = NFP_NET_CFG_UPDATE_RSS;
2437
2438         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2439                 return -EIO;
2440
2441         return 0;
2442 }
2443
2444 static int
2445 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2446                           struct rte_eth_rss_conf *rss_conf)
2447 {
2448         uint64_t rss_hf;
2449         uint32_t cfg_rss_ctrl;
2450         uint8_t key;
2451         int i;
2452         struct nfp_net_hw *hw;
2453
2454         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455
2456         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2457                 return -EINVAL;
2458
2459         rss_hf = rss_conf->rss_hf;
2460         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2461
2462         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2463                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2464
2465         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2466                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2467
2468         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2469                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2470
2471         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2472                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2473
2474         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2475                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2476
2477         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2478                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2479
2480         /* Reading the key size */
2481         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2482
2483         /* Reading the key byte a byte */
2484         for (i = 0; i < rss_conf->rss_key_len; i++) {
2485                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2486                 memcpy(&rss_conf->rss_key[i], &key, 1);
2487         }
2488
2489         return 0;
2490 }
2491
2492 /* Initialise and register driver with DPDK Application */
2493 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2494         .dev_configure          = nfp_net_configure,
2495         .dev_start              = nfp_net_start,
2496         .dev_stop               = nfp_net_stop,
2497         .dev_close              = nfp_net_close,
2498         .promiscuous_enable     = nfp_net_promisc_enable,
2499         .promiscuous_disable    = nfp_net_promisc_disable,
2500         .link_update            = nfp_net_link_update,
2501         .stats_get              = nfp_net_stats_get,
2502         .stats_reset            = nfp_net_stats_reset,
2503         .dev_infos_get          = nfp_net_infos_get,
2504         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2505         .mtu_set                = nfp_net_dev_mtu_set,
2506         .vlan_offload_set       = nfp_net_vlan_offload_set,
2507         .reta_update            = nfp_net_reta_update,
2508         .reta_query             = nfp_net_reta_query,
2509         .rss_hash_update        = nfp_net_rss_hash_update,
2510         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2511         .rx_queue_setup         = nfp_net_rx_queue_setup,
2512         .rx_queue_release       = nfp_net_rx_queue_release,
2513         .rx_queue_count         = nfp_net_rx_queue_count,
2514         .tx_queue_setup         = nfp_net_tx_queue_setup,
2515         .tx_queue_release       = nfp_net_tx_queue_release,
2516         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2517         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2518 };
2519
2520 /*
2521  * All eth_dev created got its private data, but before nfp_net_init, that
2522  * private data is referencing private data for all the PF ports. This is due
2523  * to how the vNIC bars are mapped based on first port, so all ports need info
2524  * about port 0 private data. Inside nfp_net_init the private data pointer is
2525  * changed to the right address for each port once the bars have been mapped.
2526  *
2527  * This functions helps to find out which port and therefore which offset
2528  * inside the private data array to use.
2529  */
2530 static int
2531 get_pf_port_number(char *name)
2532 {
2533         char *pf_str = name;
2534         int size = 0;
2535
2536         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2537                 pf_str++;
2538
2539         if (size == 30)
2540                 /*
2541                  * This should not happen at all and it would mean major
2542                  * implementation fault.
2543                  */
2544                 rte_panic("nfp_net: problem with pf device name\n");
2545
2546         /* Expecting _portX with X within [0,7] */
2547         pf_str += 5;
2548
2549         return (int)strtol(pf_str, NULL, 10);
2550 }
2551
2552 static int
2553 nfp_net_init(struct rte_eth_dev *eth_dev)
2554 {
2555         struct rte_pci_device *pci_dev;
2556         struct nfp_net_hw *hw, *hwport0;
2557
2558         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2559         uint32_t start_q;
2560         int stride = 4;
2561
2562         nspu_desc_t *nspu_desc = NULL;
2563         uint64_t bar_offset;
2564         int port = 0;
2565
2566         PMD_INIT_FUNC_TRACE();
2567
2568         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2569
2570         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2571             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2572                 port = get_pf_port_number(eth_dev->data->name);
2573                 if (port < 0 || port > 7) {
2574                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2575                         return -ENODEV;
2576                 }
2577
2578                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2579
2580                 /* This points to port 0 private data */
2581                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2582
2583                 /* This points to the specific port private data */
2584                 hw = &hwport0[port];
2585                 hw->pf_port_idx = port;
2586         } else {
2587                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2588                 hwport0 = 0;
2589         }
2590
2591         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2592         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2593         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2594
2595         /* For secondary processes, the primary has done all the work */
2596         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2597                 return 0;
2598
2599         rte_eth_copy_pci_info(eth_dev, pci_dev);
2600         /* hotplug is not possible with multiport PF */
2601         if (!hw->pf_multiport_enabled)
2602                 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2603
2604         hw->device_id = pci_dev->id.device_id;
2605         hw->vendor_id = pci_dev->id.vendor_id;
2606         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2607         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2608
2609         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2610                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2611                      pci_dev->addr.domain, pci_dev->addr.bus,
2612                      pci_dev->addr.devid, pci_dev->addr.function);
2613
2614         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2615         if (hw->ctrl_bar == NULL) {
2616                 RTE_LOG(ERR, PMD,
2617                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2618                 return -ENODEV;
2619         }
2620
2621         if (hw->is_pf && port == 0) {
2622                 nspu_desc = hw->nspu_desc;
2623
2624                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2625                         /*
2626                          * A firmware should be there after PF probe so this
2627                          * should not happen.
2628                          */
2629                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2630                         return -ENODEV;
2631                 }
2632
2633                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2634                 hw->ctrl_bar += bar_offset;
2635                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2636         }
2637
2638         if (port > 0) {
2639                 if (!hwport0->ctrl_bar)
2640                         return -ENODEV;
2641
2642                 /* address based on port0 offset */
2643                 hw->ctrl_bar = hwport0->ctrl_bar +
2644                                (port * NFP_PF_CSR_SLICE_SIZE);
2645         }
2646
2647         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2648
2649         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2650         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2651
2652         /* Work out where in the BAR the queues start. */
2653         switch (pci_dev->id.device_id) {
2654         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2655         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2656         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2657                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2658                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2659                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2660                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2661                 break;
2662         default:
2663                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2664                 return -ENODEV;
2665         }
2666
2667         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2668         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2669
2670         if (hw->is_pf && port == 0) {
2671                 /* configure access to tx/rx vNIC BARs */
2672                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2673                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2674                                     bar_offset);
2675                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2676
2677                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2678                 hwport0->hw_queues += bar_offset;
2679         }
2680
2681         if (hw->is_pf) {
2682                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2683                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2684                 eth_dev->data->dev_private = hw;
2685         } else {
2686                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2687                              tx_bar_off;
2688                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2689                              rx_bar_off;
2690         }
2691
2692         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2693                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2694
2695         nfp_net_cfg_queue_setup(hw);
2696
2697         /* Get some of the read-only fields from the config BAR */
2698         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2699         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2700         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2701         hw->mtu = hw->max_mtu;
2702
2703         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2704                 hw->rx_offset = NFP_NET_RX_OFFSET;
2705         else
2706                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2707
2708         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2709                      hw->ver, hw->max_mtu);
2710         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2711                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2712                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2713                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2714                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2715                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2716                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2717                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2718                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2719                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2720
2721         hw->ctrl = 0;
2722
2723         hw->stride_rx = stride;
2724         hw->stride_tx = stride;
2725
2726         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2727                      hw->max_rx_queues, hw->max_tx_queues);
2728
2729         /* Initializing spinlock for reconfigs */
2730         rte_spinlock_init(&hw->reconfig_lock);
2731
2732         /* Allocating memory for mac addr */
2733         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2734         if (eth_dev->data->mac_addrs == NULL) {
2735                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2736                 return -ENOMEM;
2737         }
2738
2739         nfp_net_read_mac(hw);
2740
2741         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2742                 /* Using random mac addresses for VFs */
2743                 eth_random_addr(&hw->mac_addr[0]);
2744                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2745         }
2746
2747         /* Copying mac address to DPDK eth_dev struct */
2748         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2749                         &eth_dev->data->mac_addrs[0]);
2750
2751         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2752                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2753                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2754                      pci_dev->id.device_id,
2755                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2756                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2757
2758         /* Registering LSC interrupt handler */
2759         rte_intr_callback_register(&pci_dev->intr_handle,
2760                                    nfp_net_dev_interrupt_handler,
2761                                    (void *)eth_dev);
2762
2763         /* Telling the firmware about the LSC interrupt entry */
2764         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2765
2766         /* Recording current stats counters values */
2767         nfp_net_stats_reset(eth_dev);
2768
2769         return 0;
2770 }
2771
2772 static int
2773 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2774                   nfpu_desc_t *nfpu_desc, void **priv)
2775 {
2776         struct rte_eth_dev *eth_dev;
2777         struct nfp_net_hw *hw;
2778         char *port_name;
2779         int ret;
2780
2781         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2782         if (!port_name)
2783                 return -ENOMEM;
2784
2785         if (ports > 1)
2786                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2787         else
2788                 sprintf(port_name, "%s", dev->device.name);
2789
2790         eth_dev = rte_eth_dev_allocate(port_name);
2791         if (!eth_dev)
2792                 return -ENOMEM;
2793
2794         if (port == 0) {
2795                 *priv = rte_zmalloc(port_name,
2796                                     sizeof(struct nfp_net_adapter) * ports,
2797                                     RTE_CACHE_LINE_SIZE);
2798                 if (!*priv) {
2799                         rte_eth_dev_release_port(eth_dev);
2800                         return -ENOMEM;
2801                 }
2802         }
2803
2804         eth_dev->data->dev_private = *priv;
2805
2806         /*
2807          * dev_private pointing to port0 dev_private because we need
2808          * to configure vNIC bars based on port0 at nfp_net_init.
2809          * Then dev_private is adjusted per port.
2810          */
2811         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2812         hw->nspu_desc = nfpu_desc->nspu;
2813         hw->nfpu_desc = nfpu_desc;
2814         hw->is_pf = 1;
2815         if (ports > 1)
2816                 hw->pf_multiport_enabled = 1;
2817
2818         eth_dev->device = &dev->device;
2819         rte_eth_copy_pci_info(eth_dev, dev);
2820
2821         ret = nfp_net_init(eth_dev);
2822
2823         if (ret)
2824                 rte_eth_dev_release_port(eth_dev);
2825
2826         rte_free(port_name);
2827
2828         return ret;
2829 }
2830
2831 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2832                             struct rte_pci_device *dev)
2833 {
2834         nfpu_desc_t *nfpu_desc;
2835         nspu_desc_t *nspu_desc;
2836         uint64_t offset_symbol;
2837         uint8_t *bar_offset;
2838         int major, minor;
2839         int total_ports;
2840         void *priv = 0;
2841         int ret = -ENODEV;
2842         int i;
2843
2844         if (!dev)
2845                 return ret;
2846
2847         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2848         if (!nfpu_desc)
2849                 return -ENOMEM;
2850
2851         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2852                 RTE_LOG(ERR, PMD,
2853                         "nfpu_open failed\n");
2854                 goto nfpu_error;
2855         }
2856
2857         nspu_desc = nfpu_desc->nspu;
2858
2859
2860         /* Check NSP ABI version */
2861         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2862                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2863                 goto error;
2864         }
2865         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2866
2867         if ((major == 0) && (minor < 20)) {
2868                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2869                 goto error;
2870         }
2871
2872         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2873                                &offset_symbol);
2874         if (ret)
2875                 goto error;
2876
2877         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2878         bar_offset += offset_symbol;
2879         total_ports = (uint32_t)*bar_offset;
2880         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2881
2882         if (total_ports <= 0 || total_ports > 8) {
2883                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2884                 ret = -ENODEV;
2885                 goto error;
2886         }
2887
2888         for (i = 0; i < total_ports; i++) {
2889                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2890                 if (ret)
2891                         goto error;
2892         }
2893
2894         return 0;
2895
2896 error:
2897         nfpu_close(nfpu_desc);
2898 nfpu_error:
2899         rte_free(nfpu_desc);
2900
2901         return ret;
2902 }
2903
2904 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2905         {
2906                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2907                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2908         },
2909         {
2910                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2911                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2912         },
2913         {
2914                 .vendor_id = 0,
2915         },
2916 };
2917
2918 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2919         {
2920                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2921                                PCI_DEVICE_ID_NFP6000_VF_NIC)
2922         },
2923         {
2924                 .vendor_id = 0,
2925         },
2926 };
2927
2928 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2929         struct rte_pci_device *pci_dev)
2930 {
2931         return rte_eth_dev_pci_generic_probe(pci_dev,
2932                 sizeof(struct nfp_net_adapter), nfp_net_init);
2933 }
2934
2935 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2936 {
2937         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2938 }
2939
2940 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
2941         .id_table = pci_id_nfp_pf_net_map,
2942         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2943         .probe = nfp_pf_pci_probe,
2944         .remove = eth_nfp_pci_remove,
2945 };
2946
2947 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
2948         .id_table = pci_id_nfp_vf_net_map,
2949         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2950         .probe = eth_nfp_pci_probe,
2951         .remove = eth_nfp_pci_remove,
2952 };
2953
2954 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
2955 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
2956 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
2957 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
2958 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
2959 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
2960
2961 /*
2962  * Local variables:
2963  * c-file-style: "Linux"
2964  * indent-tabs-mode: t
2965  * End:
2966  */