drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfpcore/nfp_cpp.h"
  59 #include "nfpcore/nfp_nffw.h"
  60 #include "nfpcore/nfp_hwinfo.h"
  61 #include "nfpcore/nfp_mip.h"
  62 #include "nfpcore/nfp_rtsym.h"
  63 #include "nfpcore/nfp_nsp.h"
  64
  65 #include "nfp_net_pmd.h"
  66 #include "nfp_net_logs.h"
  67 #include "nfp_net_ctrl.h"
  68
  69 /* Prototypes */
  70 static void nfp_net_close(struct rte_eth_dev *dev);
  71 static int nfp_net_configure(struct rte_eth_dev *dev);
  72 static void nfp_net_dev_interrupt_handler(void *param);
  73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  76                               struct rte_eth_dev_info *dev_info);
  77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  83                                        uint16_t queue_idx);
  84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  85                                   uint16_t nb_pkts);
  86 static void nfp_net_rx_queue_release(void *rxq);
  87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_rxconf *rx_conf,
  90                                   struct rte_mempool *mp);
  91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  92 static void nfp_net_tx_queue_release(void *txq);
  93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  94                                   uint16_t nb_desc, unsigned int socket_id,
  95                                   const struct rte_eth_txconf *tx_conf);
  96 static int nfp_net_start(struct rte_eth_dev *dev);
  97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  98                               struct rte_eth_stats *stats);
  99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 100 static void nfp_net_stop(struct rte_eth_dev *dev);
 101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 102                                   uint16_t nb_pkts);
 103
 104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 106                                    struct rte_eth_rss_conf *rss_conf);
 107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 108                     struct rte_eth_rss_reta_entry64 *reta_conf,
 109                     uint16_t reta_size);
 110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 111                         struct rte_eth_rss_conf *rss_conf);
 112
 113 /* The offset of the queue controller queues in the PCIe Target */
 114 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 115
 116 /* Maximum value which can be added to a queue with one transaction */
 117 #define NFP_QCP_MAX_ADD 0x7f
 118
 119 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 120         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 121
 122 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 123 enum nfp_qcp_ptr {
 124         NFP_QCP_READ_PTR = 0,
 125         NFP_QCP_WRITE_PTR
 126 };
 127
 128 /*
 129  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 130  * @q: Base address for queue structure
 131  * @ptr: Add to the Read or Write pointer
 132  * @val: Value to add to the queue pointer
 133  *
 134  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 135  */
 136 static inline void
 137 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 138 {
 139         uint32_t off;
 140
 141         if (ptr == NFP_QCP_READ_PTR)
 142                 off = NFP_QCP_QUEUE_ADD_RPTR;
 143         else
 144                 off = NFP_QCP_QUEUE_ADD_WPTR;
 145
 146         while (val > NFP_QCP_MAX_ADD) {
 147                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 148                 val -= NFP_QCP_MAX_ADD;
 149         }
 150
 151         nn_writel(rte_cpu_to_le_32(val), q + off);
 152 }
 153
 154 /*
 155  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 156  * @q:  Base address for queue structure
 157  * @ptr: Read or Write pointer
 158  */
 159 static inline uint32_t
 160 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 161 {
 162         uint32_t off;
 163         uint32_t val;
 164
 165         if (ptr == NFP_QCP_READ_PTR)
 166                 off = NFP_QCP_QUEUE_STS_LO;
 167         else
 168                 off = NFP_QCP_QUEUE_STS_HI;
 169
 170         val = rte_cpu_to_le_32(nn_readl(q + off));
 171
 172         if (ptr == NFP_QCP_READ_PTR)
 173                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 174         else
 175                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 176 }
 177
 178 /*
 179  * Functions to read/write from/to Config BAR
 180  * Performs any endian conversion necessary.
 181  */
 182 static inline uint8_t
 183 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 184 {
 185         return nn_readb(hw->ctrl_bar + off);
 186 }
 187
 188 static inline void
 189 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 190 {
 191         nn_writeb(val, hw->ctrl_bar + off);
 192 }
 193
 194 static inline uint32_t
 195 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 196 {
 197         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 198 }
 199
 200 static inline void
 201 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 202 {
 203         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 204 }
 205
 206 static inline uint64_t
 207 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 208 {
 209         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 210 }
 211
 212 static inline void
 213 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 214 {
 215         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 216 }
 217
 218 static void
 219 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 220 {
 221         unsigned i;
 222
 223         if (rxq->rxbufs == NULL)
 224                 return;
 225
 226         for (i = 0; i < rxq->rx_count; i++) {
 227                 if (rxq->rxbufs[i].mbuf) {
 228                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 229                         rxq->rxbufs[i].mbuf = NULL;
 230                 }
 231         }
 232 }
 233
 234 static void
 235 nfp_net_rx_queue_release(void *rx_queue)
 236 {
 237         struct nfp_net_rxq *rxq = rx_queue;
 238
 239         if (rxq) {
 240                 nfp_net_rx_queue_release_mbufs(rxq);
 241                 rte_free(rxq->rxbufs);
 242                 rte_free(rxq);
 243         }
 244 }
 245
 246 static void
 247 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 248 {
 249         nfp_net_rx_queue_release_mbufs(rxq);
 250         rxq->rd_p = 0;
 251         rxq->nb_rx_hold = 0;
 252 }
 253
 254 static void
 255 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 256 {
 257         unsigned i;
 258
 259         if (txq->txbufs == NULL)
 260                 return;
 261
 262         for (i = 0; i < txq->tx_count; i++) {
 263                 if (txq->txbufs[i].mbuf) {
 264                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 265                         txq->txbufs[i].mbuf = NULL;
 266                 }
 267         }
 268 }
 269
 270 static void
 271 nfp_net_tx_queue_release(void *tx_queue)
 272 {
 273         struct nfp_net_txq *txq = tx_queue;
 274
 275         if (txq) {
 276                 nfp_net_tx_queue_release_mbufs(txq);
 277                 rte_free(txq->txbufs);
 278                 rte_free(txq);
 279         }
 280 }
 281
 282 static void
 283 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 284 {
 285         nfp_net_tx_queue_release_mbufs(txq);
 286         txq->wr_p = 0;
 287         txq->rd_p = 0;
 288 }
 289
 290 static int
 291 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 292 {
 293         int cnt;
 294         uint32_t new;
 295         struct timespec wait;
 296
 297         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 298                     hw->qcp_cfg);
 299
 300         if (hw->qcp_cfg == NULL)
 301                 rte_panic("Bad configuration queue pointer\n");
 302
 303         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 304
 305         wait.tv_sec = 0;
 306         wait.tv_nsec = 1000000;
 307
 308         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 309
 310         /* Poll update field, waiting for NFP to ack the config */
 311         for (cnt = 0; ; cnt++) {
 312                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 313                 if (new == 0)
 314                         break;
 315                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 316                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 317                         return -1;
 318                 }
 319                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 320                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 321                                           " %dms", update, cnt);
 322                         rte_panic("Exiting\n");
 323                 }
 324                 nanosleep(&wait, 0); /* waiting for a 1ms */
 325         }
 326         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 327         return 0;
 328 }
 329
 330 /*
 331  * Reconfigure the NIC
 332  * @nn:    device to reconfigure
 333  * @ctrl:    The value for the ctrl field in the BAR config
 334  * @update:  The value for the update field in the BAR config
 335  *
 336  * Write the update word to the BAR and ping the reconfig queue. Then poll
 337  * until the firmware has acknowledged the update by zeroing the update word.
 338  */
 339 static int
 340 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 341 {
 342         uint32_t err;
 343
 344         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 345                     ctrl, update);
 346
 347         rte_spinlock_lock(&hw->reconfig_lock);
 348
 349         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 350         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 351
 352         rte_wmb();
 353
 354         err = __nfp_net_reconfig(hw, update);
 355
 356         rte_spinlock_unlock(&hw->reconfig_lock);
 357
 358         if (!err)
 359                 return 0;
 360
 361         /*
 362          * Reconfig errors imply situations where they can be handled.
 363          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 364          */
 365         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 366                      ctrl, update);
 367         return -EIO;
 368 }
 369
 370 /*
 371  * Configure an Ethernet device. This function must be invoked first
 372  * before any other function in the Ethernet API. This function can
 373  * also be re-invoked when a device is in the stopped state.
 374  */
 375 static int
 376 nfp_net_configure(struct rte_eth_dev *dev)
 377 {
 378         struct rte_eth_conf *dev_conf;
 379         struct rte_eth_rxmode *rxmode;
 380         struct rte_eth_txmode *txmode;
 381         struct nfp_net_hw *hw;
 382
 383         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 384
 385         /*
 386          * A DPDK app sends info about how many queues to use and how
 387          * those queues need to be configured. This is used by the
 388          * DPDK core and it makes sure no more queues than those
 389          * advertised by the driver are requested. This function is
 390          * called after that internal process
 391          */
 392
 393         PMD_INIT_LOG(DEBUG, "Configure");
 394
 395         dev_conf = &dev->data->dev_conf;
 396         rxmode = &dev_conf->rxmode;
 397         txmode = &dev_conf->txmode;
 398
 399         /* Checking TX mode */
 400         if (txmode->mq_mode) {
 401                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 402                 return -EINVAL;
 403         }
 404
 405         /* Checking RX mode */
 406         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 407             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 408                 PMD_INIT_LOG(INFO, "RSS not supported");
 409                 return -EINVAL;
 410         }
 411
 412         /* Checking RX offloads */
 413         if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT) {
 414                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 415                 return -EINVAL;
 416         }
 417
 418         if ((rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) &&
 419             !(hw->cap & NFP_NET_CFG_CTRL_RXCSUM))
 420                 PMD_INIT_LOG(INFO, "RXCSUM not supported");
 421
 422         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 423                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 424                 return -EINVAL;
 425         }
 426
 427         if ((rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) &&
 428             !(hw->cap & NFP_NET_CFG_CTRL_RXVLAN)) {
 429                 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 430                 return -EINVAL;
 431         }
 432
 433         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
 434                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 435                 return -EINVAL;
 436         }
 437
 438         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
 439                 PMD_INIT_LOG(INFO, "LRO not supported");
 440                 return -EINVAL;
 441         }
 442
 443         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP) {
 444                 PMD_INIT_LOG(INFO, "QINQ STRIP not supported");
 445                 return -EINVAL;
 446         }
 447
 448         if (rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) {
 449                 PMD_INIT_LOG(INFO, "Outer IP checksum not supported");
 450                 return -EINVAL;
 451         }
 452
 453         if (rxmode->offloads & DEV_RX_OFFLOAD_MACSEC_STRIP) {
 454                 PMD_INIT_LOG(INFO, "MACSEC strip not supported");
 455                 return -EINVAL;
 456         }
 457
 458         if (rxmode->offloads & DEV_RX_OFFLOAD_MACSEC_STRIP) {
 459                 PMD_INIT_LOG(INFO, "MACSEC strip not supported");
 460                 return -EINVAL;
 461         }
 462
 463         if (!(rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP))
 464                 PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!");
 465
 466         if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) &&
 467             !(hw->cap & NFP_NET_CFG_CTRL_SCATTER)) {
 468                 PMD_INIT_LOG(INFO, "Scatter not supported");
 469                 return -EINVAL;
 470         }
 471
 472         if (rxmode->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
 473                 PMD_INIT_LOG(INFO, "timestamp offfload not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->offloads & DEV_RX_OFFLOAD_SECURITY) {
 478                 PMD_INIT_LOG(INFO, "security offload not supported");
 479                 return -EINVAL;
 480         }
 481
 482         /* checking TX offloads */
 483         if ((txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) &&
 484             !(hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
 485                 PMD_INIT_LOG(INFO, "vlan insert offload not supported");
 486                 return -EINVAL;
 487         }
 488
 489         if ((txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) &&
 490             !(hw->cap & NFP_NET_CFG_CTRL_TXCSUM)) {
 491                 PMD_INIT_LOG(INFO, "TX checksum offload not supported");
 492                 return -EINVAL;
 493         }
 494
 495         if (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) {
 496                 PMD_INIT_LOG(INFO, "TX SCTP checksum offload not supported");
 497                 return -EINVAL;
 498         }
 499
 500         if ((txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) &&
 501             !(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)) {
 502                 PMD_INIT_LOG(INFO, "TSO TCP offload not supported");
 503                 return -EINVAL;
 504         }
 505
 506         if (txmode->offloads & DEV_TX_OFFLOAD_UDP_TSO) {
 507                 PMD_INIT_LOG(INFO, "TSO UDP offload not supported");
 508                 return -EINVAL;
 509         }
 510
 511         if (txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) {
 512                 PMD_INIT_LOG(INFO, "TX outer checksum offload not supported");
 513                 return -EINVAL;
 514         }
 515
 516         if (txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) {
 517                 PMD_INIT_LOG(INFO, "QINQ insert offload not supported");
 518                 return -EINVAL;
 519         }
 520
 521         if (txmode->offloads & DEV_TX_OFFLOAD_VXLAN_TNL_TSO ||
 522             txmode->offloads & DEV_TX_OFFLOAD_GRE_TNL_TSO ||
 523             txmode->offloads & DEV_TX_OFFLOAD_IPIP_TNL_TSO ||
 524             txmode->offloads & DEV_TX_OFFLOAD_GENEVE_TNL_TSO) {
 525                 PMD_INIT_LOG(INFO, "tunneling offload not supported");
 526                 return -EINVAL;
 527         }
 528
 529         if (txmode->offloads & DEV_TX_OFFLOAD_MACSEC_INSERT) {
 530                 PMD_INIT_LOG(INFO, "TX MACSEC offload not supported");
 531                 return -EINVAL;
 532         }
 533
 534         if (txmode->offloads & DEV_TX_OFFLOAD_MT_LOCKFREE) {
 535                 PMD_INIT_LOG(INFO, "multiqueue lockfree not supported");
 536                 return -EINVAL;
 537         }
 538
 539         if ((txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) &&
 540             !(hw->cap & NFP_NET_CFG_CTRL_GATHER)) {
 541                 PMD_INIT_LOG(INFO, "TX multisegs  not supported");
 542                 return -EINVAL;
 543         }
 544
 545         if (txmode->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
 546                 PMD_INIT_LOG(INFO, "mbuf fast-free not supported");
 547                 return -EINVAL;
 548         }
 549
 550         if (txmode->offloads & DEV_TX_OFFLOAD_SECURITY) {
 551                 PMD_INIT_LOG(INFO, "TX security offload not supported");
 552                 return -EINVAL;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static void
 559 nfp_net_enable_queues(struct rte_eth_dev *dev)
 560 {
 561         struct nfp_net_hw *hw;
 562         uint64_t enabled_queues = 0;
 563         int i;
 564
 565         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 566
 567         /* Enabling the required TX queues in the device */
 568         for (i = 0; i < dev->data->nb_tx_queues; i++)
 569                 enabled_queues |= (1 << i);
 570
 571         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 572
 573         enabled_queues = 0;
 574
 575         /* Enabling the required RX queues in the device */
 576         for (i = 0; i < dev->data->nb_rx_queues; i++)
 577                 enabled_queues |= (1 << i);
 578
 579         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 580 }
 581
 582 static void
 583 nfp_net_disable_queues(struct rte_eth_dev *dev)
 584 {
 585         struct nfp_net_hw *hw;
 586         uint32_t new_ctrl, update = 0;
 587
 588         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 589
 590         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 591         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 592
 593         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 594         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 595                  NFP_NET_CFG_UPDATE_MSIX;
 596
 597         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 598                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 599
 600         /* If an error when reconfig we avoid to change hw state */
 601         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 602                 return;
 603
 604         hw->ctrl = new_ctrl;
 605 }
 606
 607 static int
 608 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 609 {
 610         int i;
 611
 612         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 613                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 614                         return -1;
 615         }
 616         return 0;
 617 }
 618
 619 static void
 620 nfp_net_params_setup(struct nfp_net_hw *hw)
 621 {
 622         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 623         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 624 }
 625
 626 static void
 627 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 628 {
 629         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 630 }
 631
 632 #define ETH_ADDR_LEN    6
 633
 634 static void
 635 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 636 {
 637         int i;
 638
 639         for (i = 0; i < ETH_ADDR_LEN; i++)
 640                 dst[i] = src[i];
 641 }
 642
 643 static int
 644 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 645 {
 646         struct nfp_eth_table *nfp_eth_table;
 647
 648         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 649         /*
 650          * hw points to port0 private data. We need hw now pointing to
 651          * right port.
 652          */
 653         hw += port;
 654         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 655                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 656
 657         free(nfp_eth_table);
 658         return 0;
 659 }
 660
 661 static void
 662 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 663 {
 664         uint32_t tmp;
 665
 666         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 667         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 668
 669         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 670         memcpy(&hw->mac_addr[4], &tmp, 2);
 671 }
 672
 673 static void
 674 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 675 {
 676         uint32_t mac0 = *(uint32_t *)mac;
 677         uint16_t mac1;
 678
 679         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 680
 681         mac += 4;
 682         mac1 = *(uint16_t *)mac;
 683         nn_writew(rte_cpu_to_be_16(mac1),
 684                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 685 }
 686
 687 static int
 688 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 689                            struct rte_intr_handle *intr_handle)
 690 {
 691         struct nfp_net_hw *hw;
 692         int i;
 693
 694         if (!intr_handle->intr_vec) {
 695                 intr_handle->intr_vec =
 696                         rte_zmalloc("intr_vec",
 697                                     dev->data->nb_rx_queues * sizeof(int), 0);
 698                 if (!intr_handle->intr_vec) {
 699                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 700                                      " intr_vec", dev->data->nb_rx_queues);
 701                         return -ENOMEM;
 702                 }
 703         }
 704
 705         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 706
 707         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 708                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 709                 /* UIO just supports one queue and no LSC*/
 710                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 711                 intr_handle->intr_vec[0] = 0;
 712         } else {
 713                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 714                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 715                         /*
 716                          * The first msix vector is reserved for non
 717                          * efd interrupts
 718                         */
 719                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 720                         intr_handle->intr_vec[i] = i + 1;
 721                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 722                                             intr_handle->intr_vec[i]);
 723                 }
 724         }
 725
 726         /* Avoiding TX interrupts */
 727         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 728         return 0;
 729 }
 730
 731 static uint32_t
 732 nfp_check_offloads(struct rte_eth_dev *dev)
 733 {
 734         struct nfp_net_hw *hw;
 735         struct rte_eth_conf *dev_conf;
 736         struct rte_eth_rxmode *rxmode;
 737         struct rte_eth_txmode *txmode;
 738         uint32_t ctrl = 0;
 739
 740         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 741
 742         dev_conf = &dev->data->dev_conf;
 743         rxmode = &dev_conf->rxmode;
 744         txmode = &dev_conf->txmode;
 745
 746         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 747                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 748                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 749         }
 750
 751         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 752                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 753                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 754         }
 755
 756         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 757                 hw->mtu = rxmode->max_rx_pkt_len;
 758
 759         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 760                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 761
 762         /* L2 broadcast */
 763         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 764                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 765
 766         /* L2 multicast */
 767         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 768                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 769
 770         /* TX checksum offload */
 771         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 772             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 773             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 774                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 775
 776         /* LSO offload */
 777         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 778                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 779                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 780                 else
 781                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 782         }
 783
 784         /* RX gather */
 785         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 786                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 787
 788         return ctrl;
 789 }
 790
 791 static int
 792 nfp_net_start(struct rte_eth_dev *dev)
 793 {
 794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 795         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 796         uint32_t new_ctrl, update = 0;
 797         struct nfp_net_hw *hw;
 798         struct rte_eth_conf *dev_conf;
 799         struct rte_eth_rxmode *rxmode;
 800         uint32_t intr_vector;
 801         int ret;
 802
 803         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 804
 805         PMD_INIT_LOG(DEBUG, "Start");
 806
 807         /* Disabling queues just in case... */
 808         nfp_net_disable_queues(dev);
 809
 810         /* Enabling the required queues in the device */
 811         nfp_net_enable_queues(dev);
 812
 813         /* check and configure queue intr-vector mapping */
 814         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 815                 if (hw->pf_multiport_enabled) {
 816                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 817                                           "with NFP multiport PF");
 818                                 return -EINVAL;
 819                 }
 820                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 821                         /*
 822                          * Better not to share LSC with RX interrupts.
 823                          * Unregistering LSC interrupt handler
 824                          */
 825                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 826                                 nfp_net_dev_interrupt_handler, (void *)dev);
 827
 828                         if (dev->data->nb_rx_queues > 1) {
 829                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 830                                              "supports 1 queue with UIO");
 831                                 return -EIO;
 832                         }
 833                 }
 834                 intr_vector = dev->data->nb_rx_queues;
 835                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 836                         return -1;
 837
 838                 nfp_configure_rx_interrupt(dev, intr_handle);
 839                 update = NFP_NET_CFG_UPDATE_MSIX;
 840         }
 841
 842         rte_intr_enable(intr_handle);
 843
 844         new_ctrl = nfp_check_offloads(dev);
 845
 846         /* Writing configuration parameters in the device */
 847         nfp_net_params_setup(hw);
 848
 849         dev_conf = &dev->data->dev_conf;
 850         rxmode = &dev_conf->rxmode;
 851
 852         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 853                 nfp_net_rss_config_default(dev);
 854                 update |= NFP_NET_CFG_UPDATE_RSS;
 855                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 856         }
 857
 858         /* Enable device */
 859         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 860
 861         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 862
 863         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 864                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 865
 866         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 867         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 868                 return -EIO;
 869
 870         /*
 871          * Allocating rte mbuffs for configured rx queues.
 872          * This requires queues being enabled before
 873          */
 874         if (nfp_net_rx_freelist_setup(dev) < 0) {
 875                 ret = -ENOMEM;
 876                 goto error;
 877         }
 878
 879         if (hw->is_pf)
 880                 /* Configure the physical port up */
 881                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 882
 883         hw->ctrl = new_ctrl;
 884
 885         return 0;
 886
 887 error:
 888         /*
 889          * An error returned by this function should mean the app
 890          * exiting and then the system releasing all the memory
 891          * allocated even memory coming from hugepages.
 892          *
 893          * The device could be enabled at this point with some queues
 894          * ready for getting packets. This is true if the call to
 895          * nfp_net_rx_freelist_setup() succeeds for some queues but
 896          * fails for subsequent queues.
 897          *
 898          * This should make the app exiting but better if we tell the
 899          * device first.
 900          */
 901         nfp_net_disable_queues(dev);
 902
 903         return ret;
 904 }
 905
 906 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 907 static void
 908 nfp_net_stop(struct rte_eth_dev *dev)
 909 {
 910         int i;
 911         struct nfp_net_hw *hw;
 912
 913         PMD_INIT_LOG(DEBUG, "Stop");
 914
 915         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916
 917         nfp_net_disable_queues(dev);
 918
 919         /* Clear queues */
 920         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 921                 nfp_net_reset_tx_queue(
 922                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 923         }
 924
 925         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 926                 nfp_net_reset_rx_queue(
 927                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 928         }
 929
 930         if (hw->is_pf)
 931                 /* Configure the physical port down */
 932                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 933 }
 934
 935 /* Reset and stop device. The device can not be restarted. */
 936 static void
 937 nfp_net_close(struct rte_eth_dev *dev)
 938 {
 939         struct nfp_net_hw *hw;
 940         struct rte_pci_device *pci_dev;
 941         int i;
 942
 943         PMD_INIT_LOG(DEBUG, "Close");
 944
 945         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 946         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 947
 948         /*
 949          * We assume that the DPDK application is stopping all the
 950          * threads/queues before calling the device close function.
 951          */
 952
 953         nfp_net_disable_queues(dev);
 954
 955         /* Clear queues */
 956         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 957                 nfp_net_reset_tx_queue(
 958                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 959         }
 960
 961         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 962                 nfp_net_reset_rx_queue(
 963                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 964         }
 965
 966         rte_intr_disable(&pci_dev->intr_handle);
 967         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 968
 969         /* unregister callback func from eal lib */
 970         rte_intr_callback_unregister(&pci_dev->intr_handle,
 971                                      nfp_net_dev_interrupt_handler,
 972                                      (void *)dev);
 973
 974         /*
 975          * The ixgbe PMD driver disables the pcie master on the
 976          * device. The i40e does not...
 977          */
 978 }
 979
 980 static void
 981 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 982 {
 983         uint32_t new_ctrl, update = 0;
 984         struct nfp_net_hw *hw;
 985
 986         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 987
 988         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 989
 990         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 991                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 992                 return;
 993         }
 994
 995         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 996                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 997                 return;
 998         }
 999
1000         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
1001         update = NFP_NET_CFG_UPDATE_GEN;
1002
1003         /*
1004          * DPDK sets promiscuous mode on just after this call assuming
1005          * it can not fail ...
1006          */
1007         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1008                 return;
1009
1010         hw->ctrl = new_ctrl;
1011 }
1012
1013 static void
1014 nfp_net_promisc_disable(struct rte_eth_dev *dev)
1015 {
1016         uint32_t new_ctrl, update = 0;
1017         struct nfp_net_hw *hw;
1018
1019         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020
1021         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1022                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
1023                 return;
1024         }
1025
1026         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1027         update = NFP_NET_CFG_UPDATE_GEN;
1028
1029         /*
1030          * DPDK sets promiscuous mode off just before this call
1031          * assuming it can not fail ...
1032          */
1033         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1034                 return;
1035
1036         hw->ctrl = new_ctrl;
1037 }
1038
1039 /*
1040  * return 0 means link status changed, -1 means not changed
1041  *
1042  * Wait to complete is needed as it can take up to 9 seconds to get the Link
1043  * status.
1044  */
1045 static int
1046 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1047 {
1048         struct nfp_net_hw *hw;
1049         struct rte_eth_link link;
1050         uint32_t nn_link_status;
1051         int ret;
1052
1053         static const uint32_t ls_to_ethtool[] = {
1054                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1055                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
1056                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
1057                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
1058                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
1059                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
1060                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1061                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1062         };
1063
1064         PMD_DRV_LOG(DEBUG, "Link update\n");
1065
1066         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1067
1068         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1069
1070         memset(&link, 0, sizeof(struct rte_eth_link));
1071
1072         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1073                 link.link_status = ETH_LINK_UP;
1074
1075         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1076
1077         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1078                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1079
1080         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1081                 link.link_speed = ETH_SPEED_NUM_NONE;
1082         else
1083                 link.link_speed = ls_to_ethtool[nn_link_status];
1084
1085         ret = rte_eth_linkstatus_set(dev, &link);
1086         if (ret == 0) {
1087                 if (link.link_status)
1088                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1089                 else
1090                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1091         }
1092         return ret;
1093 }
1094
1095 static int
1096 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1097 {
1098         int i;
1099         struct nfp_net_hw *hw;
1100         struct rte_eth_stats nfp_dev_stats;
1101
1102         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103
1104         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1105
1106         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1107
1108         /* reading per RX ring stats */
1109         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1110                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1111                         break;
1112
1113                 nfp_dev_stats.q_ipackets[i] =
1114                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1115
1116                 nfp_dev_stats.q_ipackets[i] -=
1117                         hw->eth_stats_base.q_ipackets[i];
1118
1119                 nfp_dev_stats.q_ibytes[i] =
1120                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1121
1122                 nfp_dev_stats.q_ibytes[i] -=
1123                         hw->eth_stats_base.q_ibytes[i];
1124         }
1125
1126         /* reading per TX ring stats */
1127         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1128                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1129                         break;
1130
1131                 nfp_dev_stats.q_opackets[i] =
1132                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1133
1134                 nfp_dev_stats.q_opackets[i] -=
1135                         hw->eth_stats_base.q_opackets[i];
1136
1137                 nfp_dev_stats.q_obytes[i] =
1138                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1139
1140                 nfp_dev_stats.q_obytes[i] -=
1141                         hw->eth_stats_base.q_obytes[i];
1142         }
1143
1144         nfp_dev_stats.ipackets =
1145                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1146
1147         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1148
1149         nfp_dev_stats.ibytes =
1150                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1151
1152         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1153
1154         nfp_dev_stats.opackets =
1155                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1156
1157         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1158
1159         nfp_dev_stats.obytes =
1160                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1161
1162         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1163
1164         /* reading general device stats */
1165         nfp_dev_stats.ierrors =
1166                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1167
1168         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1169
1170         nfp_dev_stats.oerrors =
1171                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1172
1173         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1174
1175         /* RX ring mbuf allocation failures */
1176         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1177
1178         nfp_dev_stats.imissed =
1179                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1180
1181         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1182
1183         if (stats) {
1184                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1185                 return 0;
1186         }
1187         return -EINVAL;
1188 }
1189
1190 static void
1191 nfp_net_stats_reset(struct rte_eth_dev *dev)
1192 {
1193         int i;
1194         struct nfp_net_hw *hw;
1195
1196         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1197
1198         /*
1199          * hw->eth_stats_base records the per counter starting point.
1200          * Lets update it now
1201          */
1202
1203         /* reading per RX ring stats */
1204         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1205                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1206                         break;
1207
1208                 hw->eth_stats_base.q_ipackets[i] =
1209                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1210
1211                 hw->eth_stats_base.q_ibytes[i] =
1212                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1213         }
1214
1215         /* reading per TX ring stats */
1216         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1217                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1218                         break;
1219
1220                 hw->eth_stats_base.q_opackets[i] =
1221                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1222
1223                 hw->eth_stats_base.q_obytes[i] =
1224                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1225         }
1226
1227         hw->eth_stats_base.ipackets =
1228                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1229
1230         hw->eth_stats_base.ibytes =
1231                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1232
1233         hw->eth_stats_base.opackets =
1234                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1235
1236         hw->eth_stats_base.obytes =
1237                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1238
1239         /* reading general device stats */
1240         hw->eth_stats_base.ierrors =
1241                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1242
1243         hw->eth_stats_base.oerrors =
1244                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1245
1246         /* RX ring mbuf allocation failures */
1247         dev->data->rx_mbuf_alloc_failed = 0;
1248
1249         hw->eth_stats_base.imissed =
1250                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1251 }
1252
1253 static void
1254 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1255 {
1256         struct nfp_net_hw *hw;
1257
1258         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259
1260         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1261         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1262         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1263         dev_info->max_rx_pktlen = hw->max_mtu;
1264         /* Next should change when PF support is implemented */
1265         dev_info->max_mac_addrs = 1;
1266
1267         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1268                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1269
1270         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1271                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1272                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1273                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1274
1275         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1276
1277         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1278                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1279
1280         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1281                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1282                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1283                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1284
1285         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1286                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1287
1288         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1289                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1290
1291         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1292                 .rx_thresh = {
1293                         .pthresh = DEFAULT_RX_PTHRESH,
1294                         .hthresh = DEFAULT_RX_HTHRESH,
1295                         .wthresh = DEFAULT_RX_WTHRESH,
1296                 },
1297                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1298                 .rx_drop_en = 0,
1299         };
1300
1301         dev_info->default_txconf = (struct rte_eth_txconf) {
1302                 .tx_thresh = {
1303                         .pthresh = DEFAULT_TX_PTHRESH,
1304                         .hthresh = DEFAULT_TX_HTHRESH,
1305                         .wthresh = DEFAULT_TX_WTHRESH,
1306                 },
1307                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1308                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1309         };
1310
1311         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1312                                            ETH_RSS_NONFRAG_IPV4_UDP |
1313                                            ETH_RSS_NONFRAG_IPV6_TCP |
1314                                            ETH_RSS_NONFRAG_IPV6_UDP;
1315
1316         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1317         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1318
1319         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1320                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1321                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1322 }
1323
1324 static const uint32_t *
1325 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1326 {
1327         static const uint32_t ptypes[] = {
1328                 /* refers to nfp_net_set_hash() */
1329                 RTE_PTYPE_INNER_L3_IPV4,
1330                 RTE_PTYPE_INNER_L3_IPV6,
1331                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1332                 RTE_PTYPE_INNER_L4_MASK,
1333                 RTE_PTYPE_UNKNOWN
1334         };
1335
1336         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1337                 return ptypes;
1338         return NULL;
1339 }
1340
1341 static uint32_t
1342 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1343 {
1344         struct nfp_net_rxq *rxq;
1345         struct nfp_net_rx_desc *rxds;
1346         uint32_t idx;
1347         uint32_t count;
1348
1349         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1350
1351         idx = rxq->rd_p;
1352
1353         count = 0;
1354
1355         /*
1356          * Other PMDs are just checking the DD bit in intervals of 4
1357          * descriptors and counting all four if the first has the DD
1358          * bit on. Of course, this is not accurate but can be good for
1359          * performance. But ideally that should be done in descriptors
1360          * chunks belonging to the same cache line
1361          */
1362
1363         while (count < rxq->rx_count) {
1364                 rxds = &rxq->rxds[idx];
1365                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1366                         break;
1367
1368                 count++;
1369                 idx++;
1370
1371                 /* Wrapping? */
1372                 if ((idx) == rxq->rx_count)
1373                         idx = 0;
1374         }
1375
1376         return count;
1377 }
1378
1379 static int
1380 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1381 {
1382         struct rte_pci_device *pci_dev;
1383         struct nfp_net_hw *hw;
1384         int base = 0;
1385
1386         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1388
1389         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1390                 base = 1;
1391
1392         /* Make sure all updates are written before un-masking */
1393         rte_wmb();
1394         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1395                       NFP_NET_CFG_ICR_UNMASKED);
1396         return 0;
1397 }
1398
1399 static int
1400 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1401 {
1402         struct rte_pci_device *pci_dev;
1403         struct nfp_net_hw *hw;
1404         int base = 0;
1405
1406         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1408
1409         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1410                 base = 1;
1411
1412         /* Make sure all updates are written before un-masking */
1413         rte_wmb();
1414         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1415         return 0;
1416 }
1417
1418 static void
1419 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1420 {
1421         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1422         struct rte_eth_link link;
1423
1424         rte_eth_linkstatus_get(dev, &link);
1425         if (link.link_status)
1426                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1427                         dev->data->port_id, link.link_speed,
1428                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1429                         ? "full-duplex" : "half-duplex");
1430         else
1431                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1432                         dev->data->port_id);
1433
1434         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1435                 pci_dev->addr.domain, pci_dev->addr.bus,
1436                 pci_dev->addr.devid, pci_dev->addr.function);
1437 }
1438
1439 /* Interrupt configuration and handling */
1440
1441 /*
1442  * nfp_net_irq_unmask - Unmask an interrupt
1443  *
1444  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1445  * clear the ICR for the entry.
1446  */
1447 static void
1448 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1449 {
1450         struct nfp_net_hw *hw;
1451         struct rte_pci_device *pci_dev;
1452
1453         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1455
1456         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1457                 /* If MSI-X auto-masking is used, clear the entry */
1458                 rte_wmb();
1459                 rte_intr_enable(&pci_dev->intr_handle);
1460         } else {
1461                 /* Make sure all updates are written before un-masking */
1462                 rte_wmb();
1463                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1464                               NFP_NET_CFG_ICR_UNMASKED);
1465         }
1466 }
1467
1468 static void
1469 nfp_net_dev_interrupt_handler(void *param)
1470 {
1471         int64_t timeout;
1472         struct rte_eth_link link;
1473         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1474
1475         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1476
1477         rte_eth_linkstatus_get(dev, &link);
1478
1479         nfp_net_link_update(dev, 0);
1480
1481         /* likely to up */
1482         if (!link.link_status) {
1483                 /* handle it 1 sec later, wait it being stable */
1484                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1485                 /* likely to down */
1486         } else {
1487                 /* handle it 4 sec later, wait it being stable */
1488                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1489         }
1490
1491         if (rte_eal_alarm_set(timeout * 1000,
1492                               nfp_net_dev_interrupt_delayed_handler,
1493                               (void *)dev) < 0) {
1494                 RTE_LOG(ERR, PMD, "Error setting alarm");
1495                 /* Unmasking */
1496                 nfp_net_irq_unmask(dev);
1497         }
1498 }
1499
1500 /*
1501  * Interrupt handler which shall be registered for alarm callback for delayed
1502  * handling specific interrupt to wait for the stable nic state. As the NIC
1503  * interrupt state is not stable for nfp after link is just down, it needs
1504  * to wait 4 seconds to get the stable status.
1505  *
1506  * @param handle   Pointer to interrupt handle.
1507  * @param param    The address of parameter (struct rte_eth_dev *)
1508  *
1509  * @return  void
1510  */
1511 static void
1512 nfp_net_dev_interrupt_delayed_handler(void *param)
1513 {
1514         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1515
1516         nfp_net_link_update(dev, 0);
1517         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1518
1519         nfp_net_dev_link_status_print(dev);
1520
1521         /* Unmasking */
1522         nfp_net_irq_unmask(dev);
1523 }
1524
1525 static int
1526 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1527 {
1528         struct nfp_net_hw *hw;
1529
1530         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1531
1532         /* check that mtu is within the allowed range */
1533         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1534                 return -EINVAL;
1535
1536         /* mtu setting is forbidden if port is started */
1537         if (dev->data->dev_started) {
1538                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1539                             dev->data->port_id);
1540                 return -EBUSY;
1541         }
1542
1543         /* switch to jumbo mode if needed */
1544         if ((uint32_t)mtu > ETHER_MAX_LEN)
1545                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1546         else
1547                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1548
1549         /* update max frame size */
1550         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1551
1552         /* writing to configuration space */
1553         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1554
1555         hw->mtu = mtu;
1556
1557         return 0;
1558 }
1559
1560 static int
1561 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1562                        uint16_t queue_idx, uint16_t nb_desc,
1563                        unsigned int socket_id,
1564                        const struct rte_eth_rxconf *rx_conf,
1565                        struct rte_mempool *mp)
1566 {
1567         const struct rte_memzone *tz;
1568         struct nfp_net_rxq *rxq;
1569         struct nfp_net_hw *hw;
1570         struct rte_eth_conf *dev_conf;
1571         struct rte_eth_rxmode *rxmode;
1572
1573         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574
1575         PMD_INIT_FUNC_TRACE();
1576
1577         /* Validating number of descriptors */
1578         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1579             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1580             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1581                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1582                 return -EINVAL;
1583         }
1584
1585         dev_conf = &dev->data->dev_conf;
1586         rxmode = &dev_conf->rxmode;
1587
1588         if (rx_conf->offloads != rxmode->offloads) {
1589                 RTE_LOG(ERR, PMD, "queue %u rx offloads not as port offloads\n",
1590                                   queue_idx);
1591                 RTE_LOG(ERR, PMD, "\tport: %" PRIx64 "\n", rxmode->offloads);
1592                 RTE_LOG(ERR, PMD, "\tqueue: %" PRIx64 "\n", rx_conf->offloads);
1593                 return -EINVAL;
1594         }
1595
1596         /*
1597          * Free memory prior to re-allocation if needed. This is the case after
1598          * calling nfp_net_stop
1599          */
1600         if (dev->data->rx_queues[queue_idx]) {
1601                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1602                 dev->data->rx_queues[queue_idx] = NULL;
1603         }
1604
1605         /* Allocating rx queue data structure */
1606         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1607                                  RTE_CACHE_LINE_SIZE, socket_id);
1608         if (rxq == NULL)
1609                 return -ENOMEM;
1610
1611         /* Hw queues mapping based on firmware confifguration */
1612         rxq->qidx = queue_idx;
1613         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1614         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1615         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1616         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1617
1618         /*
1619          * Tracking mbuf size for detecting a potential mbuf overflow due to
1620          * RX offset
1621          */
1622         rxq->mem_pool = mp;
1623         rxq->mbuf_size = rxq->mem_pool->elt_size;
1624         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1625         hw->flbufsz = rxq->mbuf_size;
1626
1627         rxq->rx_count = nb_desc;
1628         rxq->port_id = dev->data->port_id;
1629         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1630         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1631                                   : ETHER_CRC_LEN);
1632         rxq->drop_en = rx_conf->rx_drop_en;
1633
1634         /*
1635          * Allocate RX ring hardware descriptors. A memzone large enough to
1636          * handle the maximum ring size is allocated in order to allow for
1637          * resizing in later calls to the queue setup function.
1638          */
1639         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1640                                    sizeof(struct nfp_net_rx_desc) *
1641                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1642                                    socket_id);
1643
1644         if (tz == NULL) {
1645                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1646                 nfp_net_rx_queue_release(rxq);
1647                 return -ENOMEM;
1648         }
1649
1650         /* Saving physical and virtual addresses for the RX ring */
1651         rxq->dma = (uint64_t)tz->iova;
1652         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1653
1654         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1655         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1656                                          sizeof(*rxq->rxbufs) * nb_desc,
1657                                          RTE_CACHE_LINE_SIZE, socket_id);
1658         if (rxq->rxbufs == NULL) {
1659                 nfp_net_rx_queue_release(rxq);
1660                 return -ENOMEM;
1661         }
1662
1663         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1664                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1665
1666         nfp_net_reset_rx_queue(rxq);
1667
1668         dev->data->rx_queues[queue_idx] = rxq;
1669         rxq->hw = hw;
1670
1671         /*
1672          * Telling the HW about the physical address of the RX ring and number
1673          * of descriptors in log2 format
1674          */
1675         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1676         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1677
1678         return 0;
1679 }
1680
1681 static int
1682 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1683 {
1684         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1685         uint64_t dma_addr;
1686         unsigned i;
1687
1688         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1689                    rxq->rx_count);
1690
1691         for (i = 0; i < rxq->rx_count; i++) {
1692                 struct nfp_net_rx_desc *rxd;
1693                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1694
1695                 if (mbuf == NULL) {
1696                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1697                                 (unsigned)rxq->qidx);
1698                         return -ENOMEM;
1699                 }
1700
1701                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1702
1703                 rxd = &rxq->rxds[i];
1704                 rxd->fld.dd = 0;
1705                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1706                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1707                 rxe[i].mbuf = mbuf;
1708                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1709         }
1710
1711         /* Make sure all writes are flushed before telling the hardware */
1712         rte_wmb();
1713
1714         /* Not advertising the whole ring as the firmware gets confused if so */
1715         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1716                    rxq->rx_count - 1);
1717
1718         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1719
1720         return 0;
1721 }
1722
1723 static int
1724 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1725                        uint16_t nb_desc, unsigned int socket_id,
1726                        const struct rte_eth_txconf *tx_conf)
1727 {
1728         const struct rte_memzone *tz;
1729         struct nfp_net_txq *txq;
1730         uint16_t tx_free_thresh;
1731         struct nfp_net_hw *hw;
1732         struct rte_eth_conf *dev_conf;
1733         struct rte_eth_txmode *txmode;
1734
1735         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736
1737         PMD_INIT_FUNC_TRACE();
1738
1739         /* Validating number of descriptors */
1740         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1741             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1742             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1743                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1744                 return -EINVAL;
1745         }
1746
1747         dev_conf = &dev->data->dev_conf;
1748         txmode = &dev_conf->txmode;
1749
1750         if (tx_conf->offloads != txmode->offloads) {
1751                 RTE_LOG(ERR, PMD, "queue %u tx offloads not as port offloads",
1752                                   queue_idx);
1753                 return -EINVAL;
1754         }
1755
1756         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1757                                     tx_conf->tx_free_thresh :
1758                                     DEFAULT_TX_FREE_THRESH);
1759
1760         if (tx_free_thresh > (nb_desc)) {
1761                 RTE_LOG(ERR, PMD,
1762                         "tx_free_thresh must be less than the number of TX "
1763                         "descriptors. (tx_free_thresh=%u port=%d "
1764                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1765                         dev->data->port_id, (int)queue_idx);
1766                 return -(EINVAL);
1767         }
1768
1769         /*
1770          * Free memory prior to re-allocation if needed. This is the case after
1771          * calling nfp_net_stop
1772          */
1773         if (dev->data->tx_queues[queue_idx]) {
1774                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1775                            queue_idx);
1776                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1777                 dev->data->tx_queues[queue_idx] = NULL;
1778         }
1779
1780         /* Allocating tx queue data structure */
1781         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1782                                  RTE_CACHE_LINE_SIZE, socket_id);
1783         if (txq == NULL) {
1784                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1785                 return -ENOMEM;
1786         }
1787
1788         /*
1789          * Allocate TX ring hardware descriptors. A memzone large enough to
1790          * handle the maximum ring size is allocated in order to allow for
1791          * resizing in later calls to the queue setup function.
1792          */
1793         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1794                                    sizeof(struct nfp_net_tx_desc) *
1795                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1796                                    socket_id);
1797         if (tz == NULL) {
1798                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1799                 nfp_net_tx_queue_release(txq);
1800                 return -ENOMEM;
1801         }
1802
1803         txq->tx_count = nb_desc;
1804         txq->tx_free_thresh = tx_free_thresh;
1805         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1806         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1807         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1808
1809         /* queue mapping based on firmware configuration */
1810         txq->qidx = queue_idx;
1811         txq->tx_qcidx = queue_idx * hw->stride_tx;
1812         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1813
1814         txq->port_id = dev->data->port_id;
1815
1816         /* Saving physical and virtual addresses for the TX ring */
1817         txq->dma = (uint64_t)tz->iova;
1818         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1819
1820         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1821         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1822                                          sizeof(*txq->txbufs) * nb_desc,
1823                                          RTE_CACHE_LINE_SIZE, socket_id);
1824         if (txq->txbufs == NULL) {
1825                 nfp_net_tx_queue_release(txq);
1826                 return -ENOMEM;
1827         }
1828         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1829                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1830
1831         nfp_net_reset_tx_queue(txq);
1832
1833         dev->data->tx_queues[queue_idx] = txq;
1834         txq->hw = hw;
1835
1836         /*
1837          * Telling the HW about the physical address of the TX ring and number
1838          * of descriptors in log2 format
1839          */
1840         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1841         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1842
1843         return 0;
1844 }
1845
1846 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1847 static inline void
1848 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1849                struct rte_mbuf *mb)
1850 {
1851         uint64_t ol_flags;
1852         struct nfp_net_hw *hw = txq->hw;
1853
1854         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1855                 goto clean_txd;
1856
1857         ol_flags = mb->ol_flags;
1858
1859         if (!(ol_flags & PKT_TX_TCP_SEG))
1860                 goto clean_txd;
1861
1862         txd->l3_offset = mb->l2_len;
1863         txd->l4_offset = mb->l2_len + mb->l3_len;
1864         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1865         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1866         txd->flags = PCIE_DESC_TX_LSO;
1867         return;
1868
1869 clean_txd:
1870         txd->flags = 0;
1871         txd->l3_offset = 0;
1872         txd->l4_offset = 0;
1873         txd->lso_hdrlen = 0;
1874         txd->mss = 0;
1875 }
1876
1877 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1878 static inline void
1879 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1880                  struct rte_mbuf *mb)
1881 {
1882         uint64_t ol_flags;
1883         struct nfp_net_hw *hw = txq->hw;
1884
1885         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1886                 return;
1887
1888         ol_flags = mb->ol_flags;
1889
1890         /* IPv6 does not need checksum */
1891         if (ol_flags & PKT_TX_IP_CKSUM)
1892                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1893
1894         switch (ol_flags & PKT_TX_L4_MASK) {
1895         case PKT_TX_UDP_CKSUM:
1896                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1897                 break;
1898         case PKT_TX_TCP_CKSUM:
1899                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1900                 break;
1901         }
1902
1903         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1904                 txd->flags |= PCIE_DESC_TX_CSUM;
1905 }
1906
1907 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1908 static inline void
1909 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1910                  struct rte_mbuf *mb)
1911 {
1912         struct nfp_net_hw *hw = rxq->hw;
1913
1914         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1915                 return;
1916
1917         /* If IPv4 and IP checksum error, fail */
1918         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1919             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1920                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1921
1922         /* If neither UDP nor TCP return */
1923         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1924             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1925                 return;
1926
1927         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1928             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1929                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1930
1931         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1932             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1933                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1934 }
1935
1936 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1937 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1938
1939 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1940
1941 /*
1942  * nfp_net_set_hash - Set mbuf hash data
1943  *
1944  * The RSS hash and hash-type are pre-pended to the packet data.
1945  * Extract and decode it and set the mbuf fields.
1946  */
1947 static inline void
1948 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1949                  struct rte_mbuf *mbuf)
1950 {
1951         struct nfp_net_hw *hw = rxq->hw;
1952         uint8_t *meta_offset;
1953         uint32_t meta_info;
1954         uint32_t hash = 0;
1955         uint32_t hash_type = 0;
1956
1957         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1958                 return;
1959
1960         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1961                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1962                         return;
1963
1964                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1965                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1966
1967         } else if (NFP_DESC_META_LEN(rxd)) {
1968                 /*
1969                  * new metadata api:
1970                  * <----  32 bit  ----->
1971                  * m    field type word
1972                  * e     data field #2
1973                  * t     data field #1
1974                  * a     data field #0
1975                  * ====================
1976                  *    packet data
1977                  *
1978                  * Field type word contains up to 8 4bit field types
1979                  * A 4bit field type refers to a data field word
1980                  * A data field word can have several 4bit field types
1981                  */
1982                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1983                 meta_offset -= NFP_DESC_META_LEN(rxd);
1984                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1985                 meta_offset += 4;
1986                 /* NFP PMD just supports metadata for hashing */
1987                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1988                 case NFP_NET_META_HASH:
1989                         /* next field type is about the hash type */
1990                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1991                         /* hash value is in the data field */
1992                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1993                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1994                         break;
1995                 default:
1996                         /* Unsupported metadata can be a performance issue */
1997                         return;
1998                 }
1999         } else {
2000                 return;
2001         }
2002
2003         mbuf->hash.rss = hash;
2004         mbuf->ol_flags |= PKT_RX_RSS_HASH;
2005
2006         switch (hash_type) {
2007         case NFP_NET_RSS_IPV4:
2008                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
2009                 break;
2010         case NFP_NET_RSS_IPV6:
2011                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
2012                 break;
2013         case NFP_NET_RSS_IPV6_EX:
2014                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2015                 break;
2016         default:
2017                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2018         }
2019 }
2020
2021 static inline void
2022 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2023 {
2024         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2025 }
2026
2027 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2028
2029 /*
2030  * RX path design:
2031  *
2032  * There are some decissions to take:
2033  * 1) How to check DD RX descriptors bit
2034  * 2) How and when to allocate new mbufs
2035  *
2036  * Current implementation checks just one single DD bit each loop. As each
2037  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2038  * a single cache line instead. Tests with this change have not shown any
2039  * performance improvement but it requires further investigation. For example,
2040  * depending on which descriptor is next, the number of descriptors could be
2041  * less than 8 for just checking those in the same cache line. This implies
2042  * extra work which could be counterproductive by itself. Indeed, last firmware
2043  * changes are just doing this: writing several descriptors with the DD bit
2044  * for saving PCIe bandwidth and DMA operations from the NFP.
2045  *
2046  * Mbuf allocation is done when a new packet is received. Then the descriptor
2047  * is automatically linked with the new mbuf and the old one is given to the
2048  * user. The main drawback with this design is mbuf allocation is heavier than
2049  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2050  * cache point of view it does not seem allocating the mbuf early on as we are
2051  * doing now have any benefit at all. Again, tests with this change have not
2052  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2053  * so looking at the implications of this type of allocation should be studied
2054  * deeply
2055  */
2056
2057 static uint16_t
2058 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2059 {
2060         struct nfp_net_rxq *rxq;
2061         struct nfp_net_rx_desc *rxds;
2062         struct nfp_net_rx_buff *rxb;
2063         struct nfp_net_hw *hw;
2064         struct rte_mbuf *mb;
2065         struct rte_mbuf *new_mb;
2066         uint16_t nb_hold;
2067         uint64_t dma_addr;
2068         int avail;
2069
2070         rxq = rx_queue;
2071         if (unlikely(rxq == NULL)) {
2072                 /*
2073                  * DPDK just checks the queue is lower than max queues
2074                  * enabled. But the queue needs to be configured
2075                  */
2076                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2077                 return -EINVAL;
2078         }
2079
2080         hw = rxq->hw;
2081         avail = 0;
2082         nb_hold = 0;
2083
2084         while (avail < nb_pkts) {
2085                 rxb = &rxq->rxbufs[rxq->rd_p];
2086                 if (unlikely(rxb == NULL)) {
2087                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2088                         break;
2089                 }
2090
2091                 rxds = &rxq->rxds[rxq->rd_p];
2092                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2093                         break;
2094
2095                 /*
2096                  * Memory barrier to ensure that we won't do other
2097                  * reads before the DD bit.
2098                  */
2099                 rte_rmb();
2100
2101                 /*
2102                  * We got a packet. Let's alloc a new mbuff for refilling the
2103                  * free descriptor ring as soon as possible
2104                  */
2105                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2106                 if (unlikely(new_mb == NULL)) {
2107                         RTE_LOG_DP(DEBUG, PMD,
2108                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2109                                 rxq->port_id, (unsigned int)rxq->qidx);
2110                         nfp_net_mbuf_alloc_failed(rxq);
2111                         break;
2112                 }
2113
2114                 nb_hold++;
2115
2116                 /*
2117                  * Grab the mbuff and refill the descriptor with the
2118                  * previously allocated mbuff
2119                  */
2120                 mb = rxb->mbuf;
2121                 rxb->mbuf = new_mb;
2122
2123                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2124                            rxds->rxd.data_len, rxq->mbuf_size);
2125
2126                 /* Size of this segment */
2127                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2128                 /* Size of the whole packet. We just support 1 segment */
2129                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2130
2131                 if (unlikely((mb->data_len + hw->rx_offset) >
2132                              rxq->mbuf_size)) {
2133                         /*
2134                          * This should not happen and the user has the
2135                          * responsibility of avoiding it. But we have
2136                          * to give some info about the error
2137                          */
2138                         RTE_LOG_DP(ERR, PMD,
2139                                 "mbuf overflow likely due to the RX offset.\n"
2140                                 "\t\tYour mbuf size should have extra space for"
2141                                 " RX offset=%u bytes.\n"
2142                                 "\t\tCurrently you just have %u bytes available"
2143                                 " but the received packet is %u bytes long",
2144                                 hw->rx_offset,
2145                                 rxq->mbuf_size - hw->rx_offset,
2146                                 mb->data_len);
2147                         return -EINVAL;
2148                 }
2149
2150                 /* Filling the received mbuff with packet info */
2151                 if (hw->rx_offset)
2152                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2153                 else
2154                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2155                                        NFP_DESC_META_LEN(rxds);
2156
2157                 /* No scatter mode supported */
2158                 mb->nb_segs = 1;
2159                 mb->next = NULL;
2160
2161                 mb->port = rxq->port_id;
2162
2163                 /* Checking the RSS flag */
2164                 nfp_net_set_hash(rxq, rxds, mb);
2165
2166                 /* Checking the checksum flag */
2167                 nfp_net_rx_cksum(rxq, rxds, mb);
2168
2169                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2170                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2171                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2172                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2173                 }
2174
2175                 /* Adding the mbuff to the mbuff array passed by the app */
2176                 rx_pkts[avail++] = mb;
2177
2178                 /* Now resetting and updating the descriptor */
2179                 rxds->vals[0] = 0;
2180                 rxds->vals[1] = 0;
2181                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2182                 rxds->fld.dd = 0;
2183                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2184                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2185
2186                 rxq->rd_p++;
2187                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2188                         rxq->rd_p = 0;
2189         }
2190
2191         if (nb_hold == 0)
2192                 return nb_hold;
2193
2194         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2195                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2196
2197         nb_hold += rxq->nb_rx_hold;
2198
2199         /*
2200          * FL descriptors needs to be written before incrementing the
2201          * FL queue WR pointer
2202          */
2203         rte_wmb();
2204         if (nb_hold > rxq->rx_free_thresh) {
2205                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2206                            rxq->port_id, (unsigned int)rxq->qidx,
2207                            (unsigned)nb_hold, (unsigned)avail);
2208                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2209                 nb_hold = 0;
2210         }
2211         rxq->nb_rx_hold = nb_hold;
2212
2213         return avail;
2214 }
2215
2216 /*
2217  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2218  * status
2219  * @txq: TX queue to work with
2220  * Returns number of descriptors freed
2221  */
2222 int
2223 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2224 {
2225         uint32_t qcp_rd_p;
2226         int todo;
2227
2228         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2229                    " status\n", txq->qidx);
2230
2231         /* Work out how many packets have been sent */
2232         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2233
2234         if (qcp_rd_p == txq->rd_p) {
2235                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2236                            "packets (%u, %u)\n", txq->qidx,
2237                            qcp_rd_p, txq->rd_p);
2238                 return 0;
2239         }
2240
2241         if (qcp_rd_p > txq->rd_p)
2242                 todo = qcp_rd_p - txq->rd_p;
2243         else
2244                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2245
2246         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2247                    qcp_rd_p, txq->rd_p, txq->rd_p);
2248
2249         if (todo == 0)
2250                 return todo;
2251
2252         txq->rd_p += todo;
2253         if (unlikely(txq->rd_p >= txq->tx_count))
2254                 txq->rd_p -= txq->tx_count;
2255
2256         return todo;
2257 }
2258
2259 /* Leaving always free descriptors for avoiding wrapping confusion */
2260 static inline
2261 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2262 {
2263         if (txq->wr_p >= txq->rd_p)
2264                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2265         else
2266                 return txq->rd_p - txq->wr_p - 8;
2267 }
2268
2269 /*
2270  * nfp_net_txq_full - Check if the TX queue free descriptors
2271  * is below tx_free_threshold
2272  *
2273  * @txq: TX queue to check
2274  *
2275  * This function uses the host copy* of read/write pointers
2276  */
2277 static inline
2278 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2279 {
2280         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2281 }
2282
2283 static uint16_t
2284 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2285 {
2286         struct nfp_net_txq *txq;
2287         struct nfp_net_hw *hw;
2288         struct nfp_net_tx_desc *txds, txd;
2289         struct rte_mbuf *pkt;
2290         uint64_t dma_addr;
2291         int pkt_size, dma_size;
2292         uint16_t free_descs, issued_descs;
2293         struct rte_mbuf **lmbuf;
2294         int i;
2295
2296         txq = tx_queue;
2297         hw = txq->hw;
2298         txds = &txq->txds[txq->wr_p];
2299
2300         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2301                    txq->qidx, txq->wr_p, nb_pkts);
2302
2303         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2304                 nfp_net_tx_free_bufs(txq);
2305
2306         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2307         if (unlikely(free_descs == 0))
2308                 return 0;
2309
2310         pkt = *tx_pkts;
2311
2312         i = 0;
2313         issued_descs = 0;
2314         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2315                    txq->qidx, nb_pkts);
2316         /* Sending packets */
2317         while ((i < nb_pkts) && free_descs) {
2318                 /* Grabbing the mbuf linked to the current descriptor */
2319                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2320                 /* Warming the cache for releasing the mbuf later on */
2321                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2322
2323                 pkt = *(tx_pkts + i);
2324
2325                 if (unlikely((pkt->nb_segs > 1) &&
2326                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2327                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2328                         rte_panic("Multisegment packet unsupported\n");
2329                 }
2330
2331                 /* Checking if we have enough descriptors */
2332                 if (unlikely(pkt->nb_segs > free_descs))
2333                         goto xmit_end;
2334
2335                 /*
2336                  * Checksum and VLAN flags just in the first descriptor for a
2337                  * multisegment packet, but TSO info needs to be in all of them.
2338                  */
2339                 txd.data_len = pkt->pkt_len;
2340                 nfp_net_tx_tso(txq, &txd, pkt);
2341                 nfp_net_tx_cksum(txq, &txd, pkt);
2342
2343                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2344                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2345                         txd.flags |= PCIE_DESC_TX_VLAN;
2346                         txd.vlan = pkt->vlan_tci;
2347                 }
2348
2349                 /*
2350                  * mbuf data_len is the data in one segment and pkt_len data
2351                  * in the whole packet. When the packet is just one segment,
2352                  * then data_len = pkt_len
2353                  */
2354                 pkt_size = pkt->pkt_len;
2355
2356                 while (pkt) {
2357                         /* Copying TSO, VLAN and cksum info */
2358                         *txds = txd;
2359
2360                         /* Releasing mbuf used by this descriptor previously*/
2361                         if (*lmbuf)
2362                                 rte_pktmbuf_free_seg(*lmbuf);
2363
2364                         /*
2365                          * Linking mbuf with descriptor for being released
2366                          * next time descriptor is used
2367                          */
2368                         *lmbuf = pkt;
2369
2370                         dma_size = pkt->data_len;
2371                         dma_addr = rte_mbuf_data_iova(pkt);
2372                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2373                                    "%" PRIx64 "\n", dma_addr);
2374
2375                         /* Filling descriptors fields */
2376                         txds->dma_len = dma_size;
2377                         txds->data_len = txd.data_len;
2378                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2379                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2380                         ASSERT(free_descs > 0);
2381                         free_descs--;
2382
2383                         txq->wr_p++;
2384                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2385                                 txq->wr_p = 0;
2386
2387                         pkt_size -= dma_size;
2388                         if (!pkt_size)
2389                                 /* End of packet */
2390                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2391                         else
2392                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2393
2394                         pkt = pkt->next;
2395                         /* Referencing next free TX descriptor */
2396                         txds = &txq->txds[txq->wr_p];
2397                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2398                         issued_descs++;
2399                 }
2400                 i++;
2401         }
2402
2403 xmit_end:
2404         /* Increment write pointers. Force memory write before we let HW know */
2405         rte_wmb();
2406         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2407
2408         return i;
2409 }
2410
2411 static int
2412 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2413 {
2414         uint32_t new_ctrl, update;
2415         struct nfp_net_hw *hw;
2416         int ret;
2417
2418         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419         new_ctrl = 0;
2420
2421         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2422             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2423                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2424                         " ETH_VLAN_EXTEND_OFFLOAD");
2425
2426         /* Enable vlan strip if it is not configured yet */
2427         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2428             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2429                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2430
2431         /* Disable vlan strip just if it is configured */
2432         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2433             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2434                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2435
2436         if (new_ctrl == 0)
2437                 return 0;
2438
2439         update = NFP_NET_CFG_UPDATE_GEN;
2440
2441         ret = nfp_net_reconfig(hw, new_ctrl, update);
2442         if (!ret)
2443                 hw->ctrl = new_ctrl;
2444
2445         return ret;
2446 }
2447
2448 static int
2449 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2450                     struct rte_eth_rss_reta_entry64 *reta_conf,
2451                     uint16_t reta_size)
2452 {
2453         uint32_t reta, mask;
2454         int i, j;
2455         int idx, shift;
2456         struct nfp_net_hw *hw =
2457                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458
2459         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2460                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2461                         "(%d) doesn't match the number hardware can supported "
2462                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2463                 return -EINVAL;
2464         }
2465
2466         /*
2467          * Update Redirection Table. There are 128 8bit-entries which can be
2468          * manage as 32 32bit-entries
2469          */
2470         for (i = 0; i < reta_size; i += 4) {
2471                 /* Handling 4 RSS entries per loop */
2472                 idx = i / RTE_RETA_GROUP_SIZE;
2473                 shift = i % RTE_RETA_GROUP_SIZE;
2474                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2475
2476                 if (!mask)
2477                         continue;
2478
2479                 reta = 0;
2480                 /* If all 4 entries were set, don't need read RETA register */
2481                 if (mask != 0xF)
2482                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2483
2484                 for (j = 0; j < 4; j++) {
2485                         if (!(mask & (0x1 << j)))
2486                                 continue;
2487                         if (mask != 0xF)
2488                                 /* Clearing the entry bits */
2489                                 reta &= ~(0xFF << (8 * j));
2490                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2491                 }
2492                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2493                               reta);
2494         }
2495         return 0;
2496 }
2497
2498 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2499 static int
2500 nfp_net_reta_update(struct rte_eth_dev *dev,
2501                     struct rte_eth_rss_reta_entry64 *reta_conf,
2502                     uint16_t reta_size)
2503 {
2504         struct nfp_net_hw *hw =
2505                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506         uint32_t update;
2507         int ret;
2508
2509         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2510                 return -EINVAL;
2511
2512         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2513         if (ret != 0)
2514                 return ret;
2515
2516         update = NFP_NET_CFG_UPDATE_RSS;
2517
2518         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2519                 return -EIO;
2520
2521         return 0;
2522 }
2523
2524  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2525 static int
2526 nfp_net_reta_query(struct rte_eth_dev *dev,
2527                    struct rte_eth_rss_reta_entry64 *reta_conf,
2528                    uint16_t reta_size)
2529 {
2530         uint8_t i, j, mask;
2531         int idx, shift;
2532         uint32_t reta;
2533         struct nfp_net_hw *hw;
2534
2535         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536
2537         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2538                 return -EINVAL;
2539
2540         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2541                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2542                         "(%d) doesn't match the number hardware can supported "
2543                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2544                 return -EINVAL;
2545         }
2546
2547         /*
2548          * Reading Redirection Table. There are 128 8bit-entries which can be
2549          * manage as 32 32bit-entries
2550          */
2551         for (i = 0; i < reta_size; i += 4) {
2552                 /* Handling 4 RSS entries per loop */
2553                 idx = i / RTE_RETA_GROUP_SIZE;
2554                 shift = i % RTE_RETA_GROUP_SIZE;
2555                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2556
2557                 if (!mask)
2558                         continue;
2559
2560                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2561                                     shift);
2562                 for (j = 0; j < 4; j++) {
2563                         if (!(mask & (0x1 << j)))
2564                                 continue;
2565                         reta_conf->reta[shift + j] =
2566                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2567                 }
2568         }
2569         return 0;
2570 }
2571
2572 static int
2573 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2574                         struct rte_eth_rss_conf *rss_conf)
2575 {
2576         struct nfp_net_hw *hw;
2577         uint64_t rss_hf;
2578         uint32_t cfg_rss_ctrl = 0;
2579         uint8_t key;
2580         int i;
2581
2582         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583
2584         /* Writing the key byte a byte */
2585         for (i = 0; i < rss_conf->rss_key_len; i++) {
2586                 memcpy(&key, &rss_conf->rss_key[i], 1);
2587                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2588         }
2589
2590         rss_hf = rss_conf->rss_hf;
2591
2592         if (rss_hf & ETH_RSS_IPV4)
2593                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2594                                 NFP_NET_CFG_RSS_IPV4_TCP |
2595                                 NFP_NET_CFG_RSS_IPV4_UDP;
2596
2597         if (rss_hf & ETH_RSS_IPV6)
2598                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2599                                 NFP_NET_CFG_RSS_IPV6_TCP |
2600                                 NFP_NET_CFG_RSS_IPV6_UDP;
2601
2602         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2603         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2604
2605         /* configuring where to apply the RSS hash */
2606         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2607
2608         /* Writing the key size */
2609         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2610
2611         return 0;
2612 }
2613
2614 static int
2615 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2616                         struct rte_eth_rss_conf *rss_conf)
2617 {
2618         uint32_t update;
2619         uint64_t rss_hf;
2620         struct nfp_net_hw *hw;
2621
2622         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2623
2624         rss_hf = rss_conf->rss_hf;
2625
2626         /* Checking if RSS is enabled */
2627         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2628                 if (rss_hf != 0) { /* Enable RSS? */
2629                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2630                         return -EINVAL;
2631                 }
2632                 return 0; /* Nothing to do */
2633         }
2634
2635         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2636                 RTE_LOG(ERR, PMD, "hash key too long\n");
2637                 return -EINVAL;
2638         }
2639
2640         nfp_net_rss_hash_write(dev, rss_conf);
2641
2642         update = NFP_NET_CFG_UPDATE_RSS;
2643
2644         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2645                 return -EIO;
2646
2647         return 0;
2648 }
2649
2650 static int
2651 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2652                           struct rte_eth_rss_conf *rss_conf)
2653 {
2654         uint64_t rss_hf;
2655         uint32_t cfg_rss_ctrl;
2656         uint8_t key;
2657         int i;
2658         struct nfp_net_hw *hw;
2659
2660         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661
2662         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2663                 return -EINVAL;
2664
2665         rss_hf = rss_conf->rss_hf;
2666         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2667
2668         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2669                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2670
2671         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2672                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2673
2674         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2675                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2676
2677         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2678                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2679
2680         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2681                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2682
2683         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2684                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2685
2686         /* Reading the key size */
2687         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2688
2689         /* Reading the key byte a byte */
2690         for (i = 0; i < rss_conf->rss_key_len; i++) {
2691                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2692                 memcpy(&rss_conf->rss_key[i], &key, 1);
2693         }
2694
2695         return 0;
2696 }
2697
2698 static int
2699 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2700 {
2701         struct rte_eth_conf *dev_conf;
2702         struct rte_eth_rss_conf rss_conf;
2703         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2704         uint16_t rx_queues = dev->data->nb_rx_queues;
2705         uint16_t queue;
2706         int i, j, ret;
2707
2708         RTE_LOG(INFO, PMD, "setting default RSS conf for %u queues\n",
2709                 rx_queues);
2710
2711         nfp_reta_conf[0].mask = ~0x0;
2712         nfp_reta_conf[1].mask = ~0x0;
2713
2714         queue = 0;
2715         for (i = 0; i < 0x40; i += 8) {
2716                 for (j = i; j < (i + 8); j++) {
2717                         nfp_reta_conf[0].reta[j] = queue;
2718                         nfp_reta_conf[1].reta[j] = queue++;
2719                         queue %= rx_queues;
2720                 }
2721         }
2722         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2723         if (ret != 0)
2724                 return ret;
2725
2726         dev_conf = &dev->data->dev_conf;
2727         if (!dev_conf) {
2728                 RTE_LOG(INFO, PMD, "wrong rss conf");
2729                 return -EINVAL;
2730         }
2731         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2732
2733         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2734
2735         return ret;
2736 }
2737
2738
2739 /* Initialise and register driver with DPDK Application */
2740 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2741         .dev_configure          = nfp_net_configure,
2742         .dev_start              = nfp_net_start,
2743         .dev_stop               = nfp_net_stop,
2744         .dev_close              = nfp_net_close,
2745         .promiscuous_enable     = nfp_net_promisc_enable,
2746         .promiscuous_disable    = nfp_net_promisc_disable,
2747         .link_update            = nfp_net_link_update,
2748         .stats_get              = nfp_net_stats_get,
2749         .stats_reset            = nfp_net_stats_reset,
2750         .dev_infos_get          = nfp_net_infos_get,
2751         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2752         .mtu_set                = nfp_net_dev_mtu_set,
2753         .vlan_offload_set       = nfp_net_vlan_offload_set,
2754         .reta_update            = nfp_net_reta_update,
2755         .reta_query             = nfp_net_reta_query,
2756         .rss_hash_update        = nfp_net_rss_hash_update,
2757         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2758         .rx_queue_setup         = nfp_net_rx_queue_setup,
2759         .rx_queue_release       = nfp_net_rx_queue_release,
2760         .rx_queue_count         = nfp_net_rx_queue_count,
2761         .tx_queue_setup         = nfp_net_tx_queue_setup,
2762         .tx_queue_release       = nfp_net_tx_queue_release,
2763         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2764         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2765 };
2766
2767 /*
2768  * All eth_dev created got its private data, but before nfp_net_init, that
2769  * private data is referencing private data for all the PF ports. This is due
2770  * to how the vNIC bars are mapped based on first port, so all ports need info
2771  * about port 0 private data. Inside nfp_net_init the private data pointer is
2772  * changed to the right address for each port once the bars have been mapped.
2773  *
2774  * This functions helps to find out which port and therefore which offset
2775  * inside the private data array to use.
2776  */
2777 static int
2778 get_pf_port_number(char *name)
2779 {
2780         char *pf_str = name;
2781         int size = 0;
2782
2783         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2784                 pf_str++;
2785
2786         if (size == 30)
2787                 /*
2788                  * This should not happen at all and it would mean major
2789                  * implementation fault.
2790                  */
2791                 rte_panic("nfp_net: problem with pf device name\n");
2792
2793         /* Expecting _portX with X within [0,7] */
2794         pf_str += 5;
2795
2796         return (int)strtol(pf_str, NULL, 10);
2797 }
2798
2799 static int
2800 nfp_net_init(struct rte_eth_dev *eth_dev)
2801 {
2802         struct rte_pci_device *pci_dev;
2803         struct nfp_net_hw *hw, *hwport0;
2804
2805         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2806         uint32_t start_q;
2807         int stride = 4;
2808         int port = 0;
2809         int err;
2810
2811         PMD_INIT_FUNC_TRACE();
2812
2813         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2814
2815         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2816             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2817                 port = get_pf_port_number(eth_dev->data->name);
2818                 if (port < 0 || port > 7) {
2819                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2820                         return -ENODEV;
2821                 }
2822
2823                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2824
2825                 /* This points to port 0 private data */
2826                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2827
2828                 /* This points to the specific port private data */
2829                 hw = &hwport0[port];
2830         } else {
2831                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2832                 hwport0 = 0;
2833         }
2834
2835         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2836         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2837         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2838
2839         /* For secondary processes, the primary has done all the work */
2840         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2841                 return 0;
2842
2843         rte_eth_copy_pci_info(eth_dev, pci_dev);
2844
2845         hw->device_id = pci_dev->id.device_id;
2846         hw->vendor_id = pci_dev->id.vendor_id;
2847         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2848         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2849
2850         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2851                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2852                      pci_dev->addr.domain, pci_dev->addr.bus,
2853                      pci_dev->addr.devid, pci_dev->addr.function);
2854
2855         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2856         if (hw->ctrl_bar == NULL) {
2857                 RTE_LOG(ERR, PMD,
2858                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2859                 return -ENODEV;
2860         }
2861
2862         if (hw->is_pf && port == 0) {
2863                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2864                                              hw->total_ports * 32768,
2865                                              &hw->ctrl_area);
2866                 if (!hw->ctrl_bar) {
2867                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar\n");
2868                         return -EIO;
2869                 }
2870
2871                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2872         }
2873
2874         if (port > 0) {
2875                 if (!hwport0->ctrl_bar)
2876                         return -ENODEV;
2877
2878                 /* address based on port0 offset */
2879                 hw->ctrl_bar = hwport0->ctrl_bar +
2880                                (port * NFP_PF_CSR_SLICE_SIZE);
2881         }
2882
2883         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2884
2885         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2886         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2887
2888         /* Work out where in the BAR the queues start. */
2889         switch (pci_dev->id.device_id) {
2890         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2891         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2892         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2893                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2894                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2895                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2896                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2897                 break;
2898         default:
2899                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2900                 err = -ENODEV;
2901                 goto dev_err_ctrl_map;
2902         }
2903
2904         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2905         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2906
2907         if (hw->is_pf && port == 0) {
2908                 /* configure access to tx/rx vNIC BARs */
2909                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2910                                                       NFP_PCIE_QUEUE(0),
2911                                                       NFP_QCP_QUEUE_AREA_SZ,
2912                                                       &hw->hwqueues_area);
2913
2914                 if (!hwport0->hw_queues) {
2915                         printf("nfp_rtsym_map fails for net.qc\n");
2916                         err = -EIO;
2917                         goto dev_err_ctrl_map;
2918                 }
2919
2920                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p\n",
2921                                     hwport0->hw_queues);
2922         }
2923
2924         if (hw->is_pf) {
2925                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2926                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2927                 eth_dev->data->dev_private = hw;
2928         } else {
2929                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2930                              tx_bar_off;
2931                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2932                              rx_bar_off;
2933         }
2934
2935         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2936                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2937
2938         nfp_net_cfg_queue_setup(hw);
2939
2940         /* Get some of the read-only fields from the config BAR */
2941         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2942         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2943         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2944         hw->mtu = ETHER_MTU;
2945
2946         /* VLAN insertion is incompatible with LSOv2 */
2947         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2948                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2949
2950         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2951                 hw->rx_offset = NFP_NET_RX_OFFSET;
2952         else
2953                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2954
2955         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2956                      hw->ver, hw->max_mtu);
2957         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2958                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2959                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2960                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2961                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2962                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2963                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2964                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2965                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2966                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2967                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2968                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2969                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2970
2971         hw->ctrl = 0;
2972
2973         hw->stride_rx = stride;
2974         hw->stride_tx = stride;
2975
2976         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2977                      hw->max_rx_queues, hw->max_tx_queues);
2978
2979         /* Initializing spinlock for reconfigs */
2980         rte_spinlock_init(&hw->reconfig_lock);
2981
2982         /* Allocating memory for mac addr */
2983         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2984         if (eth_dev->data->mac_addrs == NULL) {
2985                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2986                 err = -ENOMEM;
2987                 goto dev_err_queues_map;
2988         }
2989
2990         if (hw->is_pf) {
2991                 nfp_net_pf_read_mac(hwport0, port);
2992                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2993         } else {
2994                 nfp_net_vf_read_mac(hw);
2995         }
2996
2997         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2998                 PMD_INIT_LOG(INFO, "Using random mac address for port %d\n",
2999                                    port);
3000                 /* Using random mac addresses for VFs */
3001                 eth_random_addr(&hw->mac_addr[0]);
3002                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
3003         }
3004
3005         /* Copying mac address to DPDK eth_dev struct */
3006         ether_addr_copy((struct ether_addr *)hw->mac_addr,
3007                         &eth_dev->data->mac_addrs[0]);
3008
3009         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
3010                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
3011                      eth_dev->data->port_id, pci_dev->id.vendor_id,
3012                      pci_dev->id.device_id,
3013                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
3014                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
3015
3016         /* Registering LSC interrupt handler */
3017         rte_intr_callback_register(&pci_dev->intr_handle,
3018                                    nfp_net_dev_interrupt_handler,
3019                                    (void *)eth_dev);
3020
3021         /* Telling the firmware about the LSC interrupt entry */
3022         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3023
3024         /* Recording current stats counters values */
3025         nfp_net_stats_reset(eth_dev);
3026
3027         return 0;
3028
3029 dev_err_queues_map:
3030                 nfp_cpp_area_free(hw->hwqueues_area);
3031 dev_err_ctrl_map:
3032                 nfp_cpp_area_free(hw->ctrl_area);
3033
3034         return err;
3035 }
3036
3037 static int
3038 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3039                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3040                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3041 {
3042         struct rte_eth_dev *eth_dev;
3043         struct nfp_net_hw *hw;
3044         char *port_name;
3045         int ret;
3046
3047         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3048         if (!port_name)
3049                 return -ENOMEM;
3050
3051         if (ports > 1)
3052                 sprintf(port_name, "%s_port%d", dev->device.name, port);
3053         else
3054                 sprintf(port_name, "%s", dev->device.name);
3055
3056         eth_dev = rte_eth_dev_allocate(port_name);
3057         if (!eth_dev)
3058                 return -ENOMEM;
3059
3060         if (port == 0) {
3061                 *priv = rte_zmalloc(port_name,
3062                                     sizeof(struct nfp_net_adapter) * ports,
3063                                     RTE_CACHE_LINE_SIZE);
3064                 if (!*priv) {
3065                         rte_eth_dev_release_port(eth_dev);
3066                         return -ENOMEM;
3067                 }
3068         }
3069
3070         eth_dev->data->dev_private = *priv;
3071
3072         /*
3073          * dev_private pointing to port0 dev_private because we need
3074          * to configure vNIC bars based on port0 at nfp_net_init.
3075          * Then dev_private is adjusted per port.
3076          */
3077         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3078         hw->cpp = cpp;
3079         hw->hwinfo = hwinfo;
3080         hw->sym_tbl = sym_tbl;
3081         hw->pf_port_idx = phys_port;
3082         hw->is_pf = 1;
3083         if (ports > 1)
3084                 hw->pf_multiport_enabled = 1;
3085
3086         hw->total_ports = ports;
3087
3088         eth_dev->device = &dev->device;
3089         rte_eth_copy_pci_info(eth_dev, dev);
3090
3091         ret = nfp_net_init(eth_dev);
3092
3093         if (ret)
3094                 rte_eth_dev_release_port(eth_dev);
3095
3096         rte_free(port_name);
3097
3098         return ret;
3099 }
3100
3101 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3102
3103 static int
3104 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3105 {
3106         struct nfp_cpp *cpp = nsp->cpp;
3107         int fw_f;
3108         char *fw_buf;
3109         char fw_name[100];
3110         char serial[100];
3111         struct stat file_stat;
3112         off_t fsize, bytes;
3113
3114         /* Looking for firmware file in order of priority */
3115
3116         /* First try to find a firmware image specific for this device */
3117         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3118                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3119                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3120                 cpp->interface & 0xff);
3121
3122         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3123
3124         RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3125         fw_f = open(fw_name, O_RDONLY);
3126         if (fw_f > 0)
3127                 goto read_fw;
3128
3129         /* Then try the PCI name */
3130         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3131
3132         RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3133         fw_f = open(fw_name, O_RDONLY);
3134         if (fw_f > 0)
3135                 goto read_fw;
3136
3137         /* Finally try the card type and media */
3138         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3139         RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3140         fw_f = open(fw_name, O_RDONLY);
3141         if (fw_f < 0) {
3142                 RTE_LOG(INFO, PMD, "Firmware file %s not found.", fw_name);
3143                 return -ENOENT;
3144         }
3145
3146 read_fw:
3147         if (fstat(fw_f, &file_stat) < 0) {
3148                 RTE_LOG(INFO, PMD, "Firmware file %s size is unknown", fw_name);
3149                 close(fw_f);
3150                 return -ENOENT;
3151         }
3152
3153         fsize = file_stat.st_size;
3154         RTE_LOG(INFO, PMD, "Firmware file found at %s with size: %" PRIu64 "\n",
3155                             fw_name, (uint64_t)fsize);
3156
3157         fw_buf = malloc((size_t)fsize);
3158         if (!fw_buf) {
3159                 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
3160                 close(fw_f);
3161                 return -ENOMEM;
3162         }
3163         memset(fw_buf, 0, fsize);
3164
3165         bytes = read(fw_f, fw_buf, fsize);
3166         if (bytes != fsize) {
3167                 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
3168                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3169                                    (uint64_t)bytes, (uint64_t)fsize);
3170                 free(fw_buf);
3171                 close(fw_f);
3172                 return -EIO;
3173         }
3174
3175         RTE_LOG(INFO, PMD, "Uploading the firmware ...");
3176         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3177         RTE_LOG(INFO, PMD, "Done");
3178
3179         free(fw_buf);
3180         close(fw_f);
3181
3182         return 0;
3183 }
3184
3185 static int
3186 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3187              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3188 {
3189         struct nfp_nsp *nsp;
3190         const char *nfp_fw_model;
3191         char card_desc[100];
3192         int err = 0;
3193
3194         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3195
3196         if (nfp_fw_model) {
3197                 RTE_LOG(INFO, PMD, "firmware model found: %s\n", nfp_fw_model);
3198         } else {
3199                 RTE_LOG(ERR, PMD, "firmware model NOT found\n");
3200                 return -EIO;
3201         }
3202
3203         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3204                 RTE_LOG(ERR, PMD, "NFP ethernet table reports wrong ports: %u\n",
3205                        nfp_eth_table->count);
3206                 return -EIO;
3207         }
3208
3209         RTE_LOG(INFO, PMD, "NFP ethernet port table reports %u ports\n",
3210                            nfp_eth_table->count);
3211
3212         RTE_LOG(INFO, PMD, "Port speed: %u\n", nfp_eth_table->ports[0].speed);
3213
3214         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3215                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3216
3217         nsp = nfp_nsp_open(cpp);
3218         if (!nsp) {
3219                 RTE_LOG(ERR, PMD, "NFP error when obtaining NSP handle\n");
3220                 return -EIO;
3221         }
3222
3223         nfp_nsp_device_soft_reset(nsp);
3224         err = nfp_fw_upload(dev, nsp, card_desc);
3225
3226         nfp_nsp_close(nsp);
3227         return err;
3228 }
3229
3230 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3231                             struct rte_pci_device *dev)
3232 {
3233         struct nfp_cpp *cpp;
3234         struct nfp_hwinfo *hwinfo;
3235         struct nfp_rtsym_table *sym_tbl;
3236         struct nfp_eth_table *nfp_eth_table = NULL;
3237         int total_ports;
3238         void *priv = 0;
3239         int ret = -ENODEV;
3240         int err;
3241         int i;
3242
3243         if (!dev)
3244                 return ret;
3245
3246         cpp = nfp_cpp_from_device_name(dev->device.name);
3247         if (!cpp) {
3248                 RTE_LOG(ERR, PMD, "A CPP handle can not be obtained");
3249                 ret = -EIO;
3250                 goto error;
3251         }
3252
3253         hwinfo = nfp_hwinfo_read(cpp);
3254         if (!hwinfo) {
3255                 RTE_LOG(ERR, PMD, "Error reading hwinfo table");
3256                 return -EIO;
3257         }
3258
3259         nfp_eth_table = nfp_eth_read_ports(cpp);
3260         if (!nfp_eth_table) {
3261                 RTE_LOG(ERR, PMD, "Error reading NFP ethernet table\n");
3262                 return -EIO;
3263         }
3264
3265         if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3266                 RTE_LOG(INFO, PMD, "Error when uploading firmware\n");
3267                 ret = -EIO;
3268                 goto error;
3269         }
3270
3271         /* Now the symbol table should be there */
3272         sym_tbl = nfp_rtsym_table_read(cpp);
3273         if (!sym_tbl) {
3274                 RTE_LOG(ERR, PMD, "Something is wrong with the firmware"
3275                                 " symbol table");
3276                 ret = -EIO;
3277                 goto error;
3278         }
3279
3280         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3281         if (total_ports != (int)nfp_eth_table->count) {
3282                 RTE_LOG(ERR, PMD, "Inconsistent number of ports\n");
3283                 ret = -EIO;
3284                 goto error;
3285         }
3286         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
3287
3288         if (total_ports <= 0 || total_ports > 8) {
3289                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
3290                 ret = -ENODEV;
3291                 goto error;
3292         }
3293
3294         for (i = 0; i < total_ports; i++) {
3295                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3296                                         nfp_eth_table->ports[i].index,
3297                                         sym_tbl, &priv);
3298                 if (ret)
3299                         break;
3300         }
3301
3302 error:
3303         free(nfp_eth_table);
3304         return ret;
3305 }
3306
3307 int nfp_logtype_init;
3308 int nfp_logtype_driver;
3309
3310 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3311         {
3312                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3313                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3314         },
3315         {
3316                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3317                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3318         },
3319         {
3320                 .vendor_id = 0,
3321         },
3322 };
3323
3324 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3325         {
3326                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3327                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3328         },
3329         {
3330                 .vendor_id = 0,
3331         },
3332 };
3333
3334 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3335         struct rte_pci_device *pci_dev)
3336 {
3337         return rte_eth_dev_pci_generic_probe(pci_dev,
3338                 sizeof(struct nfp_net_adapter), nfp_net_init);
3339 }
3340
3341 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3342 {
3343         struct rte_eth_dev *eth_dev;
3344         struct nfp_net_hw *hw, *hwport0;
3345         int port = 0;
3346
3347         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3348         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3349             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3350                 port = get_pf_port_number(eth_dev->data->name);
3351                 /*
3352                  * hotplug is not possible with multiport PF although freeing
3353                  * data structures can be done for first port.
3354                  */
3355                 if (port != 0)
3356                         return -ENOTSUP;
3357                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3358                 hw = &hwport0[port];
3359                 nfp_cpp_area_free(hw->ctrl_area);
3360                 nfp_cpp_area_free(hw->hwqueues_area);
3361                 free(hw->hwinfo);
3362                 free(hw->sym_tbl);
3363                 nfp_cpp_free(hw->cpp);
3364         } else {
3365                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3366         }
3367         /* hotplug is not possible with multiport PF */
3368         if (hw->pf_multiport_enabled)
3369                 return -ENOTSUP;
3370         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3371 }
3372
3373 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3374         .id_table = pci_id_nfp_pf_net_map,
3375         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3376         .probe = nfp_pf_pci_probe,
3377         .remove = eth_nfp_pci_remove,
3378 };
3379
3380 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3381         .id_table = pci_id_nfp_vf_net_map,
3382         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3383         .probe = eth_nfp_pci_probe,
3384         .remove = eth_nfp_pci_remove,
3385 };
3386
3387 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3388 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3389 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3390 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3391 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3392 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3393
3394 RTE_INIT(nfp_init_log);
3395 static void
3396 nfp_init_log(void)
3397 {
3398         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3399         if (nfp_logtype_init >= 0)
3400                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3401         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3402         if (nfp_logtype_driver >= 0)
3403                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3404 }
3405 /*
3406  * Local variables:
3407  * c-file-style: "Linux"
3408  * indent-tabs-mode: t
3409  * End:
3410  */