drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfpcore/nfp_cpp.h"
  59 #include "nfpcore/nfp_nffw.h"
  60 #include "nfpcore/nfp_hwinfo.h"
  61 #include "nfpcore/nfp_mip.h"
  62 #include "nfpcore/nfp_rtsym.h"
  63 #include "nfpcore/nfp_nsp.h"
  64
  65 #include "nfp_net_pmd.h"
  66 #include "nfp_net_logs.h"
  67 #include "nfp_net_ctrl.h"
  68
  69 /* Prototypes */
  70 static void nfp_net_close(struct rte_eth_dev *dev);
  71 static int nfp_net_configure(struct rte_eth_dev *dev);
  72 static void nfp_net_dev_interrupt_handler(void *param);
  73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  76                               struct rte_eth_dev_info *dev_info);
  77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  83                                        uint16_t queue_idx);
  84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  85                                   uint16_t nb_pkts);
  86 static void nfp_net_rx_queue_release(void *rxq);
  87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_rxconf *rx_conf,
  90                                   struct rte_mempool *mp);
  91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  92 static void nfp_net_tx_queue_release(void *txq);
  93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  94                                   uint16_t nb_desc, unsigned int socket_id,
  95                                   const struct rte_eth_txconf *tx_conf);
  96 static int nfp_net_start(struct rte_eth_dev *dev);
  97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  98                               struct rte_eth_stats *stats);
  99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 100 static void nfp_net_stop(struct rte_eth_dev *dev);
 101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 102                                   uint16_t nb_pkts);
 103
 104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 106                                    struct rte_eth_rss_conf *rss_conf);
 107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 108                     struct rte_eth_rss_reta_entry64 *reta_conf,
 109                     uint16_t reta_size);
 110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 111                         struct rte_eth_rss_conf *rss_conf);
 112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 113                              struct ether_addr *mac_addr);
 114
 115 /* The offset of the queue controller queues in the PCIe Target */
 116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 117
 118 /* Maximum value which can be added to a queue with one transaction */
 119 #define NFP_QCP_MAX_ADD 0x7f
 120
 121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 122         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 123
 124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 125 enum nfp_qcp_ptr {
 126         NFP_QCP_READ_PTR = 0,
 127         NFP_QCP_WRITE_PTR
 128 };
 129
 130 /*
 131  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 132  * @q: Base address for queue structure
 133  * @ptr: Add to the Read or Write pointer
 134  * @val: Value to add to the queue pointer
 135  *
 136  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 137  */
 138 static inline void
 139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 140 {
 141         uint32_t off;
 142
 143         if (ptr == NFP_QCP_READ_PTR)
 144                 off = NFP_QCP_QUEUE_ADD_RPTR;
 145         else
 146                 off = NFP_QCP_QUEUE_ADD_WPTR;
 147
 148         while (val > NFP_QCP_MAX_ADD) {
 149                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 150                 val -= NFP_QCP_MAX_ADD;
 151         }
 152
 153         nn_writel(rte_cpu_to_le_32(val), q + off);
 154 }
 155
 156 /*
 157  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 158  * @q:  Base address for queue structure
 159  * @ptr: Read or Write pointer
 160  */
 161 static inline uint32_t
 162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 163 {
 164         uint32_t off;
 165         uint32_t val;
 166
 167         if (ptr == NFP_QCP_READ_PTR)
 168                 off = NFP_QCP_QUEUE_STS_LO;
 169         else
 170                 off = NFP_QCP_QUEUE_STS_HI;
 171
 172         val = rte_cpu_to_le_32(nn_readl(q + off));
 173
 174         if (ptr == NFP_QCP_READ_PTR)
 175                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 176         else
 177                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 178 }
 179
 180 /*
 181  * Functions to read/write from/to Config BAR
 182  * Performs any endian conversion necessary.
 183  */
 184 static inline uint8_t
 185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 186 {
 187         return nn_readb(hw->ctrl_bar + off);
 188 }
 189
 190 static inline void
 191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 192 {
 193         nn_writeb(val, hw->ctrl_bar + off);
 194 }
 195
 196 static inline uint32_t
 197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 198 {
 199         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 200 }
 201
 202 static inline void
 203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 204 {
 205         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 206 }
 207
 208 static inline uint64_t
 209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 210 {
 211         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 212 }
 213
 214 static inline void
 215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 216 {
 217         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 218 }
 219
 220 static void
 221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 222 {
 223         unsigned i;
 224
 225         if (rxq->rxbufs == NULL)
 226                 return;
 227
 228         for (i = 0; i < rxq->rx_count; i++) {
 229                 if (rxq->rxbufs[i].mbuf) {
 230                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 231                         rxq->rxbufs[i].mbuf = NULL;
 232                 }
 233         }
 234 }
 235
 236 static void
 237 nfp_net_rx_queue_release(void *rx_queue)
 238 {
 239         struct nfp_net_rxq *rxq = rx_queue;
 240
 241         if (rxq) {
 242                 nfp_net_rx_queue_release_mbufs(rxq);
 243                 rte_free(rxq->rxbufs);
 244                 rte_free(rxq);
 245         }
 246 }
 247
 248 static void
 249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 250 {
 251         nfp_net_rx_queue_release_mbufs(rxq);
 252         rxq->rd_p = 0;
 253         rxq->nb_rx_hold = 0;
 254 }
 255
 256 static void
 257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 258 {
 259         unsigned i;
 260
 261         if (txq->txbufs == NULL)
 262                 return;
 263
 264         for (i = 0; i < txq->tx_count; i++) {
 265                 if (txq->txbufs[i].mbuf) {
 266                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 267                         txq->txbufs[i].mbuf = NULL;
 268                 }
 269         }
 270 }
 271
 272 static void
 273 nfp_net_tx_queue_release(void *tx_queue)
 274 {
 275         struct nfp_net_txq *txq = tx_queue;
 276
 277         if (txq) {
 278                 nfp_net_tx_queue_release_mbufs(txq);
 279                 rte_free(txq->txbufs);
 280                 rte_free(txq);
 281         }
 282 }
 283
 284 static void
 285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 286 {
 287         nfp_net_tx_queue_release_mbufs(txq);
 288         txq->wr_p = 0;
 289         txq->rd_p = 0;
 290 }
 291
 292 static int
 293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 294 {
 295         int cnt;
 296         uint32_t new;
 297         struct timespec wait;
 298
 299         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 300                     hw->qcp_cfg);
 301
 302         if (hw->qcp_cfg == NULL)
 303                 rte_panic("Bad configuration queue pointer\n");
 304
 305         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 306
 307         wait.tv_sec = 0;
 308         wait.tv_nsec = 1000000;
 309
 310         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 311
 312         /* Poll update field, waiting for NFP to ack the config */
 313         for (cnt = 0; ; cnt++) {
 314                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 315                 if (new == 0)
 316                         break;
 317                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 318                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 319                         return -1;
 320                 }
 321                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 322                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 323                                           " %dms", update, cnt);
 324                         rte_panic("Exiting\n");
 325                 }
 326                 nanosleep(&wait, 0); /* waiting for a 1ms */
 327         }
 328         PMD_DRV_LOG(DEBUG, "Ack DONE");
 329         return 0;
 330 }
 331
 332 /*
 333  * Reconfigure the NIC
 334  * @nn:    device to reconfigure
 335  * @ctrl:    The value for the ctrl field in the BAR config
 336  * @update:  The value for the update field in the BAR config
 337  *
 338  * Write the update word to the BAR and ping the reconfig queue. Then poll
 339  * until the firmware has acknowledged the update by zeroing the update word.
 340  */
 341 static int
 342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 343 {
 344         uint32_t err;
 345
 346         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 347                     ctrl, update);
 348
 349         rte_spinlock_lock(&hw->reconfig_lock);
 350
 351         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 352         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 353
 354         rte_wmb();
 355
 356         err = __nfp_net_reconfig(hw, update);
 357
 358         rte_spinlock_unlock(&hw->reconfig_lock);
 359
 360         if (!err)
 361                 return 0;
 362
 363         /*
 364          * Reconfig errors imply situations where they can be handled.
 365          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 366          */
 367         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 368                      ctrl, update);
 369         return -EIO;
 370 }
 371
 372 /*
 373  * Configure an Ethernet device. This function must be invoked first
 374  * before any other function in the Ethernet API. This function can
 375  * also be re-invoked when a device is in the stopped state.
 376  */
 377 static int
 378 nfp_net_configure(struct rte_eth_dev *dev)
 379 {
 380         struct rte_eth_conf *dev_conf;
 381         struct rte_eth_rxmode *rxmode;
 382         struct rte_eth_txmode *txmode;
 383         struct nfp_net_hw *hw;
 384
 385         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 386
 387         /*
 388          * A DPDK app sends info about how many queues to use and how
 389          * those queues need to be configured. This is used by the
 390          * DPDK core and it makes sure no more queues than those
 391          * advertised by the driver are requested. This function is
 392          * called after that internal process
 393          */
 394
 395         PMD_INIT_LOG(DEBUG, "Configure");
 396
 397         dev_conf = &dev->data->dev_conf;
 398         rxmode = &dev_conf->rxmode;
 399         txmode = &dev_conf->txmode;
 400
 401         /* Checking TX mode */
 402         if (txmode->mq_mode) {
 403                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 404                 return -EINVAL;
 405         }
 406
 407         /* Checking RX mode */
 408         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 409             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 410                 PMD_INIT_LOG(INFO, "RSS not supported");
 411                 return -EINVAL;
 412         }
 413
 414         /* Checking RX offloads */
 415         if (!(rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP))
 416                 PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!");
 417
 418         return 0;
 419 }
 420
 421 static void
 422 nfp_net_enable_queues(struct rte_eth_dev *dev)
 423 {
 424         struct nfp_net_hw *hw;
 425         uint64_t enabled_queues = 0;
 426         int i;
 427
 428         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 429
 430         /* Enabling the required TX queues in the device */
 431         for (i = 0; i < dev->data->nb_tx_queues; i++)
 432                 enabled_queues |= (1 << i);
 433
 434         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 435
 436         enabled_queues = 0;
 437
 438         /* Enabling the required RX queues in the device */
 439         for (i = 0; i < dev->data->nb_rx_queues; i++)
 440                 enabled_queues |= (1 << i);
 441
 442         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 443 }
 444
 445 static void
 446 nfp_net_disable_queues(struct rte_eth_dev *dev)
 447 {
 448         struct nfp_net_hw *hw;
 449         uint32_t new_ctrl, update = 0;
 450
 451         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 452
 453         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 454         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 455
 456         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 457         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 458                  NFP_NET_CFG_UPDATE_MSIX;
 459
 460         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 461                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 462
 463         /* If an error when reconfig we avoid to change hw state */
 464         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 465                 return;
 466
 467         hw->ctrl = new_ctrl;
 468 }
 469
 470 static int
 471 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 472 {
 473         int i;
 474
 475         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 476                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 477                         return -1;
 478         }
 479         return 0;
 480 }
 481
 482 static void
 483 nfp_net_params_setup(struct nfp_net_hw *hw)
 484 {
 485         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 486         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 487 }
 488
 489 static void
 490 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 491 {
 492         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 493 }
 494
 495 #define ETH_ADDR_LEN    6
 496
 497 static void
 498 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 499 {
 500         int i;
 501
 502         for (i = 0; i < ETH_ADDR_LEN; i++)
 503                 dst[i] = src[i];
 504 }
 505
 506 static int
 507 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 508 {
 509         struct nfp_eth_table *nfp_eth_table;
 510
 511         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 512         /*
 513          * hw points to port0 private data. We need hw now pointing to
 514          * right port.
 515          */
 516         hw += port;
 517         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 518                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 519
 520         free(nfp_eth_table);
 521         return 0;
 522 }
 523
 524 static void
 525 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 526 {
 527         uint32_t tmp;
 528
 529         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 530         memcpy(&hw->mac_addr[0], &tmp, 4);
 531
 532         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 533         memcpy(&hw->mac_addr[4], &tmp, 2);
 534 }
 535
 536 static void
 537 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 538 {
 539         uint32_t mac0 = *(uint32_t *)mac;
 540         uint16_t mac1;
 541
 542         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 543
 544         mac += 4;
 545         mac1 = *(uint16_t *)mac;
 546         nn_writew(rte_cpu_to_be_16(mac1),
 547                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 548 }
 549
 550 int
 551 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 552 {
 553         struct nfp_net_hw *hw;
 554         uint32_t update, ctrl;
 555
 556         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 557         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 558             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 559                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 560                                   " port enabled");
 561                 return -EBUSY;
 562         }
 563
 564         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 565             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 566                 return -EBUSY;
 567
 568         /* Writing new MAC to the specific port BAR address */
 569         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 570
 571         /* Signal the NIC about the change */
 572         update = NFP_NET_CFG_UPDATE_MACADDR;
 573         ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
 574         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 575                 PMD_INIT_LOG(INFO, "MAC address update failed");
 576                 return -EIO;
 577         }
 578         return 0;
 579 }
 580
 581 static int
 582 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 583                            struct rte_intr_handle *intr_handle)
 584 {
 585         struct nfp_net_hw *hw;
 586         int i;
 587
 588         if (!intr_handle->intr_vec) {
 589                 intr_handle->intr_vec =
 590                         rte_zmalloc("intr_vec",
 591                                     dev->data->nb_rx_queues * sizeof(int), 0);
 592                 if (!intr_handle->intr_vec) {
 593                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 594                                      " intr_vec", dev->data->nb_rx_queues);
 595                         return -ENOMEM;
 596                 }
 597         }
 598
 599         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 600
 601         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 602                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 603                 /* UIO just supports one queue and no LSC*/
 604                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 605                 intr_handle->intr_vec[0] = 0;
 606         } else {
 607                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 608                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 609                         /*
 610                          * The first msix vector is reserved for non
 611                          * efd interrupts
 612                         */
 613                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 614                         intr_handle->intr_vec[i] = i + 1;
 615                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 616                                             intr_handle->intr_vec[i]);
 617                 }
 618         }
 619
 620         /* Avoiding TX interrupts */
 621         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 622         return 0;
 623 }
 624
 625 static uint32_t
 626 nfp_check_offloads(struct rte_eth_dev *dev)
 627 {
 628         struct nfp_net_hw *hw;
 629         struct rte_eth_conf *dev_conf;
 630         struct rte_eth_rxmode *rxmode;
 631         struct rte_eth_txmode *txmode;
 632         uint32_t ctrl = 0;
 633
 634         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 635
 636         dev_conf = &dev->data->dev_conf;
 637         rxmode = &dev_conf->rxmode;
 638         txmode = &dev_conf->txmode;
 639
 640         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 641                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 642                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 643         }
 644
 645         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 646                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 647                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 648         }
 649
 650         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 651                 hw->mtu = rxmode->max_rx_pkt_len;
 652
 653         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 654                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 655
 656         /* L2 broadcast */
 657         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 658                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 659
 660         /* L2 multicast */
 661         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 662                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 663
 664         /* TX checksum offload */
 665         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 666             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 667             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 668                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 669
 670         /* LSO offload */
 671         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 672                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 673                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 674                 else
 675                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 676         }
 677
 678         /* RX gather */
 679         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 680                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 681
 682         return ctrl;
 683 }
 684
 685 static int
 686 nfp_net_start(struct rte_eth_dev *dev)
 687 {
 688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 690         uint32_t new_ctrl, update = 0;
 691         struct nfp_net_hw *hw;
 692         struct rte_eth_conf *dev_conf;
 693         struct rte_eth_rxmode *rxmode;
 694         uint32_t intr_vector;
 695         int ret;
 696
 697         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 698
 699         PMD_INIT_LOG(DEBUG, "Start");
 700
 701         /* Disabling queues just in case... */
 702         nfp_net_disable_queues(dev);
 703
 704         /* Enabling the required queues in the device */
 705         nfp_net_enable_queues(dev);
 706
 707         /* check and configure queue intr-vector mapping */
 708         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 709                 if (hw->pf_multiport_enabled) {
 710                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 711                                           "with NFP multiport PF");
 712                                 return -EINVAL;
 713                 }
 714                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 715                         /*
 716                          * Better not to share LSC with RX interrupts.
 717                          * Unregistering LSC interrupt handler
 718                          */
 719                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 720                                 nfp_net_dev_interrupt_handler, (void *)dev);
 721
 722                         if (dev->data->nb_rx_queues > 1) {
 723                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 724                                              "supports 1 queue with UIO");
 725                                 return -EIO;
 726                         }
 727                 }
 728                 intr_vector = dev->data->nb_rx_queues;
 729                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 730                         return -1;
 731
 732                 nfp_configure_rx_interrupt(dev, intr_handle);
 733                 update = NFP_NET_CFG_UPDATE_MSIX;
 734         }
 735
 736         rte_intr_enable(intr_handle);
 737
 738         new_ctrl = nfp_check_offloads(dev);
 739
 740         /* Writing configuration parameters in the device */
 741         nfp_net_params_setup(hw);
 742
 743         dev_conf = &dev->data->dev_conf;
 744         rxmode = &dev_conf->rxmode;
 745
 746         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 747                 nfp_net_rss_config_default(dev);
 748                 update |= NFP_NET_CFG_UPDATE_RSS;
 749                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 750         }
 751
 752         /* Enable device */
 753         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 754
 755         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 756
 757         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 758                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 759
 760         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 761         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 762                 return -EIO;
 763
 764         /*
 765          * Allocating rte mbuffs for configured rx queues.
 766          * This requires queues being enabled before
 767          */
 768         if (nfp_net_rx_freelist_setup(dev) < 0) {
 769                 ret = -ENOMEM;
 770                 goto error;
 771         }
 772
 773         if (hw->is_pf)
 774                 /* Configure the physical port up */
 775                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 776
 777         hw->ctrl = new_ctrl;
 778
 779         return 0;
 780
 781 error:
 782         /*
 783          * An error returned by this function should mean the app
 784          * exiting and then the system releasing all the memory
 785          * allocated even memory coming from hugepages.
 786          *
 787          * The device could be enabled at this point with some queues
 788          * ready for getting packets. This is true if the call to
 789          * nfp_net_rx_freelist_setup() succeeds for some queues but
 790          * fails for subsequent queues.
 791          *
 792          * This should make the app exiting but better if we tell the
 793          * device first.
 794          */
 795         nfp_net_disable_queues(dev);
 796
 797         return ret;
 798 }
 799
 800 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 801 static void
 802 nfp_net_stop(struct rte_eth_dev *dev)
 803 {
 804         int i;
 805         struct nfp_net_hw *hw;
 806
 807         PMD_INIT_LOG(DEBUG, "Stop");
 808
 809         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 810
 811         nfp_net_disable_queues(dev);
 812
 813         /* Clear queues */
 814         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 815                 nfp_net_reset_tx_queue(
 816                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 817         }
 818
 819         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 820                 nfp_net_reset_rx_queue(
 821                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 822         }
 823
 824         if (hw->is_pf)
 825                 /* Configure the physical port down */
 826                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 827 }
 828
 829 /* Reset and stop device. The device can not be restarted. */
 830 static void
 831 nfp_net_close(struct rte_eth_dev *dev)
 832 {
 833         struct nfp_net_hw *hw;
 834         struct rte_pci_device *pci_dev;
 835         int i;
 836
 837         PMD_INIT_LOG(DEBUG, "Close");
 838
 839         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 840         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 841
 842         /*
 843          * We assume that the DPDK application is stopping all the
 844          * threads/queues before calling the device close function.
 845          */
 846
 847         nfp_net_disable_queues(dev);
 848
 849         /* Clear queues */
 850         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 851                 nfp_net_reset_tx_queue(
 852                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 853         }
 854
 855         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 856                 nfp_net_reset_rx_queue(
 857                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 858         }
 859
 860         rte_intr_disable(&pci_dev->intr_handle);
 861         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 862
 863         /* unregister callback func from eal lib */
 864         rte_intr_callback_unregister(&pci_dev->intr_handle,
 865                                      nfp_net_dev_interrupt_handler,
 866                                      (void *)dev);
 867
 868         /*
 869          * The ixgbe PMD driver disables the pcie master on the
 870          * device. The i40e does not...
 871          */
 872 }
 873
 874 static void
 875 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 876 {
 877         uint32_t new_ctrl, update = 0;
 878         struct nfp_net_hw *hw;
 879
 880         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 881
 882         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 883
 884         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 885                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 886                 return;
 887         }
 888
 889         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 890                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 891                 return;
 892         }
 893
 894         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 895         update = NFP_NET_CFG_UPDATE_GEN;
 896
 897         /*
 898          * DPDK sets promiscuous mode on just after this call assuming
 899          * it can not fail ...
 900          */
 901         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 902                 return;
 903
 904         hw->ctrl = new_ctrl;
 905 }
 906
 907 static void
 908 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 909 {
 910         uint32_t new_ctrl, update = 0;
 911         struct nfp_net_hw *hw;
 912
 913         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914
 915         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 916                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 917                 return;
 918         }
 919
 920         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 921         update = NFP_NET_CFG_UPDATE_GEN;
 922
 923         /*
 924          * DPDK sets promiscuous mode off just before this call
 925          * assuming it can not fail ...
 926          */
 927         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 928                 return;
 929
 930         hw->ctrl = new_ctrl;
 931 }
 932
 933 /*
 934  * return 0 means link status changed, -1 means not changed
 935  *
 936  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 937  * status.
 938  */
 939 static int
 940 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 941 {
 942         struct nfp_net_hw *hw;
 943         struct rte_eth_link link;
 944         uint32_t nn_link_status;
 945         int ret;
 946
 947         static const uint32_t ls_to_ethtool[] = {
 948                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 949                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 950                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 951                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 952                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 953                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 954                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 955                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 956         };
 957
 958         PMD_DRV_LOG(DEBUG, "Link update");
 959
 960         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961
 962         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 963
 964         memset(&link, 0, sizeof(struct rte_eth_link));
 965
 966         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 967                 link.link_status = ETH_LINK_UP;
 968
 969         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 970
 971         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 972                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 973
 974         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 975                 link.link_speed = ETH_SPEED_NUM_NONE;
 976         else
 977                 link.link_speed = ls_to_ethtool[nn_link_status];
 978
 979         ret = rte_eth_linkstatus_set(dev, &link);
 980         if (ret == 0) {
 981                 if (link.link_status)
 982                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 983                 else
 984                         PMD_DRV_LOG(INFO, "NIC Link is Down");
 985         }
 986         return ret;
 987 }
 988
 989 static int
 990 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 991 {
 992         int i;
 993         struct nfp_net_hw *hw;
 994         struct rte_eth_stats nfp_dev_stats;
 995
 996         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997
 998         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
 999
1000         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1001
1002         /* reading per RX ring stats */
1003         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1004                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1005                         break;
1006
1007                 nfp_dev_stats.q_ipackets[i] =
1008                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1009
1010                 nfp_dev_stats.q_ipackets[i] -=
1011                         hw->eth_stats_base.q_ipackets[i];
1012
1013                 nfp_dev_stats.q_ibytes[i] =
1014                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1015
1016                 nfp_dev_stats.q_ibytes[i] -=
1017                         hw->eth_stats_base.q_ibytes[i];
1018         }
1019
1020         /* reading per TX ring stats */
1021         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1022                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1023                         break;
1024
1025                 nfp_dev_stats.q_opackets[i] =
1026                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1027
1028                 nfp_dev_stats.q_opackets[i] -=
1029                         hw->eth_stats_base.q_opackets[i];
1030
1031                 nfp_dev_stats.q_obytes[i] =
1032                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1033
1034                 nfp_dev_stats.q_obytes[i] -=
1035                         hw->eth_stats_base.q_obytes[i];
1036         }
1037
1038         nfp_dev_stats.ipackets =
1039                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1040
1041         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1042
1043         nfp_dev_stats.ibytes =
1044                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1045
1046         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1047
1048         nfp_dev_stats.opackets =
1049                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1050
1051         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1052
1053         nfp_dev_stats.obytes =
1054                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1055
1056         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1057
1058         /* reading general device stats */
1059         nfp_dev_stats.ierrors =
1060                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1061
1062         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1063
1064         nfp_dev_stats.oerrors =
1065                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1066
1067         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1068
1069         /* RX ring mbuf allocation failures */
1070         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1071
1072         nfp_dev_stats.imissed =
1073                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1074
1075         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1076
1077         if (stats) {
1078                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1079                 return 0;
1080         }
1081         return -EINVAL;
1082 }
1083
1084 static void
1085 nfp_net_stats_reset(struct rte_eth_dev *dev)
1086 {
1087         int i;
1088         struct nfp_net_hw *hw;
1089
1090         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091
1092         /*
1093          * hw->eth_stats_base records the per counter starting point.
1094          * Lets update it now
1095          */
1096
1097         /* reading per RX ring stats */
1098         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1099                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1100                         break;
1101
1102                 hw->eth_stats_base.q_ipackets[i] =
1103                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1104
1105                 hw->eth_stats_base.q_ibytes[i] =
1106                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1107         }
1108
1109         /* reading per TX ring stats */
1110         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1111                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1112                         break;
1113
1114                 hw->eth_stats_base.q_opackets[i] =
1115                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1116
1117                 hw->eth_stats_base.q_obytes[i] =
1118                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1119         }
1120
1121         hw->eth_stats_base.ipackets =
1122                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1123
1124         hw->eth_stats_base.ibytes =
1125                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1126
1127         hw->eth_stats_base.opackets =
1128                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1129
1130         hw->eth_stats_base.obytes =
1131                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1132
1133         /* reading general device stats */
1134         hw->eth_stats_base.ierrors =
1135                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1136
1137         hw->eth_stats_base.oerrors =
1138                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1139
1140         /* RX ring mbuf allocation failures */
1141         dev->data->rx_mbuf_alloc_failed = 0;
1142
1143         hw->eth_stats_base.imissed =
1144                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1145 }
1146
1147 static void
1148 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1149 {
1150         struct nfp_net_hw *hw;
1151
1152         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153
1154         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1155         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1156         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1157         dev_info->max_rx_pktlen = hw->max_mtu;
1158         /* Next should change when PF support is implemented */
1159         dev_info->max_mac_addrs = 1;
1160
1161         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1162                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1163
1164         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1165                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1166                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1167                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1168
1169         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1170
1171         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1172                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1173
1174         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1175                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1176                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1177                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1178
1179         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1180                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1181
1182         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1183                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1184
1185         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1186                 .rx_thresh = {
1187                         .pthresh = DEFAULT_RX_PTHRESH,
1188                         .hthresh = DEFAULT_RX_HTHRESH,
1189                         .wthresh = DEFAULT_RX_WTHRESH,
1190                 },
1191                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1192                 .rx_drop_en = 0,
1193         };
1194
1195         dev_info->default_txconf = (struct rte_eth_txconf) {
1196                 .tx_thresh = {
1197                         .pthresh = DEFAULT_TX_PTHRESH,
1198                         .hthresh = DEFAULT_TX_HTHRESH,
1199                         .wthresh = DEFAULT_TX_WTHRESH,
1200                 },
1201                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1202                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1203         };
1204
1205         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1206                                            ETH_RSS_NONFRAG_IPV4_UDP |
1207                                            ETH_RSS_NONFRAG_IPV6_TCP |
1208                                            ETH_RSS_NONFRAG_IPV6_UDP;
1209
1210         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1211         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1212
1213         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1214                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1215                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1216 }
1217
1218 static const uint32_t *
1219 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1220 {
1221         static const uint32_t ptypes[] = {
1222                 /* refers to nfp_net_set_hash() */
1223                 RTE_PTYPE_INNER_L3_IPV4,
1224                 RTE_PTYPE_INNER_L3_IPV6,
1225                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1226                 RTE_PTYPE_INNER_L4_MASK,
1227                 RTE_PTYPE_UNKNOWN
1228         };
1229
1230         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1231                 return ptypes;
1232         return NULL;
1233 }
1234
1235 static uint32_t
1236 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1237 {
1238         struct nfp_net_rxq *rxq;
1239         struct nfp_net_rx_desc *rxds;
1240         uint32_t idx;
1241         uint32_t count;
1242
1243         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1244
1245         idx = rxq->rd_p;
1246
1247         count = 0;
1248
1249         /*
1250          * Other PMDs are just checking the DD bit in intervals of 4
1251          * descriptors and counting all four if the first has the DD
1252          * bit on. Of course, this is not accurate but can be good for
1253          * performance. But ideally that should be done in descriptors
1254          * chunks belonging to the same cache line
1255          */
1256
1257         while (count < rxq->rx_count) {
1258                 rxds = &rxq->rxds[idx];
1259                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1260                         break;
1261
1262                 count++;
1263                 idx++;
1264
1265                 /* Wrapping? */
1266                 if ((idx) == rxq->rx_count)
1267                         idx = 0;
1268         }
1269
1270         return count;
1271 }
1272
1273 static int
1274 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1275 {
1276         struct rte_pci_device *pci_dev;
1277         struct nfp_net_hw *hw;
1278         int base = 0;
1279
1280         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1281         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1282
1283         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1284                 base = 1;
1285
1286         /* Make sure all updates are written before un-masking */
1287         rte_wmb();
1288         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1289                       NFP_NET_CFG_ICR_UNMASKED);
1290         return 0;
1291 }
1292
1293 static int
1294 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1295 {
1296         struct rte_pci_device *pci_dev;
1297         struct nfp_net_hw *hw;
1298         int base = 0;
1299
1300         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1302
1303         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1304                 base = 1;
1305
1306         /* Make sure all updates are written before un-masking */
1307         rte_wmb();
1308         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1309         return 0;
1310 }
1311
1312 static void
1313 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1314 {
1315         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1316         struct rte_eth_link link;
1317
1318         rte_eth_linkstatus_get(dev, &link);
1319         if (link.link_status)
1320                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1321                             dev->data->port_id, link.link_speed,
1322                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1323                             ? "full-duplex" : "half-duplex");
1324         else
1325                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1326                             dev->data->port_id);
1327
1328         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1329                 pci_dev->addr.domain, pci_dev->addr.bus,
1330                 pci_dev->addr.devid, pci_dev->addr.function);
1331 }
1332
1333 /* Interrupt configuration and handling */
1334
1335 /*
1336  * nfp_net_irq_unmask - Unmask an interrupt
1337  *
1338  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1339  * clear the ICR for the entry.
1340  */
1341 static void
1342 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1343 {
1344         struct nfp_net_hw *hw;
1345         struct rte_pci_device *pci_dev;
1346
1347         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1349
1350         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1351                 /* If MSI-X auto-masking is used, clear the entry */
1352                 rte_wmb();
1353                 rte_intr_enable(&pci_dev->intr_handle);
1354         } else {
1355                 /* Make sure all updates are written before un-masking */
1356                 rte_wmb();
1357                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1358                               NFP_NET_CFG_ICR_UNMASKED);
1359         }
1360 }
1361
1362 static void
1363 nfp_net_dev_interrupt_handler(void *param)
1364 {
1365         int64_t timeout;
1366         struct rte_eth_link link;
1367         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1368
1369         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1370
1371         rte_eth_linkstatus_get(dev, &link);
1372
1373         nfp_net_link_update(dev, 0);
1374
1375         /* likely to up */
1376         if (!link.link_status) {
1377                 /* handle it 1 sec later, wait it being stable */
1378                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1379                 /* likely to down */
1380         } else {
1381                 /* handle it 4 sec later, wait it being stable */
1382                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1383         }
1384
1385         if (rte_eal_alarm_set(timeout * 1000,
1386                               nfp_net_dev_interrupt_delayed_handler,
1387                               (void *)dev) < 0) {
1388                 PMD_INIT_LOG(ERR, "Error setting alarm");
1389                 /* Unmasking */
1390                 nfp_net_irq_unmask(dev);
1391         }
1392 }
1393
1394 /*
1395  * Interrupt handler which shall be registered for alarm callback for delayed
1396  * handling specific interrupt to wait for the stable nic state. As the NIC
1397  * interrupt state is not stable for nfp after link is just down, it needs
1398  * to wait 4 seconds to get the stable status.
1399  *
1400  * @param handle   Pointer to interrupt handle.
1401  * @param param    The address of parameter (struct rte_eth_dev *)
1402  *
1403  * @return  void
1404  */
1405 static void
1406 nfp_net_dev_interrupt_delayed_handler(void *param)
1407 {
1408         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1409
1410         nfp_net_link_update(dev, 0);
1411         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1412
1413         nfp_net_dev_link_status_print(dev);
1414
1415         /* Unmasking */
1416         nfp_net_irq_unmask(dev);
1417 }
1418
1419 static int
1420 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1421 {
1422         struct nfp_net_hw *hw;
1423
1424         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425
1426         /* check that mtu is within the allowed range */
1427         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1428                 return -EINVAL;
1429
1430         /* mtu setting is forbidden if port is started */
1431         if (dev->data->dev_started) {
1432                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1433                             dev->data->port_id);
1434                 return -EBUSY;
1435         }
1436
1437         /* switch to jumbo mode if needed */
1438         if ((uint32_t)mtu > ETHER_MAX_LEN)
1439                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1440         else
1441                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1442
1443         /* update max frame size */
1444         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1445
1446         /* writing to configuration space */
1447         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1448
1449         hw->mtu = mtu;
1450
1451         return 0;
1452 }
1453
1454 static int
1455 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1456                        uint16_t queue_idx, uint16_t nb_desc,
1457                        unsigned int socket_id,
1458                        const struct rte_eth_rxconf *rx_conf,
1459                        struct rte_mempool *mp)
1460 {
1461         const struct rte_memzone *tz;
1462         struct nfp_net_rxq *rxq;
1463         struct nfp_net_hw *hw;
1464
1465         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466
1467         PMD_INIT_FUNC_TRACE();
1468
1469         /* Validating number of descriptors */
1470         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1471             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1472             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1473                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1474                 return -EINVAL;
1475         }
1476
1477         /*
1478          * Free memory prior to re-allocation if needed. This is the case after
1479          * calling nfp_net_stop
1480          */
1481         if (dev->data->rx_queues[queue_idx]) {
1482                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1483                 dev->data->rx_queues[queue_idx] = NULL;
1484         }
1485
1486         /* Allocating rx queue data structure */
1487         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1488                                  RTE_CACHE_LINE_SIZE, socket_id);
1489         if (rxq == NULL)
1490                 return -ENOMEM;
1491
1492         /* Hw queues mapping based on firmware confifguration */
1493         rxq->qidx = queue_idx;
1494         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1495         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1496         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1497         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1498
1499         /*
1500          * Tracking mbuf size for detecting a potential mbuf overflow due to
1501          * RX offset
1502          */
1503         rxq->mem_pool = mp;
1504         rxq->mbuf_size = rxq->mem_pool->elt_size;
1505         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1506         hw->flbufsz = rxq->mbuf_size;
1507
1508         rxq->rx_count = nb_desc;
1509         rxq->port_id = dev->data->port_id;
1510         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1511         rxq->drop_en = rx_conf->rx_drop_en;
1512
1513         /*
1514          * Allocate RX ring hardware descriptors. A memzone large enough to
1515          * handle the maximum ring size is allocated in order to allow for
1516          * resizing in later calls to the queue setup function.
1517          */
1518         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1519                                    sizeof(struct nfp_net_rx_desc) *
1520                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1521                                    socket_id);
1522
1523         if (tz == NULL) {
1524                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1525                 nfp_net_rx_queue_release(rxq);
1526                 return -ENOMEM;
1527         }
1528
1529         /* Saving physical and virtual addresses for the RX ring */
1530         rxq->dma = (uint64_t)tz->iova;
1531         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1532
1533         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1534         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1535                                          sizeof(*rxq->rxbufs) * nb_desc,
1536                                          RTE_CACHE_LINE_SIZE, socket_id);
1537         if (rxq->rxbufs == NULL) {
1538                 nfp_net_rx_queue_release(rxq);
1539                 return -ENOMEM;
1540         }
1541
1542         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1543                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1544
1545         nfp_net_reset_rx_queue(rxq);
1546
1547         dev->data->rx_queues[queue_idx] = rxq;
1548         rxq->hw = hw;
1549
1550         /*
1551          * Telling the HW about the physical address of the RX ring and number
1552          * of descriptors in log2 format
1553          */
1554         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1555         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1556
1557         return 0;
1558 }
1559
1560 static int
1561 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1562 {
1563         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1564         uint64_t dma_addr;
1565         unsigned i;
1566
1567         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1568                    rxq->rx_count);
1569
1570         for (i = 0; i < rxq->rx_count; i++) {
1571                 struct nfp_net_rx_desc *rxd;
1572                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1573
1574                 if (mbuf == NULL) {
1575                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1576                                 (unsigned)rxq->qidx);
1577                         return -ENOMEM;
1578                 }
1579
1580                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1581
1582                 rxd = &rxq->rxds[i];
1583                 rxd->fld.dd = 0;
1584                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1585                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1586                 rxe[i].mbuf = mbuf;
1587                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1588         }
1589
1590         /* Make sure all writes are flushed before telling the hardware */
1591         rte_wmb();
1592
1593         /* Not advertising the whole ring as the firmware gets confused if so */
1594         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1595                    rxq->rx_count - 1);
1596
1597         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1598
1599         return 0;
1600 }
1601
1602 static int
1603 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1604                        uint16_t nb_desc, unsigned int socket_id,
1605                        const struct rte_eth_txconf *tx_conf)
1606 {
1607         const struct rte_memzone *tz;
1608         struct nfp_net_txq *txq;
1609         uint16_t tx_free_thresh;
1610         struct nfp_net_hw *hw;
1611
1612         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613
1614         PMD_INIT_FUNC_TRACE();
1615
1616         /* Validating number of descriptors */
1617         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1618             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1619             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1620                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1621                 return -EINVAL;
1622         }
1623
1624         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1625                                     tx_conf->tx_free_thresh :
1626                                     DEFAULT_TX_FREE_THRESH);
1627
1628         if (tx_free_thresh > (nb_desc)) {
1629                 PMD_DRV_LOG(ERR,
1630                         "tx_free_thresh must be less than the number of TX "
1631                         "descriptors. (tx_free_thresh=%u port=%d "
1632                         "queue=%d)", (unsigned int)tx_free_thresh,
1633                         dev->data->port_id, (int)queue_idx);
1634                 return -(EINVAL);
1635         }
1636
1637         /*
1638          * Free memory prior to re-allocation if needed. This is the case after
1639          * calling nfp_net_stop
1640          */
1641         if (dev->data->tx_queues[queue_idx]) {
1642                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1643                            queue_idx);
1644                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1645                 dev->data->tx_queues[queue_idx] = NULL;
1646         }
1647
1648         /* Allocating tx queue data structure */
1649         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1650                                  RTE_CACHE_LINE_SIZE, socket_id);
1651         if (txq == NULL) {
1652                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1653                 return -ENOMEM;
1654         }
1655
1656         /*
1657          * Allocate TX ring hardware descriptors. A memzone large enough to
1658          * handle the maximum ring size is allocated in order to allow for
1659          * resizing in later calls to the queue setup function.
1660          */
1661         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1662                                    sizeof(struct nfp_net_tx_desc) *
1663                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1664                                    socket_id);
1665         if (tz == NULL) {
1666                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1667                 nfp_net_tx_queue_release(txq);
1668                 return -ENOMEM;
1669         }
1670
1671         txq->tx_count = nb_desc;
1672         txq->tx_free_thresh = tx_free_thresh;
1673         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1674         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1675         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1676
1677         /* queue mapping based on firmware configuration */
1678         txq->qidx = queue_idx;
1679         txq->tx_qcidx = queue_idx * hw->stride_tx;
1680         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1681
1682         txq->port_id = dev->data->port_id;
1683
1684         /* Saving physical and virtual addresses for the TX ring */
1685         txq->dma = (uint64_t)tz->iova;
1686         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1687
1688         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1689         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1690                                          sizeof(*txq->txbufs) * nb_desc,
1691                                          RTE_CACHE_LINE_SIZE, socket_id);
1692         if (txq->txbufs == NULL) {
1693                 nfp_net_tx_queue_release(txq);
1694                 return -ENOMEM;
1695         }
1696         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1697                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1698
1699         nfp_net_reset_tx_queue(txq);
1700
1701         dev->data->tx_queues[queue_idx] = txq;
1702         txq->hw = hw;
1703
1704         /*
1705          * Telling the HW about the physical address of the TX ring and number
1706          * of descriptors in log2 format
1707          */
1708         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1709         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1710
1711         return 0;
1712 }
1713
1714 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1715 static inline void
1716 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1717                struct rte_mbuf *mb)
1718 {
1719         uint64_t ol_flags;
1720         struct nfp_net_hw *hw = txq->hw;
1721
1722         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1723                 goto clean_txd;
1724
1725         ol_flags = mb->ol_flags;
1726
1727         if (!(ol_flags & PKT_TX_TCP_SEG))
1728                 goto clean_txd;
1729
1730         txd->l3_offset = mb->l2_len;
1731         txd->l4_offset = mb->l2_len + mb->l3_len;
1732         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1733         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1734         txd->flags = PCIE_DESC_TX_LSO;
1735         return;
1736
1737 clean_txd:
1738         txd->flags = 0;
1739         txd->l3_offset = 0;
1740         txd->l4_offset = 0;
1741         txd->lso_hdrlen = 0;
1742         txd->mss = 0;
1743 }
1744
1745 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1746 static inline void
1747 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1748                  struct rte_mbuf *mb)
1749 {
1750         uint64_t ol_flags;
1751         struct nfp_net_hw *hw = txq->hw;
1752
1753         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1754                 return;
1755
1756         ol_flags = mb->ol_flags;
1757
1758         /* IPv6 does not need checksum */
1759         if (ol_flags & PKT_TX_IP_CKSUM)
1760                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1761
1762         switch (ol_flags & PKT_TX_L4_MASK) {
1763         case PKT_TX_UDP_CKSUM:
1764                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1765                 break;
1766         case PKT_TX_TCP_CKSUM:
1767                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1768                 break;
1769         }
1770
1771         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1772                 txd->flags |= PCIE_DESC_TX_CSUM;
1773 }
1774
1775 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1776 static inline void
1777 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1778                  struct rte_mbuf *mb)
1779 {
1780         struct nfp_net_hw *hw = rxq->hw;
1781
1782         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1783                 return;
1784
1785         /* If IPv4 and IP checksum error, fail */
1786         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1787             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1788                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1789
1790         /* If neither UDP nor TCP return */
1791         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1792             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1793                 return;
1794
1795         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1796             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1797                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1798
1799         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1800             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1801                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1802 }
1803
1804 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1805 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1806
1807 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1808
1809 /*
1810  * nfp_net_set_hash - Set mbuf hash data
1811  *
1812  * The RSS hash and hash-type are pre-pended to the packet data.
1813  * Extract and decode it and set the mbuf fields.
1814  */
1815 static inline void
1816 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1817                  struct rte_mbuf *mbuf)
1818 {
1819         struct nfp_net_hw *hw = rxq->hw;
1820         uint8_t *meta_offset;
1821         uint32_t meta_info;
1822         uint32_t hash = 0;
1823         uint32_t hash_type = 0;
1824
1825         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1826                 return;
1827
1828         /* this is true for new firmwares */
1829         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1830             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1831              NFP_DESC_META_LEN(rxd))) {
1832                 /*
1833                  * new metadata api:
1834                  * <----  32 bit  ----->
1835                  * m    field type word
1836                  * e     data field #2
1837                  * t     data field #1
1838                  * a     data field #0
1839                  * ====================
1840                  *    packet data
1841                  *
1842                  * Field type word contains up to 8 4bit field types
1843                  * A 4bit field type refers to a data field word
1844                  * A data field word can have several 4bit field types
1845                  */
1846                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1847                 meta_offset -= NFP_DESC_META_LEN(rxd);
1848                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1849                 meta_offset += 4;
1850                 /* NFP PMD just supports metadata for hashing */
1851                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1852                 case NFP_NET_META_HASH:
1853                         /* next field type is about the hash type */
1854                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1855                         /* hash value is in the data field */
1856                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1857                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1858                         break;
1859                 default:
1860                         /* Unsupported metadata can be a performance issue */
1861                         return;
1862                 }
1863         } else {
1864                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1865                         return;
1866
1867                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1868                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1869         }
1870
1871         mbuf->hash.rss = hash;
1872         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1873
1874         switch (hash_type) {
1875         case NFP_NET_RSS_IPV4:
1876                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1877                 break;
1878         case NFP_NET_RSS_IPV6:
1879                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1880                 break;
1881         case NFP_NET_RSS_IPV6_EX:
1882                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1883                 break;
1884         default:
1885                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1886         }
1887 }
1888
1889 static inline void
1890 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1891 {
1892         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1893 }
1894
1895 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1896
1897 /*
1898  * RX path design:
1899  *
1900  * There are some decissions to take:
1901  * 1) How to check DD RX descriptors bit
1902  * 2) How and when to allocate new mbufs
1903  *
1904  * Current implementation checks just one single DD bit each loop. As each
1905  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1906  * a single cache line instead. Tests with this change have not shown any
1907  * performance improvement but it requires further investigation. For example,
1908  * depending on which descriptor is next, the number of descriptors could be
1909  * less than 8 for just checking those in the same cache line. This implies
1910  * extra work which could be counterproductive by itself. Indeed, last firmware
1911  * changes are just doing this: writing several descriptors with the DD bit
1912  * for saving PCIe bandwidth and DMA operations from the NFP.
1913  *
1914  * Mbuf allocation is done when a new packet is received. Then the descriptor
1915  * is automatically linked with the new mbuf and the old one is given to the
1916  * user. The main drawback with this design is mbuf allocation is heavier than
1917  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1918  * cache point of view it does not seem allocating the mbuf early on as we are
1919  * doing now have any benefit at all. Again, tests with this change have not
1920  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1921  * so looking at the implications of this type of allocation should be studied
1922  * deeply
1923  */
1924
1925 static uint16_t
1926 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1927 {
1928         struct nfp_net_rxq *rxq;
1929         struct nfp_net_rx_desc *rxds;
1930         struct nfp_net_rx_buff *rxb;
1931         struct nfp_net_hw *hw;
1932         struct rte_mbuf *mb;
1933         struct rte_mbuf *new_mb;
1934         uint16_t nb_hold;
1935         uint64_t dma_addr;
1936         int avail;
1937
1938         rxq = rx_queue;
1939         if (unlikely(rxq == NULL)) {
1940                 /*
1941                  * DPDK just checks the queue is lower than max queues
1942                  * enabled. But the queue needs to be configured
1943                  */
1944                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1945                 return -EINVAL;
1946         }
1947
1948         hw = rxq->hw;
1949         avail = 0;
1950         nb_hold = 0;
1951
1952         while (avail < nb_pkts) {
1953                 rxb = &rxq->rxbufs[rxq->rd_p];
1954                 if (unlikely(rxb == NULL)) {
1955                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1956                         break;
1957                 }
1958
1959                 rxds = &rxq->rxds[rxq->rd_p];
1960                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1961                         break;
1962
1963                 /*
1964                  * Memory barrier to ensure that we won't do other
1965                  * reads before the DD bit.
1966                  */
1967                 rte_rmb();
1968
1969                 /*
1970                  * We got a packet. Let's alloc a new mbuff for refilling the
1971                  * free descriptor ring as soon as possible
1972                  */
1973                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1974                 if (unlikely(new_mb == NULL)) {
1975                         RTE_LOG_DP(DEBUG, PMD,
1976                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1977                                 rxq->port_id, (unsigned int)rxq->qidx);
1978                         nfp_net_mbuf_alloc_failed(rxq);
1979                         break;
1980                 }
1981
1982                 nb_hold++;
1983
1984                 /*
1985                  * Grab the mbuff and refill the descriptor with the
1986                  * previously allocated mbuff
1987                  */
1988                 mb = rxb->mbuf;
1989                 rxb->mbuf = new_mb;
1990
1991                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
1992                            rxds->rxd.data_len, rxq->mbuf_size);
1993
1994                 /* Size of this segment */
1995                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1996                 /* Size of the whole packet. We just support 1 segment */
1997                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1998
1999                 if (unlikely((mb->data_len + hw->rx_offset) >
2000                              rxq->mbuf_size)) {
2001                         /*
2002                          * This should not happen and the user has the
2003                          * responsibility of avoiding it. But we have
2004                          * to give some info about the error
2005                          */
2006                         RTE_LOG_DP(ERR, PMD,
2007                                 "mbuf overflow likely due to the RX offset.\n"
2008                                 "\t\tYour mbuf size should have extra space for"
2009                                 " RX offset=%u bytes.\n"
2010                                 "\t\tCurrently you just have %u bytes available"
2011                                 " but the received packet is %u bytes long",
2012                                 hw->rx_offset,
2013                                 rxq->mbuf_size - hw->rx_offset,
2014                                 mb->data_len);
2015                         return -EINVAL;
2016                 }
2017
2018                 /* Filling the received mbuff with packet info */
2019                 if (hw->rx_offset)
2020                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2021                 else
2022                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2023                                        NFP_DESC_META_LEN(rxds);
2024
2025                 /* No scatter mode supported */
2026                 mb->nb_segs = 1;
2027                 mb->next = NULL;
2028
2029                 mb->port = rxq->port_id;
2030
2031                 /* Checking the RSS flag */
2032                 nfp_net_set_hash(rxq, rxds, mb);
2033
2034                 /* Checking the checksum flag */
2035                 nfp_net_rx_cksum(rxq, rxds, mb);
2036
2037                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2038                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2039                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2040                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2041                 }
2042
2043                 /* Adding the mbuff to the mbuff array passed by the app */
2044                 rx_pkts[avail++] = mb;
2045
2046                 /* Now resetting and updating the descriptor */
2047                 rxds->vals[0] = 0;
2048                 rxds->vals[1] = 0;
2049                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2050                 rxds->fld.dd = 0;
2051                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2052                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2053
2054                 rxq->rd_p++;
2055                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2056                         rxq->rd_p = 0;
2057         }
2058
2059         if (nb_hold == 0)
2060                 return nb_hold;
2061
2062         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2063                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2064
2065         nb_hold += rxq->nb_rx_hold;
2066
2067         /*
2068          * FL descriptors needs to be written before incrementing the
2069          * FL queue WR pointer
2070          */
2071         rte_wmb();
2072         if (nb_hold > rxq->rx_free_thresh) {
2073                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2074                            rxq->port_id, (unsigned int)rxq->qidx,
2075                            (unsigned)nb_hold, (unsigned)avail);
2076                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2077                 nb_hold = 0;
2078         }
2079         rxq->nb_rx_hold = nb_hold;
2080
2081         return avail;
2082 }
2083
2084 /*
2085  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2086  * status
2087  * @txq: TX queue to work with
2088  * Returns number of descriptors freed
2089  */
2090 int
2091 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2092 {
2093         uint32_t qcp_rd_p;
2094         int todo;
2095
2096         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2097                    " status", txq->qidx);
2098
2099         /* Work out how many packets have been sent */
2100         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2101
2102         if (qcp_rd_p == txq->rd_p) {
2103                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2104                            "packets (%u, %u)", txq->qidx,
2105                            qcp_rd_p, txq->rd_p);
2106                 return 0;
2107         }
2108
2109         if (qcp_rd_p > txq->rd_p)
2110                 todo = qcp_rd_p - txq->rd_p;
2111         else
2112                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2113
2114         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2115                    qcp_rd_p, txq->rd_p, txq->rd_p);
2116
2117         if (todo == 0)
2118                 return todo;
2119
2120         txq->rd_p += todo;
2121         if (unlikely(txq->rd_p >= txq->tx_count))
2122                 txq->rd_p -= txq->tx_count;
2123
2124         return todo;
2125 }
2126
2127 /* Leaving always free descriptors for avoiding wrapping confusion */
2128 static inline
2129 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2130 {
2131         if (txq->wr_p >= txq->rd_p)
2132                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2133         else
2134                 return txq->rd_p - txq->wr_p - 8;
2135 }
2136
2137 /*
2138  * nfp_net_txq_full - Check if the TX queue free descriptors
2139  * is below tx_free_threshold
2140  *
2141  * @txq: TX queue to check
2142  *
2143  * This function uses the host copy* of read/write pointers
2144  */
2145 static inline
2146 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2147 {
2148         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2149 }
2150
2151 static uint16_t
2152 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2153 {
2154         struct nfp_net_txq *txq;
2155         struct nfp_net_hw *hw;
2156         struct nfp_net_tx_desc *txds, txd;
2157         struct rte_mbuf *pkt;
2158         uint64_t dma_addr;
2159         int pkt_size, dma_size;
2160         uint16_t free_descs, issued_descs;
2161         struct rte_mbuf **lmbuf;
2162         int i;
2163
2164         txq = tx_queue;
2165         hw = txq->hw;
2166         txds = &txq->txds[txq->wr_p];
2167
2168         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2169                    txq->qidx, txq->wr_p, nb_pkts);
2170
2171         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2172                 nfp_net_tx_free_bufs(txq);
2173
2174         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2175         if (unlikely(free_descs == 0))
2176                 return 0;
2177
2178         pkt = *tx_pkts;
2179
2180         i = 0;
2181         issued_descs = 0;
2182         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2183                    txq->qidx, nb_pkts);
2184         /* Sending packets */
2185         while ((i < nb_pkts) && free_descs) {
2186                 /* Grabbing the mbuf linked to the current descriptor */
2187                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2188                 /* Warming the cache for releasing the mbuf later on */
2189                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2190
2191                 pkt = *(tx_pkts + i);
2192
2193                 if (unlikely((pkt->nb_segs > 1) &&
2194                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2195                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2196                         rte_panic("Multisegment packet unsupported\n");
2197                 }
2198
2199                 /* Checking if we have enough descriptors */
2200                 if (unlikely(pkt->nb_segs > free_descs))
2201                         goto xmit_end;
2202
2203                 /*
2204                  * Checksum and VLAN flags just in the first descriptor for a
2205                  * multisegment packet, but TSO info needs to be in all of them.
2206                  */
2207                 txd.data_len = pkt->pkt_len;
2208                 nfp_net_tx_tso(txq, &txd, pkt);
2209                 nfp_net_tx_cksum(txq, &txd, pkt);
2210
2211                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2212                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2213                         txd.flags |= PCIE_DESC_TX_VLAN;
2214                         txd.vlan = pkt->vlan_tci;
2215                 }
2216
2217                 /*
2218                  * mbuf data_len is the data in one segment and pkt_len data
2219                  * in the whole packet. When the packet is just one segment,
2220                  * then data_len = pkt_len
2221                  */
2222                 pkt_size = pkt->pkt_len;
2223
2224                 while (pkt) {
2225                         /* Copying TSO, VLAN and cksum info */
2226                         *txds = txd;
2227
2228                         /* Releasing mbuf used by this descriptor previously*/
2229                         if (*lmbuf)
2230                                 rte_pktmbuf_free_seg(*lmbuf);
2231
2232                         /*
2233                          * Linking mbuf with descriptor for being released
2234                          * next time descriptor is used
2235                          */
2236                         *lmbuf = pkt;
2237
2238                         dma_size = pkt->data_len;
2239                         dma_addr = rte_mbuf_data_iova(pkt);
2240                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2241                                    "%" PRIx64 "", dma_addr);
2242
2243                         /* Filling descriptors fields */
2244                         txds->dma_len = dma_size;
2245                         txds->data_len = txd.data_len;
2246                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2247                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2248                         ASSERT(free_descs > 0);
2249                         free_descs--;
2250
2251                         txq->wr_p++;
2252                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2253                                 txq->wr_p = 0;
2254
2255                         pkt_size -= dma_size;
2256                         if (!pkt_size)
2257                                 /* End of packet */
2258                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2259                         else
2260                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2261
2262                         pkt = pkt->next;
2263                         /* Referencing next free TX descriptor */
2264                         txds = &txq->txds[txq->wr_p];
2265                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2266                         issued_descs++;
2267                 }
2268                 i++;
2269         }
2270
2271 xmit_end:
2272         /* Increment write pointers. Force memory write before we let HW know */
2273         rte_wmb();
2274         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2275
2276         return i;
2277 }
2278
2279 static int
2280 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2281 {
2282         uint32_t new_ctrl, update;
2283         struct nfp_net_hw *hw;
2284         int ret;
2285
2286         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         new_ctrl = 0;
2288
2289         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2290             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2291                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2292                         " ETH_VLAN_EXTEND_OFFLOAD");
2293
2294         /* Enable vlan strip if it is not configured yet */
2295         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2296             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2297                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2298
2299         /* Disable vlan strip just if it is configured */
2300         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2301             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2302                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2303
2304         if (new_ctrl == 0)
2305                 return 0;
2306
2307         update = NFP_NET_CFG_UPDATE_GEN;
2308
2309         ret = nfp_net_reconfig(hw, new_ctrl, update);
2310         if (!ret)
2311                 hw->ctrl = new_ctrl;
2312
2313         return ret;
2314 }
2315
2316 static int
2317 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2318                     struct rte_eth_rss_reta_entry64 *reta_conf,
2319                     uint16_t reta_size)
2320 {
2321         uint32_t reta, mask;
2322         int i, j;
2323         int idx, shift;
2324         struct nfp_net_hw *hw =
2325                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326
2327         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2328                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2329                         "(%d) doesn't match the number hardware can supported "
2330                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2331                 return -EINVAL;
2332         }
2333
2334         /*
2335          * Update Redirection Table. There are 128 8bit-entries which can be
2336          * manage as 32 32bit-entries
2337          */
2338         for (i = 0; i < reta_size; i += 4) {
2339                 /* Handling 4 RSS entries per loop */
2340                 idx = i / RTE_RETA_GROUP_SIZE;
2341                 shift = i % RTE_RETA_GROUP_SIZE;
2342                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2343
2344                 if (!mask)
2345                         continue;
2346
2347                 reta = 0;
2348                 /* If all 4 entries were set, don't need read RETA register */
2349                 if (mask != 0xF)
2350                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2351
2352                 for (j = 0; j < 4; j++) {
2353                         if (!(mask & (0x1 << j)))
2354                                 continue;
2355                         if (mask != 0xF)
2356                                 /* Clearing the entry bits */
2357                                 reta &= ~(0xFF << (8 * j));
2358                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2359                 }
2360                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2361                               reta);
2362         }
2363         return 0;
2364 }
2365
2366 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2367 static int
2368 nfp_net_reta_update(struct rte_eth_dev *dev,
2369                     struct rte_eth_rss_reta_entry64 *reta_conf,
2370                     uint16_t reta_size)
2371 {
2372         struct nfp_net_hw *hw =
2373                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         uint32_t update;
2375         int ret;
2376
2377         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2378                 return -EINVAL;
2379
2380         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2381         if (ret != 0)
2382                 return ret;
2383
2384         update = NFP_NET_CFG_UPDATE_RSS;
2385
2386         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2387                 return -EIO;
2388
2389         return 0;
2390 }
2391
2392  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2393 static int
2394 nfp_net_reta_query(struct rte_eth_dev *dev,
2395                    struct rte_eth_rss_reta_entry64 *reta_conf,
2396                    uint16_t reta_size)
2397 {
2398         uint8_t i, j, mask;
2399         int idx, shift;
2400         uint32_t reta;
2401         struct nfp_net_hw *hw;
2402
2403         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404
2405         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2406                 return -EINVAL;
2407
2408         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2409                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2410                         "(%d) doesn't match the number hardware can supported "
2411                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2412                 return -EINVAL;
2413         }
2414
2415         /*
2416          * Reading Redirection Table. There are 128 8bit-entries which can be
2417          * manage as 32 32bit-entries
2418          */
2419         for (i = 0; i < reta_size; i += 4) {
2420                 /* Handling 4 RSS entries per loop */
2421                 idx = i / RTE_RETA_GROUP_SIZE;
2422                 shift = i % RTE_RETA_GROUP_SIZE;
2423                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2424
2425                 if (!mask)
2426                         continue;
2427
2428                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2429                                     shift);
2430                 for (j = 0; j < 4; j++) {
2431                         if (!(mask & (0x1 << j)))
2432                                 continue;
2433                         reta_conf->reta[shift + j] =
2434                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2435                 }
2436         }
2437         return 0;
2438 }
2439
2440 static int
2441 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2442                         struct rte_eth_rss_conf *rss_conf)
2443 {
2444         struct nfp_net_hw *hw;
2445         uint64_t rss_hf;
2446         uint32_t cfg_rss_ctrl = 0;
2447         uint8_t key;
2448         int i;
2449
2450         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451
2452         /* Writing the key byte a byte */
2453         for (i = 0; i < rss_conf->rss_key_len; i++) {
2454                 memcpy(&key, &rss_conf->rss_key[i], 1);
2455                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2456         }
2457
2458         rss_hf = rss_conf->rss_hf;
2459
2460         if (rss_hf & ETH_RSS_IPV4)
2461                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2462                                 NFP_NET_CFG_RSS_IPV4_TCP |
2463                                 NFP_NET_CFG_RSS_IPV4_UDP;
2464
2465         if (rss_hf & ETH_RSS_IPV6)
2466                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2467                                 NFP_NET_CFG_RSS_IPV6_TCP |
2468                                 NFP_NET_CFG_RSS_IPV6_UDP;
2469
2470         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2471         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2472
2473         /* configuring where to apply the RSS hash */
2474         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2475
2476         /* Writing the key size */
2477         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2478
2479         return 0;
2480 }
2481
2482 static int
2483 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2484                         struct rte_eth_rss_conf *rss_conf)
2485 {
2486         uint32_t update;
2487         uint64_t rss_hf;
2488         struct nfp_net_hw *hw;
2489
2490         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491
2492         rss_hf = rss_conf->rss_hf;
2493
2494         /* Checking if RSS is enabled */
2495         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2496                 if (rss_hf != 0) { /* Enable RSS? */
2497                         PMD_DRV_LOG(ERR, "RSS unsupported");
2498                         return -EINVAL;
2499                 }
2500                 return 0; /* Nothing to do */
2501         }
2502
2503         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2504                 PMD_DRV_LOG(ERR, "hash key too long");
2505                 return -EINVAL;
2506         }
2507
2508         nfp_net_rss_hash_write(dev, rss_conf);
2509
2510         update = NFP_NET_CFG_UPDATE_RSS;
2511
2512         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2513                 return -EIO;
2514
2515         return 0;
2516 }
2517
2518 static int
2519 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2520                           struct rte_eth_rss_conf *rss_conf)
2521 {
2522         uint64_t rss_hf;
2523         uint32_t cfg_rss_ctrl;
2524         uint8_t key;
2525         int i;
2526         struct nfp_net_hw *hw;
2527
2528         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529
2530         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2531                 return -EINVAL;
2532
2533         rss_hf = rss_conf->rss_hf;
2534         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2535
2536         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2537                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2538
2539         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2540                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2541
2542         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2543                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2544
2545         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2546                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2547
2548         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2549                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2550
2551         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2552                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2553
2554         /* Reading the key size */
2555         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2556
2557         /* Reading the key byte a byte */
2558         for (i = 0; i < rss_conf->rss_key_len; i++) {
2559                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2560                 memcpy(&rss_conf->rss_key[i], &key, 1);
2561         }
2562
2563         return 0;
2564 }
2565
2566 static int
2567 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2568 {
2569         struct rte_eth_conf *dev_conf;
2570         struct rte_eth_rss_conf rss_conf;
2571         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2572         uint16_t rx_queues = dev->data->nb_rx_queues;
2573         uint16_t queue;
2574         int i, j, ret;
2575
2576         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2577                 rx_queues);
2578
2579         nfp_reta_conf[0].mask = ~0x0;
2580         nfp_reta_conf[1].mask = ~0x0;
2581
2582         queue = 0;
2583         for (i = 0; i < 0x40; i += 8) {
2584                 for (j = i; j < (i + 8); j++) {
2585                         nfp_reta_conf[0].reta[j] = queue;
2586                         nfp_reta_conf[1].reta[j] = queue++;
2587                         queue %= rx_queues;
2588                 }
2589         }
2590         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2591         if (ret != 0)
2592                 return ret;
2593
2594         dev_conf = &dev->data->dev_conf;
2595         if (!dev_conf) {
2596                 PMD_DRV_LOG(INFO, "wrong rss conf");
2597                 return -EINVAL;
2598         }
2599         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2600
2601         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2602
2603         return ret;
2604 }
2605
2606
2607 /* Initialise and register driver with DPDK Application */
2608 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2609         .dev_configure          = nfp_net_configure,
2610         .dev_start              = nfp_net_start,
2611         .dev_stop               = nfp_net_stop,
2612         .dev_close              = nfp_net_close,
2613         .promiscuous_enable     = nfp_net_promisc_enable,
2614         .promiscuous_disable    = nfp_net_promisc_disable,
2615         .link_update            = nfp_net_link_update,
2616         .stats_get              = nfp_net_stats_get,
2617         .stats_reset            = nfp_net_stats_reset,
2618         .dev_infos_get          = nfp_net_infos_get,
2619         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2620         .mtu_set                = nfp_net_dev_mtu_set,
2621         .mac_addr_set           = nfp_set_mac_addr,
2622         .vlan_offload_set       = nfp_net_vlan_offload_set,
2623         .reta_update            = nfp_net_reta_update,
2624         .reta_query             = nfp_net_reta_query,
2625         .rss_hash_update        = nfp_net_rss_hash_update,
2626         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2627         .rx_queue_setup         = nfp_net_rx_queue_setup,
2628         .rx_queue_release       = nfp_net_rx_queue_release,
2629         .rx_queue_count         = nfp_net_rx_queue_count,
2630         .tx_queue_setup         = nfp_net_tx_queue_setup,
2631         .tx_queue_release       = nfp_net_tx_queue_release,
2632         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2633         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2634 };
2635
2636 /*
2637  * All eth_dev created got its private data, but before nfp_net_init, that
2638  * private data is referencing private data for all the PF ports. This is due
2639  * to how the vNIC bars are mapped based on first port, so all ports need info
2640  * about port 0 private data. Inside nfp_net_init the private data pointer is
2641  * changed to the right address for each port once the bars have been mapped.
2642  *
2643  * This functions helps to find out which port and therefore which offset
2644  * inside the private data array to use.
2645  */
2646 static int
2647 get_pf_port_number(char *name)
2648 {
2649         char *pf_str = name;
2650         int size = 0;
2651
2652         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2653                 pf_str++;
2654
2655         if (size == 30)
2656                 /*
2657                  * This should not happen at all and it would mean major
2658                  * implementation fault.
2659                  */
2660                 rte_panic("nfp_net: problem with pf device name\n");
2661
2662         /* Expecting _portX with X within [0,7] */
2663         pf_str += 5;
2664
2665         return (int)strtol(pf_str, NULL, 10);
2666 }
2667
2668 static int
2669 nfp_net_init(struct rte_eth_dev *eth_dev)
2670 {
2671         struct rte_pci_device *pci_dev;
2672         struct nfp_net_hw *hw, *hwport0;
2673
2674         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2675         uint32_t start_q;
2676         int stride = 4;
2677         int port = 0;
2678         int err;
2679
2680         PMD_INIT_FUNC_TRACE();
2681
2682         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2683
2684         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2685             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2686                 port = get_pf_port_number(eth_dev->data->name);
2687                 if (port < 0 || port > 7) {
2688                         PMD_DRV_LOG(ERR, "Port value is wrong");
2689                         return -ENODEV;
2690                 }
2691
2692                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2693
2694                 /* This points to port 0 private data */
2695                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2696
2697                 /* This points to the specific port private data */
2698                 hw = &hwport0[port];
2699         } else {
2700                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2701                 hwport0 = 0;
2702         }
2703
2704         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2705         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2706         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2707
2708         /* For secondary processes, the primary has done all the work */
2709         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2710                 return 0;
2711
2712         rte_eth_copy_pci_info(eth_dev, pci_dev);
2713
2714         hw->device_id = pci_dev->id.device_id;
2715         hw->vendor_id = pci_dev->id.vendor_id;
2716         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2717         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2718
2719         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2720                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2721                      pci_dev->addr.domain, pci_dev->addr.bus,
2722                      pci_dev->addr.devid, pci_dev->addr.function);
2723
2724         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2725         if (hw->ctrl_bar == NULL) {
2726                 PMD_DRV_LOG(ERR,
2727                         "hw->ctrl_bar is NULL. BAR0 not configured");
2728                 return -ENODEV;
2729         }
2730
2731         if (hw->is_pf && port == 0) {
2732                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2733                                              hw->total_ports * 32768,
2734                                              &hw->ctrl_area);
2735                 if (!hw->ctrl_bar) {
2736                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2737                         return -EIO;
2738                 }
2739
2740                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2741         }
2742
2743         if (port > 0) {
2744                 if (!hwport0->ctrl_bar)
2745                         return -ENODEV;
2746
2747                 /* address based on port0 offset */
2748                 hw->ctrl_bar = hwport0->ctrl_bar +
2749                                (port * NFP_PF_CSR_SLICE_SIZE);
2750         }
2751
2752         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2753
2754         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2755         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2756
2757         /* Work out where in the BAR the queues start. */
2758         switch (pci_dev->id.device_id) {
2759         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2760         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2761         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2762                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2763                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2764                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2765                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2766                 break;
2767         default:
2768                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2769                 err = -ENODEV;
2770                 goto dev_err_ctrl_map;
2771         }
2772
2773         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2774         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2775
2776         if (hw->is_pf && port == 0) {
2777                 /* configure access to tx/rx vNIC BARs */
2778                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2779                                                       NFP_PCIE_QUEUE(0),
2780                                                       NFP_QCP_QUEUE_AREA_SZ,
2781                                                       &hw->hwqueues_area);
2782
2783                 if (!hwport0->hw_queues) {
2784                         printf("nfp_rtsym_map fails for net.qc");
2785                         err = -EIO;
2786                         goto dev_err_ctrl_map;
2787                 }
2788
2789                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2790                                     hwport0->hw_queues);
2791         }
2792
2793         if (hw->is_pf) {
2794                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2795                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2796                 eth_dev->data->dev_private = hw;
2797         } else {
2798                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2799                              tx_bar_off;
2800                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2801                              rx_bar_off;
2802         }
2803
2804         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2805                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2806
2807         nfp_net_cfg_queue_setup(hw);
2808
2809         /* Get some of the read-only fields from the config BAR */
2810         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2811         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2812         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2813         hw->mtu = ETHER_MTU;
2814
2815         /* VLAN insertion is incompatible with LSOv2 */
2816         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2817                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2818
2819         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2820                 hw->rx_offset = NFP_NET_RX_OFFSET;
2821         else
2822                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2823
2824         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2825                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2826                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2827
2828         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2829                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2830                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2831                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2832                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2833                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2834                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2835                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2836                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2837                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2838                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2839                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2840                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2841                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2842                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2843
2844         hw->ctrl = 0;
2845
2846         hw->stride_rx = stride;
2847         hw->stride_tx = stride;
2848
2849         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2850                      hw->max_rx_queues, hw->max_tx_queues);
2851
2852         /* Initializing spinlock for reconfigs */
2853         rte_spinlock_init(&hw->reconfig_lock);
2854
2855         /* Allocating memory for mac addr */
2856         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2857         if (eth_dev->data->mac_addrs == NULL) {
2858                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2859                 err = -ENOMEM;
2860                 goto dev_err_queues_map;
2861         }
2862
2863         if (hw->is_pf) {
2864                 nfp_net_pf_read_mac(hwport0, port);
2865                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2866         } else {
2867                 nfp_net_vf_read_mac(hw);
2868         }
2869
2870         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2871                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2872                                    port);
2873                 /* Using random mac addresses for VFs */
2874                 eth_random_addr(&hw->mac_addr[0]);
2875                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2876         }
2877
2878         /* Copying mac address to DPDK eth_dev struct */
2879         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2880                         &eth_dev->data->mac_addrs[0]);
2881
2882         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2883                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2884                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2885                      pci_dev->id.device_id,
2886                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2887                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2888
2889         /* Registering LSC interrupt handler */
2890         rte_intr_callback_register(&pci_dev->intr_handle,
2891                                    nfp_net_dev_interrupt_handler,
2892                                    (void *)eth_dev);
2893
2894         /* Telling the firmware about the LSC interrupt entry */
2895         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2896
2897         /* Recording current stats counters values */
2898         nfp_net_stats_reset(eth_dev);
2899
2900         return 0;
2901
2902 dev_err_queues_map:
2903                 nfp_cpp_area_free(hw->hwqueues_area);
2904 dev_err_ctrl_map:
2905                 nfp_cpp_area_free(hw->ctrl_area);
2906
2907         return err;
2908 }
2909
2910 static int
2911 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2912                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2913                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2914 {
2915         struct rte_eth_dev *eth_dev;
2916         struct nfp_net_hw *hw;
2917         char *port_name;
2918         int ret;
2919
2920         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2921         if (!port_name)
2922                 return -ENOMEM;
2923
2924         if (ports > 1)
2925                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2926         else
2927                 sprintf(port_name, "%s", dev->device.name);
2928
2929         eth_dev = rte_eth_dev_allocate(port_name);
2930         if (!eth_dev)
2931                 return -ENOMEM;
2932
2933         if (port == 0) {
2934                 *priv = rte_zmalloc(port_name,
2935                                     sizeof(struct nfp_net_adapter) * ports,
2936                                     RTE_CACHE_LINE_SIZE);
2937                 if (!*priv) {
2938                         rte_eth_dev_release_port(eth_dev);
2939                         return -ENOMEM;
2940                 }
2941         }
2942
2943         eth_dev->data->dev_private = *priv;
2944
2945         /*
2946          * dev_private pointing to port0 dev_private because we need
2947          * to configure vNIC bars based on port0 at nfp_net_init.
2948          * Then dev_private is adjusted per port.
2949          */
2950         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2951         hw->cpp = cpp;
2952         hw->hwinfo = hwinfo;
2953         hw->sym_tbl = sym_tbl;
2954         hw->pf_port_idx = phys_port;
2955         hw->is_pf = 1;
2956         if (ports > 1)
2957                 hw->pf_multiport_enabled = 1;
2958
2959         hw->total_ports = ports;
2960
2961         eth_dev->device = &dev->device;
2962         rte_eth_copy_pci_info(eth_dev, dev);
2963
2964         ret = nfp_net_init(eth_dev);
2965
2966         if (ret)
2967                 rte_eth_dev_release_port(eth_dev);
2968         else
2969                 rte_eth_dev_probing_finish(eth_dev);
2970
2971         rte_free(port_name);
2972
2973         return ret;
2974 }
2975
2976 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
2977
2978 static int
2979 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
2980 {
2981         struct nfp_cpp *cpp = nsp->cpp;
2982         int fw_f;
2983         char *fw_buf;
2984         char fw_name[125];
2985         char serial[40];
2986         struct stat file_stat;
2987         off_t fsize, bytes;
2988
2989         /* Looking for firmware file in order of priority */
2990
2991         /* First try to find a firmware image specific for this device */
2992         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
2993                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
2994                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
2995                 cpp->interface & 0xff);
2996
2997         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
2998
2999         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3000         fw_f = open(fw_name, O_RDONLY);
3001         if (fw_f > 0)
3002                 goto read_fw;
3003
3004         /* Then try the PCI name */
3005         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3006
3007         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3008         fw_f = open(fw_name, O_RDONLY);
3009         if (fw_f > 0)
3010                 goto read_fw;
3011
3012         /* Finally try the card type and media */
3013         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3014         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3015         fw_f = open(fw_name, O_RDONLY);
3016         if (fw_f < 0) {
3017                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3018                 return -ENOENT;
3019         }
3020
3021 read_fw:
3022         if (fstat(fw_f, &file_stat) < 0) {
3023                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3024                 close(fw_f);
3025                 return -ENOENT;
3026         }
3027
3028         fsize = file_stat.st_size;
3029         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3030                             fw_name, (uint64_t)fsize);
3031
3032         fw_buf = malloc((size_t)fsize);
3033         if (!fw_buf) {
3034                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3035                 close(fw_f);
3036                 return -ENOMEM;
3037         }
3038         memset(fw_buf, 0, fsize);
3039
3040         bytes = read(fw_f, fw_buf, fsize);
3041         if (bytes != fsize) {
3042                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3043                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3044                                    (uint64_t)bytes, (uint64_t)fsize);
3045                 free(fw_buf);
3046                 close(fw_f);
3047                 return -EIO;
3048         }
3049
3050         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3051         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3052         PMD_DRV_LOG(INFO, "Done");
3053
3054         free(fw_buf);
3055         close(fw_f);
3056
3057         return 0;
3058 }
3059
3060 static int
3061 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3062              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3063 {
3064         struct nfp_nsp *nsp;
3065         const char *nfp_fw_model;
3066         char card_desc[100];
3067         int err = 0;
3068
3069         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3070
3071         if (nfp_fw_model) {
3072                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3073         } else {
3074                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3075                 return -EIO;
3076         }
3077
3078         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3079                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3080                        nfp_eth_table->count);
3081                 return -EIO;
3082         }
3083
3084         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3085                            nfp_eth_table->count);
3086
3087         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3088
3089         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3090                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3091
3092         nsp = nfp_nsp_open(cpp);
3093         if (!nsp) {
3094                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3095                 return -EIO;
3096         }
3097
3098         nfp_nsp_device_soft_reset(nsp);
3099         err = nfp_fw_upload(dev, nsp, card_desc);
3100
3101         nfp_nsp_close(nsp);
3102         return err;
3103 }
3104
3105 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3106                             struct rte_pci_device *dev)
3107 {
3108         struct nfp_cpp *cpp;
3109         struct nfp_hwinfo *hwinfo;
3110         struct nfp_rtsym_table *sym_tbl;
3111         struct nfp_eth_table *nfp_eth_table = NULL;
3112         int total_ports;
3113         void *priv = 0;
3114         int ret = -ENODEV;
3115         int err;
3116         int i;
3117
3118         if (!dev)
3119                 return ret;
3120
3121         cpp = nfp_cpp_from_device_name(dev->device.name);
3122         if (!cpp) {
3123                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3124                 ret = -EIO;
3125                 goto error;
3126         }
3127
3128         hwinfo = nfp_hwinfo_read(cpp);
3129         if (!hwinfo) {
3130                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3131                 return -EIO;
3132         }
3133
3134         nfp_eth_table = nfp_eth_read_ports(cpp);
3135         if (!nfp_eth_table) {
3136                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3137                 return -EIO;
3138         }
3139
3140         if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3141                 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3142                 ret = -EIO;
3143                 goto error;
3144         }
3145
3146         /* Now the symbol table should be there */
3147         sym_tbl = nfp_rtsym_table_read(cpp);
3148         if (!sym_tbl) {
3149                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3150                                 " symbol table");
3151                 ret = -EIO;
3152                 goto error;
3153         }
3154
3155         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3156         if (total_ports != (int)nfp_eth_table->count) {
3157                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3158                 ret = -EIO;
3159                 goto error;
3160         }
3161         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3162
3163         if (total_ports <= 0 || total_ports > 8) {
3164                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3165                 ret = -ENODEV;
3166                 goto error;
3167         }
3168
3169         for (i = 0; i < total_ports; i++) {
3170                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3171                                         nfp_eth_table->ports[i].index,
3172                                         sym_tbl, &priv);
3173                 if (ret)
3174                         break;
3175         }
3176
3177 error:
3178         free(nfp_eth_table);
3179         return ret;
3180 }
3181
3182 int nfp_logtype_init;
3183 int nfp_logtype_driver;
3184
3185 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3186         {
3187                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3188                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3189         },
3190         {
3191                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3192                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3193         },
3194         {
3195                 .vendor_id = 0,
3196         },
3197 };
3198
3199 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3200         {
3201                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3202                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3203         },
3204         {
3205                 .vendor_id = 0,
3206         },
3207 };
3208
3209 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3210         struct rte_pci_device *pci_dev)
3211 {
3212         return rte_eth_dev_pci_generic_probe(pci_dev,
3213                 sizeof(struct nfp_net_adapter), nfp_net_init);
3214 }
3215
3216 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3217 {
3218         struct rte_eth_dev *eth_dev;
3219         struct nfp_net_hw *hw, *hwport0;
3220         int port = 0;
3221
3222         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3223         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3224             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3225                 port = get_pf_port_number(eth_dev->data->name);
3226                 /*
3227                  * hotplug is not possible with multiport PF although freeing
3228                  * data structures can be done for first port.
3229                  */
3230                 if (port != 0)
3231                         return -ENOTSUP;
3232                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3233                 hw = &hwport0[port];
3234                 nfp_cpp_area_free(hw->ctrl_area);
3235                 nfp_cpp_area_free(hw->hwqueues_area);
3236                 free(hw->hwinfo);
3237                 free(hw->sym_tbl);
3238                 nfp_cpp_free(hw->cpp);
3239         } else {
3240                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3241         }
3242         /* hotplug is not possible with multiport PF */
3243         if (hw->pf_multiport_enabled)
3244                 return -ENOTSUP;
3245         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3246 }
3247
3248 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3249         .id_table = pci_id_nfp_pf_net_map,
3250         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3251         .probe = nfp_pf_pci_probe,
3252         .remove = eth_nfp_pci_remove,
3253 };
3254
3255 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3256         .id_table = pci_id_nfp_vf_net_map,
3257         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3258         .probe = eth_nfp_pci_probe,
3259         .remove = eth_nfp_pci_remove,
3260 };
3261
3262 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3263 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3264 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3265 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3266 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3267 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3268
3269 RTE_INIT(nfp_init_log);
3270 static void
3271 nfp_init_log(void)
3272 {
3273         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3274         if (nfp_logtype_init >= 0)
3275                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3276         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3277         if (nfp_logtype_driver >= 0)
3278                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3279 }
3280 /*
3281  * Local variables:
3282  * c-file-style: "Linux"
3283  * indent-tabs-mode: t
3284  * End:
3285  */