2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * vim:shiftwidth=8:noexpandtab
35 * @file dpdk/pmd/nfp_net_pmd.h
37 * Netronome NFP_NET PDM driver
40 #ifndef _NFP_NET_PMD_H_
41 #define _NFP_NET_PMD_H_
43 #define NFP_NET_PMD_VERSION "0.1"
44 #define PCI_VENDOR_ID_NETRONOME 0x19ee
45 #define PCI_DEVICE_ID_NFP6000_PF_NIC 0x6000
46 #define PCI_DEVICE_ID_NFP6000_VF_NIC 0x6003
48 /* Forward declaration */
49 struct nfp_net_adapter;
52 * The maximum number of descriptors is limited by design as
53 * DPDK uses uint16_t variables for these values
55 #define NFP_NET_MAX_TX_DESC (32 * 1024)
56 #define NFP_NET_MIN_TX_DESC 64
58 #define NFP_NET_MAX_RX_DESC (32 * 1024)
59 #define NFP_NET_MIN_RX_DESC 64
62 #define NFP_NET_CRTL_BAR 0
63 #define NFP_NET_TX_BAR 2
64 #define NFP_NET_RX_BAR 2
66 /* Macros for accessing the Queue Controller Peripheral 'CSRs' */
67 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800)
68 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000
69 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004
70 #define NFP_QCP_QUEUE_STS_LO 0x0008
71 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask (0x3ffff)
72 #define NFP_QCP_QUEUE_STS_HI 0x000c
73 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask (0x3ffff)
75 /* Interrupt definitions */
76 #define NFP_NET_IRQ_LSC_IDX 0
78 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
79 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
81 /* Default values for RX/TX configuration */
82 #define DEFAULT_RX_FREE_THRESH 32
83 #define DEFAULT_RX_PTHRESH 8
84 #define DEFAULT_RX_HTHRESH 8
85 #define DEFAULT_RX_WTHRESH 0
87 #define DEFAULT_TX_RS_THRESH 32
88 #define DEFAULT_TX_FREE_THRESH 32
89 #define DEFAULT_TX_PTHRESH 32
90 #define DEFAULT_TX_HTHRESH 0
91 #define DEFAULT_TX_WTHRESH 0
92 #define DEFAULT_TX_RSBIT_THRESH 32
94 /* Alignment for dma zones */
95 #define NFP_MEMZONE_ALIGN 128
98 * This is used by the reconfig protocol. It sets the maximum time waiting in
99 * milliseconds before a reconfig timeout happens.
101 #define NFP_NET_POLL_TIMEOUT 5000
103 #define NFP_QCP_QUEUE_ADDR_SZ (0x800)
105 #define NFP_NET_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
106 #define NFP_NET_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
108 /* Version number helper defines */
109 #define NFD_CFG_CLASS_VER_msk 0xff
110 #define NFD_CFG_CLASS_VER_shf 24
111 #define NFD_CFG_CLASS_VER(x) (((x) & 0xff) << 24)
112 #define NFD_CFG_CLASS_VER_of(x) (((x) >> 24) & 0xff)
113 #define NFD_CFG_CLASS_TYPE_msk 0xff
114 #define NFD_CFG_CLASS_TYPE_shf 16
115 #define NFD_CFG_CLASS_TYPE(x) (((x) & 0xff) << 16)
116 #define NFD_CFG_CLASS_TYPE_of(x) (((x) >> 16) & 0xff)
117 #define NFD_CFG_MAJOR_VERSION_msk 0xff
118 #define NFD_CFG_MAJOR_VERSION_shf 8
119 #define NFD_CFG_MAJOR_VERSION(x) (((x) & 0xff) << 8)
120 #define NFD_CFG_MAJOR_VERSION_of(x) (((x) >> 8) & 0xff)
121 #define NFD_CFG_MINOR_VERSION_msk 0xff
122 #define NFD_CFG_MINOR_VERSION_shf 0
123 #define NFD_CFG_MINOR_VERSION(x) (((x) & 0xff) << 0)
124 #define NFD_CFG_MINOR_VERSION_of(x) (((x) >> 0) & 0xff)
126 #include <linux/types.h>
128 static inline uint8_t nn_readb(volatile const void *addr)
130 return *((volatile const uint8_t *)(addr));
133 static inline void nn_writeb(uint8_t val, volatile void *addr)
135 *((volatile uint8_t *)(addr)) = val;
138 static inline uint32_t nn_readl(volatile const void *addr)
140 return *((volatile const uint32_t *)(addr));
143 static inline void nn_writel(uint32_t val, volatile void *addr)
145 *((volatile uint32_t *)(addr)) = val;
148 static inline uint64_t nn_readq(volatile void *addr)
150 const volatile uint32_t *p = addr;
153 high = nn_readl((volatile const void *)(p + 1));
154 low = nn_readl((volatile const void *)p);
156 return low + ((uint64_t)high << 32);
159 static inline void nn_writeq(uint64_t val, volatile void *addr)
161 nn_writel(val >> 32, (volatile char *)addr + 4);
162 nn_writel(val, addr);
165 /* TX descriptor format */
166 #define PCIE_DESC_TX_EOP (1 << 7)
167 #define PCIE_DESC_TX_OFFSET_MASK (0x7f)
169 /* Flags in the host TX descriptor */
170 #define PCIE_DESC_TX_CSUM (1 << 7)
171 #define PCIE_DESC_TX_IP4_CSUM (1 << 6)
172 #define PCIE_DESC_TX_TCP_CSUM (1 << 5)
173 #define PCIE_DESC_TX_UDP_CSUM (1 << 4)
174 #define PCIE_DESC_TX_VLAN (1 << 3)
175 #define PCIE_DESC_TX_LSO (1 << 2)
176 #define PCIE_DESC_TX_ENCAP_NONE (0)
177 #define PCIE_DESC_TX_ENCAP_VXLAN (1 << 1)
178 #define PCIE_DESC_TX_ENCAP_GRE (1 << 0)
180 struct nfp_net_tx_desc {
183 uint8_t dma_addr_hi; /* High bits of host buf address */
184 __le16 dma_len; /* Length to DMA for this desc */
185 uint8_t offset_eop; /* Offset in buf where pkt starts +
186 * highest bit is eop flag.
188 __le32 dma_addr_lo; /* Low 32bit of host buf addr */
190 __le16 lso; /* MSS to be used for LSO */
191 uint8_t l4_offset; /* LSO, where the L4 data starts */
192 uint8_t flags; /* TX Flags, see @PCIE_DESC_TX_* */
194 __le16 vlan; /* VLAN tag to add if indicated */
195 __le16 data_len; /* Length of frame + meta data */
196 } __attribute__((__packed__));
202 struct nfp_net_hw *hw; /* Backpointer to nfp_net structure */
205 * Queue information: @qidx is the queue index from Linux's
206 * perspective. @tx_qcidx is the index of the Queue
207 * Controller Peripheral queue relative to the TX queue BAR.
208 * @cnt is the size of the queue in number of
209 * descriptors. @qcp_q is a pointer to the base of the queue
210 * structure on the NFP
215 * Read and Write pointers. @wr_p and @rd_p are host side pointer,
216 * they are free running and have little relation to the QCP pointers *
217 * @qcp_rd_p is a local copy queue controller peripheral read pointer
226 uint32_t tx_free_thresh;
230 * For each descriptor keep a reference to the mbuff and
231 * DMA address used until completion is signalled.
234 struct rte_mbuf *mbuf;
238 * Information about the host side queue location. @txds is
239 * the virtual address for the queue, @dma is the DMA address
240 * of the queue and @size is the size in bytes for the queue
243 struct nfp_net_tx_desc *txds;
246 * At this point 56 bytes have been used for all the fields in the
247 * TX critical path. We have room for 8 bytes and still all placed
248 * in a cache line. We are not using the threshold values below nor
249 * the txq_flags but if we need to, we can add the most used in the
252 uint32_t tx_rs_thresh; /* not used by now. Future? */
253 uint32_t tx_pthresh; /* not used by now. Future? */
254 uint32_t tx_hthresh; /* not used by now. Future? */
255 uint32_t tx_wthresh; /* not used by now. Future? */
256 uint32_t txq_flags; /* not used by now. Future? */
261 } __attribute__ ((__aligned__(64)));
263 /* RX and freelist descriptor format */
264 #define PCIE_DESC_RX_DD (1 << 7)
265 #define PCIE_DESC_RX_META_LEN_MASK (0x7f)
267 /* Flags in the RX descriptor */
268 #define PCIE_DESC_RX_RSS (1 << 15)
269 #define PCIE_DESC_RX_I_IP4_CSUM (1 << 14)
270 #define PCIE_DESC_RX_I_IP4_CSUM_OK (1 << 13)
271 #define PCIE_DESC_RX_I_TCP_CSUM (1 << 12)
272 #define PCIE_DESC_RX_I_TCP_CSUM_OK (1 << 11)
273 #define PCIE_DESC_RX_I_UDP_CSUM (1 << 10)
274 #define PCIE_DESC_RX_I_UDP_CSUM_OK (1 << 9)
275 #define PCIE_DESC_RX_INGRESS_PORT (1 << 8)
276 #define PCIE_DESC_RX_EOP (1 << 7)
277 #define PCIE_DESC_RX_IP4_CSUM (1 << 6)
278 #define PCIE_DESC_RX_IP4_CSUM_OK (1 << 5)
279 #define PCIE_DESC_RX_TCP_CSUM (1 << 4)
280 #define PCIE_DESC_RX_TCP_CSUM_OK (1 << 3)
281 #define PCIE_DESC_RX_UDP_CSUM (1 << 2)
282 #define PCIE_DESC_RX_UDP_CSUM_OK (1 << 1)
283 #define PCIE_DESC_RX_VLAN (1 << 0)
285 struct nfp_net_rx_desc {
287 /* Freelist descriptor */
294 } __attribute__((__packed__)) fld;
304 } __attribute__((__packed__)) rxd;
310 struct nfp_net_rx_buff {
311 struct rte_mbuf *mbuf;
315 struct nfp_net_hw *hw; /* Backpointer to nfp_net structure */
318 * @qcp_fl and @qcp_rx are pointers to the base addresses of the
319 * freelist and RX queue controller peripheral queue structures on the
326 * Read and Write pointers. @wr_p and @rd_p are host side
327 * pointer, they are free running and have little relation to
328 * the QCP pointers. @wr_p is where the driver adds new
329 * freelist descriptors and @rd_p is where the driver start
330 * reading descriptors for newly arrive packets from.
336 * For each buffer placed on the freelist, record the
339 struct nfp_net_rx_buff *rxbufs;
342 * Information about the host side queue location. @rxds is
343 * the virtual address for the queue
345 struct nfp_net_rx_desc *rxds;
348 * The mempool is created by the user specifying a mbuf size.
349 * We save here the reference of the mempool needed in the RX
350 * path and the mbuf size for checking received packets can be
351 * safely copied to the mbuf using the NFP_NET_RX_OFFSET
353 struct rte_mempool *mem_pool;
357 * Next two fields are used for giving more free descriptors
360 uint16_t rx_free_thresh;
363 /* the size of the queue in number of descriptors */
367 * Fields above this point fit in a single cache line and are all used
368 * in the RX critical path. Fields below this point are just used
369 * during queue configuration or not used at all (yet)
372 /* referencing dev->data->port_id */
375 uint8_t crc_len; /* Not used by now */
376 uint8_t drop_en; /* Not used by now */
378 /* DMA address of the queue */
382 * Queue information: @qidx is the queue index from Linux's
383 * perspective. @fl_qcidx is the index of the Queue
384 * Controller peripheral queue relative to the RX queue BAR
385 * used for the freelist and @rx_qcidx is the Queue Controller
386 * Peripheral index for the RX queue.
391 } __attribute__ ((__aligned__(64)));
394 /* Info from the firmware */
401 /* Current values for control */
413 uint32_t max_tx_queues;
414 uint32_t max_rx_queues;
418 uint16_t subsystem_device_id;
419 uint16_t subsystem_vendor_id;
420 #if defined(DSTQ_SELECTION)
422 uint16_t device_function;
426 uint8_t mac_addr[ETHER_ADDR_LEN];
428 /* Records starting point for counters */
429 struct rte_eth_stats eth_stats_base;
431 #ifdef NFP_NET_LIBNFP
433 struct nfp_cpp_area *ctrl_area;
434 struct nfp_cpp_area *tx_area;
435 struct nfp_cpp_area *rx_area;
436 struct nfp_cpp_area *msix_area;
440 struct nfp_net_adapter {
441 struct nfp_net_hw hw;
444 #define NFP_NET_DEV_PRIVATE_TO_HW(adapter)\
445 (&((struct nfp_net_adapter *)adapter)->hw)
447 #endif /* _NFP_NET_PMD_H_ */
450 * c-file-style: "Linux"
451 * indent-tabs-mode: t