14 #define CFG_EXP_BAR_ADDR_SZ 1
15 #define CFG_EXP_BAR_MAP_TYPE 1
17 #define EXP_BAR_TARGET_SHIFT 23
18 #define EXP_BAR_LENGTH_SHIFT 27 /* 0=32, 1=64 bit increment */
19 #define EXP_BAR_MAP_TYPE_SHIFT 29 /* Bulk BAR map */
21 /* NFP target for NSP access */
22 #define NFP_NSP_TARGET 7
24 /* Expansion BARs for mapping PF vnic BARs */
25 #define NFP_NET_PF_CFG_EXP_BAR 6
26 #define NFP_NET_PF_HW_QUEUES_EXP_BAR 5
29 * This is an NFP internal address used for configuring properly an NFP
32 #define MEM_CMD_BASE_ADDR 0x8100000000
34 /* NSP interface registers */
35 #define NSP_BASE (MEM_CMD_BASE_ADDR + 0x22100)
36 #define NSP_STATUS 0x00
37 #define NSP_COMMAND 0x08
38 #define NSP_BUFFER 0x10
39 #define NSP_DEFAULT_BUF 0x18
40 #define NSP_DEFAULT_BUF_CFG 0x20
42 #define NSP_MAGIC 0xab10
43 #define NSP_STATUS_MAGIC(x) (((x) >> 48) & 0xffff)
44 #define NSP_STATUS_MAJOR(x) (int)(((x) >> 44) & 0xf)
45 #define NSP_STATUS_MINOR(x) (int)(((x) >> 32) & 0xfff)
48 #define NSP_CMD_RESET 1
49 #define NSP_CMD_FW_LOAD 6
50 #define NSP_CMD_GET_SYMBOL 14
52 #define NSP_BUFFER_CFG_SIZE_MASK (0xff)
54 #define NSP_REG_ADDR(d, off, reg) ((uint8_t *)(d)->mem_base + (off) + (reg))
55 #define NSP_REG_VAL(p) (*(uint64_t *)(p))
58 * An NFP expansion BAR is configured for allowing access to a specific NFP
62 * desc: struct with basic NSP addresses to work with
63 * expbar: NFP PF expansion BAR index to configure
64 * tgt: NFP target to configure access
65 * addr: NFP target address
68 * pcie_offset: NFP PCI BAR offset to work with
71 nfp_nspu_mem_bar_cfg(nspu_desc_t *desc, int expbar, int tgt,
72 uint64_t addr, uint64_t *pcie_offset)
80 * NFP CPP address to configure. This comes from NFP 6000
81 * datasheet document based on Bulk mapping.
83 x = (addr >> (barsz - 3)) << (21 - (40 - (barsz - 3)));
84 x |= CFG_EXP_BAR_MAP_TYPE << EXP_BAR_MAP_TYPE_SHIFT;
85 x |= CFG_EXP_BAR_ADDR_SZ << EXP_BAR_LENGTH_SHIFT;
86 x |= tgt << EXP_BAR_TARGET_SHIFT;
88 /* Getting expansion bar configuration register address */
89 expbar_ptr = (uint32_t *)desc->cfg_base;
90 /* Each physical PCI BAR has 8 NFP expansion BARs */
91 expbar_ptr += (desc->pcie_bar * 8) + expbar;
93 /* Writing to the expansion BAR register */
94 *expbar_ptr = (uint32_t)x;
96 /* Getting the pcie offset to work with from userspace */
97 y = addr & ((uint64_t)(1 << (barsz - 3)) - 1);
102 * Configuring an expansion bar for accessing NSP userspace interface. This
103 * function configures always the same expansion bar, which implies access to
104 * previously configured NFP target is lost.
107 nspu_xlate(nspu_desc_t *desc, uint64_t addr, uint64_t *pcie_offset)
109 nfp_nspu_mem_bar_cfg(desc, desc->exp_bar, NFP_NSP_TARGET, addr,
114 nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor)
116 uint64_t pcie_offset;
119 nspu_xlate(desc, NSP_BASE, &pcie_offset);
120 nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, pcie_offset, NSP_STATUS));
122 if (NSP_STATUS_MAGIC(nsp_reg) != NSP_MAGIC)
125 *major = NSP_STATUS_MAJOR(nsp_reg);
126 *minor = NSP_STATUS_MINOR(nsp_reg);
132 nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz,
133 int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap)
135 uint64_t offset, buffaddr;
139 desc->pcie_bar = pcie_bar;
140 desc->exp_bar = exp_bar;
141 desc->barsz = pcie_barsz;
142 desc->windowsz = 1 << (desc->barsz - 3);
143 desc->cfg_base = exp_bar_cfg_base;
144 desc->mem_base = exp_bar_mmap;
146 nspu_xlate(desc, NSP_BASE, &offset);
149 * Other NSPU clients can use other buffers. Let's tell NSPU we use the
152 buffaddr = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF));
153 NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_BUFFER)) = buffaddr;
155 /* NFP internal addresses are 40 bits. Clean all other bits here */
156 buffaddr = buffaddr & (((uint64_t)1 << 40) - 1);
157 desc->bufaddr = buffaddr;
159 /* Lets get information about the buffer */
160 nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF_CFG));
162 /* Buffer size comes in MBs. Coversion to bytes */
163 desc->buf_size = ((size_t)nsp_reg & NSP_BUFFER_CFG_SIZE_MASK) << 20;
168 #define NSPU_NFP_BUF(addr, base, off) \
169 (*(uint64_t *)((uint8_t *)(addr)->mem_base + ((base) | (off))))
171 #define NSPU_HOST_BUF(base, off) (*(uint64_t *)((uint8_t *)(base) + (off)))
174 nspu_buff_write(nspu_desc_t *desc, void *buffer, size_t size)
176 uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
177 uint64_t windowsz = desc->windowsz;
178 uint64_t buffaddr, j, i = 0;
181 if (size > desc->buf_size)
184 buffaddr = desc->bufaddr;
185 windowsz = desc->windowsz;
188 /* Expansion bar reconfiguration per window size */
189 nspu_xlate(desc, buffaddr + i, &pcie_offset);
190 pcie_window_base = pcie_offset & (~(windowsz - 1));
191 pcie_window_offset = pcie_offset & (windowsz - 1);
192 for (j = pcie_window_offset; ((j < windowsz) && (i < size));
194 NSPU_NFP_BUF(desc, pcie_window_base, j) =
195 NSPU_HOST_BUF(buffer, i);
204 nspu_buff_read(nspu_desc_t *desc, void *buffer, size_t size)
206 uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
207 uint64_t windowsz, i = 0, j;
211 if (size > desc->buf_size)
214 buffaddr = desc->bufaddr;
215 windowsz = desc->windowsz;
218 /* Expansion bar reconfiguration per window size */
219 nspu_xlate(desc, buffaddr + i, &pcie_offset);
220 pcie_window_base = pcie_offset & (~(windowsz - 1));
221 pcie_window_offset = pcie_offset & (windowsz - 1);
222 for (j = pcie_window_offset; ((j < windowsz) && (i < size));
224 NSPU_HOST_BUF(buffer, i) =
225 NSPU_NFP_BUF(desc, pcie_window_base, j);
234 nspu_command(nspu_desc_t *desc, uint16_t cmd, int read, int write,
235 void *buffer, size_t rsize, size_t wsize)
237 uint64_t status, cmd_reg;
243 /* Same expansion BAR is used for different things */
244 nspu_xlate(desc, NSP_BASE, &offset);
246 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
248 while ((status & 0x1) && (retry < retries)) {
249 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
254 if (retry == retries)
258 ret = nspu_buff_write(desc, buffer, wsize);
262 /* Expansion BAR changes when writing the buffer */
263 nspu_xlate(desc, NSP_BASE, &offset);
266 NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)) =
267 (uint64_t)wsize << 32 | (uint64_t)cmd << 16 | 1;
271 cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
272 while ((cmd_reg & 0x1) && (retry < retries)) {
273 cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
277 if (retry == retries)
281 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
282 while ((status & 0x1) && (retry < retries)) {
283 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
288 if (retry == retries)
291 ret = status & (0xff << 8);
296 ret = nspu_buff_read(desc, buffer, rsize);
305 nfp_fw_reset(nspu_desc_t *nspu_desc)
309 res = nspu_command(nspu_desc, NSP_CMD_RESET, 0, 0, 0, 0, 0);
312 RTE_LOG(INFO, PMD, "fw reset failed: error %d", res);
317 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
318 #define DEFAULT_FW_FILENAME "nic_dpdk_default.nffw"
321 nfp_fw_upload(nspu_desc_t *nspu_desc)
326 struct stat file_stat;
331 size = nspu_desc->buf_size;
333 sprintf(filename, "%s/%s", DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
334 fw_f = open(filename, O_RDONLY);
336 RTE_LOG(INFO, PMD, "Firmware file %s/%s not found.",
337 DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
341 fstat(fw_f, &file_stat);
343 fsize = file_stat.st_size;
344 RTE_LOG(DEBUG, PMD, "Firmware file with size: %" PRIu64 "\n",
347 if (fsize > (off_t)size) {
348 RTE_LOG(INFO, PMD, "fw file too big: %" PRIu64
349 " bytes (%" PRIu64 " max)",
350 (uint64_t)fsize, (uint64_t)size);
354 fw_buf = malloc((size_t)size);
356 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
359 memset(fw_buf, 0, size);
361 bytes = read(fw_f, fw_buf, fsize);
362 if (bytes != fsize) {
363 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
364 "Just %" PRIu64 " of %" PRIu64 " bytes read.",
365 (uint64_t)bytes, (uint64_t)fsize);
370 ret = nspu_command(nspu_desc, NSP_CMD_FW_LOAD, 0, 1, fw_buf, 0, bytes);
377 /* Firmware symbol descriptor size */
378 #define NFP_SYM_DESC_LEN 40
380 #define SYMBOL_DATA(b, off) (*(int64_t *)((b) + (off)))
381 #define SYMBOL_UDATA(b, off) (*(uint64_t *)((b) + (off)))
383 /* Firmware symbols contain information about how to access what they
384 * represent. It can be as simple as an numeric variable declared at a
385 * specific NFP memory, but it can also be more complex structures and
386 * related to specific hardware functionalities or components. Target,
387 * domain and address allow to create the BAR window for accessing such
388 * hw object and size defines the length to map.
390 * A vNIC is a network interface implemented inside the NFP and using a
391 * subset of device PCI BARs. Specific firmware symbols allow to map those
392 * vNIC bars by host drivers like the NFP PMD.
394 * Accessing what the symbol represents implies to map the access through
395 * a PCI BAR window. NFP expansion BARs are used in this regard through
396 * the NSPU interface.
399 nfp_nspu_set_bar_from_symbl(nspu_desc_t *desc, const char *symbl,
400 uint32_t expbar, uint64_t *pcie_offset,
410 sym_buf = malloc(desc->buf_size);
411 strncpy(sym_buf, symbl, strlen(symbl));
412 ret = nspu_command(desc, NSP_CMD_GET_SYMBOL, 1, 1, sym_buf,
413 NFP_SYM_DESC_LEN, strlen(symbl));
415 RTE_LOG(DEBUG, PMD, "symbol resolution (%s) failed\n", symbl);
419 /* Reading symbol information */
420 type = SYMBOL_DATA(sym_buf, 0);
421 target = SYMBOL_DATA(sym_buf, 8);
422 domain = SYMBOL_DATA(sym_buf, 16);
423 addr = SYMBOL_UDATA(sym_buf, 24);
424 *size = (ssize_t)SYMBOL_UDATA(sym_buf, 32);
427 RTE_LOG(INFO, PMD, "wrong symbol type\n");
431 if (!(target == 7 || target == -7)) {
432 RTE_LOG(INFO, PMD, "wrong symbol target\n");
436 if (domain == 8 || domain == 9) {
437 RTE_LOG(INFO, PMD, "wrong symbol domain\n");
442 /* Adjusting address based on symbol location */
443 if ((domain >= 24) && (domain < 28) && (target == 7)) {
444 addr = 1ULL << 37 | addr | ((uint64_t)domain & 0x3) << 35;
446 addr = 1ULL << 39 | addr | ((uint64_t)domain & 0x3f) << 32;
451 /* Configuring NFP expansion bar for mapping specific PCI BAR window */
452 nfp_nspu_mem_bar_cfg(desc, expbar, target, addr, pcie_offset);
454 /* This is the PCI BAR offset to use by the host */
455 *pcie_offset |= ((expbar & 0x7) << (desc->barsz - 3));
463 nfp_nsp_fw_setup(nspu_desc_t *desc, const char *sym, uint64_t *pcie_offset)
465 ssize_t bar0_sym_size;
467 /* If the symbol resolution works, it implies a firmware app
470 if (!nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR,
471 pcie_offset, &bar0_sym_size))
474 /* No firmware app detected or not the right one */
475 RTE_LOG(INFO, PMD, "No firmware detected. Resetting NFP...\n");
476 if (nfp_fw_reset(desc) < 0) {
477 RTE_LOG(ERR, PMD, "nfp fw reset failed\n");
481 RTE_LOG(INFO, PMD, "Reset done.\n");
482 RTE_LOG(INFO, PMD, "Uploading firmware...\n");
484 if (nfp_fw_upload(desc) < 0) {
485 RTE_LOG(ERR, PMD, "nfp fw upload failed\n");
489 RTE_LOG(INFO, PMD, "Done.\n");
491 /* Now the symbol should be there */
492 if (nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR,
493 pcie_offset, &bar0_sym_size)) {
494 RTE_LOG(ERR, PMD, "nfp PF BAR symbol resolution failed\n");
502 nfp_nsp_map_ctrl_bar(nspu_desc_t *desc, uint64_t *pcie_offset)
504 ssize_t bar0_sym_size;
506 if (nfp_nspu_set_bar_from_symbl(desc, "_pf0_net_bar0",
507 NFP_NET_PF_CFG_EXP_BAR,
508 pcie_offset, &bar0_sym_size))
515 * This is a hardcoded fixed NFP internal CPP bus address for the hw queues unit
516 * inside the PCIE island.
518 #define NFP_CPP_PCIE_QUEUES ((uint64_t)(1ULL << 39) | 0x80000 | \
519 ((uint64_t)0x4 & 0x3f) << 32)
521 /* Configure a specific NFP expansion bar for accessing the vNIC rx/tx BARs */
523 nfp_nsp_map_queues_bar(nspu_desc_t *desc, uint64_t *pcie_offset)
525 nfp_nspu_mem_bar_cfg(desc, NFP_NET_PF_HW_QUEUES_EXP_BAR, 0,
526 NFP_CPP_PCIE_QUEUES, pcie_offset);
528 /* This is the pcie offset to use by the host */
529 *pcie_offset |= ((NFP_NET_PF_HW_QUEUES_EXP_BAR & 0x7) << (27 - 3));