14 #define CFG_EXP_BAR_ADDR_SZ 1
15 #define CFG_EXP_BAR_MAP_TYPE 1
17 #define EXP_BAR_TARGET_SHIFT 23
18 #define EXP_BAR_LENGTH_SHIFT 27 /* 0=32, 1=64 bit increment */
19 #define EXP_BAR_MAP_TYPE_SHIFT 29 /* Bulk BAR map */
21 /* NFP target for NSP access */
22 #define NFP_NSP_TARGET 7
25 * This is an NFP internal address used for configuring properly an NFP
28 #define MEM_CMD_BASE_ADDR 0x8100000000
30 /* NSP interface registers */
31 #define NSP_BASE (MEM_CMD_BASE_ADDR + 0x22100)
32 #define NSP_STATUS 0x00
33 #define NSP_COMMAND 0x08
34 #define NSP_BUFFER 0x10
35 #define NSP_DEFAULT_BUF 0x18
36 #define NSP_DEFAULT_BUF_CFG 0x20
38 #define NSP_MAGIC 0xab10
39 #define NSP_STATUS_MAGIC(x) (((x) >> 48) & 0xffff)
40 #define NSP_STATUS_MAJOR(x) (int)(((x) >> 44) & 0xf)
41 #define NSP_STATUS_MINOR(x) (int)(((x) >> 32) & 0xfff)
44 #define NSP_CMD_RESET 1
45 #define NSP_CMD_FW_LOAD 6
46 #define NSP_CMD_GET_SYMBOL 14
48 #define NSP_BUFFER_CFG_SIZE_MASK (0xff)
50 #define NSP_REG_ADDR(d, off, reg) ((uint8_t *)(d)->mem_base + (off) + (reg))
51 #define NSP_REG_VAL(p) (*(uint64_t *)(p))
54 * An NFP expansion BAR is configured for allowing access to a specific NFP
58 * desc: struct with basic NSP addresses to work with
59 * expbar: NFP PF expansion BAR index to configure
60 * tgt: NFP target to configure access
61 * addr: NFP target address
64 * pcie_offset: NFP PCI BAR offset to work with
67 nfp_nspu_mem_bar_cfg(nspu_desc_t *desc, int expbar, int tgt,
68 uint64_t addr, uint64_t *pcie_offset)
76 * NFP CPP address to configure. This comes from NFP 6000
77 * datasheet document based on Bulk mapping.
79 x = (addr >> (barsz - 3)) << (21 - (40 - (barsz - 3)));
80 x |= CFG_EXP_BAR_MAP_TYPE << EXP_BAR_MAP_TYPE_SHIFT;
81 x |= CFG_EXP_BAR_ADDR_SZ << EXP_BAR_LENGTH_SHIFT;
82 x |= tgt << EXP_BAR_TARGET_SHIFT;
84 /* Getting expansion bar configuration register address */
85 expbar_ptr = (uint32_t *)desc->cfg_base;
86 /* Each physical PCI BAR has 8 NFP expansion BARs */
87 expbar_ptr += (desc->pcie_bar * 8) + expbar;
89 /* Writing to the expansion BAR register */
90 *expbar_ptr = (uint32_t)x;
92 /* Getting the pcie offset to work with from userspace */
93 y = addr & ((uint64_t)(1 << (barsz - 3)) - 1);
98 * Configuring an expansion bar for accessing NSP userspace interface. This
99 * function configures always the same expansion bar, which implies access to
100 * previously configured NFP target is lost.
103 nspu_xlate(nspu_desc_t *desc, uint64_t addr, uint64_t *pcie_offset)
105 nfp_nspu_mem_bar_cfg(desc, desc->exp_bar, NFP_NSP_TARGET, addr,
110 nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor)
112 uint64_t pcie_offset;
115 nspu_xlate(desc, NSP_BASE, &pcie_offset);
116 nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, pcie_offset, NSP_STATUS));
118 if (NSP_STATUS_MAGIC(nsp_reg) != NSP_MAGIC)
121 *major = NSP_STATUS_MAJOR(nsp_reg);
122 *minor = NSP_STATUS_MINOR(nsp_reg);
128 nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz,
129 int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap)
131 uint64_t offset, buffaddr;
135 desc->pcie_bar = pcie_bar;
136 desc->exp_bar = exp_bar;
137 desc->barsz = pcie_barsz;
138 desc->windowsz = 1 << (desc->barsz - 3);
139 desc->cfg_base = exp_bar_cfg_base;
140 desc->mem_base = exp_bar_mmap;
142 nspu_xlate(desc, NSP_BASE, &offset);
145 * Other NSPU clients can use other buffers. Let's tell NSPU we use the
148 buffaddr = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF));
149 NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_BUFFER)) = buffaddr;
151 /* NFP internal addresses are 40 bits. Clean all other bits here */
152 buffaddr = buffaddr & (((uint64_t)1 << 40) - 1);
153 desc->bufaddr = buffaddr;
155 /* Lets get information about the buffer */
156 nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF_CFG));
158 /* Buffer size comes in MBs. Coversion to bytes */
159 desc->buf_size = ((size_t)nsp_reg & NSP_BUFFER_CFG_SIZE_MASK) << 20;
164 #define NSPU_NFP_BUF(addr, base, off) \
165 (*(uint64_t *)((uint8_t *)(addr)->mem_base + ((base) | (off))))
167 #define NSPU_HOST_BUF(base, off) (*(uint64_t *)((uint8_t *)(base) + (off)))
170 nspu_buff_write(nspu_desc_t *desc, void *buffer, size_t size)
172 uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
173 uint64_t windowsz = desc->windowsz;
174 uint64_t buffaddr, j, i = 0;
177 if (size > desc->buf_size)
180 buffaddr = desc->bufaddr;
181 windowsz = desc->windowsz;
184 /* Expansion bar reconfiguration per window size */
185 nspu_xlate(desc, buffaddr + i, &pcie_offset);
186 pcie_window_base = pcie_offset & (~(windowsz - 1));
187 pcie_window_offset = pcie_offset & (windowsz - 1);
188 for (j = pcie_window_offset; ((j < windowsz) && (i < size));
190 NSPU_NFP_BUF(desc, pcie_window_base, j) =
191 NSPU_HOST_BUF(buffer, i);
200 nspu_buff_read(nspu_desc_t *desc, void *buffer, size_t size)
202 uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
203 uint64_t windowsz, i = 0, j;
207 if (size > desc->buf_size)
210 buffaddr = desc->bufaddr;
211 windowsz = desc->windowsz;
214 /* Expansion bar reconfiguration per window size */
215 nspu_xlate(desc, buffaddr + i, &pcie_offset);
216 pcie_window_base = pcie_offset & (~(windowsz - 1));
217 pcie_window_offset = pcie_offset & (windowsz - 1);
218 for (j = pcie_window_offset; ((j < windowsz) && (i < size));
220 NSPU_HOST_BUF(buffer, i) =
221 NSPU_NFP_BUF(desc, pcie_window_base, j);
230 nspu_command(nspu_desc_t *desc, uint16_t cmd, int read, int write,
231 void *buffer, size_t rsize, size_t wsize)
233 uint64_t status, cmd_reg;
239 /* Same expansion BAR is used for different things */
240 nspu_xlate(desc, NSP_BASE, &offset);
242 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
244 while ((status & 0x1) && (retry < retries)) {
245 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
250 if (retry == retries)
254 ret = nspu_buff_write(desc, buffer, wsize);
258 /* Expansion BAR changes when writing the buffer */
259 nspu_xlate(desc, NSP_BASE, &offset);
262 NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)) =
263 (uint64_t)wsize << 32 | (uint64_t)cmd << 16 | 1;
267 cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
268 while ((cmd_reg & 0x1) && (retry < retries)) {
269 cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
273 if (retry == retries)
277 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
278 while ((status & 0x1) && (retry < retries)) {
279 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
284 if (retry == retries)
287 ret = status & (0xff << 8);
292 ret = nspu_buff_read(desc, buffer, rsize);
301 nfp_fw_reset(nspu_desc_t *nspu_desc)
305 res = nspu_command(nspu_desc, NSP_CMD_RESET, 0, 0, 0, 0, 0);
308 RTE_LOG(INFO, PMD, "fw reset failed: error %d", res);
313 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
314 #define DEFAULT_FW_FILENAME "nic_dpdk_default.nffw"
317 nfp_fw_upload(nspu_desc_t *nspu_desc)
322 struct stat file_stat;
327 size = nspu_desc->buf_size;
329 sprintf(filename, "%s/%s", DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
330 fw_f = open(filename, O_RDONLY);
332 RTE_LOG(INFO, PMD, "Firmware file %s/%s not found.",
333 DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
337 fstat(fw_f, &file_stat);
339 fsize = file_stat.st_size;
340 RTE_LOG(DEBUG, PMD, "Firmware file with size: %" PRIu64 "\n",
343 if (fsize > (off_t)size) {
344 RTE_LOG(INFO, PMD, "fw file too big: %" PRIu64
345 " bytes (%" PRIu64 " max)",
346 (uint64_t)fsize, (uint64_t)size);
350 fw_buf = malloc((size_t)size);
352 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
355 memset(fw_buf, 0, size);
357 bytes = read(fw_f, fw_buf, fsize);
358 if (bytes != fsize) {
359 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
360 "Just %" PRIu64 " of %" PRIu64 " bytes read.",
361 (uint64_t)bytes, (uint64_t)fsize);
366 ret = nspu_command(nspu_desc, NSP_CMD_FW_LOAD, 0, 1, fw_buf, 0, bytes);
373 /* Firmware symbol descriptor size */
374 #define NFP_SYM_DESC_LEN 40
376 #define SYMBOL_DATA(b, off) (*(int64_t *)((b) + (off)))
377 #define SYMBOL_UDATA(b, off) (*(uint64_t *)((b) + (off)))
379 /* Firmware symbols contain information about how to access what they
380 * represent. It can be as simple as an numeric variable declared at a
381 * specific NFP memory, but it can also be more complex structures and
382 * related to specific hardware functionalities or components. Target,
383 * domain and address allow to create the BAR window for accessing such
384 * hw object and size defines the length to map.
386 * A vNIC is a network interface implemented inside the NFP and using a
387 * subset of device PCI BARs. Specific firmware symbols allow to map those
388 * vNIC bars by host drivers like the NFP PMD.
390 * Accessing what the symbol represents implies to map the access through
391 * a PCI BAR window. NFP expansion BARs are used in this regard through
392 * the NSPU interface.
395 nfp_nspu_set_bar_from_symbl(nspu_desc_t *desc, const char *symbl,
396 uint32_t expbar, uint64_t *pcie_offset,
406 sym_buf = malloc(desc->buf_size);
407 strncpy(sym_buf, symbl, strlen(symbl));
408 ret = nspu_command(desc, NSP_CMD_GET_SYMBOL, 1, 1, sym_buf,
409 NFP_SYM_DESC_LEN, strlen(symbl));
411 RTE_LOG(DEBUG, PMD, "symbol resolution (%s) failed\n", symbl);
415 /* Reading symbol information */
416 type = SYMBOL_DATA(sym_buf, 0);
417 target = SYMBOL_DATA(sym_buf, 8);
418 domain = SYMBOL_DATA(sym_buf, 16);
419 addr = SYMBOL_UDATA(sym_buf, 24);
420 *size = (ssize_t)SYMBOL_UDATA(sym_buf, 32);
423 RTE_LOG(INFO, PMD, "wrong symbol type\n");
427 if (!(target == 7 || target == -7)) {
428 RTE_LOG(INFO, PMD, "wrong symbol target\n");
432 if (domain == 8 || domain == 9) {
433 RTE_LOG(INFO, PMD, "wrong symbol domain\n");
438 /* Adjusting address based on symbol location */
439 if ((domain >= 24) && (domain < 28) && (target == 7)) {
440 addr = 1ULL << 37 | addr | ((uint64_t)domain & 0x3) << 35;
442 addr = 1ULL << 39 | addr | ((uint64_t)domain & 0x3f) << 32;
447 /* Configuring NFP expansion bar for mapping specific PCI BAR window */
448 nfp_nspu_mem_bar_cfg(desc, expbar, target, addr, pcie_offset);
450 /* This is the PCI BAR offset to use by the host */
451 *pcie_offset |= ((expbar & 0x7) << (desc->barsz - 3));