drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             18
  33 #define ECORE_REVISION_VERSION          7
  34 #define ECORE_ENGINEERING_VERSION       1
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define MAX_HWFNS_PER_DEVICE    2
  45 #define NAME_SIZE 128 /* @DPDK */
  46 #define ECORE_WFQ_UNIT  100
  47 #include "../qede_logs.h" /* @DPDK */
  48
  49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  51 /* Constants */
  52 #define ECORE_WID_SIZE          (1024)
  53
  54 /* Configurable */
  55 #define ECORE_PF_DEMS_SIZE      (4)
  56
  57 /* cau states */
  58 enum ecore_coalescing_mode {
  59         ECORE_COAL_MODE_DISABLE,
  60         ECORE_COAL_MODE_ENABLE
  61 };
  62
  63 enum ecore_nvm_cmd {
  64         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  65         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  66         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  67         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  68         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  69         ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
  70         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  71         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  72         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  73         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  74         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  75         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  76 };
  77
  78 #ifndef LINUX_REMOVE
  79 #if !defined(CONFIG_ECORE_L2)
  80 #define CONFIG_ECORE_L2
  81 #define CONFIG_ECORE_SRIOV
  82 #endif
  83 #endif
  84
  85 /* helpers */
  86 #ifndef __EXTRACT__LINUX__
  87 #define MASK_FIELD(_name, _value)                                       \
  88                 ((_value) &= (_name##_MASK))
  89
  90 #define FIELD_VALUE(_name, _value)                                      \
  91                 ((_value & _name##_MASK) << _name##_SHIFT)
  92
  93 #define SET_FIELD(value, name, flag)                                    \
  94 do {                                                                    \
  95         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  96         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  97 } while (0)
  98
  99 #define GET_FIELD(value, name)                                          \
 100         (((value) >> (name##_SHIFT)) & name##_MASK)
 101
 102 #define GET_MFW_FIELD(name, field)                              \
 103         (((name) & (field ## _MASK)) >> (field ## _OFFSET))
 104
 105 #define SET_MFW_FIELD(name, field, value)                               \
 106 do {                                                                    \
 107         (name) &= ~((field ## _MASK));          \
 108         (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
 109 } while (0)
 110 #endif
 111
 112 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 113 {
 114         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 115                       (cid * ECORE_PF_DEMS_SIZE);
 116
 117         return db_addr;
 118 }
 119
 120 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 121 {
 122         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 123                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 124
 125         return db_addr;
 126 }
 127
 128 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 129         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 130          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 131
 132 #ifndef LINUX_REMOVE
 133 #ifndef U64_HI
 134 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 135 #endif
 136
 137 #ifndef U64_LO
 138 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 139 #endif
 140 #endif
 141
 142 #ifndef __EXTRACT__LINUX__
 143 enum DP_LEVEL {
 144         ECORE_LEVEL_VERBOSE     = 0x0,
 145         ECORE_LEVEL_INFO        = 0x1,
 146         ECORE_LEVEL_NOTICE      = 0x2,
 147         ECORE_LEVEL_ERR         = 0x3,
 148 };
 149
 150 #define ECORE_LOG_LEVEL_SHIFT   (30)
 151 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 152 #define ECORE_LOG_INFO_MASK     (0x40000000)
 153 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 154
 155 enum DP_MODULE {
 156 #ifndef LINUX_REMOVE
 157         ECORE_MSG_DRV           = 0x0001,
 158         ECORE_MSG_PROBE         = 0x0002,
 159         ECORE_MSG_LINK          = 0x0004,
 160         ECORE_MSG_TIMER         = 0x0008,
 161         ECORE_MSG_IFDOWN        = 0x0010,
 162         ECORE_MSG_IFUP          = 0x0020,
 163         ECORE_MSG_RX_ERR        = 0x0040,
 164         ECORE_MSG_TX_ERR        = 0x0080,
 165         ECORE_MSG_TX_QUEUED     = 0x0100,
 166         ECORE_MSG_INTR          = 0x0200,
 167         ECORE_MSG_TX_DONE       = 0x0400,
 168         ECORE_MSG_RX_STATUS     = 0x0800,
 169         ECORE_MSG_PKTDATA       = 0x1000,
 170         ECORE_MSG_HW            = 0x2000,
 171         ECORE_MSG_WOL           = 0x4000,
 172 #endif
 173         ECORE_MSG_SPQ           = 0x10000,
 174         ECORE_MSG_STATS         = 0x20000,
 175         ECORE_MSG_DCB           = 0x40000,
 176         ECORE_MSG_IOV           = 0x80000,
 177         ECORE_MSG_SP            = 0x100000,
 178         ECORE_MSG_STORAGE       = 0x200000,
 179         ECORE_MSG_OOO           = 0x200000,
 180         ECORE_MSG_CXT           = 0x800000,
 181         ECORE_MSG_LL2           = 0x1000000,
 182         ECORE_MSG_ILT           = 0x2000000,
 183         ECORE_MSG_RDMA          = 0x4000000,
 184         ECORE_MSG_DEBUG         = 0x8000000,
 185         /* to be added...up to 0x8000000 */
 186 };
 187 #endif
 188
 189 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 190
 191 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 192         (val == (cond1) ? true1 : \
 193          (val == (cond2) ? true2 : def))
 194
 195 /* forward */
 196 struct ecore_ptt_pool;
 197 struct ecore_spq;
 198 struct ecore_sb_info;
 199 struct ecore_sb_attn_info;
 200 struct ecore_cxt_mngr;
 201 struct ecore_dma_mem;
 202 struct ecore_sb_sp_info;
 203 struct ecore_ll2_info;
 204 struct ecore_l2_info;
 205 struct ecore_igu_info;
 206 struct ecore_mcp_info;
 207 struct ecore_dcbx_info;
 208
 209 struct ecore_rt_data {
 210         u32     *init_val;
 211         bool    *b_valid;
 212 };
 213
 214 enum ecore_tunn_mode {
 215         ECORE_MODE_L2GENEVE_TUNN,
 216         ECORE_MODE_IPGENEVE_TUNN,
 217         ECORE_MODE_L2GRE_TUNN,
 218         ECORE_MODE_IPGRE_TUNN,
 219         ECORE_MODE_VXLAN_TUNN,
 220 };
 221
 222 enum ecore_tunn_clss {
 223         ECORE_TUNN_CLSS_MAC_VLAN,
 224         ECORE_TUNN_CLSS_MAC_VNI,
 225         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 226         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 227         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 228         MAX_ECORE_TUNN_CLSS,
 229 };
 230
 231 struct ecore_tunn_update_type {
 232         bool b_update_mode;
 233         bool b_mode_enabled;
 234         enum ecore_tunn_clss tun_cls;
 235 };
 236
 237 struct ecore_tunn_update_udp_port {
 238         bool b_update_port;
 239         u16 port;
 240 };
 241
 242 struct ecore_tunnel_info {
 243         struct ecore_tunn_update_type vxlan;
 244         struct ecore_tunn_update_type l2_geneve;
 245         struct ecore_tunn_update_type ip_geneve;
 246         struct ecore_tunn_update_type l2_gre;
 247         struct ecore_tunn_update_type ip_gre;
 248
 249         struct ecore_tunn_update_udp_port vxlan_port;
 250         struct ecore_tunn_update_udp_port geneve_port;
 251
 252         bool b_update_rx_cls;
 253         bool b_update_tx_cls;
 254 };
 255
 256 /* The PCI personality is not quite synonymous to protocol ID:
 257  * 1. All personalities need CORE connections
 258  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 259  */
 260 enum ecore_pci_personality {
 261         ECORE_PCI_ETH,
 262         ECORE_PCI_FCOE,
 263         ECORE_PCI_ISCSI,
 264         ECORE_PCI_ETH_ROCE,
 265         ECORE_PCI_ETH_IWARP,
 266         ECORE_PCI_ETH_RDMA,
 267         ECORE_PCI_DEFAULT /* default in shmem */
 268 };
 269
 270 /* All VFs are symmetric, all counters are PF + all VFs */
 271 struct ecore_qm_iids {
 272         u32 cids;
 273         u32 vf_cids;
 274         u32 tids;
 275 };
 276
 277 #define MAX_PF_PER_PORT 8
 278
 279 /* HW / FW resources, output of features supported below, most information
 280  * is received from MFW.
 281  */
 282 enum ecore_resources {
 283         ECORE_L2_QUEUE,
 284         ECORE_VPORT,
 285         ECORE_RSS_ENG,
 286         ECORE_PQ,
 287         ECORE_RL,
 288         ECORE_MAC,
 289         ECORE_VLAN,
 290         ECORE_RDMA_CNQ_RAM,
 291         ECORE_ILT,
 292         ECORE_LL2_QUEUE,
 293         ECORE_CMDQS_CQS,
 294         ECORE_RDMA_STATS_QUEUE,
 295         ECORE_BDQ,
 296
 297         /* This is needed only internally for matching against the IGU.
 298          * In case of legacy MFW, would be set to `0'.
 299          */
 300         ECORE_SB,
 301
 302         ECORE_MAX_RESC,
 303 };
 304
 305 /* Features that require resources, given as input to the resource management
 306  * algorithm, the output are the resources above
 307  */
 308 enum ecore_feature {
 309         ECORE_PF_L2_QUE,
 310         ECORE_PF_TC,
 311         ECORE_VF,
 312         ECORE_EXTRA_VF_QUE,
 313         ECORE_VMQ,
 314         ECORE_RDMA_CNQ,
 315         ECORE_ISCSI_CQ,
 316         ECORE_FCOE_CQ,
 317         ECORE_VF_L2_QUE,
 318         ECORE_MAX_FEATURES,
 319 };
 320
 321 enum ecore_port_mode {
 322         ECORE_PORT_MODE_DE_2X40G,
 323         ECORE_PORT_MODE_DE_2X50G,
 324         ECORE_PORT_MODE_DE_1X100G,
 325         ECORE_PORT_MODE_DE_4X10G_F,
 326         ECORE_PORT_MODE_DE_4X10G_E,
 327         ECORE_PORT_MODE_DE_4X20G,
 328         ECORE_PORT_MODE_DE_1X40G,
 329         ECORE_PORT_MODE_DE_2X25G,
 330         ECORE_PORT_MODE_DE_1X25G,
 331         ECORE_PORT_MODE_DE_4X25G,
 332         ECORE_PORT_MODE_DE_2X10G,
 333 };
 334
 335 enum ecore_dev_cap {
 336         ECORE_DEV_CAP_ETH,
 337         ECORE_DEV_CAP_FCOE,
 338         ECORE_DEV_CAP_ISCSI,
 339         ECORE_DEV_CAP_ROCE,
 340         ECORE_DEV_CAP_IWARP
 341 };
 342
 343 #ifndef __EXTRACT__LINUX__
 344 enum ecore_hw_err_type {
 345         ECORE_HW_ERR_FAN_FAIL,
 346         ECORE_HW_ERR_MFW_RESP_FAIL,
 347         ECORE_HW_ERR_HW_ATTN,
 348         ECORE_HW_ERR_DMAE_FAIL,
 349         ECORE_HW_ERR_RAMROD_FAIL,
 350         ECORE_HW_ERR_FW_ASSERT,
 351 };
 352 #endif
 353
 354 struct ecore_hw_info {
 355         /* PCI personality */
 356         enum ecore_pci_personality personality;
 357 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 358         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 359          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 360          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 361 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 362         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 363          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 364 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 365         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 366          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 367 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 368         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 369          ECORE_IS_RDMA_PERSONALITY(dev))
 370
 371         /* Resource Allocation scheme results */
 372         u32 resc_start[ECORE_MAX_RESC];
 373         u32 resc_num[ECORE_MAX_RESC];
 374         u32 feat_num[ECORE_MAX_FEATURES];
 375
 376         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 377         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 378         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 379                                          RESC_NUM(_p_hwfn, resc))
 380         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 381
 382         /* Amount of traffic classes HW supports */
 383         u8 num_hw_tc;
 384
 385 /* Amount of TCs which should be active according to DCBx or upper layer driver
 386  * configuration
 387  */
 388
 389         u8 num_active_tc;
 390
 391         /* The traffic class used by PF for it's offloaded protocol */
 392         u8 offload_tc;
 393
 394         u32 concrete_fid;
 395         u16 opaque_fid;
 396         u16 ovlan;
 397         u32 part_num[4];
 398
 399         unsigned char hw_mac_addr[ETH_ALEN];
 400         u64 node_wwn; /* For FCoE only */
 401         u64 port_wwn; /* For FCoE only */
 402
 403         u16 num_iscsi_conns;
 404         u16 num_fcoe_conns;
 405
 406         struct ecore_igu_info *p_igu_info;
 407         /* Sriov */
 408         u8 max_chains_per_vf;
 409
 410         u32 port_mode;
 411         u32     hw_mode;
 412         unsigned long device_capabilities;
 413
 414         /* Default DCBX mode */
 415         u8 dcbx_mode;
 416
 417         u16 mtu;
 418 };
 419
 420 /* maximun size of read/write commands (HW limit) */
 421 #define DMAE_MAX_RW_SIZE        0x2000
 422
 423 struct ecore_dmae_info {
 424         /* Mutex for synchronizing access to functions */
 425         osal_mutex_t    mutex;
 426
 427         u8 channel;
 428
 429         dma_addr_t completion_word_phys_addr;
 430
 431         /* The memory location where the DMAE writes the completion
 432          * value when an operation is finished on this context.
 433          */
 434         u32 *p_completion_word;
 435
 436         dma_addr_t intermediate_buffer_phys_addr;
 437
 438         /* An intermediate buffer for DMAE operations that use virtual
 439          * addresses - data is DMA'd to/from this buffer and then
 440          * memcpy'd to/from the virtual address
 441          */
 442         u32 *p_intermediate_buffer;
 443
 444         dma_addr_t dmae_cmd_phys_addr;
 445         struct dmae_cmd *p_dmae_cmd;
 446 };
 447
 448 struct ecore_wfq_data {
 449         u32 default_min_speed; /* When wfq feature is not configured */
 450         u32 min_speed; /* when feature is configured for any 1 vport */
 451         bool configured;
 452 };
 453
 454 struct ecore_qm_info {
 455         struct init_qm_pq_params    *qm_pq_params;
 456         struct init_qm_vport_params *qm_vport_params;
 457         struct init_qm_port_params  *qm_port_params;
 458         u16                     start_pq;
 459         u8                      start_vport;
 460         u16                     pure_lb_pq;
 461         u16                     offload_pq;
 462         u16                     pure_ack_pq;
 463         u16                     ooo_pq;
 464         u16                     first_vf_pq;
 465         u16                     first_mcos_pq;
 466         u16                     first_rl_pq;
 467         u16                     num_pqs;
 468         u16                     num_vf_pqs;
 469         u8                      num_vports;
 470         u8                      max_phys_tcs_per_port;
 471         u8                      ooo_tc;
 472         bool                    pf_rl_en;
 473         bool                    pf_wfq_en;
 474         bool                    vport_rl_en;
 475         bool                    vport_wfq_en;
 476         u8                      pf_wfq;
 477         u32                     pf_rl;
 478         struct ecore_wfq_data   *wfq_data;
 479         u8                      num_pf_rls;
 480 };
 481
 482 struct storm_stats {
 483         u32 address;
 484         u32 len;
 485 };
 486
 487 struct ecore_fw_data {
 488 #ifdef CONFIG_ECORE_BINARY_FW
 489         struct fw_ver_info *fw_ver_info;
 490 #endif
 491         const u8 *modes_tree_buf;
 492         union init_op *init_ops;
 493         const u32 *arr_data;
 494         u32 init_ops_size;
 495 };
 496
 497 struct ecore_hwfn {
 498         struct ecore_dev                *p_dev;
 499         u8                              my_id;          /* ID inside the PF */
 500 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 501         u8                              rel_pf_id;      /* Relative to engine*/
 502         u8                              abs_pf_id;
 503         #define ECORE_PATH_ID(_p_hwfn) \
 504                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 505         u8                              port_id;
 506         bool                            b_active;
 507
 508         u32                             dp_module;
 509         u8                              dp_level;
 510         char                            name[NAME_SIZE];
 511         void                            *dp_ctx;
 512
 513         bool                            first_on_engine;
 514         bool                            hw_init_done;
 515
 516         u8                              num_funcs_on_engine;
 517         u8                              enabled_func_idx;
 518
 519         /* BAR access */
 520         void OSAL_IOMEM                 *regview;
 521         void OSAL_IOMEM                 *doorbells;
 522         u64                             db_phys_addr;
 523         unsigned long                   db_size;
 524
 525         /* PTT pool */
 526         struct ecore_ptt_pool           *p_ptt_pool;
 527
 528         /* HW info */
 529         struct ecore_hw_info            hw_info;
 530
 531         /* rt_array (for init-tool) */
 532         struct ecore_rt_data            rt_data;
 533
 534         /* SPQ */
 535         struct ecore_spq                *p_spq;
 536
 537         /* EQ */
 538         struct ecore_eq                 *p_eq;
 539
 540         /* Consolidate Q*/
 541         struct ecore_consq              *p_consq;
 542
 543         /* Slow-Path definitions */
 544         osal_dpc_t                      sp_dpc;
 545         bool                            b_sp_dpc_enabled;
 546
 547         struct ecore_ptt                *p_main_ptt;
 548         struct ecore_ptt                *p_dpc_ptt;
 549
 550         struct ecore_sb_sp_info         *p_sp_sb;
 551         struct ecore_sb_attn_info       *p_sb_attn;
 552
 553         /* Protocol related */
 554         bool                            using_ll2;
 555         struct ecore_ll2_info           *p_ll2_info;
 556         struct ecore_ooo_info           *p_ooo_info;
 557         struct ecore_iscsi_info         *p_iscsi_info;
 558         struct ecore_fcoe_info          *p_fcoe_info;
 559         struct ecore_rdma_info          *p_rdma_info;
 560         struct ecore_pf_params          pf_params;
 561
 562         bool                            b_rdma_enabled_in_prs;
 563         u32                             rdma_prs_search_reg;
 564
 565         struct ecore_cxt_mngr           *p_cxt_mngr;
 566
 567         /* Flag indicating whether interrupts are enabled or not*/
 568         bool                            b_int_enabled;
 569         bool                            b_int_requested;
 570
 571         /* True if the driver requests for the link */
 572         bool                            b_drv_link_init;
 573
 574         struct ecore_vf_iov             *vf_iov_info;
 575         struct ecore_pf_iov             *pf_iov_info;
 576         struct ecore_mcp_info           *mcp_info;
 577         struct ecore_dcbx_info          *p_dcbx_info;
 578
 579         struct ecore_dmae_info          dmae_info;
 580
 581         /* QM init */
 582         struct ecore_qm_info            qm_info;
 583
 584 #ifdef CONFIG_ECORE_ZIPPED_FW
 585         /* Buffer for unzipping firmware data */
 586         void *unzip_buf;
 587 #endif
 588
 589         struct dbg_tools_data           dbg_info;
 590
 591         struct z_stream_s               *stream;
 592
 593         /* PWM region specific data */
 594         u32                             dpi_size;
 595         u32                             dpi_count;
 596         u32                             dpi_start_offset; /* this is used to
 597                                                            * calculate th
 598                                                            * doorbell address
 599                                                            */
 600
 601         /* If one of the following is set then EDPM shouldn't be used */
 602         u8                              dcbx_no_edpm;
 603         u8                              db_bar_no_edpm;
 604
 605         /* L2-related */
 606         struct ecore_l2_info            *p_l2_info;
 607
 608         /* @DPDK */
 609         struct ecore_ptt                *p_arfs_ptt;
 610 };
 611
 612 #ifndef __EXTRACT__LINUX__
 613 enum ecore_mf_mode {
 614         ECORE_MF_DEFAULT,
 615         ECORE_MF_OVLAN,
 616         ECORE_MF_NPAR,
 617 };
 618 #endif
 619
 620 /* @DPDK */
 621 struct ecore_dbg_feature {
 622         u8                              *dump_buf;
 623         u32                             buf_size;
 624         u32                             dumped_dwords;
 625 };
 626
 627 enum qed_dbg_features {
 628         DBG_FEATURE_BUS,
 629         DBG_FEATURE_GRC,
 630         DBG_FEATURE_IDLE_CHK,
 631         DBG_FEATURE_MCP_TRACE,
 632         DBG_FEATURE_REG_FIFO,
 633         DBG_FEATURE_PROTECTION_OVERRIDE,
 634         DBG_FEATURE_NUM
 635 };
 636
 637 enum ecore_dev_type {
 638         ECORE_DEV_TYPE_BB,
 639         ECORE_DEV_TYPE_AH,
 640 };
 641
 642 struct ecore_dev {
 643         u32                             dp_module;
 644         u8                              dp_level;
 645         char                            name[NAME_SIZE];
 646         void                            *dp_ctx;
 647
 648         enum ecore_dev_type             type;
 649 /* Translate type/revision combo into the proper conditions */
 650 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 651 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 652 #ifndef ASIC_ONLY
 653 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 654                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 655 #else
 656 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 657 #endif
 658 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 659 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 660
 661         u16 vendor_id;
 662         u16 device_id;
 663 #define ECORE_DEV_ID_MASK       0xff00
 664 #define ECORE_DEV_ID_MASK_BB    0x1600
 665 #define ECORE_DEV_ID_MASK_AH    0x8000
 666
 667         u16                             chip_num;
 668         #define CHIP_NUM_MASK                   0xffff
 669         #define CHIP_NUM_SHIFT                  16
 670
 671         u16                             chip_rev;
 672         #define CHIP_REV_MASK                   0xf
 673         #define CHIP_REV_SHIFT                  12
 674 #ifndef ASIC_ONLY
 675         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 676         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 677         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 678         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 679                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 680         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 681         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 682         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 683                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 684         #define CHIP_REV_IS_SLOW(_p_dev) \
 685                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 686         #define CHIP_REV_IS_A0(_p_dev) \
 687                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 688                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 689                  !(_p_dev)->chip_rev)
 690         #define CHIP_REV_IS_B0(_p_dev) \
 691                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 692                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 693                  (_p_dev)->chip_rev == 1)
 694         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 695 #else
 696         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 697         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 698 #endif
 699
 700         u16                             chip_metal;
 701         #define CHIP_METAL_MASK                 0xff
 702         #define CHIP_METAL_SHIFT                4
 703
 704         u16                             chip_bond_id;
 705         #define CHIP_BOND_ID_MASK               0xf
 706         #define CHIP_BOND_ID_SHIFT              0
 707
 708         u8                              num_engines;
 709         u8                              num_ports_in_engines;
 710         u8                              num_funcs_in_port;
 711
 712         u8                              path_id;
 713         enum ecore_mf_mode              mf_mode;
 714         #define IS_MF_DEFAULT(_p_hwfn)  \
 715                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 716         #define IS_MF_SI(_p_hwfn)       \
 717                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 718         #define IS_MF_SD(_p_hwfn)       \
 719                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 720
 721         int                             pcie_width;
 722         int                             pcie_speed;
 723
 724         /* Add MF related configuration */
 725         u8                              mcp_rev;
 726         u8                              boot_mode;
 727
 728         u8                              wol;
 729
 730         u32                             int_mode;
 731         enum ecore_coalescing_mode      int_coalescing_mode;
 732         u16                             rx_coalesce_usecs;
 733         u16                             tx_coalesce_usecs;
 734
 735         /* Start Bar offset of first hwfn */
 736         void OSAL_IOMEM                 *regview;
 737         void OSAL_IOMEM                 *doorbells;
 738         u64                             db_phys_addr;
 739         unsigned long                   db_size;
 740
 741         /* PCI */
 742         u8                              cache_shift;
 743
 744         /* Init */
 745         const struct iro                *iro_arr;
 746         #define IRO (p_hwfn->p_dev->iro_arr)
 747
 748         /* HW functions */
 749         u8                              num_hwfns;
 750         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 751
 752         /* SRIOV */
 753         struct ecore_hw_sriov_info      *p_iov_info;
 754 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 755         struct ecore_tunnel_info        tunnel;
 756         bool                            b_is_vf;
 757         bool                            b_dont_override_vf_msix;
 758
 759         u32                             drv_type;
 760
 761         u32                             rdma_max_sge;
 762         u32                             rdma_max_inline;
 763         u32                             rdma_max_srq_sge;
 764
 765         struct ecore_eth_stats          *reset_stats;
 766         struct ecore_fw_data            *fw_data;
 767
 768         u32                             mcp_nvm_resp;
 769
 770         /* Recovery */
 771         bool                            recov_in_prog;
 772
 773 /* Indicates whether should prevent attentions from being reasserted */
 774
 775         bool                            attn_clr_en;
 776
 777         /* Indicates whether allowing the MFW to collect a crash dump */
 778         bool                            allow_mdump;
 779
 780         /* Indicates if the reg_fifo is checked after any register access */
 781         bool                            chk_reg_fifo;
 782
 783 #ifndef ASIC_ONLY
 784         bool                            b_is_emul_full;
 785 #endif
 786
 787 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 788         void                            *firmware;
 789         u64                             fw_len;
 790 #endif
 791
 792         /* @DPDK */
 793         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 794         u8                              engine_for_debug;
 795 };
 796
 797 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 798                                                   : MAX_NUM_VFS_K2)
 799 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 800                                                   : MAX_NUM_L2_QUEUES_K2)
 801 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 802                                                   : MAX_NUM_PORTS_K2)
 803 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 804                                                   : MAX_SB_PER_PATH_K2)
 805 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 806                                                   : MAX_NUM_PFS_K2)
 807
 808 /**
 809  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 810  *        the concrete value.
 811  *
 812  * @param concrete_fid
 813  *
 814  * @return OSAL_INLINE u8
 815  */
 816 static OSAL_INLINE u8
 817 ecore_concrete_to_sw_fid(__rte_unused struct ecore_dev *p_dev, u32 concrete_fid)
 818 {
 819         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 820         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 821         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 822         u8 sw_fid;
 823
 824         if (vf_valid)
 825                 sw_fid = vfid + MAX_NUM_PFS;
 826         else
 827                 sw_fid = pfid;
 828
 829         return sw_fid;
 830 }
 831
 832 #define PURE_LB_TC 8
 833 #define PKT_LB_TC 9
 834
 835 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 836 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 837                                            struct ecore_ptt *p_ptt,
 838                                            u32 min_pf_rate);
 839
 840 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 841 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 842 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 843 int ecore_device_num_engines(struct ecore_dev *p_dev);
 844 int ecore_device_num_ports(struct ecore_dev *p_dev);
 845 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 846                            u8 *mac);
 847
 848 /* Flags for indication of required queues */
 849 #define PQ_FLAGS_RLS    (1 << 0)
 850 #define PQ_FLAGS_MCOS   (1 << 1)
 851 #define PQ_FLAGS_LB     (1 << 2)
 852 #define PQ_FLAGS_OOO    (1 << 3)
 853 #define PQ_FLAGS_ACK    (1 << 4)
 854 #define PQ_FLAGS_OFLD   (1 << 5)
 855 #define PQ_FLAGS_VFS    (1 << 6)
 856
 857 /* physical queue index for cm context intialization */
 858 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 859 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 860 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 861 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 862
 863 /* amount of resources used in qm init */
 864 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 865 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 866 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 867 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 868 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 869
 870 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 871
 872 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 873
 874 #endif /* __ECORE_H */