drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             18
  33 #define ECORE_REVISION_VERSION          7
  34 #define ECORE_ENGINEERING_VERSION       1
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define MAX_HWFNS_PER_DEVICE    2
  45 #define NAME_SIZE 128 /* @DPDK */
  46 #define ECORE_WFQ_UNIT  100
  47 #include "../qede_logs.h" /* @DPDK */
  48
  49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  51 /* Constants */
  52 #define ECORE_WID_SIZE          (1024)
  53 #define ECORE_MIN_WIDS          (4)
  54
  55 /* Configurable */
  56 #define ECORE_PF_DEMS_SIZE      (4)
  57
  58 /* cau states */
  59 enum ecore_coalescing_mode {
  60         ECORE_COAL_MODE_DISABLE,
  61         ECORE_COAL_MODE_ENABLE
  62 };
  63
  64 enum ecore_nvm_cmd {
  65         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  66         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  67         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  68         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  69         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  70         ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
  71         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  72         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  73         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  74         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  75         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  76         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  77 };
  78
  79 #ifndef LINUX_REMOVE
  80 #if !defined(CONFIG_ECORE_L2)
  81 #define CONFIG_ECORE_L2
  82 #define CONFIG_ECORE_SRIOV
  83 #endif
  84 #endif
  85
  86 /* helpers */
  87 #ifndef __EXTRACT__LINUX__
  88 #define MASK_FIELD(_name, _value)                                       \
  89                 ((_value) &= (_name##_MASK))
  90
  91 #define FIELD_VALUE(_name, _value)                                      \
  92                 ((_value & _name##_MASK) << _name##_SHIFT)
  93
  94 #define SET_FIELD(value, name, flag)                                    \
  95 do {                                                                    \
  96         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  97         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  98 } while (0)
  99
 100 #define GET_FIELD(value, name)                                          \
 101         (((value) >> (name##_SHIFT)) & name##_MASK)
 102
 103 #define GET_MFW_FIELD(name, field)                              \
 104         (((name) & (field ## _MASK)) >> (field ## _OFFSET))
 105
 106 #define SET_MFW_FIELD(name, field, value)                               \
 107 do {                                                                    \
 108         (name) &= ~((field ## _MASK));          \
 109         (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
 110 } while (0)
 111 #endif
 112
 113 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 114 {
 115         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 116                       (cid * ECORE_PF_DEMS_SIZE);
 117
 118         return db_addr;
 119 }
 120
 121 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 122 {
 123         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 124                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 125
 126         return db_addr;
 127 }
 128
 129 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 130         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 131          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 132
 133 #ifndef LINUX_REMOVE
 134 #ifndef U64_HI
 135 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 136 #endif
 137
 138 #ifndef U64_LO
 139 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 140 #endif
 141 #endif
 142
 143 #ifndef __EXTRACT__LINUX__
 144 enum DP_LEVEL {
 145         ECORE_LEVEL_VERBOSE     = 0x0,
 146         ECORE_LEVEL_INFO        = 0x1,
 147         ECORE_LEVEL_NOTICE      = 0x2,
 148         ECORE_LEVEL_ERR         = 0x3,
 149 };
 150
 151 #define ECORE_LOG_LEVEL_SHIFT   (30)
 152 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 153 #define ECORE_LOG_INFO_MASK     (0x40000000)
 154 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 155
 156 enum DP_MODULE {
 157 #ifndef LINUX_REMOVE
 158         ECORE_MSG_DRV           = 0x0001,
 159         ECORE_MSG_PROBE         = 0x0002,
 160         ECORE_MSG_LINK          = 0x0004,
 161         ECORE_MSG_TIMER         = 0x0008,
 162         ECORE_MSG_IFDOWN        = 0x0010,
 163         ECORE_MSG_IFUP          = 0x0020,
 164         ECORE_MSG_RX_ERR        = 0x0040,
 165         ECORE_MSG_TX_ERR        = 0x0080,
 166         ECORE_MSG_TX_QUEUED     = 0x0100,
 167         ECORE_MSG_INTR          = 0x0200,
 168         ECORE_MSG_TX_DONE       = 0x0400,
 169         ECORE_MSG_RX_STATUS     = 0x0800,
 170         ECORE_MSG_PKTDATA       = 0x1000,
 171         ECORE_MSG_HW            = 0x2000,
 172         ECORE_MSG_WOL           = 0x4000,
 173 #endif
 174         ECORE_MSG_SPQ           = 0x10000,
 175         ECORE_MSG_STATS         = 0x20000,
 176         ECORE_MSG_DCB           = 0x40000,
 177         ECORE_MSG_IOV           = 0x80000,
 178         ECORE_MSG_SP            = 0x100000,
 179         ECORE_MSG_STORAGE       = 0x200000,
 180         ECORE_MSG_OOO           = 0x200000,
 181         ECORE_MSG_CXT           = 0x800000,
 182         ECORE_MSG_LL2           = 0x1000000,
 183         ECORE_MSG_ILT           = 0x2000000,
 184         ECORE_MSG_RDMA          = 0x4000000,
 185         ECORE_MSG_DEBUG         = 0x8000000,
 186         /* to be added...up to 0x8000000 */
 187 };
 188 #endif
 189
 190 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 191
 192 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 193         (val == (cond1) ? true1 : \
 194          (val == (cond2) ? true2 : def))
 195
 196 /* forward */
 197 struct ecore_ptt_pool;
 198 struct ecore_spq;
 199 struct ecore_sb_info;
 200 struct ecore_sb_attn_info;
 201 struct ecore_cxt_mngr;
 202 struct ecore_dma_mem;
 203 struct ecore_sb_sp_info;
 204 struct ecore_ll2_info;
 205 struct ecore_l2_info;
 206 struct ecore_igu_info;
 207 struct ecore_mcp_info;
 208 struct ecore_dcbx_info;
 209
 210 struct ecore_rt_data {
 211         u32     *init_val;
 212         bool    *b_valid;
 213 };
 214
 215 enum ecore_tunn_mode {
 216         ECORE_MODE_L2GENEVE_TUNN,
 217         ECORE_MODE_IPGENEVE_TUNN,
 218         ECORE_MODE_L2GRE_TUNN,
 219         ECORE_MODE_IPGRE_TUNN,
 220         ECORE_MODE_VXLAN_TUNN,
 221 };
 222
 223 enum ecore_tunn_clss {
 224         ECORE_TUNN_CLSS_MAC_VLAN,
 225         ECORE_TUNN_CLSS_MAC_VNI,
 226         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 227         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 228         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 229         MAX_ECORE_TUNN_CLSS,
 230 };
 231
 232 struct ecore_tunn_update_type {
 233         bool b_update_mode;
 234         bool b_mode_enabled;
 235         enum ecore_tunn_clss tun_cls;
 236 };
 237
 238 struct ecore_tunn_update_udp_port {
 239         bool b_update_port;
 240         u16 port;
 241 };
 242
 243 struct ecore_tunnel_info {
 244         struct ecore_tunn_update_type vxlan;
 245         struct ecore_tunn_update_type l2_geneve;
 246         struct ecore_tunn_update_type ip_geneve;
 247         struct ecore_tunn_update_type l2_gre;
 248         struct ecore_tunn_update_type ip_gre;
 249
 250         struct ecore_tunn_update_udp_port vxlan_port;
 251         struct ecore_tunn_update_udp_port geneve_port;
 252
 253         bool b_update_rx_cls;
 254         bool b_update_tx_cls;
 255 };
 256
 257 /* The PCI personality is not quite synonymous to protocol ID:
 258  * 1. All personalities need CORE connections
 259  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 260  */
 261 enum ecore_pci_personality {
 262         ECORE_PCI_ETH,
 263         ECORE_PCI_FCOE,
 264         ECORE_PCI_ISCSI,
 265         ECORE_PCI_ETH_ROCE,
 266         ECORE_PCI_ETH_IWARP,
 267         ECORE_PCI_ETH_RDMA,
 268         ECORE_PCI_DEFAULT /* default in shmem */
 269 };
 270
 271 /* All VFs are symmetric, all counters are PF + all VFs */
 272 struct ecore_qm_iids {
 273         u32 cids;
 274         u32 vf_cids;
 275         u32 tids;
 276 };
 277
 278 #define MAX_PF_PER_PORT 8
 279
 280 /* HW / FW resources, output of features supported below, most information
 281  * is received from MFW.
 282  */
 283 enum ecore_resources {
 284         ECORE_L2_QUEUE,
 285         ECORE_VPORT,
 286         ECORE_RSS_ENG,
 287         ECORE_PQ,
 288         ECORE_RL,
 289         ECORE_MAC,
 290         ECORE_VLAN,
 291         ECORE_RDMA_CNQ_RAM,
 292         ECORE_ILT,
 293         ECORE_LL2_QUEUE,
 294         ECORE_CMDQS_CQS,
 295         ECORE_RDMA_STATS_QUEUE,
 296         ECORE_BDQ,
 297
 298         /* This is needed only internally for matching against the IGU.
 299          * In case of legacy MFW, would be set to `0'.
 300          */
 301         ECORE_SB,
 302
 303         ECORE_MAX_RESC,
 304 };
 305
 306 /* Features that require resources, given as input to the resource management
 307  * algorithm, the output are the resources above
 308  */
 309 enum ecore_feature {
 310         ECORE_PF_L2_QUE,
 311         ECORE_PF_TC,
 312         ECORE_VF,
 313         ECORE_EXTRA_VF_QUE,
 314         ECORE_VMQ,
 315         ECORE_RDMA_CNQ,
 316         ECORE_ISCSI_CQ,
 317         ECORE_FCOE_CQ,
 318         ECORE_VF_L2_QUE,
 319         ECORE_MAX_FEATURES,
 320 };
 321
 322 enum ecore_port_mode {
 323         ECORE_PORT_MODE_DE_2X40G,
 324         ECORE_PORT_MODE_DE_2X50G,
 325         ECORE_PORT_MODE_DE_1X100G,
 326         ECORE_PORT_MODE_DE_4X10G_F,
 327         ECORE_PORT_MODE_DE_4X10G_E,
 328         ECORE_PORT_MODE_DE_4X20G,
 329         ECORE_PORT_MODE_DE_1X40G,
 330         ECORE_PORT_MODE_DE_2X25G,
 331         ECORE_PORT_MODE_DE_1X25G,
 332         ECORE_PORT_MODE_DE_4X25G,
 333         ECORE_PORT_MODE_DE_2X10G,
 334 };
 335
 336 enum ecore_dev_cap {
 337         ECORE_DEV_CAP_ETH,
 338         ECORE_DEV_CAP_FCOE,
 339         ECORE_DEV_CAP_ISCSI,
 340         ECORE_DEV_CAP_ROCE,
 341         ECORE_DEV_CAP_IWARP
 342 };
 343
 344 #ifndef __EXTRACT__LINUX__
 345 enum ecore_hw_err_type {
 346         ECORE_HW_ERR_FAN_FAIL,
 347         ECORE_HW_ERR_MFW_RESP_FAIL,
 348         ECORE_HW_ERR_HW_ATTN,
 349         ECORE_HW_ERR_DMAE_FAIL,
 350         ECORE_HW_ERR_RAMROD_FAIL,
 351         ECORE_HW_ERR_FW_ASSERT,
 352 };
 353 #endif
 354
 355 enum ecore_db_rec_exec {
 356         DB_REC_DRY_RUN,
 357         DB_REC_REAL_DEAL,
 358         DB_REC_ONCE,
 359 };
 360
 361 struct ecore_hw_info {
 362         /* PCI personality */
 363         enum ecore_pci_personality personality;
 364 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 365         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 366          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 367          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 368 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 369         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 370          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 371 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 372         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 373          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 374 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 375         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 376          ECORE_IS_RDMA_PERSONALITY(dev))
 377
 378         /* Resource Allocation scheme results */
 379         u32 resc_start[ECORE_MAX_RESC];
 380         u32 resc_num[ECORE_MAX_RESC];
 381         u32 feat_num[ECORE_MAX_FEATURES];
 382
 383         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 384         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 385         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 386                                          RESC_NUM(_p_hwfn, resc))
 387         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 388
 389         /* Amount of traffic classes HW supports */
 390         u8 num_hw_tc;
 391
 392 /* Amount of TCs which should be active according to DCBx or upper layer driver
 393  * configuration
 394  */
 395
 396         u8 num_active_tc;
 397
 398         /* The traffic class used by PF for it's offloaded protocol */
 399         u8 offload_tc;
 400
 401         u32 concrete_fid;
 402         u16 opaque_fid;
 403         u16 ovlan;
 404         u32 part_num[4];
 405
 406         unsigned char hw_mac_addr[ETH_ALEN];
 407         u64 node_wwn; /* For FCoE only */
 408         u64 port_wwn; /* For FCoE only */
 409
 410         u16 num_iscsi_conns;
 411         u16 num_fcoe_conns;
 412
 413         struct ecore_igu_info *p_igu_info;
 414         /* Sriov */
 415         u8 max_chains_per_vf;
 416
 417         u32 port_mode;
 418         u32     hw_mode;
 419         unsigned long device_capabilities;
 420
 421         /* Default DCBX mode */
 422         u8 dcbx_mode;
 423
 424         u16 mtu;
 425 };
 426
 427 /* maximun size of read/write commands (HW limit) */
 428 #define DMAE_MAX_RW_SIZE        0x2000
 429
 430 struct ecore_dmae_info {
 431         /* Mutex for synchronizing access to functions */
 432         osal_mutex_t    mutex;
 433
 434         u8 channel;
 435
 436         dma_addr_t completion_word_phys_addr;
 437
 438         /* The memory location where the DMAE writes the completion
 439          * value when an operation is finished on this context.
 440          */
 441         u32 *p_completion_word;
 442
 443         dma_addr_t intermediate_buffer_phys_addr;
 444
 445         /* An intermediate buffer for DMAE operations that use virtual
 446          * addresses - data is DMA'd to/from this buffer and then
 447          * memcpy'd to/from the virtual address
 448          */
 449         u32 *p_intermediate_buffer;
 450
 451         dma_addr_t dmae_cmd_phys_addr;
 452         struct dmae_cmd *p_dmae_cmd;
 453 };
 454
 455 struct ecore_wfq_data {
 456         u32 default_min_speed; /* When wfq feature is not configured */
 457         u32 min_speed; /* when feature is configured for any 1 vport */
 458         bool configured;
 459 };
 460
 461 struct ecore_qm_info {
 462         struct init_qm_pq_params    *qm_pq_params;
 463         struct init_qm_vport_params *qm_vport_params;
 464         struct init_qm_port_params  *qm_port_params;
 465         u16                     start_pq;
 466         u8                      start_vport;
 467         u16                     pure_lb_pq;
 468         u16                     offload_pq;
 469         u16                     pure_ack_pq;
 470         u16                     ooo_pq;
 471         u16                     first_vf_pq;
 472         u16                     first_mcos_pq;
 473         u16                     first_rl_pq;
 474         u16                     num_pqs;
 475         u16                     num_vf_pqs;
 476         u8                      num_vports;
 477         u8                      max_phys_tcs_per_port;
 478         u8                      ooo_tc;
 479         bool                    pf_rl_en;
 480         bool                    pf_wfq_en;
 481         bool                    vport_rl_en;
 482         bool                    vport_wfq_en;
 483         u8                      pf_wfq;
 484         u32                     pf_rl;
 485         struct ecore_wfq_data   *wfq_data;
 486         u8                      num_pf_rls;
 487 };
 488
 489 struct ecore_db_recovery_info {
 490         osal_list_t list;
 491         osal_spinlock_t lock;
 492         u32 db_recovery_counter;
 493 };
 494
 495 struct storm_stats {
 496         u32 address;
 497         u32 len;
 498 };
 499
 500 struct ecore_fw_data {
 501 #ifdef CONFIG_ECORE_BINARY_FW
 502         struct fw_ver_info *fw_ver_info;
 503 #endif
 504         const u8 *modes_tree_buf;
 505         union init_op *init_ops;
 506         const u32 *arr_data;
 507         u32 init_ops_size;
 508 };
 509
 510 struct ecore_hwfn {
 511         struct ecore_dev                *p_dev;
 512         u8                              my_id;          /* ID inside the PF */
 513 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 514         u8                              rel_pf_id;      /* Relative to engine*/
 515         u8                              abs_pf_id;
 516 #define ECORE_PATH_ID(_p_hwfn) \
 517         (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
 518         u8                              port_id;
 519         bool                            b_active;
 520
 521         u32                             dp_module;
 522         u8                              dp_level;
 523         char                            name[NAME_SIZE];
 524         void                            *dp_ctx;
 525
 526         bool                            first_on_engine;
 527         bool                            hw_init_done;
 528
 529         u8                              num_funcs_on_engine;
 530         u8                              enabled_func_idx;
 531
 532         /* BAR access */
 533         void OSAL_IOMEM                 *regview;
 534         void OSAL_IOMEM                 *doorbells;
 535         u64                             db_phys_addr;
 536         unsigned long                   db_size;
 537
 538         /* PTT pool */
 539         struct ecore_ptt_pool           *p_ptt_pool;
 540
 541         /* HW info */
 542         struct ecore_hw_info            hw_info;
 543
 544         /* rt_array (for init-tool) */
 545         struct ecore_rt_data            rt_data;
 546
 547         /* SPQ */
 548         struct ecore_spq                *p_spq;
 549
 550         /* EQ */
 551         struct ecore_eq                 *p_eq;
 552
 553         /* Consolidate Q*/
 554         struct ecore_consq              *p_consq;
 555
 556         /* Slow-Path definitions */
 557         osal_dpc_t                      sp_dpc;
 558         bool                            b_sp_dpc_enabled;
 559
 560         struct ecore_ptt                *p_main_ptt;
 561         struct ecore_ptt                *p_dpc_ptt;
 562
 563         struct ecore_sb_sp_info         *p_sp_sb;
 564         struct ecore_sb_attn_info       *p_sb_attn;
 565
 566         /* Protocol related */
 567         bool                            using_ll2;
 568         struct ecore_ll2_info           *p_ll2_info;
 569         struct ecore_ooo_info           *p_ooo_info;
 570         struct ecore_iscsi_info         *p_iscsi_info;
 571         struct ecore_fcoe_info          *p_fcoe_info;
 572         struct ecore_rdma_info          *p_rdma_info;
 573         struct ecore_pf_params          pf_params;
 574
 575         bool                            b_rdma_enabled_in_prs;
 576         u32                             rdma_prs_search_reg;
 577
 578         struct ecore_cxt_mngr           *p_cxt_mngr;
 579
 580         /* Flag indicating whether interrupts are enabled or not*/
 581         bool                            b_int_enabled;
 582         bool                            b_int_requested;
 583
 584         /* True if the driver requests for the link */
 585         bool                            b_drv_link_init;
 586
 587         struct ecore_vf_iov             *vf_iov_info;
 588         struct ecore_pf_iov             *pf_iov_info;
 589         struct ecore_mcp_info           *mcp_info;
 590         struct ecore_dcbx_info          *p_dcbx_info;
 591
 592         struct ecore_dmae_info          dmae_info;
 593
 594         /* QM init */
 595         struct ecore_qm_info            qm_info;
 596
 597 #ifdef CONFIG_ECORE_ZIPPED_FW
 598         /* Buffer for unzipping firmware data */
 599         void *unzip_buf;
 600 #endif
 601
 602         struct dbg_tools_data           dbg_info;
 603
 604         struct z_stream_s               *stream;
 605
 606         /* PWM region specific data */
 607         u32                             dpi_size;
 608         u32                             dpi_count;
 609         u32                             dpi_start_offset; /* this is used to
 610                                                            * calculate th
 611                                                            * doorbell address
 612                                                            */
 613
 614         /* If one of the following is set then EDPM shouldn't be used */
 615         u8                              dcbx_no_edpm;
 616         u8                              db_bar_no_edpm;
 617
 618         /* L2-related */
 619         struct ecore_l2_info            *p_l2_info;
 620
 621         /* Mechanism for recovering from doorbell drop */
 622         struct ecore_db_recovery_info   db_recovery_info;
 623
 624         /* @DPDK */
 625         struct ecore_ptt                *p_arfs_ptt;
 626 };
 627
 628 #ifndef __EXTRACT__LINUX__
 629 enum ecore_mf_mode {
 630         ECORE_MF_DEFAULT,
 631         ECORE_MF_OVLAN,
 632         ECORE_MF_NPAR,
 633 };
 634 #endif
 635
 636 /* @DPDK */
 637 struct ecore_dbg_feature {
 638         u8                              *dump_buf;
 639         u32                             buf_size;
 640         u32                             dumped_dwords;
 641 };
 642
 643 enum qed_dbg_features {
 644         DBG_FEATURE_BUS,
 645         DBG_FEATURE_GRC,
 646         DBG_FEATURE_IDLE_CHK,
 647         DBG_FEATURE_MCP_TRACE,
 648         DBG_FEATURE_REG_FIFO,
 649         DBG_FEATURE_PROTECTION_OVERRIDE,
 650         DBG_FEATURE_NUM
 651 };
 652
 653 enum ecore_dev_type {
 654         ECORE_DEV_TYPE_BB,
 655         ECORE_DEV_TYPE_AH,
 656 };
 657
 658 struct ecore_dev {
 659         u32                             dp_module;
 660         u8                              dp_level;
 661         char                            name[NAME_SIZE];
 662         void                            *dp_ctx;
 663
 664         enum ecore_dev_type             type;
 665 /* Translate type/revision combo into the proper conditions */
 666 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 667 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 668 #ifndef ASIC_ONLY
 669 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 670                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 671 #else
 672 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 673 #endif
 674 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 675 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 676
 677         u16 vendor_id;
 678         u16 device_id;
 679 #define ECORE_DEV_ID_MASK       0xff00
 680 #define ECORE_DEV_ID_MASK_BB    0x1600
 681 #define ECORE_DEV_ID_MASK_AH    0x8000
 682
 683         u16                             chip_num;
 684 #define CHIP_NUM_MASK                   0xffff
 685 #define CHIP_NUM_SHIFT                  0
 686
 687         u8                              chip_rev;
 688 #define CHIP_REV_MASK                   0xf
 689 #define CHIP_REV_SHIFT                  0
 690 #ifndef ASIC_ONLY
 691 #define CHIP_REV_IS_TEDIBEAR(_p_dev)    ((_p_dev)->chip_rev == 0x5)
 692 #define CHIP_REV_IS_EMUL_A0(_p_dev)     ((_p_dev)->chip_rev == 0xe)
 693 #define CHIP_REV_IS_EMUL_B0(_p_dev)     ((_p_dev)->chip_rev == 0xc)
 694 #define CHIP_REV_IS_EMUL(_p_dev) \
 695         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
 696 #define CHIP_REV_IS_FPGA_A0(_p_dev)     ((_p_dev)->chip_rev == 0xf)
 697 #define CHIP_REV_IS_FPGA_B0(_p_dev)     ((_p_dev)->chip_rev == 0xd)
 698 #define CHIP_REV_IS_FPGA(_p_dev) \
 699         (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
 700 #define CHIP_REV_IS_SLOW(_p_dev) \
 701         (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 702 #define CHIP_REV_IS_A0(_p_dev) \
 703         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
 704          (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
 705 #define CHIP_REV_IS_B0(_p_dev) \
 706         (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
 707          ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
 708 #define CHIP_REV_IS_ASIC(_p_dev)        !CHIP_REV_IS_SLOW(_p_dev)
 709 #else
 710 #define CHIP_REV_IS_A0(_p_dev) \
 711         (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
 712 #define CHIP_REV_IS_B0(_p_dev) \
 713         ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
 714 #endif
 715
 716         u8                              chip_metal;
 717 #define CHIP_METAL_MASK                 0xff
 718 #define CHIP_METAL_SHIFT                0
 719
 720         u8                              chip_bond_id;
 721 #define CHIP_BOND_ID_MASK               0xff
 722 #define CHIP_BOND_ID_SHIFT              0
 723
 724         u8                              num_engines;
 725         u8                              num_ports;
 726         u8                              num_ports_in_engine;
 727         u8                              num_funcs_in_port;
 728
 729         u8                              path_id;
 730         enum ecore_mf_mode              mf_mode;
 731 #define IS_MF_DEFAULT(_p_hwfn)  \
 732         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 733 #define IS_MF_SI(_p_hwfn)       \
 734         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 735 #define IS_MF_SD(_p_hwfn)       \
 736         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 737
 738         int                             pcie_width;
 739         int                             pcie_speed;
 740
 741         /* Add MF related configuration */
 742         u8                              mcp_rev;
 743         u8                              boot_mode;
 744
 745         u8                              wol;
 746
 747         u32                             int_mode;
 748         enum ecore_coalescing_mode      int_coalescing_mode;
 749         u16                             rx_coalesce_usecs;
 750         u16                             tx_coalesce_usecs;
 751
 752         /* Start Bar offset of first hwfn */
 753         void OSAL_IOMEM                 *regview;
 754         void OSAL_IOMEM                 *doorbells;
 755         u64                             db_phys_addr;
 756         unsigned long                   db_size;
 757
 758         /* PCI */
 759         u8                              cache_shift;
 760
 761         /* Init */
 762         const struct iro                *iro_arr;
 763         #define IRO (p_hwfn->p_dev->iro_arr)
 764
 765         /* HW functions */
 766         u8                              num_hwfns;
 767         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 768 #define ECORE_IS_CMT(dev)               ((dev)->num_hwfns > 1)
 769
 770         /* SRIOV */
 771         struct ecore_hw_sriov_info      *p_iov_info;
 772 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 773         struct ecore_tunnel_info        tunnel;
 774         bool                            b_is_vf;
 775         bool                            b_dont_override_vf_msix;
 776
 777         u32                             drv_type;
 778
 779         u32                             rdma_max_sge;
 780         u32                             rdma_max_inline;
 781         u32                             rdma_max_srq_sge;
 782
 783         struct ecore_eth_stats          *reset_stats;
 784         struct ecore_fw_data            *fw_data;
 785
 786         u32                             mcp_nvm_resp;
 787
 788         /* Recovery */
 789         bool                            recov_in_prog;
 790
 791 /* Indicates whether should prevent attentions from being reasserted */
 792
 793         bool                            attn_clr_en;
 794
 795         /* Indicates whether allowing the MFW to collect a crash dump */
 796         bool                            allow_mdump;
 797
 798         /* Indicates if the reg_fifo is checked after any register access */
 799         bool                            chk_reg_fifo;
 800
 801 #ifndef ASIC_ONLY
 802         bool                            b_is_emul_full;
 803 #endif
 804
 805 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 806         void                            *firmware;
 807         u64                             fw_len;
 808 #endif
 809
 810         /* @DPDK */
 811         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 812         u8                              engine_for_debug;
 813 };
 814
 815 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 816                                                   : MAX_NUM_VFS_K2)
 817 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 818                                                   : MAX_NUM_L2_QUEUES_K2)
 819 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 820                                                   : MAX_NUM_PORTS_K2)
 821 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 822                                                   : MAX_SB_PER_PATH_K2)
 823 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 824                                                   : MAX_NUM_PFS_K2)
 825
 826 /**
 827  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 828  *        the concrete value.
 829  *
 830  * @param concrete_fid
 831  *
 832  * @return OSAL_INLINE u8
 833  */
 834 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
 835 {
 836         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 837         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 838         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 839         u8 sw_fid;
 840
 841         if (vf_valid)
 842                 sw_fid = vfid + MAX_NUM_PFS;
 843         else
 844                 sw_fid = pfid;
 845
 846         return sw_fid;
 847 }
 848
 849 #define PURE_LB_TC 8
 850 #define PKT_LB_TC 9
 851
 852 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 853 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 854                                            struct ecore_ptt *p_ptt,
 855                                            u32 min_pf_rate);
 856
 857 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 858 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 859 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 860 int ecore_device_num_engines(struct ecore_dev *p_dev);
 861 int ecore_device_num_ports(struct ecore_dev *p_dev);
 862 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 863                            u8 *mac);
 864
 865 /* Flags for indication of required queues */
 866 #define PQ_FLAGS_RLS    (1 << 0)
 867 #define PQ_FLAGS_MCOS   (1 << 1)
 868 #define PQ_FLAGS_LB     (1 << 2)
 869 #define PQ_FLAGS_OOO    (1 << 3)
 870 #define PQ_FLAGS_ACK    (1 << 4)
 871 #define PQ_FLAGS_OFLD   (1 << 5)
 872 #define PQ_FLAGS_VFS    (1 << 6)
 873
 874 /* physical queue index for cm context intialization */
 875 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 876 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 877 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 878 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 879
 880 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 881
 882 /* doorbell recovery mechanism */
 883 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
 884 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 885                                enum ecore_db_rec_exec);
 886
 887 /* amount of resources used in qm init */
 888 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 889 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 890 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 891 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 892 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 893
 894 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 895
 896 #endif /* __ECORE_H */