drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             18
  33 #define ECORE_REVISION_VERSION          7
  34 #define ECORE_ENGINEERING_VERSION       1
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define MAX_HWFNS_PER_DEVICE    2
  45 #define NAME_SIZE 128 /* @DPDK */
  46 #define ECORE_WFQ_UNIT  100
  47 #include "../qede_logs.h" /* @DPDK */
  48
  49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  51 /* Constants */
  52 #define ECORE_WID_SIZE          (1024)
  53
  54 /* Configurable */
  55 #define ECORE_PF_DEMS_SIZE      (4)
  56
  57 /* cau states */
  58 enum ecore_coalescing_mode {
  59         ECORE_COAL_MODE_DISABLE,
  60         ECORE_COAL_MODE_ENABLE
  61 };
  62
  63 enum ecore_nvm_cmd {
  64         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  65         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  66         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  67         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  68         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  69         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  70         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  71         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  72         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  73         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  74         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  75 };
  76
  77 #ifndef LINUX_REMOVE
  78 #if !defined(CONFIG_ECORE_L2)
  79 #define CONFIG_ECORE_L2
  80 #define CONFIG_ECORE_SRIOV
  81 #endif
  82 #endif
  83
  84 /* helpers */
  85 #ifndef __EXTRACT__LINUX__
  86 #define MASK_FIELD(_name, _value)                                       \
  87                 ((_value) &= (_name##_MASK))
  88
  89 #define FIELD_VALUE(_name, _value)                                      \
  90                 ((_value & _name##_MASK) << _name##_SHIFT)
  91
  92 #define SET_FIELD(value, name, flag)                                    \
  93 do {                                                                    \
  94         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  95         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  96 } while (0)
  97
  98 #define GET_FIELD(value, name)                                          \
  99         (((value) >> (name##_SHIFT)) & name##_MASK)
 100 #endif
 101
 102 #define ECORE_MFW_GET_FIELD(name, field)                                \
 103         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
 104
 105 #define ECORE_MFW_SET_FIELD(name, field, value)                         \
 106 do {                                                                    \
 107         (name) &= ~(field ## _MASK);                                    \
 108         (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));  \
 109 } while (0)
 110
 111 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 112 {
 113         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 114                       (cid * ECORE_PF_DEMS_SIZE);
 115
 116         return db_addr;
 117 }
 118
 119 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 120 {
 121         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 122                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 123
 124         return db_addr;
 125 }
 126
 127 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 128         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 129          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 130
 131 #ifndef LINUX_REMOVE
 132 #ifndef U64_HI
 133 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 134 #endif
 135
 136 #ifndef U64_LO
 137 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 138 #endif
 139 #endif
 140
 141 #ifndef __EXTRACT__LINUX__
 142 enum DP_LEVEL {
 143         ECORE_LEVEL_VERBOSE     = 0x0,
 144         ECORE_LEVEL_INFO        = 0x1,
 145         ECORE_LEVEL_NOTICE      = 0x2,
 146         ECORE_LEVEL_ERR         = 0x3,
 147 };
 148
 149 #define ECORE_LOG_LEVEL_SHIFT   (30)
 150 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 151 #define ECORE_LOG_INFO_MASK     (0x40000000)
 152 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 153
 154 enum DP_MODULE {
 155 #ifndef LINUX_REMOVE
 156         ECORE_MSG_DRV           = 0x0001,
 157         ECORE_MSG_PROBE         = 0x0002,
 158         ECORE_MSG_LINK          = 0x0004,
 159         ECORE_MSG_TIMER         = 0x0008,
 160         ECORE_MSG_IFDOWN        = 0x0010,
 161         ECORE_MSG_IFUP          = 0x0020,
 162         ECORE_MSG_RX_ERR        = 0x0040,
 163         ECORE_MSG_TX_ERR        = 0x0080,
 164         ECORE_MSG_TX_QUEUED     = 0x0100,
 165         ECORE_MSG_INTR          = 0x0200,
 166         ECORE_MSG_TX_DONE       = 0x0400,
 167         ECORE_MSG_RX_STATUS     = 0x0800,
 168         ECORE_MSG_PKTDATA       = 0x1000,
 169         ECORE_MSG_HW            = 0x2000,
 170         ECORE_MSG_WOL           = 0x4000,
 171 #endif
 172         ECORE_MSG_SPQ           = 0x10000,
 173         ECORE_MSG_STATS         = 0x20000,
 174         ECORE_MSG_DCB           = 0x40000,
 175         ECORE_MSG_IOV           = 0x80000,
 176         ECORE_MSG_SP            = 0x100000,
 177         ECORE_MSG_STORAGE       = 0x200000,
 178         ECORE_MSG_OOO           = 0x200000,
 179         ECORE_MSG_CXT           = 0x800000,
 180         ECORE_MSG_LL2           = 0x1000000,
 181         ECORE_MSG_ILT           = 0x2000000,
 182         ECORE_MSG_RDMA          = 0x4000000,
 183         ECORE_MSG_DEBUG         = 0x8000000,
 184         /* to be added...up to 0x8000000 */
 185 };
 186 #endif
 187
 188 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 189
 190 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 191         (val == (cond1) ? true1 : \
 192          (val == (cond2) ? true2 : def))
 193
 194 /* forward */
 195 struct ecore_ptt_pool;
 196 struct ecore_spq;
 197 struct ecore_sb_info;
 198 struct ecore_sb_attn_info;
 199 struct ecore_cxt_mngr;
 200 struct ecore_dma_mem;
 201 struct ecore_sb_sp_info;
 202 struct ecore_ll2_info;
 203 struct ecore_l2_info;
 204 struct ecore_igu_info;
 205 struct ecore_mcp_info;
 206 struct ecore_dcbx_info;
 207
 208 struct ecore_rt_data {
 209         u32     *init_val;
 210         bool    *b_valid;
 211 };
 212
 213 enum ecore_tunn_mode {
 214         ECORE_MODE_L2GENEVE_TUNN,
 215         ECORE_MODE_IPGENEVE_TUNN,
 216         ECORE_MODE_L2GRE_TUNN,
 217         ECORE_MODE_IPGRE_TUNN,
 218         ECORE_MODE_VXLAN_TUNN,
 219 };
 220
 221 enum ecore_tunn_clss {
 222         ECORE_TUNN_CLSS_MAC_VLAN,
 223         ECORE_TUNN_CLSS_MAC_VNI,
 224         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 225         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 226         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 227         MAX_ECORE_TUNN_CLSS,
 228 };
 229
 230 struct ecore_tunn_update_type {
 231         bool b_update_mode;
 232         bool b_mode_enabled;
 233         enum ecore_tunn_clss tun_cls;
 234 };
 235
 236 struct ecore_tunn_update_udp_port {
 237         bool b_update_port;
 238         u16 port;
 239 };
 240
 241 struct ecore_tunnel_info {
 242         struct ecore_tunn_update_type vxlan;
 243         struct ecore_tunn_update_type l2_geneve;
 244         struct ecore_tunn_update_type ip_geneve;
 245         struct ecore_tunn_update_type l2_gre;
 246         struct ecore_tunn_update_type ip_gre;
 247
 248         struct ecore_tunn_update_udp_port vxlan_port;
 249         struct ecore_tunn_update_udp_port geneve_port;
 250
 251         bool b_update_rx_cls;
 252         bool b_update_tx_cls;
 253 };
 254
 255 /* The PCI personality is not quite synonymous to protocol ID:
 256  * 1. All personalities need CORE connections
 257  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 258  */
 259 enum ecore_pci_personality {
 260         ECORE_PCI_ETH,
 261         ECORE_PCI_FCOE,
 262         ECORE_PCI_ISCSI,
 263         ECORE_PCI_ETH_ROCE,
 264         ECORE_PCI_ETH_IWARP,
 265         ECORE_PCI_ETH_RDMA,
 266         ECORE_PCI_DEFAULT /* default in shmem */
 267 };
 268
 269 /* All VFs are symmetric, all counters are PF + all VFs */
 270 struct ecore_qm_iids {
 271         u32 cids;
 272         u32 vf_cids;
 273         u32 tids;
 274 };
 275
 276 #define MAX_PF_PER_PORT 8
 277
 278 /* HW / FW resources, output of features supported below, most information
 279  * is received from MFW.
 280  */
 281 enum ecore_resources {
 282         ECORE_L2_QUEUE,
 283         ECORE_VPORT,
 284         ECORE_RSS_ENG,
 285         ECORE_PQ,
 286         ECORE_RL,
 287         ECORE_MAC,
 288         ECORE_VLAN,
 289         ECORE_RDMA_CNQ_RAM,
 290         ECORE_ILT,
 291         ECORE_LL2_QUEUE,
 292         ECORE_CMDQS_CQS,
 293         ECORE_RDMA_STATS_QUEUE,
 294         ECORE_BDQ,
 295
 296         /* This is needed only internally for matching against the IGU.
 297          * In case of legacy MFW, would be set to `0'.
 298          */
 299         ECORE_SB,
 300
 301         ECORE_MAX_RESC,
 302 };
 303
 304 /* Features that require resources, given as input to the resource management
 305  * algorithm, the output are the resources above
 306  */
 307 enum ecore_feature {
 308         ECORE_PF_L2_QUE,
 309         ECORE_PF_TC,
 310         ECORE_VF,
 311         ECORE_EXTRA_VF_QUE,
 312         ECORE_VMQ,
 313         ECORE_RDMA_CNQ,
 314         ECORE_ISCSI_CQ,
 315         ECORE_FCOE_CQ,
 316         ECORE_VF_L2_QUE,
 317         ECORE_MAX_FEATURES,
 318 };
 319
 320 enum ecore_port_mode {
 321         ECORE_PORT_MODE_DE_2X40G,
 322         ECORE_PORT_MODE_DE_2X50G,
 323         ECORE_PORT_MODE_DE_1X100G,
 324         ECORE_PORT_MODE_DE_4X10G_F,
 325         ECORE_PORT_MODE_DE_4X10G_E,
 326         ECORE_PORT_MODE_DE_4X20G,
 327         ECORE_PORT_MODE_DE_1X40G,
 328         ECORE_PORT_MODE_DE_2X25G,
 329         ECORE_PORT_MODE_DE_1X25G,
 330         ECORE_PORT_MODE_DE_4X25G,
 331         ECORE_PORT_MODE_DE_2X10G,
 332 };
 333
 334 enum ecore_dev_cap {
 335         ECORE_DEV_CAP_ETH,
 336         ECORE_DEV_CAP_FCOE,
 337         ECORE_DEV_CAP_ISCSI,
 338         ECORE_DEV_CAP_ROCE,
 339         ECORE_DEV_CAP_IWARP
 340 };
 341
 342 #ifndef __EXTRACT__LINUX__
 343 enum ecore_hw_err_type {
 344         ECORE_HW_ERR_FAN_FAIL,
 345         ECORE_HW_ERR_MFW_RESP_FAIL,
 346         ECORE_HW_ERR_HW_ATTN,
 347         ECORE_HW_ERR_DMAE_FAIL,
 348         ECORE_HW_ERR_RAMROD_FAIL,
 349         ECORE_HW_ERR_FW_ASSERT,
 350 };
 351 #endif
 352
 353 struct ecore_hw_info {
 354         /* PCI personality */
 355         enum ecore_pci_personality personality;
 356 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 357         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 358          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 359          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 360 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 361         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 362          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 363 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 364         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 365          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 366 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 367         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 368          ECORE_IS_RDMA_PERSONALITY(dev))
 369
 370         /* Resource Allocation scheme results */
 371         u32 resc_start[ECORE_MAX_RESC];
 372         u32 resc_num[ECORE_MAX_RESC];
 373         u32 feat_num[ECORE_MAX_FEATURES];
 374
 375         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 376         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 377         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 378                                          RESC_NUM(_p_hwfn, resc))
 379         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 380
 381         /* Amount of traffic classes HW supports */
 382         u8 num_hw_tc;
 383
 384 /* Amount of TCs which should be active according to DCBx or upper layer driver
 385  * configuration
 386  */
 387
 388         u8 num_active_tc;
 389
 390         /* The traffic class used by PF for it's offloaded protocol */
 391         u8 offload_tc;
 392
 393         u32 concrete_fid;
 394         u16 opaque_fid;
 395         u16 ovlan;
 396         u32 part_num[4];
 397
 398         unsigned char hw_mac_addr[ETH_ALEN];
 399         u64 node_wwn; /* For FCoE only */
 400         u64 port_wwn; /* For FCoE only */
 401
 402         u16 num_iscsi_conns;
 403         u16 num_fcoe_conns;
 404
 405         struct ecore_igu_info *p_igu_info;
 406         /* Sriov */
 407         u8 max_chains_per_vf;
 408
 409         u32 port_mode;
 410         u32     hw_mode;
 411         unsigned long device_capabilities;
 412
 413         /* Default DCBX mode */
 414         u8 dcbx_mode;
 415
 416         u16 mtu;
 417 };
 418
 419 /* maximun size of read/write commands (HW limit) */
 420 #define DMAE_MAX_RW_SIZE        0x2000
 421
 422 struct ecore_dmae_info {
 423         /* Mutex for synchronizing access to functions */
 424         osal_mutex_t    mutex;
 425
 426         u8 channel;
 427
 428         dma_addr_t completion_word_phys_addr;
 429
 430         /* The memory location where the DMAE writes the completion
 431          * value when an operation is finished on this context.
 432          */
 433         u32 *p_completion_word;
 434
 435         dma_addr_t intermediate_buffer_phys_addr;
 436
 437         /* An intermediate buffer for DMAE operations that use virtual
 438          * addresses - data is DMA'd to/from this buffer and then
 439          * memcpy'd to/from the virtual address
 440          */
 441         u32 *p_intermediate_buffer;
 442
 443         dma_addr_t dmae_cmd_phys_addr;
 444         struct dmae_cmd *p_dmae_cmd;
 445 };
 446
 447 struct ecore_wfq_data {
 448         u32 default_min_speed; /* When wfq feature is not configured */
 449         u32 min_speed; /* when feature is configured for any 1 vport */
 450         bool configured;
 451 };
 452
 453 struct ecore_qm_info {
 454         struct init_qm_pq_params    *qm_pq_params;
 455         struct init_qm_vport_params *qm_vport_params;
 456         struct init_qm_port_params  *qm_port_params;
 457         u16                     start_pq;
 458         u8                      start_vport;
 459         u16                     pure_lb_pq;
 460         u16                     offload_pq;
 461         u16                     pure_ack_pq;
 462         u16                     ooo_pq;
 463         u16                     first_vf_pq;
 464         u16                     first_mcos_pq;
 465         u16                     first_rl_pq;
 466         u16                     num_pqs;
 467         u16                     num_vf_pqs;
 468         u8                      num_vports;
 469         u8                      max_phys_tcs_per_port;
 470         u8                      ooo_tc;
 471         bool                    pf_rl_en;
 472         bool                    pf_wfq_en;
 473         bool                    vport_rl_en;
 474         bool                    vport_wfq_en;
 475         u8                      pf_wfq;
 476         u32                     pf_rl;
 477         struct ecore_wfq_data   *wfq_data;
 478         u8                      num_pf_rls;
 479 };
 480
 481 struct storm_stats {
 482         u32 address;
 483         u32 len;
 484 };
 485
 486 struct ecore_fw_data {
 487 #ifdef CONFIG_ECORE_BINARY_FW
 488         struct fw_ver_info *fw_ver_info;
 489 #endif
 490         const u8 *modes_tree_buf;
 491         union init_op *init_ops;
 492         const u32 *arr_data;
 493         u32 init_ops_size;
 494 };
 495
 496 struct ecore_hwfn {
 497         struct ecore_dev                *p_dev;
 498         u8                              my_id;          /* ID inside the PF */
 499 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 500         u8                              rel_pf_id;      /* Relative to engine*/
 501         u8                              abs_pf_id;
 502         #define ECORE_PATH_ID(_p_hwfn) \
 503                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 504         u8                              port_id;
 505         bool                            b_active;
 506
 507         u32                             dp_module;
 508         u8                              dp_level;
 509         char                            name[NAME_SIZE];
 510         void                            *dp_ctx;
 511
 512         bool                            first_on_engine;
 513         bool                            hw_init_done;
 514
 515         u8                              num_funcs_on_engine;
 516         u8                              enabled_func_idx;
 517
 518         /* BAR access */
 519         void OSAL_IOMEM                 *regview;
 520         void OSAL_IOMEM                 *doorbells;
 521         u64                             db_phys_addr;
 522         unsigned long                   db_size;
 523
 524         /* PTT pool */
 525         struct ecore_ptt_pool           *p_ptt_pool;
 526
 527         /* HW info */
 528         struct ecore_hw_info            hw_info;
 529
 530         /* rt_array (for init-tool) */
 531         struct ecore_rt_data            rt_data;
 532
 533         /* SPQ */
 534         struct ecore_spq                *p_spq;
 535
 536         /* EQ */
 537         struct ecore_eq                 *p_eq;
 538
 539         /* Consolidate Q*/
 540         struct ecore_consq              *p_consq;
 541
 542         /* Slow-Path definitions */
 543         osal_dpc_t                      sp_dpc;
 544         bool                            b_sp_dpc_enabled;
 545
 546         struct ecore_ptt                *p_main_ptt;
 547         struct ecore_ptt                *p_dpc_ptt;
 548
 549         struct ecore_sb_sp_info         *p_sp_sb;
 550         struct ecore_sb_attn_info       *p_sb_attn;
 551
 552         /* Protocol related */
 553         bool                            using_ll2;
 554         struct ecore_ll2_info           *p_ll2_info;
 555         struct ecore_ooo_info           *p_ooo_info;
 556         struct ecore_iscsi_info         *p_iscsi_info;
 557         struct ecore_fcoe_info          *p_fcoe_info;
 558         struct ecore_rdma_info          *p_rdma_info;
 559         struct ecore_pf_params          pf_params;
 560
 561         bool                            b_rdma_enabled_in_prs;
 562         u32                             rdma_prs_search_reg;
 563
 564         struct ecore_cxt_mngr           *p_cxt_mngr;
 565
 566         /* Flag indicating whether interrupts are enabled or not*/
 567         bool                            b_int_enabled;
 568         bool                            b_int_requested;
 569
 570         /* True if the driver requests for the link */
 571         bool                            b_drv_link_init;
 572
 573         struct ecore_vf_iov             *vf_iov_info;
 574         struct ecore_pf_iov             *pf_iov_info;
 575         struct ecore_mcp_info           *mcp_info;
 576         struct ecore_dcbx_info          *p_dcbx_info;
 577
 578         struct ecore_dmae_info          dmae_info;
 579
 580         /* QM init */
 581         struct ecore_qm_info            qm_info;
 582
 583 #ifdef CONFIG_ECORE_ZIPPED_FW
 584         /* Buffer for unzipping firmware data */
 585         void *unzip_buf;
 586 #endif
 587
 588         struct dbg_tools_data           dbg_info;
 589
 590         struct z_stream_s               *stream;
 591
 592         /* PWM region specific data */
 593         u32                             dpi_size;
 594         u32                             dpi_count;
 595         u32                             dpi_start_offset; /* this is used to
 596                                                            * calculate th
 597                                                            * doorbell address
 598                                                            */
 599
 600         /* If one of the following is set then EDPM shouldn't be used */
 601         u8                              dcbx_no_edpm;
 602         u8                              db_bar_no_edpm;
 603
 604         /* L2-related */
 605         struct ecore_l2_info            *p_l2_info;
 606
 607         /* @DPDK */
 608         struct ecore_ptt                *p_arfs_ptt;
 609 };
 610
 611 #ifndef __EXTRACT__LINUX__
 612 enum ecore_mf_mode {
 613         ECORE_MF_DEFAULT,
 614         ECORE_MF_OVLAN,
 615         ECORE_MF_NPAR,
 616 };
 617 #endif
 618
 619 /* @DPDK */
 620 struct ecore_dbg_feature {
 621         u8                              *dump_buf;
 622         u32                             buf_size;
 623         u32                             dumped_dwords;
 624 };
 625
 626 enum qed_dbg_features {
 627         DBG_FEATURE_BUS,
 628         DBG_FEATURE_GRC,
 629         DBG_FEATURE_IDLE_CHK,
 630         DBG_FEATURE_MCP_TRACE,
 631         DBG_FEATURE_REG_FIFO,
 632         DBG_FEATURE_PROTECTION_OVERRIDE,
 633         DBG_FEATURE_NUM
 634 };
 635
 636 enum ecore_dev_type {
 637         ECORE_DEV_TYPE_BB,
 638         ECORE_DEV_TYPE_AH,
 639 };
 640
 641 struct ecore_dev {
 642         u32                             dp_module;
 643         u8                              dp_level;
 644         char                            name[NAME_SIZE];
 645         void                            *dp_ctx;
 646
 647         enum ecore_dev_type             type;
 648 /* Translate type/revision combo into the proper conditions */
 649 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 650 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 651 #ifndef ASIC_ONLY
 652 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 653                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 654 #else
 655 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 656 #endif
 657 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 658 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 659
 660         u16 vendor_id;
 661         u16 device_id;
 662 #define ECORE_DEV_ID_MASK       0xff00
 663 #define ECORE_DEV_ID_MASK_BB    0x1600
 664 #define ECORE_DEV_ID_MASK_AH    0x8000
 665
 666         u16                             chip_num;
 667         #define CHIP_NUM_MASK                   0xffff
 668         #define CHIP_NUM_SHIFT                  16
 669
 670         u16                             chip_rev;
 671         #define CHIP_REV_MASK                   0xf
 672         #define CHIP_REV_SHIFT                  12
 673 #ifndef ASIC_ONLY
 674         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 675         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 676         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 677         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 678                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 679         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 680         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 681         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 682                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 683         #define CHIP_REV_IS_SLOW(_p_dev) \
 684                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 685         #define CHIP_REV_IS_A0(_p_dev) \
 686                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 687                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 688                  !(_p_dev)->chip_rev)
 689         #define CHIP_REV_IS_B0(_p_dev) \
 690                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 691                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 692                  (_p_dev)->chip_rev == 1)
 693         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 694 #else
 695         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 696         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 697 #endif
 698
 699         u16                             chip_metal;
 700         #define CHIP_METAL_MASK                 0xff
 701         #define CHIP_METAL_SHIFT                4
 702
 703         u16                             chip_bond_id;
 704         #define CHIP_BOND_ID_MASK               0xf
 705         #define CHIP_BOND_ID_SHIFT              0
 706
 707         u8                              num_engines;
 708         u8                              num_ports_in_engines;
 709         u8                              num_funcs_in_port;
 710
 711         u8                              path_id;
 712         enum ecore_mf_mode              mf_mode;
 713         #define IS_MF_DEFAULT(_p_hwfn)  \
 714                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 715         #define IS_MF_SI(_p_hwfn)       \
 716                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 717         #define IS_MF_SD(_p_hwfn)       \
 718                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 719
 720         int                             pcie_width;
 721         int                             pcie_speed;
 722
 723         /* Add MF related configuration */
 724         u8                              mcp_rev;
 725         u8                              boot_mode;
 726
 727         u8                              wol;
 728
 729         u32                             int_mode;
 730         enum ecore_coalescing_mode      int_coalescing_mode;
 731         u16                             rx_coalesce_usecs;
 732         u16                             tx_coalesce_usecs;
 733
 734         /* Start Bar offset of first hwfn */
 735         void OSAL_IOMEM                 *regview;
 736         void OSAL_IOMEM                 *doorbells;
 737         u64                             db_phys_addr;
 738         unsigned long                   db_size;
 739
 740         /* PCI */
 741         u8                              cache_shift;
 742
 743         /* Init */
 744         const struct iro                *iro_arr;
 745         #define IRO (p_hwfn->p_dev->iro_arr)
 746
 747         /* HW functions */
 748         u8                              num_hwfns;
 749         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 750
 751         /* SRIOV */
 752         struct ecore_hw_sriov_info      *p_iov_info;
 753 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 754         struct ecore_tunnel_info        tunnel;
 755         bool                            b_is_vf;
 756
 757         u32                             drv_type;
 758
 759         u32                             rdma_max_sge;
 760         u32                             rdma_max_inline;
 761         u32                             rdma_max_srq_sge;
 762
 763         struct ecore_eth_stats          *reset_stats;
 764         struct ecore_fw_data            *fw_data;
 765
 766         u32                             mcp_nvm_resp;
 767
 768         /* Recovery */
 769         bool                            recov_in_prog;
 770
 771 /* Indicates whether should prevent attentions from being reasserted */
 772
 773         bool                            attn_clr_en;
 774
 775         /* Indicates whether allowing the MFW to collect a crash dump */
 776         bool                            allow_mdump;
 777
 778         /* Indicates if the reg_fifo is checked after any register access */
 779         bool                            chk_reg_fifo;
 780
 781 #ifndef ASIC_ONLY
 782         bool                            b_is_emul_full;
 783 #endif
 784
 785 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 786         void                            *firmware;
 787         u64                             fw_len;
 788 #endif
 789
 790         /* @DPDK */
 791         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 792         u8                              engine_for_debug;
 793 };
 794
 795 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 796                                                   : MAX_NUM_VFS_K2)
 797 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 798                                                   : MAX_NUM_L2_QUEUES_K2)
 799 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 800                                                   : MAX_NUM_PORTS_K2)
 801 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 802                                                   : MAX_SB_PER_PATH_K2)
 803 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 804                                                   : MAX_NUM_PFS_K2)
 805
 806 /**
 807  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 808  *        the concrete value.
 809  *
 810  * @param concrete_fid
 811  *
 812  * @return OSAL_INLINE u8
 813  */
 814 static OSAL_INLINE u8
 815 ecore_concrete_to_sw_fid(__rte_unused struct ecore_dev *p_dev, u32 concrete_fid)
 816 {
 817         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 818         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 819         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 820         u8 sw_fid;
 821
 822         if (vf_valid)
 823                 sw_fid = vfid + MAX_NUM_PFS;
 824         else
 825                 sw_fid = pfid;
 826
 827         return sw_fid;
 828 }
 829
 830 #define PURE_LB_TC 8
 831 #define PKT_LB_TC 9
 832
 833 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 834 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 835                                            struct ecore_ptt *p_ptt,
 836                                            u32 min_pf_rate);
 837
 838 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 839 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 840 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 841 int ecore_device_num_engines(struct ecore_dev *p_dev);
 842 int ecore_device_num_ports(struct ecore_dev *p_dev);
 843 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 844                            u8 *mac);
 845
 846 /* Flags for indication of required queues */
 847 #define PQ_FLAGS_RLS    (1 << 0)
 848 #define PQ_FLAGS_MCOS   (1 << 1)
 849 #define PQ_FLAGS_LB     (1 << 2)
 850 #define PQ_FLAGS_OOO    (1 << 3)
 851 #define PQ_FLAGS_ACK    (1 << 4)
 852 #define PQ_FLAGS_OFLD   (1 << 5)
 853 #define PQ_FLAGS_VFS    (1 << 6)
 854
 855 /* physical queue index for cm context intialization */
 856 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 857 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 858 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 859 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 860
 861 /* amount of resources used in qm init */
 862 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 863 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 864 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 865 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 866 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 867
 868 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 869
 870 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 871
 872 #endif /* __ECORE_H */