drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             30
  33 #define ECORE_REVISION_VERSION          8
  34 #define ECORE_ENGINEERING_VERSION       0
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define IS_ECORE_PACING(p_hwfn) \
  45         (!!(p_hwfn->b_en_pacing))
  46
  47 #define MAX_HWFNS_PER_DEVICE    2
  48 #define NAME_SIZE 128 /* @DPDK */
  49 #define ECORE_WFQ_UNIT  100
  50 #include "../qede_logs.h" /* @DPDK */
  51
  52 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  53 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  54 /* Constants */
  55 #define ECORE_WID_SIZE          (1024)
  56 #define ECORE_MIN_WIDS          (4)
  57
  58 /* Configurable */
  59 #define ECORE_PF_DEMS_SIZE      (4)
  60
  61 /* cau states */
  62 enum ecore_coalescing_mode {
  63         ECORE_COAL_MODE_DISABLE,
  64         ECORE_COAL_MODE_ENABLE
  65 };
  66
  67 enum ecore_nvm_cmd {
  68         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  69         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  70         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  71         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  72         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  73         ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
  74         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  75         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  76         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  77         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  78         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  79         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  80 };
  81
  82 #ifndef LINUX_REMOVE
  83 #if !defined(CONFIG_ECORE_L2)
  84 #define CONFIG_ECORE_L2
  85 #define CONFIG_ECORE_SRIOV
  86 #endif
  87 #endif
  88
  89 /* helpers */
  90 #ifndef __EXTRACT__LINUX__
  91 #define MASK_FIELD(_name, _value)                                       \
  92                 ((_value) &= (_name##_MASK))
  93
  94 #define FIELD_VALUE(_name, _value)                                      \
  95                 ((_value & _name##_MASK) << _name##_SHIFT)
  96
  97 #define SET_FIELD(value, name, flag)                                    \
  98 do {                                                                    \
  99         (value) &= ~(name##_MASK << name##_SHIFT);                      \
 100         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
 101 } while (0)
 102
 103 #define GET_FIELD(value, name)                                          \
 104         (((value) >> (name##_SHIFT)) & name##_MASK)
 105
 106 #define GET_MFW_FIELD(name, field)                              \
 107         (((name) & (field ## _MASK)) >> (field ## _OFFSET))
 108
 109 #define SET_MFW_FIELD(name, field, value)                               \
 110 do {                                                                    \
 111         (name) &= ~((field ## _MASK));          \
 112         (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
 113 } while (0)
 114 #endif
 115
 116 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 117 {
 118         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 119                       (cid * ECORE_PF_DEMS_SIZE);
 120
 121         return db_addr;
 122 }
 123
 124 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 125 {
 126         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 127                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 128
 129         return db_addr;
 130 }
 131
 132 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 133         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 134          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 135
 136 #ifndef LINUX_REMOVE
 137 #ifndef U64_HI
 138 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 139 #endif
 140
 141 #ifndef U64_LO
 142 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 143 #endif
 144 #endif
 145
 146 #ifndef __EXTRACT__LINUX__
 147 enum DP_LEVEL {
 148         ECORE_LEVEL_VERBOSE     = 0x0,
 149         ECORE_LEVEL_INFO        = 0x1,
 150         ECORE_LEVEL_NOTICE      = 0x2,
 151         ECORE_LEVEL_ERR         = 0x3,
 152 };
 153
 154 #define ECORE_LOG_LEVEL_SHIFT   (30)
 155 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 156 #define ECORE_LOG_INFO_MASK     (0x40000000)
 157 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 158
 159 enum DP_MODULE {
 160 #ifndef LINUX_REMOVE
 161         ECORE_MSG_DRV           = 0x0001,
 162         ECORE_MSG_PROBE         = 0x0002,
 163         ECORE_MSG_LINK          = 0x0004,
 164         ECORE_MSG_TIMER         = 0x0008,
 165         ECORE_MSG_IFDOWN        = 0x0010,
 166         ECORE_MSG_IFUP          = 0x0020,
 167         ECORE_MSG_RX_ERR        = 0x0040,
 168         ECORE_MSG_TX_ERR        = 0x0080,
 169         ECORE_MSG_TX_QUEUED     = 0x0100,
 170         ECORE_MSG_INTR          = 0x0200,
 171         ECORE_MSG_TX_DONE       = 0x0400,
 172         ECORE_MSG_RX_STATUS     = 0x0800,
 173         ECORE_MSG_PKTDATA       = 0x1000,
 174         ECORE_MSG_HW            = 0x2000,
 175         ECORE_MSG_WOL           = 0x4000,
 176 #endif
 177         ECORE_MSG_SPQ           = 0x10000,
 178         ECORE_MSG_STATS         = 0x20000,
 179         ECORE_MSG_DCB           = 0x40000,
 180         ECORE_MSG_IOV           = 0x80000,
 181         ECORE_MSG_SP            = 0x100000,
 182         ECORE_MSG_STORAGE       = 0x200000,
 183         ECORE_MSG_OOO           = 0x200000,
 184         ECORE_MSG_CXT           = 0x800000,
 185         ECORE_MSG_LL2           = 0x1000000,
 186         ECORE_MSG_ILT           = 0x2000000,
 187         ECORE_MSG_RDMA          = 0x4000000,
 188         ECORE_MSG_DEBUG         = 0x8000000,
 189         /* to be added...up to 0x8000000 */
 190 };
 191 #endif
 192
 193 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 194
 195 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 196         (val == (cond1) ? true1 : \
 197          (val == (cond2) ? true2 : def))
 198
 199 /* forward */
 200 struct ecore_ptt_pool;
 201 struct ecore_spq;
 202 struct ecore_sb_info;
 203 struct ecore_sb_attn_info;
 204 struct ecore_cxt_mngr;
 205 struct ecore_dma_mem;
 206 struct ecore_sb_sp_info;
 207 struct ecore_ll2_info;
 208 struct ecore_l2_info;
 209 struct ecore_igu_info;
 210 struct ecore_mcp_info;
 211 struct ecore_dcbx_info;
 212
 213 struct ecore_rt_data {
 214         u32     *init_val;
 215         bool    *b_valid;
 216 };
 217
 218 enum ecore_tunn_mode {
 219         ECORE_MODE_L2GENEVE_TUNN,
 220         ECORE_MODE_IPGENEVE_TUNN,
 221         ECORE_MODE_L2GRE_TUNN,
 222         ECORE_MODE_IPGRE_TUNN,
 223         ECORE_MODE_VXLAN_TUNN,
 224 };
 225
 226 enum ecore_tunn_clss {
 227         ECORE_TUNN_CLSS_MAC_VLAN,
 228         ECORE_TUNN_CLSS_MAC_VNI,
 229         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 230         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 231         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 232         MAX_ECORE_TUNN_CLSS,
 233 };
 234
 235 struct ecore_tunn_update_type {
 236         bool b_update_mode;
 237         bool b_mode_enabled;
 238         enum ecore_tunn_clss tun_cls;
 239 };
 240
 241 struct ecore_tunn_update_udp_port {
 242         bool b_update_port;
 243         u16 port;
 244 };
 245
 246 struct ecore_tunnel_info {
 247         struct ecore_tunn_update_type vxlan;
 248         struct ecore_tunn_update_type l2_geneve;
 249         struct ecore_tunn_update_type ip_geneve;
 250         struct ecore_tunn_update_type l2_gre;
 251         struct ecore_tunn_update_type ip_gre;
 252
 253         struct ecore_tunn_update_udp_port vxlan_port;
 254         struct ecore_tunn_update_udp_port geneve_port;
 255
 256         bool b_update_rx_cls;
 257         bool b_update_tx_cls;
 258 };
 259
 260 /* The PCI personality is not quite synonymous to protocol ID:
 261  * 1. All personalities need CORE connections
 262  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 263  */
 264 enum ecore_pci_personality {
 265         ECORE_PCI_ETH,
 266         ECORE_PCI_FCOE,
 267         ECORE_PCI_ISCSI,
 268         ECORE_PCI_ETH_ROCE,
 269         ECORE_PCI_ETH_IWARP,
 270         ECORE_PCI_ETH_RDMA,
 271         ECORE_PCI_DEFAULT /* default in shmem */
 272 };
 273
 274 /* All VFs are symmetric, all counters are PF + all VFs */
 275 struct ecore_qm_iids {
 276         u32 cids;
 277         u32 vf_cids;
 278         u32 tids;
 279 };
 280
 281 #define MAX_PF_PER_PORT 8
 282
 283 /* HW / FW resources, output of features supported below, most information
 284  * is received from MFW.
 285  */
 286 enum ecore_resources {
 287         ECORE_L2_QUEUE,
 288         ECORE_VPORT,
 289         ECORE_RSS_ENG,
 290         ECORE_PQ,
 291         ECORE_RL,
 292         ECORE_MAC,
 293         ECORE_VLAN,
 294         ECORE_RDMA_CNQ_RAM,
 295         ECORE_ILT,
 296         ECORE_LL2_QUEUE,
 297         ECORE_CMDQS_CQS,
 298         ECORE_RDMA_STATS_QUEUE,
 299         ECORE_BDQ,
 300
 301         /* This is needed only internally for matching against the IGU.
 302          * In case of legacy MFW, would be set to `0'.
 303          */
 304         ECORE_SB,
 305
 306         ECORE_MAX_RESC,
 307 };
 308
 309 /* Features that require resources, given as input to the resource management
 310  * algorithm, the output are the resources above
 311  */
 312 enum ecore_feature {
 313         ECORE_PF_L2_QUE,
 314         ECORE_PF_TC,
 315         ECORE_VF,
 316         ECORE_EXTRA_VF_QUE,
 317         ECORE_VMQ,
 318         ECORE_RDMA_CNQ,
 319         ECORE_ISCSI_CQ,
 320         ECORE_FCOE_CQ,
 321         ECORE_VF_L2_QUE,
 322         ECORE_MAX_FEATURES,
 323 };
 324
 325 enum ecore_port_mode {
 326         ECORE_PORT_MODE_DE_2X40G,
 327         ECORE_PORT_MODE_DE_2X50G,
 328         ECORE_PORT_MODE_DE_1X100G,
 329         ECORE_PORT_MODE_DE_4X10G_F,
 330         ECORE_PORT_MODE_DE_4X10G_E,
 331         ECORE_PORT_MODE_DE_4X20G,
 332         ECORE_PORT_MODE_DE_1X40G,
 333         ECORE_PORT_MODE_DE_2X25G,
 334         ECORE_PORT_MODE_DE_1X25G,
 335         ECORE_PORT_MODE_DE_4X25G,
 336         ECORE_PORT_MODE_DE_2X10G,
 337 };
 338
 339 enum ecore_dev_cap {
 340         ECORE_DEV_CAP_ETH,
 341         ECORE_DEV_CAP_FCOE,
 342         ECORE_DEV_CAP_ISCSI,
 343         ECORE_DEV_CAP_ROCE,
 344         ECORE_DEV_CAP_IWARP
 345 };
 346
 347 #ifndef __EXTRACT__LINUX__
 348 enum ecore_hw_err_type {
 349         ECORE_HW_ERR_FAN_FAIL,
 350         ECORE_HW_ERR_MFW_RESP_FAIL,
 351         ECORE_HW_ERR_HW_ATTN,
 352         ECORE_HW_ERR_DMAE_FAIL,
 353         ECORE_HW_ERR_RAMROD_FAIL,
 354         ECORE_HW_ERR_FW_ASSERT,
 355 };
 356 #endif
 357
 358 enum ecore_db_rec_exec {
 359         DB_REC_DRY_RUN,
 360         DB_REC_REAL_DEAL,
 361         DB_REC_ONCE,
 362 };
 363
 364 struct ecore_hw_info {
 365         /* PCI personality */
 366         enum ecore_pci_personality personality;
 367 #define ECORE_IS_RDMA_PERSONALITY(dev) \
 368         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 369          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 370          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 371 #define ECORE_IS_ROCE_PERSONALITY(dev) \
 372         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 373          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 374 #define ECORE_IS_IWARP_PERSONALITY(dev) \
 375         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 376          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 377 #define ECORE_IS_L2_PERSONALITY(dev) \
 378         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 379          ECORE_IS_RDMA_PERSONALITY(dev))
 380 #define ECORE_IS_FCOE_PERSONALITY(dev) \
 381         ((dev)->hw_info.personality == ECORE_PCI_FCOE)
 382 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
 383         ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
 384
 385         /* Resource Allocation scheme results */
 386         u32 resc_start[ECORE_MAX_RESC];
 387         u32 resc_num[ECORE_MAX_RESC];
 388         u32 feat_num[ECORE_MAX_FEATURES];
 389
 390         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 391         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 392         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 393                                          RESC_NUM(_p_hwfn, resc))
 394         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 395
 396         /* Amount of traffic classes HW supports */
 397         u8 num_hw_tc;
 398
 399 /* Amount of TCs which should be active according to DCBx or upper layer driver
 400  * configuration
 401  */
 402
 403         u8 num_active_tc;
 404
 405         /* The traffic class used by PF for it's offloaded protocol */
 406         u8 offload_tc;
 407
 408         u32 concrete_fid;
 409         u16 opaque_fid;
 410         u16 ovlan;
 411         u32 part_num[4];
 412
 413         unsigned char hw_mac_addr[ETH_ALEN];
 414         u64 node_wwn; /* For FCoE only */
 415         u64 port_wwn; /* For FCoE only */
 416
 417         u16 num_iscsi_conns;
 418         u16 num_fcoe_conns;
 419
 420         struct ecore_igu_info *p_igu_info;
 421         /* Sriov */
 422         u8 max_chains_per_vf;
 423
 424         u32 port_mode;
 425         u32     hw_mode;
 426         unsigned long device_capabilities;
 427
 428         /* Default DCBX mode */
 429         u8 dcbx_mode;
 430
 431         u16 mtu;
 432 };
 433
 434 /* maximun size of read/write commands (HW limit) */
 435 #define DMAE_MAX_RW_SIZE        0x2000
 436
 437 struct ecore_dmae_info {
 438         /* Spinlock for synchronizing access to functions */
 439         osal_spinlock_t lock;
 440
 441         bool b_mem_ready;
 442
 443         u8 channel;
 444
 445         dma_addr_t completion_word_phys_addr;
 446
 447         /* The memory location where the DMAE writes the completion
 448          * value when an operation is finished on this context.
 449          */
 450         u32 *p_completion_word;
 451
 452         dma_addr_t intermediate_buffer_phys_addr;
 453
 454         /* An intermediate buffer for DMAE operations that use virtual
 455          * addresses - data is DMA'd to/from this buffer and then
 456          * memcpy'd to/from the virtual address
 457          */
 458         u32 *p_intermediate_buffer;
 459
 460         dma_addr_t dmae_cmd_phys_addr;
 461         struct dmae_cmd *p_dmae_cmd;
 462 };
 463
 464 struct ecore_wfq_data {
 465         u32 default_min_speed; /* When wfq feature is not configured */
 466         u32 min_speed; /* when feature is configured for any 1 vport */
 467         bool configured;
 468 };
 469
 470 struct ecore_qm_info {
 471         struct init_qm_pq_params    *qm_pq_params;
 472         struct init_qm_vport_params *qm_vport_params;
 473         struct init_qm_port_params  *qm_port_params;
 474         u16                     start_pq;
 475         u8                      start_vport;
 476         u16                     pure_lb_pq;
 477         u16                     offload_pq;
 478         u16                     pure_ack_pq;
 479         u16                     ooo_pq;
 480         u16                     first_vf_pq;
 481         u16                     first_mcos_pq;
 482         u16                     first_rl_pq;
 483         u16                     num_pqs;
 484         u16                     num_vf_pqs;
 485         u8                      num_vports;
 486         u8                      max_phys_tcs_per_port;
 487         u8                      ooo_tc;
 488         bool                    pf_rl_en;
 489         bool                    pf_wfq_en;
 490         bool                    vport_rl_en;
 491         bool                    vport_wfq_en;
 492         u8                      pf_wfq;
 493         u32                     pf_rl;
 494         struct ecore_wfq_data   *wfq_data;
 495         u8                      num_pf_rls;
 496 };
 497
 498 struct ecore_db_recovery_info {
 499         osal_list_t list;
 500         osal_spinlock_t lock;
 501         u32 db_recovery_counter;
 502 };
 503
 504 struct storm_stats {
 505         u32 address;
 506         u32 len;
 507 };
 508
 509 struct ecore_fw_data {
 510 #ifdef CONFIG_ECORE_BINARY_FW
 511         struct fw_ver_info *fw_ver_info;
 512 #endif
 513         const u8 *modes_tree_buf;
 514         union init_op *init_ops;
 515         const u32 *arr_data;
 516         u32 init_ops_size;
 517 };
 518
 519 enum ecore_mf_mode_bit {
 520         /* Supports PF-classification based on tag */
 521         ECORE_MF_OVLAN_CLSS,
 522
 523         /* Supports PF-classification based on MAC */
 524         ECORE_MF_LLH_MAC_CLSS,
 525
 526         /* Supports PF-classification based on protocol type */
 527         ECORE_MF_LLH_PROTO_CLSS,
 528
 529         /* Requires a default PF to be set */
 530         ECORE_MF_NEED_DEF_PF,
 531
 532         /* Allow LL2 to multicast/broadcast */
 533         ECORE_MF_LL2_NON_UNICAST,
 534
 535         /* Allow Cross-PF [& child VFs] Tx-switching */
 536         ECORE_MF_INTER_PF_SWITCH,
 537
 538         /* TODO - if we ever re-utilize any of this logic, we can rename */
 539         ECORE_MF_UFP_SPECIFIC,
 540
 541         ECORE_MF_DISABLE_ARFS,
 542
 543         /* Use vlan for steering */
 544         ECORE_MF_8021Q_TAGGING,
 545
 546         /* Use stag for steering */
 547         ECORE_MF_8021AD_TAGGING,
 548 };
 549
 550 enum ecore_ufp_mode {
 551         ECORE_UFP_MODE_ETS,
 552         ECORE_UFP_MODE_VNIC_BW,
 553 };
 554
 555 enum ecore_ufp_pri_type {
 556         ECORE_UFP_PRI_OS,
 557         ECORE_UFP_PRI_VNIC
 558 };
 559
 560 struct ecore_ufp_info {
 561         enum ecore_ufp_pri_type pri_type;
 562         enum ecore_ufp_mode mode;
 563         u8 tc;
 564 };
 565
 566 enum BAR_ID {
 567         BAR_ID_0,       /* used for GRC */
 568         BAR_ID_1        /* Used for doorbells */
 569 };
 570
 571 struct ecore_hwfn {
 572         struct ecore_dev                *p_dev;
 573         u8                              my_id;          /* ID inside the PF */
 574 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 575         u8                              rel_pf_id;      /* Relative to engine*/
 576         u8                              abs_pf_id;
 577 #define ECORE_PATH_ID(_p_hwfn) \
 578         (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
 579         u8                              port_id;
 580         bool                            b_active;
 581
 582         u32                             dp_module;
 583         u8                              dp_level;
 584         char                            name[NAME_SIZE];
 585         void                            *dp_ctx;
 586
 587         bool                            first_on_engine;
 588         bool                            hw_init_done;
 589
 590         u8                              num_funcs_on_engine;
 591         u8                              enabled_func_idx;
 592
 593         /* BAR access */
 594         void OSAL_IOMEM                 *regview;
 595         void OSAL_IOMEM                 *doorbells;
 596         u64                             db_phys_addr;
 597         unsigned long                   db_size;
 598
 599         /* PTT pool */
 600         struct ecore_ptt_pool           *p_ptt_pool;
 601
 602         /* HW info */
 603         struct ecore_hw_info            hw_info;
 604
 605         /* rt_array (for init-tool) */
 606         struct ecore_rt_data            rt_data;
 607
 608         /* SPQ */
 609         struct ecore_spq                *p_spq;
 610
 611         /* EQ */
 612         struct ecore_eq                 *p_eq;
 613
 614         /* Consolidate Q*/
 615         struct ecore_consq              *p_consq;
 616
 617         /* Slow-Path definitions */
 618         osal_dpc_t                      sp_dpc;
 619         bool                            b_sp_dpc_enabled;
 620
 621         struct ecore_ptt                *p_main_ptt;
 622         struct ecore_ptt                *p_dpc_ptt;
 623
 624         struct ecore_sb_sp_info         *p_sp_sb;
 625         struct ecore_sb_attn_info       *p_sb_attn;
 626
 627         /* Protocol related */
 628         bool                            using_ll2;
 629         struct ecore_ll2_info           *p_ll2_info;
 630         struct ecore_ooo_info           *p_ooo_info;
 631         struct ecore_iscsi_info         *p_iscsi_info;
 632         struct ecore_fcoe_info          *p_fcoe_info;
 633         struct ecore_rdma_info          *p_rdma_info;
 634         struct ecore_pf_params          pf_params;
 635
 636         bool                            b_rdma_enabled_in_prs;
 637         u32                             rdma_prs_search_reg;
 638
 639         struct ecore_cxt_mngr           *p_cxt_mngr;
 640
 641         /* Flag indicating whether interrupts are enabled or not*/
 642         bool                            b_int_enabled;
 643         bool                            b_int_requested;
 644
 645         /* True if the driver requests for the link */
 646         bool                            b_drv_link_init;
 647
 648         struct ecore_vf_iov             *vf_iov_info;
 649         struct ecore_pf_iov             *pf_iov_info;
 650         struct ecore_mcp_info           *mcp_info;
 651         struct ecore_dcbx_info          *p_dcbx_info;
 652         struct ecore_ufp_info           ufp_info;
 653
 654         struct ecore_dmae_info          dmae_info;
 655
 656         /* QM init */
 657         struct ecore_qm_info            qm_info;
 658
 659 #ifdef CONFIG_ECORE_ZIPPED_FW
 660         /* Buffer for unzipping firmware data */
 661         void *unzip_buf;
 662 #endif
 663
 664         struct dbg_tools_data           dbg_info;
 665
 666         struct z_stream_s               *stream;
 667
 668         /* PWM region specific data */
 669         u32                             dpi_size;
 670         u32                             dpi_count;
 671         u32                             dpi_start_offset; /* this is used to
 672                                                            * calculate th
 673                                                            * doorbell address
 674                                                            */
 675
 676         /* If one of the following is set then EDPM shouldn't be used */
 677         u8                              dcbx_no_edpm;
 678         u8                              db_bar_no_edpm;
 679
 680         /* L2-related */
 681         struct ecore_l2_info            *p_l2_info;
 682
 683         /* Mechanism for recovering from doorbell drop */
 684         struct ecore_db_recovery_info   db_recovery_info;
 685
 686         /* Enable/disable pacing, if request to enable then
 687          * IOV and mcos configuration will be skipped.
 688          * this actually reflects the value requested in
 689          * struct ecore_hw_prepare_params by ecore client.
 690          */
 691         bool b_en_pacing;
 692
 693         /* @DPDK */
 694         struct ecore_ptt                *p_arfs_ptt;
 695 };
 696
 697 enum ecore_mf_mode {
 698         ECORE_MF_DEFAULT,
 699         ECORE_MF_OVLAN,
 700         ECORE_MF_NPAR,
 701         ECORE_MF_UFP,
 702 };
 703
 704 /* @DPDK */
 705 struct ecore_dbg_feature {
 706         u8                              *dump_buf;
 707         u32                             buf_size;
 708         u32                             dumped_dwords;
 709 };
 710
 711 enum qed_dbg_features {
 712         DBG_FEATURE_BUS,
 713         DBG_FEATURE_GRC,
 714         DBG_FEATURE_IDLE_CHK,
 715         DBG_FEATURE_MCP_TRACE,
 716         DBG_FEATURE_REG_FIFO,
 717         DBG_FEATURE_PROTECTION_OVERRIDE,
 718         DBG_FEATURE_NUM
 719 };
 720
 721 enum ecore_dev_type {
 722         ECORE_DEV_TYPE_BB,
 723         ECORE_DEV_TYPE_AH,
 724 };
 725
 726 struct ecore_dev {
 727         u32                             dp_module;
 728         u8                              dp_level;
 729         char                            name[NAME_SIZE];
 730         void                            *dp_ctx;
 731
 732         enum ecore_dev_type             type;
 733 /* Translate type/revision combo into the proper conditions */
 734 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 735 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 736 #ifndef ASIC_ONLY
 737 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 738                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 739 #else
 740 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 741 #endif
 742 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 743 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 744
 745         u16 vendor_id;
 746         u16 device_id;
 747 #define ECORE_DEV_ID_MASK       0xff00
 748 #define ECORE_DEV_ID_MASK_BB    0x1600
 749 #define ECORE_DEV_ID_MASK_AH    0x8000
 750
 751         u16                             chip_num;
 752 #define CHIP_NUM_MASK                   0xffff
 753 #define CHIP_NUM_SHIFT                  0
 754
 755         u8                              chip_rev;
 756 #define CHIP_REV_MASK                   0xf
 757 #define CHIP_REV_SHIFT                  0
 758 #ifndef ASIC_ONLY
 759 #define CHIP_REV_IS_TEDIBEAR(_p_dev)    ((_p_dev)->chip_rev == 0x5)
 760 #define CHIP_REV_IS_EMUL_A0(_p_dev)     ((_p_dev)->chip_rev == 0xe)
 761 #define CHIP_REV_IS_EMUL_B0(_p_dev)     ((_p_dev)->chip_rev == 0xc)
 762 #define CHIP_REV_IS_EMUL(_p_dev) \
 763         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
 764 #define CHIP_REV_IS_FPGA_A0(_p_dev)     ((_p_dev)->chip_rev == 0xf)
 765 #define CHIP_REV_IS_FPGA_B0(_p_dev)     ((_p_dev)->chip_rev == 0xd)
 766 #define CHIP_REV_IS_FPGA(_p_dev) \
 767         (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
 768 #define CHIP_REV_IS_SLOW(_p_dev) \
 769         (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 770 #define CHIP_REV_IS_A0(_p_dev) \
 771         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
 772          (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
 773 #define CHIP_REV_IS_B0(_p_dev) \
 774         (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
 775          ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
 776 #define CHIP_REV_IS_ASIC(_p_dev)        !CHIP_REV_IS_SLOW(_p_dev)
 777 #else
 778 #define CHIP_REV_IS_A0(_p_dev) \
 779         (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
 780 #define CHIP_REV_IS_B0(_p_dev) \
 781         ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
 782 #endif
 783
 784         u8                              chip_metal;
 785 #define CHIP_METAL_MASK                 0xff
 786 #define CHIP_METAL_SHIFT                0
 787
 788         u8                              chip_bond_id;
 789 #define CHIP_BOND_ID_MASK               0xff
 790 #define CHIP_BOND_ID_SHIFT              0
 791
 792         u8                              num_engines;
 793         u8                              num_ports;
 794         u8                              num_ports_in_engine;
 795         u8                              num_funcs_in_port;
 796
 797         u8                              path_id;
 798
 799         unsigned long                   mf_bits;
 800         enum ecore_mf_mode              mf_mode;
 801 #define IS_MF_DEFAULT(_p_hwfn)  \
 802         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 803 #define IS_MF_SI(_p_hwfn)       \
 804         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 805 #define IS_MF_SD(_p_hwfn)       \
 806         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 807
 808         int                             pcie_width;
 809         int                             pcie_speed;
 810
 811         /* Add MF related configuration */
 812         u8                              mcp_rev;
 813         u8                              boot_mode;
 814
 815         u8                              wol;
 816
 817         u32                             int_mode;
 818         enum ecore_coalescing_mode      int_coalescing_mode;
 819         u16                             rx_coalesce_usecs;
 820         u16                             tx_coalesce_usecs;
 821
 822         /* Start Bar offset of first hwfn */
 823         void OSAL_IOMEM                 *regview;
 824         void OSAL_IOMEM                 *doorbells;
 825         u64                             db_phys_addr;
 826         unsigned long                   db_size;
 827
 828         /* PCI */
 829         u8                              cache_shift;
 830
 831         /* Init */
 832         const struct iro                *iro_arr;
 833         #define IRO (p_hwfn->p_dev->iro_arr)
 834
 835         /* HW functions */
 836         u8                              num_hwfns;
 837         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 838 #define ECORE_IS_CMT(dev)               ((dev)->num_hwfns > 1)
 839
 840         /* SRIOV */
 841         struct ecore_hw_sriov_info      *p_iov_info;
 842 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 843         struct ecore_tunnel_info        tunnel;
 844         bool                            b_is_vf;
 845         bool                            b_dont_override_vf_msix;
 846
 847         u32                             drv_type;
 848
 849         u32                             rdma_max_sge;
 850         u32                             rdma_max_inline;
 851         u32                             rdma_max_srq_sge;
 852
 853         struct ecore_eth_stats          *reset_stats;
 854         struct ecore_fw_data            *fw_data;
 855
 856         u32                             mcp_nvm_resp;
 857
 858         /* Recovery */
 859         bool                            recov_in_prog;
 860
 861 /* Indicates whether should prevent attentions from being reasserted */
 862
 863         bool                            attn_clr_en;
 864
 865         /* Indicates whether allowing the MFW to collect a crash dump */
 866         bool                            allow_mdump;
 867
 868         /* Indicates if the reg_fifo is checked after any register access */
 869         bool                            chk_reg_fifo;
 870
 871 #ifndef ASIC_ONLY
 872         bool                            b_is_emul_full;
 873 #endif
 874
 875 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 876         void                            *firmware;
 877         u64                             fw_len;
 878 #endif
 879
 880         /* @DPDK */
 881         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 882         u8                              engine_for_debug;
 883 };
 884
 885 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 886                                                   : MAX_NUM_VFS_K2)
 887 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 888                                                   : MAX_NUM_L2_QUEUES_K2)
 889 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 890                                                   : MAX_NUM_PORTS_K2)
 891 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 892                                                   : MAX_SB_PER_PATH_K2)
 893 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 894                                                   : MAX_NUM_PFS_K2)
 895
 896 #define CRC8_TABLE_SIZE 256
 897
 898 /**
 899  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 900  *        the concrete value.
 901  *
 902  * @param concrete_fid
 903  *
 904  * @return OSAL_INLINE u8
 905  */
 906 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
 907 {
 908         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 909         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 910         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 911         u8 sw_fid;
 912
 913         if (vf_valid)
 914                 sw_fid = vfid + MAX_NUM_PFS;
 915         else
 916                 sw_fid = pfid;
 917
 918         return sw_fid;
 919 }
 920
 921 #define PKT_LB_TC 9
 922 #define MAX_NUM_VOQS_E4 20
 923
 924 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 925 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 926                                            struct ecore_ptt *p_ptt,
 927                                            u32 min_pf_rate);
 928
 929 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 930 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 931 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 932 int ecore_device_num_engines(struct ecore_dev *p_dev);
 933 int ecore_device_num_ports(struct ecore_dev *p_dev);
 934 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 935                            u8 *mac);
 936
 937 /* Flags for indication of required queues */
 938 #define PQ_FLAGS_RLS    (1 << 0)
 939 #define PQ_FLAGS_MCOS   (1 << 1)
 940 #define PQ_FLAGS_LB     (1 << 2)
 941 #define PQ_FLAGS_OOO    (1 << 3)
 942 #define PQ_FLAGS_ACK    (1 << 4)
 943 #define PQ_FLAGS_OFLD   (1 << 5)
 944 #define PQ_FLAGS_VFS    (1 << 6)
 945 #define PQ_FLAGS_LLT    (1 << 7)
 946
 947 /* physical queue index for cm context intialization */
 948 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 949 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 950 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 951 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
 952
 953 /* qm vport for rate limit configuration */
 954 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
 955
 956 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 957
 958 /* doorbell recovery mechanism */
 959 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
 960 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 961                                enum ecore_db_rec_exec);
 962
 963 /* amount of resources used in qm init */
 964 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 965 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 966 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 967 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 968 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 969
 970 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 971
 972 #endif /* __ECORE_H */