drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "common_hsi.h"
  12 #include "ecore_hsi_common.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_status.h"
  16 #include "ecore.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_init_fw_funcs.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_hw.h"
  21 #include "ecore_dev_api.h"
  22 #include "ecore_sriov.h"
  23 #include "ecore_mcp.h"
  24
  25 /* Max number of connection types in HW (DQ/CDU etc.) */
  26 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  27 #define NUM_TASK_TYPES          2
  28 #define NUM_TASK_PF_SEGMENTS    4
  29 #define NUM_TASK_VF_SEGMENTS    1
  30
  31 /* Doorbell-Queue constants */
  32 #define DQ_RANGE_SHIFT  4
  33 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  34
  35 /* Searcher constants */
  36 #define SRC_MIN_NUM_ELEMS 256
  37
  38 /* Timers constants */
  39 #define TM_SHIFT        7
  40 #define TM_ALIGN        (1 << TM_SHIFT)
  41 #define TM_ELEM_SIZE    4
  42
  43 /* ILT constants */
  44 /* If for some reason, HW P size is modified to be less than 32K,
  45  * special handling needs to be made for CDU initialization
  46  */
  47 #define ILT_DEFAULT_HW_P_SIZE   3
  48
  49 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  50 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  51
  52 /* ILT entry structure */
  53 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  54 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  55 #define ILT_ENTRY_VALID_MASK            0x1ULL
  56 #define ILT_ENTRY_VALID_SHIFT           52
  57 #define ILT_ENTRY_IN_REGS               2
  58 #define ILT_REG_SIZE_IN_BYTES           4
  59
  60 /* connection context union */
  61 union conn_context {
  62         struct e4_core_conn_context core_ctx;
  63         struct e4_eth_conn_context eth_ctx;
  64 };
  65
  66 /* TYPE-0 task context - iSCSI, FCOE */
  67 union type0_task_context {
  68 };
  69
  70 /* TYPE-1 task context - ROCE */
  71 union type1_task_context {
  72 };
  73
  74 struct src_ent {
  75         u8 opaque[56];
  76         u64 next;
  77 };
  78
  79 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  80 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  81
  82 #define CONN_CXT_SIZE(p_hwfn) \
  83         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  84
  85 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  86
  87 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  88         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  89
  90 /* Alignment is inherent to the type1_task_context structure */
  91 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  92
  93 /* PF per protocl configuration object */
  94 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  95 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  96
  97 struct ecore_tid_seg {
  98         u32 count;
  99         u8 type;
 100         bool has_fl_mem;
 101 };
 102
 103 struct ecore_conn_type_cfg {
 104         u32 cid_count;
 105         u32 cids_per_vf;
 106         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 107 };
 108
 109 /* ILT Client configuration,
 110  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 111  * 1 - for connection context (CDUC) and for each task context we need two
 112  * values, for regular task context and for force load memory
 113  */
 114 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 115 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 116 #define CDUC_BLK                (0)
 117 #define SRQ_BLK                 (0)
 118 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 119 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 120
 121 enum ilt_clients {
 122         ILT_CLI_CDUC,
 123         ILT_CLI_CDUT,
 124         ILT_CLI_QM,
 125         ILT_CLI_TM,
 126         ILT_CLI_SRC,
 127         ILT_CLI_TSDM,
 128         ILT_CLI_MAX
 129 };
 130
 131 struct ilt_cfg_pair {
 132         u32 reg;
 133         u32 val;
 134 };
 135
 136 struct ecore_ilt_cli_blk {
 137         u32 total_size;         /* 0 means not active */
 138         u32 real_size_in_page;
 139         u32 start_line;
 140         u32 dynamic_line_cnt;
 141 };
 142
 143 struct ecore_ilt_client_cfg {
 144         bool active;
 145
 146         /* ILT boundaries */
 147         struct ilt_cfg_pair first;
 148         struct ilt_cfg_pair last;
 149         struct ilt_cfg_pair p_size;
 150
 151         /* ILT client blocks for PF */
 152         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 153         u32 pf_total_lines;
 154
 155         /* ILT client blocks for VFs */
 156         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 157         u32 vf_total_lines;
 158 };
 159
 160 /* Per Path -
 161  *      ILT shadow table
 162  *      Protocol acquired CID lists
 163  *      PF start line in ILT
 164  */
 165 struct ecore_dma_mem {
 166         dma_addr_t p_phys;
 167         void *p_virt;
 168         osal_size_t size;
 169 };
 170
 171 #define MAP_WORD_SIZE           sizeof(unsigned long)
 172 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 173
 174 struct ecore_cid_acquired_map {
 175         u32 start_cid;
 176         u32 max_count;
 177         unsigned long *cid_map;
 178 };
 179
 180 struct ecore_cxt_mngr {
 181         /* Per protocl configuration */
 182         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 183
 184         /* computed ILT structure */
 185         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 186
 187         /* Task type sizes */
 188         u32 task_type_size[NUM_TASK_TYPES];
 189
 190         /* total number of VFs for this hwfn -
 191          * ALL VFs are symmetric in terms of HW resources
 192          */
 193         u32 vf_count;
 194
 195         /* Acquired CIDs */
 196         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 197         /* TBD - do we want this allocated to reserve space? */
 198         struct ecore_cid_acquired_map
 199                 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
 200
 201         /* ILT  shadow table */
 202         struct ecore_dma_mem *ilt_shadow;
 203         u32 pf_start_line;
 204
 205         /* Mutex for a dynamic ILT allocation */
 206         osal_mutex_t mutex;
 207
 208         /* SRC T2 */
 209         struct ecore_dma_mem *t2;
 210         u32 t2_num_pages;
 211         u64 first_free;
 212         u64 last_free;
 213
 214         /* The infrastructure originally was very generic and context/task
 215          * oriented - per connection-type we would set how many of those
 216          * are needed, and later when determining how much memory we're
 217          * needing for a given block we'd iterate over all the relevant
 218          * connection-types.
 219          * But since then we've had some additional resources, some of which
 220          * require memory which is indepent of the general context/task
 221          * scheme. We add those here explicitly per-feature.
 222          */
 223
 224         /* total number of SRQ's for this hwfn */
 225         u32                             srq_count;
 226
 227         /* Maximal number of L2 steering filters */
 228         u32                             arfs_count;
 229
 230         /* TODO - VF arfs filters ? */
 231 };
 232
 233 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 234 {
 235         return type == PROTOCOLID_TOE;
 236 }
 237
 238 static bool tm_tid_proto(enum protocol_type type)
 239 {
 240         return type == PROTOCOLID_FCOE;
 241 }
 242
 243 /* counts the iids for the CDU/CDUC ILT client configuration */
 244 struct ecore_cdu_iids {
 245         u32 pf_cids;
 246         u32 per_vf_cids;
 247 };
 248
 249 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 250                                struct ecore_cdu_iids *iids)
 251 {
 252         u32 type;
 253
 254         for (type = 0; type < MAX_CONN_TYPES; type++) {
 255                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 256                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 257         }
 258 }
 259
 260 /* counts the iids for the Searcher block configuration */
 261 struct ecore_src_iids {
 262         u32 pf_cids;
 263         u32 per_vf_cids;
 264 };
 265
 266 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 267                                struct ecore_src_iids *iids)
 268 {
 269         u32 i;
 270
 271         for (i = 0; i < MAX_CONN_TYPES; i++) {
 272                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 273                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 274         }
 275
 276         /* Add L2 filtering filters in addition */
 277         iids->pf_cids += p_mngr->arfs_count;
 278 }
 279
 280 /* counts the iids for the Timers block configuration */
 281 struct ecore_tm_iids {
 282         u32 pf_cids;
 283         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 284         u32 pf_tids_total;
 285         u32 per_vf_cids;
 286         u32 per_vf_tids;
 287 };
 288
 289 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 290                               struct ecore_tm_iids *iids)
 291 {
 292         bool tm_vf_required = false;
 293         bool tm_required = false;
 294         u32 i, j;
 295
 296         for (i = 0; i < MAX_CONN_TYPES; i++) {
 297                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 298
 299                 if (tm_cid_proto(i) || tm_required) {
 300                         if (p_cfg->cid_count)
 301                                 tm_required = true;
 302
 303                         iids->pf_cids += p_cfg->cid_count;
 304                 }
 305
 306                 if (tm_cid_proto(i) || tm_vf_required) {
 307                         if (p_cfg->cids_per_vf)
 308                                 tm_vf_required = true;
 309
 310                 }
 311
 312                 if (tm_tid_proto(i)) {
 313                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 314
 315                         /* for each segment there is at most one
 316                          * protocol for which count is not 0.
 317                          */
 318                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 319                                 iids->pf_tids[j] += segs[j].count;
 320
 321                         /* The last array elelment is for the VFs. As for PF
 322                          * segments there can be only one protocol for
 323                          * which this value is not 0.
 324                          */
 325                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 326                 }
 327         }
 328
 329         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 330         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 331         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 332
 333         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 334                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 335                 iids->pf_tids_total += iids->pf_tids[j];
 336         }
 337 }
 338
 339 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
 340                               struct ecore_qm_iids *iids)
 341 {
 342         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 343         struct ecore_tid_seg *segs;
 344         u32 vf_cids = 0, type, j;
 345         u32 vf_tids = 0;
 346
 347         for (type = 0; type < MAX_CONN_TYPES; type++) {
 348                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 349                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 350
 351                 segs = p_mngr->conn_cfg[type].tid_seg;
 352                 /* for each segment there is at most one
 353                  * protocol for which count is not 0.
 354                  */
 355                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 356                         iids->tids += segs[j].count;
 357
 358                 /* The last array elelment is for the VFs. As for PF
 359                  * segments there can be only one protocol for
 360                  * which this value is not 0.
 361                  */
 362                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 363         }
 364
 365         iids->vf_cids += vf_cids * p_mngr->vf_count;
 366         iids->tids += vf_tids * p_mngr->vf_count;
 367
 368         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 369                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 370                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 371 }
 372
 373 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 374                                                     u32 seg)
 375 {
 376         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 377         u32 i;
 378
 379         /* Find the protocol with tid count > 0 for this segment.
 380          * Note: there can only be one and this is already validated.
 381          */
 382         for (i = 0; i < MAX_CONN_TYPES; i++) {
 383                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 384                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 385         }
 386         return OSAL_NULL;
 387 }
 388
 389 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
 390 {
 391         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 392
 393         p_mgr->srq_count = num_srqs;
 394 }
 395
 396 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
 397 {
 398         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 399
 400         return p_mgr->srq_count;
 401 }
 402
 403 /* set the iids (cid/tid) count per protocol */
 404 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 405                                    enum protocol_type type,
 406                                    u32 cid_count, u32 vf_cid_cnt)
 407 {
 408         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 409         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 410
 411         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 412         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 413 }
 414
 415 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 416                                   enum protocol_type type, u32 *vf_cid)
 417 {
 418         if (vf_cid)
 419                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 420
 421         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 422 }
 423
 424 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 425                                   enum protocol_type type)
 426 {
 427         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 428 }
 429
 430 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 431                                          enum protocol_type type)
 432 {
 433         u32 cnt = 0;
 434         int i;
 435
 436         for (i = 0; i < TASK_SEGMENTS; i++)
 437                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 438
 439         return cnt;
 440 }
 441
 442 static OSAL_INLINE void
 443 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 444                               enum protocol_type proto,
 445                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 446 {
 447         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 448         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 449
 450         p_seg->count = count;
 451         p_seg->has_fl_mem = has_fl;
 452         p_seg->type = seg_type;
 453 }
 454
 455 /* the *p_line parameter must be either 0 for the first invocation or the
 456  * value returned in the previous invocation.
 457  */
 458 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 459                                    struct ecore_ilt_cli_blk *p_blk,
 460                                    u32 start_line,
 461                                    u32 total_size, u32 elem_size)
 462 {
 463         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 464
 465         /* verify that it's called once for each block */
 466         if (p_blk->total_size)
 467                 return;
 468
 469         p_blk->total_size = total_size;
 470         p_blk->real_size_in_page = 0;
 471         if (elem_size)
 472                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 473         p_blk->start_line = start_line;
 474 }
 475
 476 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 477                                    struct ecore_ilt_client_cfg *p_cli,
 478                                    struct ecore_ilt_cli_blk *p_blk,
 479                                    u32 *p_line, enum ilt_clients client_id)
 480 {
 481         if (!p_blk->total_size)
 482                 return;
 483
 484         if (!p_cli->active)
 485                 p_cli->first.val = *p_line;
 486
 487         p_cli->active = true;
 488         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 489         p_cli->last.val = *p_line - 1;
 490
 491         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 492                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 493                    " [Real %08x] Start line %d\n",
 494                    client_id, p_cli->first.val, p_cli->last.val,
 495                    p_blk->total_size, p_blk->real_size_in_page,
 496                    p_blk->start_line);
 497 }
 498
 499 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 500                                           enum ilt_clients ilt_client)
 501 {
 502         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 503         struct ecore_ilt_client_cfg *p_cli;
 504         u32 lines_to_skip = 0;
 505         u32 cxts_per_p;
 506
 507         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 508
 509         if (ilt_client == ILT_CLI_CDUC) {
 510                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 511
 512                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 513                     (u32)CONN_CXT_SIZE(p_hwfn);
 514
 515                 lines_to_skip = cid_count / cxts_per_p;
 516         }
 517
 518         return lines_to_skip;
 519 }
 520
 521 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 522 {
 523         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 524         u32 curr_line, total, i, task_size, line;
 525         struct ecore_ilt_client_cfg *p_cli;
 526         struct ecore_ilt_cli_blk *p_blk;
 527         struct ecore_cdu_iids cdu_iids;
 528         struct ecore_src_iids src_iids;
 529         struct ecore_qm_iids qm_iids;
 530         struct ecore_tm_iids tm_iids;
 531         struct ecore_tid_seg *p_seg;
 532
 533         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 534         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 535         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 536         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 537
 538         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 539
 540         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 541                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 542                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 543
 544         /* CDUC */
 545         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 546
 547         curr_line = p_mngr->pf_start_line;
 548
 549         /* CDUC PF */
 550         p_cli->pf_total_lines = 0;
 551
 552         /* get the counters for the CDUC,CDUC and QM clients  */
 553         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 554
 555         p_blk = &p_cli->pf_blks[CDUC_BLK];
 556
 557         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 558
 559         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 560                                total, CONN_CXT_SIZE(p_hwfn));
 561
 562         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 563         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 564
 565         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 566                                                                  ILT_CLI_CDUC);
 567
 568         /* CDUC VF */
 569         p_blk = &p_cli->vf_blks[CDUC_BLK];
 570         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 571
 572         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 573                                total, CONN_CXT_SIZE(p_hwfn));
 574
 575         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 576         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 577
 578         for (i = 1; i < p_mngr->vf_count; i++)
 579                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 580                                        ILT_CLI_CDUC);
 581
 582         /* CDUT PF */
 583         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 584         p_cli->first.val = curr_line;
 585
 586         /* first the 'working' task memory */
 587         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 588                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 589                 if (!p_seg || p_seg->count == 0)
 590                         continue;
 591
 592                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 593                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 594                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 595                                        p_mngr->task_type_size[p_seg->type]);
 596
 597                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 598                                        ILT_CLI_CDUT);
 599         }
 600
 601         /* next the 'init' task memory (forced load memory) */
 602         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 603                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 604                 if (!p_seg || p_seg->count == 0)
 605                         continue;
 606
 607                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 608
 609                 if (!p_seg->has_fl_mem) {
 610                         /* The segment is active (total size pf 'working'
 611                          * memory is > 0) but has no FL (forced-load, Init)
 612                          * memory. Thus:
 613                          *
 614                          * 1.   The total-size in the corrsponding FL block of
 615                          *      the ILT client is set to 0 - No ILT line are
 616                          *      provisioned and no ILT memory allocated.
 617                          *
 618                          * 2.   The start-line of said block is set to the
 619                          *      start line of the matching working memory
 620                          *      block in the ILT client. This is later used to
 621                          *      configure the CDU segment offset registers and
 622                          *      results in an FL command for TIDs of this
 623                          *      segment behaves as regular load commands
 624                          *      (loading TIDs from the working memory).
 625                          */
 626                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 627
 628                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 629                         continue;
 630                 }
 631                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 632
 633                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 634                                        curr_line, total,
 635                                        p_mngr->task_type_size[p_seg->type]);
 636
 637                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 638                                        ILT_CLI_CDUT);
 639         }
 640         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 641
 642         /* CDUT VF */
 643         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 644         if (p_seg && p_seg->count) {
 645                 /* Stricly speaking we need to iterate over all VF
 646                  * task segment types, but a VF has only 1 segment
 647                  */
 648
 649                 /* 'working' memory */
 650                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 651
 652                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 653                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 654                                        curr_line, total,
 655                                        p_mngr->task_type_size[p_seg->type]);
 656
 657                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 658                                        ILT_CLI_CDUT);
 659
 660                 /* 'init' memory */
 661                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 662                 if (!p_seg->has_fl_mem) {
 663                         /* see comment above */
 664                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 665                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 666                 } else {
 667                         task_size = p_mngr->task_type_size[p_seg->type];
 668                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 669                                                curr_line, total, task_size);
 670                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 671                                                ILT_CLI_CDUT);
 672                 }
 673                 p_cli->vf_total_lines = curr_line -
 674                     p_cli->vf_blks[0].start_line;
 675
 676                 /* Now for the rest of the VFs */
 677                 for (i = 1; i < p_mngr->vf_count; i++) {
 678                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 679                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 680                                                ILT_CLI_CDUT);
 681
 682                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 683                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 684                                                ILT_CLI_CDUT);
 685                 }
 686         }
 687
 688         /* QM */
 689         p_cli = &p_mngr->clients[ILT_CLI_QM];
 690         p_blk = &p_cli->pf_blks[0];
 691
 692         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 693         total = ecore_qm_pf_mem_size(qm_iids.cids,
 694                                      qm_iids.vf_cids, qm_iids.tids,
 695                                      p_hwfn->qm_info.num_pqs,
 696                                      p_hwfn->qm_info.num_vf_pqs);
 697
 698         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 699                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 700                    " num_vf_pqs=%d, memory_size=%d)\n",
 701                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 702                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 703
 704         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 705                                QM_PQ_ELEMENT_SIZE);
 706
 707         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 708         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 709
 710         /* SRC */
 711         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 712         ecore_cxt_src_iids(p_mngr, &src_iids);
 713
 714         /* Both the PF and VFs searcher connections are stored in the per PF
 715          * database. Thus sum the PF searcher cids and all the VFs searcher
 716          * cids.
 717          */
 718         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 719         if (total) {
 720                 u32 local_max = OSAL_MAX_T(u32, total,
 721                                            SRC_MIN_NUM_ELEMS);
 722
 723                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 724
 725                 p_blk = &p_cli->pf_blks[0];
 726                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 727                                        total * sizeof(struct src_ent),
 728                                        sizeof(struct src_ent));
 729
 730                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 731                                        ILT_CLI_SRC);
 732                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 733         }
 734
 735         /* TM PF */
 736         p_cli = &p_mngr->clients[ILT_CLI_TM];
 737         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 738         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 739         if (total) {
 740                 p_blk = &p_cli->pf_blks[0];
 741                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 742                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 743
 744                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 745                                        ILT_CLI_TM);
 746                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 747         }
 748
 749         /* TM VF */
 750         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 751         if (total) {
 752                 p_blk = &p_cli->vf_blks[0];
 753                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 754                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 755
 756                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 757                                        ILT_CLI_TM);
 758
 759                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 760                 for (i = 1; i < p_mngr->vf_count; i++) {
 761                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 762                                                ILT_CLI_TM);
 763                 }
 764         }
 765
 766         /* TSDM (SRQ CONTEXT) */
 767         total = ecore_cxt_get_srq_count(p_hwfn);
 768
 769         if (total) {
 770                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 771                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 772                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 773                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 774
 775                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 776                                        ILT_CLI_TSDM);
 777                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 778         }
 779
 780         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 781             RESC_NUM(p_hwfn, ECORE_ILT)) {
 782                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 783                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 784                 return ECORE_INVAL;
 785         }
 786
 787         return ECORE_SUCCESS;
 788 }
 789
 790 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 791 {
 792         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 793         u32 i;
 794
 795         if (!p_mngr->t2)
 796                 return;
 797
 798         for (i = 0; i < p_mngr->t2_num_pages; i++)
 799                 if (p_mngr->t2[i].p_virt)
 800                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 801                                                p_mngr->t2[i].p_virt,
 802                                                p_mngr->t2[i].p_phys,
 803                                                p_mngr->t2[i].size);
 804
 805         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 806 }
 807
 808 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 809 {
 810         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 811         u32 conn_num, total_size, ent_per_page, psz, i;
 812         struct ecore_ilt_client_cfg *p_src;
 813         struct ecore_src_iids src_iids;
 814         struct ecore_dma_mem *p_t2;
 815         enum _ecore_status_t rc;
 816
 817         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 818
 819         /* if the SRC ILT client is inactive - there are no connection
 820          * requiring the searcer, leave.
 821          */
 822         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 823         if (!p_src->active)
 824                 return ECORE_SUCCESS;
 825
 826         ecore_cxt_src_iids(p_mngr, &src_iids);
 827         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 828         total_size = conn_num * sizeof(struct src_ent);
 829
 830         /* use the same page size as the SRC ILT client */
 831         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 832         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 833
 834         /* allocate t2 */
 835         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 836                                  p_mngr->t2_num_pages *
 837                                  sizeof(struct ecore_dma_mem));
 838         if (!p_mngr->t2) {
 839                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 840                 rc = ECORE_NOMEM;
 841                 goto t2_fail;
 842         }
 843
 844         /* allocate t2 pages */
 845         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 846                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 847                 void **p_virt = &p_mngr->t2[i].p_virt;
 848
 849                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 850                                                   &p_mngr->t2[i].p_phys, size);
 851                 if (!p_mngr->t2[i].p_virt) {
 852                         rc = ECORE_NOMEM;
 853                         goto t2_fail;
 854                 }
 855                 OSAL_MEM_ZERO(*p_virt, size);
 856                 p_mngr->t2[i].size = size;
 857                 total_size -= size;
 858         }
 859
 860         /* Set the t2 pointers */
 861
 862         /* entries per page - must be a power of two */
 863         ent_per_page = psz / sizeof(struct src_ent);
 864
 865         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 866
 867         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 868         p_mngr->last_free = (u64)p_t2->p_phys +
 869             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 870
 871         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 872                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 873                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 874                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 875                 u32 j;
 876
 877                 for (j = 0; j < ent_num - 1; j++) {
 878                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 879                         entries[j].next = OSAL_CPU_TO_BE64(val);
 880                 }
 881
 882                 if (i < p_mngr->t2_num_pages - 1)
 883                         val = (u64)p_mngr->t2[i + 1].p_phys;
 884                 else
 885                         val = 0;
 886                 entries[j].next = OSAL_CPU_TO_BE64(val);
 887
 888                 conn_num -= ent_num;
 889         }
 890
 891         return ECORE_SUCCESS;
 892
 893 t2_fail:
 894         ecore_cxt_src_t2_free(p_hwfn);
 895         return rc;
 896 }
 897
 898 #define for_each_ilt_valid_client(pos, clients)         \
 899         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 900                 if (!clients[pos].active) {             \
 901                         continue;                       \
 902                 } else                                  \
 903
 904
 905 /* Total number of ILT lines used by this PF */
 906 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 907 {
 908         u32 size = 0;
 909         u32 i;
 910
 911         for_each_ilt_valid_client(i, ilt_clients)
 912                 size += (ilt_clients[i].last.val -
 913                          ilt_clients[i].first.val + 1);
 914
 915         return size;
 916 }
 917
 918 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 919 {
 920         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 921         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 922         u32 ilt_size, i;
 923
 924         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 925
 926         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 927                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 928
 929                 if (p_dma->p_virt)
 930                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 931                                                p_dma->p_virt,
 932                                                p_dma->p_phys, p_dma->size);
 933                 p_dma->p_virt = OSAL_NULL;
 934         }
 935         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 936 }
 937
 938 static enum _ecore_status_t
 939 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 940                     struct ecore_ilt_cli_blk *p_blk,
 941                     enum ilt_clients ilt_client, u32 start_line_offset)
 942 {
 943         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 944         u32 lines, line, sz_left, lines_to_skip = 0;
 945
 946         /* Special handling for RoCE that supports dynamic allocation */
 947         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 948                 return ECORE_SUCCESS;
 949
 950         lines_to_skip = p_blk->dynamic_line_cnt;
 951
 952         if (!p_blk->total_size)
 953                 return ECORE_SUCCESS;
 954
 955         sz_left = p_blk->total_size;
 956         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 957         line = p_blk->start_line + start_line_offset -
 958             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 959
 960         for (; lines; lines--) {
 961                 dma_addr_t p_phys;
 962                 void *p_virt;
 963                 u32 size;
 964
 965                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 966
 967 /* @DPDK */
 968 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 969                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 970                                                          &p_phys, size,
 971                                                          ILT_BLOCK_ALIGN_SIZE);
 972                 if (!p_virt)
 973                         return ECORE_NOMEM;
 974                 OSAL_MEM_ZERO(p_virt, size);
 975
 976                 ilt_shadow[line].p_phys = p_phys;
 977                 ilt_shadow[line].p_virt = p_virt;
 978                 ilt_shadow[line].size = size;
 979
 980                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 981                            "ILT shadow: Line [%d] Physical 0x%lx"
 982                            " Virtual %p Size %d\n",
 983                            line, (unsigned long)p_phys, p_virt, size);
 984
 985                 sz_left -= size;
 986                 line++;
 987         }
 988
 989         return ECORE_SUCCESS;
 990 }
 991
 992 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 993 {
 994         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 995         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 996         struct ecore_ilt_cli_blk *p_blk;
 997         u32 size, i, j, k;
 998         enum _ecore_status_t rc;
 999
1000         size = ecore_cxt_ilt_shadow_size(clients);
1001         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1002                                          size * sizeof(struct ecore_dma_mem));
1003
1004         if (!p_mngr->ilt_shadow) {
1005                 DP_NOTICE(p_hwfn, true,
1006                           "Failed to allocate ilt shadow table\n");
1007                 rc = ECORE_NOMEM;
1008                 goto ilt_shadow_fail;
1009         }
1010
1011         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1012                    "Allocated 0x%x bytes for ilt shadow\n",
1013                    (u32)(size * sizeof(struct ecore_dma_mem)));
1014
1015         for_each_ilt_valid_client(i, clients) {
1016                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1017                         p_blk = &clients[i].pf_blks[j];
1018                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1019                         if (rc != ECORE_SUCCESS)
1020                                 goto ilt_shadow_fail;
1021                 }
1022                 for (k = 0; k < p_mngr->vf_count; k++) {
1023                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1024                                 u32 lines = clients[i].vf_total_lines * k;
1025
1026                                 p_blk = &clients[i].vf_blks[j];
1027                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1028                                                          i, lines);
1029                                 if (rc != ECORE_SUCCESS)
1030                                         goto ilt_shadow_fail;
1031                         }
1032                 }
1033         }
1034
1035         return ECORE_SUCCESS;
1036
1037 ilt_shadow_fail:
1038         ecore_ilt_shadow_free(p_hwfn);
1039         return rc;
1040 }
1041
1042 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1043 {
1044         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1045         u32 type, vf;
1046
1047         for (type = 0; type < MAX_CONN_TYPES; type++) {
1048                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1049                 p_mngr->acquired[type].max_count = 0;
1050                 p_mngr->acquired[type].start_cid = 0;
1051
1052                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1053                         OSAL_FREE(p_hwfn->p_dev,
1054                                   p_mngr->acquired_vf[type][vf].cid_map);
1055                         p_mngr->acquired_vf[type][vf].max_count = 0;
1056                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1057                 }
1058         }
1059 }
1060
1061 static enum _ecore_status_t
1062 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1063                            u32 cid_start, u32 cid_count,
1064                            struct ecore_cid_acquired_map *p_map)
1065 {
1066         u32 size;
1067
1068         if (!cid_count)
1069                 return ECORE_SUCCESS;
1070
1071         size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1072         p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1073         if (p_map->cid_map == OSAL_NULL)
1074                 return ECORE_NOMEM;
1075
1076         p_map->max_count = cid_count;
1077         p_map->start_cid = cid_start;
1078
1079         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1080                    "Type %08x start: %08x count %08x\n",
1081                    type, p_map->start_cid, p_map->max_count);
1082
1083         return ECORE_SUCCESS;
1084 }
1085
1086 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1087 {
1088         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1089         u32 start_cid = 0, vf_start_cid = 0;
1090         u32 type, vf;
1091
1092         for (type = 0; type < MAX_CONN_TYPES; type++) {
1093                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1094                 struct ecore_cid_acquired_map *p_map;
1095
1096                 /* Handle PF maps */
1097                 p_map = &p_mngr->acquired[type];
1098                 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1099                                                p_cfg->cid_count, p_map))
1100                         goto cid_map_fail;
1101
1102                 /* Handle VF maps */
1103                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1104                         p_map = &p_mngr->acquired_vf[type][vf];
1105                         if (ecore_cid_map_alloc_single(p_hwfn, type,
1106                                                        vf_start_cid,
1107                                                        p_cfg->cids_per_vf,
1108                                                        p_map))
1109                                 goto cid_map_fail;
1110                 }
1111
1112                 start_cid += p_cfg->cid_count;
1113                 vf_start_cid += p_cfg->cids_per_vf;
1114         }
1115
1116         return ECORE_SUCCESS;
1117
1118 cid_map_fail:
1119         ecore_cid_map_free(p_hwfn);
1120         return ECORE_NOMEM;
1121 }
1122
1123 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1124 {
1125         struct ecore_ilt_client_cfg *clients;
1126         struct ecore_cxt_mngr *p_mngr;
1127         u32 i;
1128
1129         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1130         if (!p_mngr) {
1131                 DP_NOTICE(p_hwfn, true,
1132                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1133                 return ECORE_NOMEM;
1134         }
1135
1136         /* Initialize ILT client registers */
1137         clients = p_mngr->clients;
1138         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1139         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1140         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1141
1142         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1143         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1144         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1145
1146         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1147         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1148         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1149
1150         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1151         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1152         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1153
1154         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1155         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1156         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1157
1158         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1159         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1160         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1161
1162         /* default ILT page size for all clients is 32K */
1163         for (i = 0; i < ILT_CLI_MAX; i++)
1164                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1165
1166         /* due to removal of ISCSI/FCoE files union type0_task_context
1167          * task_type_size will be 0. So hardcoded for now.
1168          */
1169         p_mngr->task_type_size[0] = 512; /* @DPDK */
1170         p_mngr->task_type_size[1] = 128; /* @DPDK */
1171
1172         if (p_hwfn->p_dev->p_iov_info)
1173                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1174
1175         /* Initialize the dynamic ILT allocation mutex */
1176 #ifdef CONFIG_ECORE_LOCK_ALLOC
1177         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1178 #endif
1179         OSAL_MUTEX_INIT(&p_mngr->mutex);
1180
1181         /* Set the cxt mangr pointer priori to further allocations */
1182         p_hwfn->p_cxt_mngr = p_mngr;
1183
1184         return ECORE_SUCCESS;
1185 }
1186
1187 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1188 {
1189         enum _ecore_status_t rc;
1190
1191         /* Allocate the ILT shadow table */
1192         rc = ecore_ilt_shadow_alloc(p_hwfn);
1193         if (rc) {
1194                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1195                 goto tables_alloc_fail;
1196         }
1197
1198         /* Allocate the T2  table */
1199         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1200         if (rc) {
1201                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1202                 goto tables_alloc_fail;
1203         }
1204
1205         /* Allocate and initialize the acquired cids bitmaps */
1206         rc = ecore_cid_map_alloc(p_hwfn);
1207         if (rc) {
1208                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1209                 goto tables_alloc_fail;
1210         }
1211
1212         return ECORE_SUCCESS;
1213
1214 tables_alloc_fail:
1215         ecore_cxt_mngr_free(p_hwfn);
1216         return rc;
1217 }
1218
1219 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1220 {
1221         if (!p_hwfn->p_cxt_mngr)
1222                 return;
1223
1224         ecore_cid_map_free(p_hwfn);
1225         ecore_cxt_src_t2_free(p_hwfn);
1226         ecore_ilt_shadow_free(p_hwfn);
1227 #ifdef CONFIG_ECORE_LOCK_ALLOC
1228         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1229 #endif
1230         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1231 }
1232
1233 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1234 {
1235         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1236         struct ecore_cid_acquired_map *p_map;
1237         struct ecore_conn_type_cfg *p_cfg;
1238         int type;
1239         u32 len;
1240
1241         /* Reset acquired cids */
1242         for (type = 0; type < MAX_CONN_TYPES; type++) {
1243                 u32 vf;
1244
1245                 p_cfg = &p_mngr->conn_cfg[type];
1246                 if (p_cfg->cid_count) {
1247                         p_map = &p_mngr->acquired[type];
1248                         len = DIV_ROUND_UP(p_map->max_count,
1249                                            BITS_PER_MAP_WORD) *
1250                               MAP_WORD_SIZE;
1251                         OSAL_MEM_ZERO(p_map->cid_map, len);
1252                 }
1253
1254                 if (!p_cfg->cids_per_vf)
1255                         continue;
1256
1257                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1258                         p_map = &p_mngr->acquired_vf[type][vf];
1259                         len = DIV_ROUND_UP(p_map->max_count,
1260                                            BITS_PER_MAP_WORD) *
1261                               MAP_WORD_SIZE;
1262                         OSAL_MEM_ZERO(p_map->cid_map, len);
1263                 }
1264         }
1265 }
1266
1267 /* HW initialization helper (per Block, per phase) */
1268
1269 /* CDU Common */
1270 #define CDUC_CXT_SIZE_SHIFT                                             \
1271         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1272
1273 #define CDUC_CXT_SIZE_MASK                                              \
1274         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1275
1276 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1277         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1278
1279 #define CDUC_BLOCK_WASTE_MASK                                           \
1280         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1281
1282 #define CDUC_NCIB_SHIFT                                                 \
1283         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1284
1285 #define CDUC_NCIB_MASK                                                  \
1286         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1287
1288 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1289         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1290
1291 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1292         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1293         CDUT_TYPE0_CXT_SIZE_SHIFT)
1294
1295 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1296         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1297
1298 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1299         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1300         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1301
1302 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1303         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1304
1305 #define CDUT_TYPE0_NCIB_MASK                                            \
1306         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1307         CDUT_TYPE0_NCIB_SHIFT)
1308
1309 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1310         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1311
1312 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1313         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1314         CDUT_TYPE1_CXT_SIZE_SHIFT)
1315
1316 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1317         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1318
1319 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1320         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1321         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1322
1323 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1324         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1325
1326 #define CDUT_TYPE1_NCIB_MASK                                            \
1327         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1328         CDUT_TYPE1_NCIB_SHIFT)
1329
1330 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1331 {
1332         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1333
1334         /* CDUC - connection configuration */
1335         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1336         cxt_size = CONN_CXT_SIZE(p_hwfn);
1337         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1338         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1339
1340         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1341         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1342         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1343         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1344
1345         /* CDUT - type-0 tasks configuration */
1346         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1347         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1348         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1349         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1350
1351         /* cxt size and block-waste are multipes of 8 */
1352         cdu_params = 0;
1353         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1354         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1355         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1356         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1357
1358         /* CDUT - type-1 tasks configuration */
1359         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1360         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1361         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1362
1363         /* cxt size and block-waste are multipes of 8 */
1364         cdu_params = 0;
1365         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1366         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1367         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1368         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1369 }
1370
1371 /* CDU PF */
1372 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1373 #define CDU_SEG_REG_TYPE_MASK           0x1
1374 #define CDU_SEG_REG_OFFSET_SHIFT        0
1375 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1376
1377 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1378 {
1379         struct ecore_ilt_client_cfg *p_cli;
1380         struct ecore_tid_seg *p_seg;
1381         u32 cdu_seg_params, offset;
1382         int i;
1383
1384         static const u32 rt_type_offset_arr[] = {
1385                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1386                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1387                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1388                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1389         };
1390
1391         static const u32 rt_type_offset_fl_arr[] = {
1392                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1393                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1394                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1395                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1396         };
1397
1398         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1399
1400         /* There are initializations only for CDUT during pf Phase */
1401         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1402                 /* Segment 0 */
1403                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1404                 if (!p_seg)
1405                         continue;
1406
1407                 /* Note: start_line is already adjusted for the CDU
1408                  * segment register granularity, so we just need to
1409                  * divide. Adjustment is implicit as we assume ILT
1410                  * Page size is larger than 32K!
1411                  */
1412                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1413                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1414                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1415
1416                 cdu_seg_params = 0;
1417                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1418                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1419                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1420
1421                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1422                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1423                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1424
1425                 cdu_seg_params = 0;
1426                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1427                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1428                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1429         }
1430 }
1431
1432 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1433 {
1434         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1435         struct ecore_mcp_link_state *p_link;
1436         struct ecore_qm_iids iids;
1437
1438         OSAL_MEM_ZERO(&iids, sizeof(iids));
1439         ecore_cxt_qm_iids(p_hwfn, &iids);
1440
1441         p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
1442
1443         ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id,
1444                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1445                             iids.cids, iids.vf_cids, iids.tids,
1446                             qm_info->start_pq,
1447                             qm_info->num_pqs - qm_info->num_vf_pqs,
1448                             qm_info->num_vf_pqs,
1449                             qm_info->start_vport,
1450                             qm_info->num_vports, qm_info->pf_wfq,
1451                             qm_info->pf_rl, p_link->speed,
1452                             p_hwfn->qm_info.qm_pq_params,
1453                             p_hwfn->qm_info.qm_vport_params);
1454 }
1455
1456 /* CM PF */
1457 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1458 {
1459         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1460                      ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1461 }
1462
1463 /* DQ PF */
1464 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1465 {
1466         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1467         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1468
1469         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1470         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1471
1472         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1473         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1474
1475         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1476         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1477
1478         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1479         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1480
1481         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1482         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1483
1484         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1485         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1486
1487         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1488         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1489
1490         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1491         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1492
1493         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1494         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1495
1496         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1497         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1498
1499         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1500         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1501
1502         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1503         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1504
1505         /* Connection types 6 & 7 are not in use, yet they must be configured
1506          * as the highest possible connection. Not configuring them means the
1507          * defaults will be  used, and with a large number of cids a bug may
1508          * occur, if the defaults will be smaller than dq_pf_max_cid /
1509          * dq_vf_max_cid.
1510          */
1511         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1512         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1513
1514         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1515         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1516 }
1517
1518 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1519 {
1520         struct ecore_ilt_client_cfg *ilt_clients;
1521         int i;
1522
1523         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1524         for_each_ilt_valid_client(i, ilt_clients) {
1525                 STORE_RT_REG(p_hwfn,
1526                              ilt_clients[i].first.reg,
1527                              ilt_clients[i].first.val);
1528                 STORE_RT_REG(p_hwfn,
1529                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1530                 STORE_RT_REG(p_hwfn,
1531                              ilt_clients[i].p_size.reg,
1532                              ilt_clients[i].p_size.val);
1533         }
1534 }
1535
1536 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1537 {
1538         struct ecore_ilt_client_cfg *p_cli;
1539         u32 blk_factor;
1540
1541         /* For simplicty  we set the 'block' to be an ILT page */
1542         if (p_hwfn->p_dev->p_iov_info) {
1543                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1544
1545                 STORE_RT_REG(p_hwfn,
1546                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1547                              p_iov->first_vf_in_pf);
1548                 STORE_RT_REG(p_hwfn,
1549                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1550                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1551         }
1552
1553         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1554         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1555         if (p_cli->active) {
1556                 STORE_RT_REG(p_hwfn,
1557                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1558                              blk_factor);
1559                 STORE_RT_REG(p_hwfn,
1560                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1561                              p_cli->pf_total_lines);
1562                 STORE_RT_REG(p_hwfn,
1563                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1564                              p_cli->vf_total_lines);
1565         }
1566
1567         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1568         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1569         if (p_cli->active) {
1570                 STORE_RT_REG(p_hwfn,
1571                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1572                              blk_factor);
1573                 STORE_RT_REG(p_hwfn,
1574                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1575                              p_cli->pf_total_lines);
1576                 STORE_RT_REG(p_hwfn,
1577                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1578                              p_cli->vf_total_lines);
1579         }
1580
1581         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1582         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1583         if (p_cli->active) {
1584                 STORE_RT_REG(p_hwfn,
1585                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1586                 STORE_RT_REG(p_hwfn,
1587                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1588                              p_cli->pf_total_lines);
1589                 STORE_RT_REG(p_hwfn,
1590                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1591                              p_cli->vf_total_lines);
1592         }
1593 }
1594
1595 /* ILT (PSWRQ2) PF */
1596 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1597 {
1598         struct ecore_ilt_client_cfg *clients;
1599         struct ecore_cxt_mngr *p_mngr;
1600         struct ecore_dma_mem *p_shdw;
1601         u32 line, rt_offst, i;
1602
1603         ecore_ilt_bounds_init(p_hwfn);
1604         ecore_ilt_vf_bounds_init(p_hwfn);
1605
1606         p_mngr = p_hwfn->p_cxt_mngr;
1607         p_shdw = p_mngr->ilt_shadow;
1608         clients = p_hwfn->p_cxt_mngr->clients;
1609
1610         for_each_ilt_valid_client(i, clients) {
1611                 /* Client's 1st val and RT array are absolute, ILT shadows'
1612                  * lines are relative.
1613                  */
1614                 line = clients[i].first.val - p_mngr->pf_start_line;
1615                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1616                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1617
1618                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1619                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1620                         u64 ilt_hw_entry = 0;
1621
1622                         /** p_virt could be OSAL_NULL incase of dynamic
1623                          *  allocation
1624                          */
1625                         if (p_shdw[line].p_virt != OSAL_NULL) {
1626                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1627                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1628                                           (p_shdw[line].p_phys >> 12));
1629
1630                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1631                                         "Setting RT[0x%08x] from"
1632                                         " ILT[0x%08x] [Client is %d] to"
1633                                         " Physical addr: 0x%lx\n",
1634                                         rt_offst, line, i,
1635                                         (unsigned long)(p_shdw[line].
1636                                                         p_phys >> 12));
1637                         }
1638
1639                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1640                 }
1641         }
1642 }
1643
1644 /* SRC (Searcher) PF */
1645 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1646 {
1647         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1648         u32 rounded_conn_num, conn_num, conn_max;
1649         struct ecore_src_iids src_iids;
1650
1651         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1652         ecore_cxt_src_iids(p_mngr, &src_iids);
1653         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1654         if (!conn_num)
1655                 return;
1656
1657         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1658         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1659
1660         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1661         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1662                      OSAL_LOG2(rounded_conn_num));
1663
1664         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1665                          p_hwfn->p_cxt_mngr->first_free);
1666         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1667                          p_hwfn->p_cxt_mngr->last_free);
1668         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1669                    "Configured SEARCHER for 0x%08x connections\n",
1670                    conn_num);
1671 }
1672
1673 /* Timers PF */
1674 #define TM_CFG_NUM_IDS_SHIFT            0
1675 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1676 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1677 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1678 #define TM_CFG_PARENT_PF_SHIFT          25
1679 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1680
1681 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1682 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1683
1684 #define TM_CFG_TID_OFFSET_SHIFT         30
1685 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1686 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1687 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1688
1689 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1690 {
1691         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1692         u32 active_seg_mask = 0, tm_offset, rt_reg;
1693         struct ecore_tm_iids tm_iids;
1694         u64 cfg_word;
1695         u8 i;
1696
1697         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1698         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1699
1700         /* @@@TBD No pre-scan for now */
1701
1702         /* Note: We assume consecutive VFs for a PF */
1703         for (i = 0; i < p_mngr->vf_count; i++) {
1704                 cfg_word = 0;
1705                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1706                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1707                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1708                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1709
1710                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1711                     (sizeof(cfg_word) / sizeof(u32)) *
1712                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1713                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1714         }
1715
1716         cfg_word = 0;
1717         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1718         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1719         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1720         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1721
1722         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1723             (sizeof(cfg_word) / sizeof(u32)) *
1724             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1725         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1726
1727         /* enale scan */
1728         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1729                      tm_iids.pf_cids ? 0x1 : 0x0);
1730
1731         /* @@@TBD how to enable the scan for the VFs */
1732
1733         tm_offset = tm_iids.per_vf_cids;
1734
1735         /* Note: We assume consecutive VFs for a PF */
1736         for (i = 0; i < p_mngr->vf_count; i++) {
1737                 cfg_word = 0;
1738                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1739                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1740                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1741                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1742                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1743
1744                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1745                     (sizeof(cfg_word) / sizeof(u32)) *
1746                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1747
1748                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1749         }
1750
1751         tm_offset = tm_iids.pf_cids;
1752         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1753                 cfg_word = 0;
1754                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1755                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1756                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1757                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1758                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1759
1760                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1761                     (sizeof(cfg_word) / sizeof(u32)) *
1762                     (NUM_OF_VFS(p_hwfn->p_dev) +
1763                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1764
1765                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1766                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1767
1768                 tm_offset += tm_iids.pf_tids[i];
1769         }
1770
1771         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1772
1773         /* @@@TBD how to enable the scan for the VFs */
1774 }
1775
1776 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1777 {
1778         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1779         struct ecore_conn_type_cfg *p_fcoe;
1780         struct ecore_tid_seg *p_tid;
1781
1782         p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1783
1784         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1785         if (!p_fcoe->cid_count)
1786                 return;
1787
1788         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1789         STORE_RT_REG_AGG(p_hwfn,
1790                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1791                         p_tid->count);
1792 }
1793
1794 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1795 {
1796         /* CDU configuration */
1797         ecore_cdu_init_common(p_hwfn);
1798 }
1799
1800 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1801 {
1802         ecore_qm_init_pf(p_hwfn, p_ptt);
1803         ecore_cm_init_pf(p_hwfn);
1804         ecore_dq_init_pf(p_hwfn);
1805         ecore_cdu_init_pf(p_hwfn);
1806         ecore_ilt_init_pf(p_hwfn);
1807         ecore_src_init_pf(p_hwfn);
1808         ecore_tm_init_pf(p_hwfn);
1809         ecore_prs_init_pf(p_hwfn);
1810 }
1811
1812 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1813                                             enum protocol_type type,
1814                                             u32 *p_cid, u8 vfid)
1815 {
1816         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1817         struct ecore_cid_acquired_map *p_map;
1818         u32 rel_cid;
1819
1820         if (type >= MAX_CONN_TYPES) {
1821                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1822                 return ECORE_INVAL;
1823         }
1824
1825         if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1826                 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1827                 return ECORE_INVAL;
1828         }
1829
1830         /* Determine the right map to take this CID from */
1831         if (vfid == ECORE_CXT_PF_CID)
1832                 p_map = &p_mngr->acquired[type];
1833         else
1834                 p_map = &p_mngr->acquired_vf[type][vfid];
1835
1836         if (p_map->cid_map == OSAL_NULL) {
1837                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1838                 return ECORE_INVAL;
1839         }
1840
1841         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1842                                            p_map->max_count);
1843
1844         if (rel_cid >= p_map->max_count) {
1845                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1846                           type);
1847                 return ECORE_NORESOURCES;
1848         }
1849
1850         OSAL_SET_BIT(rel_cid, p_map->cid_map);
1851
1852         *p_cid = rel_cid + p_map->start_cid;
1853
1854         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1855                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1856                    *p_cid, rel_cid, vfid, type);
1857
1858         return ECORE_SUCCESS;
1859 }
1860
1861 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1862                                            enum protocol_type type,
1863                                            u32 *p_cid)
1864 {
1865         return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1866 }
1867
1868 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1869                                         u32 cid, u8 vfid,
1870                                         enum protocol_type *p_type,
1871                                         struct ecore_cid_acquired_map **pp_map)
1872 {
1873         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1874         u32 rel_cid;
1875
1876         /* Iterate over protocols and find matching cid range */
1877         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1878                 if (vfid == ECORE_CXT_PF_CID)
1879                         *pp_map = &p_mngr->acquired[*p_type];
1880                 else
1881                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1882
1883                 if (!((*pp_map)->cid_map))
1884                         continue;
1885                 if (cid >= (*pp_map)->start_cid &&
1886                     cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1887                         break;
1888                 }
1889         }
1890         if (*p_type == MAX_CONN_TYPES) {
1891                 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1892                 goto fail;
1893         }
1894
1895         rel_cid = cid - (*pp_map)->start_cid;
1896         if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1897                 DP_NOTICE(p_hwfn, true,
1898                           "CID %d [vifd %02x] not acquired", cid, vfid);
1899                 goto fail;
1900         }
1901
1902         return true;
1903 fail:
1904         *p_type = MAX_CONN_TYPES;
1905         *pp_map = OSAL_NULL;
1906         return false;
1907 }
1908
1909 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1910 {
1911         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1912         enum protocol_type type;
1913         bool b_acquired;
1914         u32 rel_cid;
1915
1916         if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1917                 DP_NOTICE(p_hwfn, true,
1918                           "Trying to return incorrect CID belonging to VF %02x\n",
1919                           vfid);
1920                 return;
1921         }
1922
1923         /* Test acquired and find matching per-protocol map */
1924         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1925                                                  &type, &p_map);
1926
1927         if (!b_acquired)
1928                 return;
1929
1930         rel_cid = cid - p_map->start_cid;
1931         OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1932
1933         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1934                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1935                    cid, rel_cid, vfid, type);
1936 }
1937
1938 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1939 {
1940         _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1941 }
1942
1943 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1944                                             struct ecore_cxt_info *p_info)
1945 {
1946         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1947         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1948         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1949         enum protocol_type type;
1950         bool b_acquired;
1951
1952         /* Test acquired and find matching per-protocol map */
1953         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1954                                                  ECORE_CXT_PF_CID,
1955                                                  &type, &p_map);
1956
1957         if (!b_acquired)
1958                 return ECORE_INVAL;
1959
1960         /* set the protocl type */
1961         p_info->type = type;
1962
1963         /* compute context virtual pointer */
1964         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1965
1966         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1967         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1968         line = p_info->iid / cxts_per_p;
1969
1970         /* Make sure context is allocated (dynamic allocation) */
1971         if (!p_mngr->ilt_shadow[line].p_virt)
1972                 return ECORE_INVAL;
1973
1974         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1975             p_info->iid % cxts_per_p * conn_cxt_size;
1976
1977         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1978                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1979                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1980
1981         return ECORE_SUCCESS;
1982 }
1983
1984 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1985 {
1986         /* Set the number of required CORE connections */
1987         u32 core_cids = 1;      /* SPQ */
1988
1989         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1990
1991         switch (p_hwfn->hw_info.personality) {
1992         case ECORE_PCI_ETH:
1993                 {
1994                 struct ecore_eth_pf_params *p_params =
1995                             &p_hwfn->pf_params.eth_pf_params;
1996
1997                 if (!p_params->num_vf_cons)
1998                         p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
1999                 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2000                                               p_params->num_cons,
2001                                               p_params->num_vf_cons);
2002                 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2003                 break;
2004                 }
2005         default:
2006                 return ECORE_INVAL;
2007         }
2008
2009         return ECORE_SUCCESS;
2010 }
2011
2012 /* This function is very RoCE oriented, if another protocol in the future
2013  * will want this feature we'll need to modify the function to be more generic
2014  */
2015 enum _ecore_status_t
2016 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2017                             enum ecore_cxt_elem_type elem_type,
2018                             u32 iid)
2019 {
2020         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2021         struct ecore_ilt_client_cfg *p_cli;
2022         struct ecore_ilt_cli_blk *p_blk;
2023         struct ecore_ptt *p_ptt;
2024         dma_addr_t p_phys;
2025         u64 ilt_hw_entry;
2026         void *p_virt;
2027         enum _ecore_status_t rc = ECORE_SUCCESS;
2028
2029         switch (elem_type) {
2030         case ECORE_ELEM_CXT:
2031                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2032                 elem_size = CONN_CXT_SIZE(p_hwfn);
2033                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2034                 break;
2035         case ECORE_ELEM_SRQ:
2036                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2037                 elem_size = SRQ_CXT_SIZE;
2038                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2039                 break;
2040         case ECORE_ELEM_TASK:
2041                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2042                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2043                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2044                 break;
2045         default:
2046                 DP_NOTICE(p_hwfn, false,
2047                           "ECORE_INVALID elem type = %d", elem_type);
2048                 return ECORE_INVAL;
2049         }
2050
2051         /* Calculate line in ilt */
2052         hw_p_size = p_cli->p_size.val;
2053         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2054         line = p_blk->start_line + (iid / elems_per_p);
2055         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2056
2057         /* If line is already allocated, do nothing, otherwise allocate it and
2058          * write it to the PSWRQ2 registers.
2059          * This section can be run in parallel from different contexts and thus
2060          * a mutex protection is needed.
2061          */
2062
2063         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2064
2065         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2066                 goto out0;
2067
2068         p_ptt = ecore_ptt_acquire(p_hwfn);
2069         if (!p_ptt) {
2070                 DP_NOTICE(p_hwfn, false,
2071                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2072                 rc = ECORE_TIMEOUT;
2073                 goto out0;
2074         }
2075
2076         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2077                                          &p_phys,
2078                                          p_blk->real_size_in_page);
2079         if (!p_virt) {
2080                 rc = ECORE_NOMEM;
2081                 goto out1;
2082         }
2083         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2084
2085         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2086         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2087         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2088                 p_blk->real_size_in_page;
2089
2090         /* compute absolute offset */
2091         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2092                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2093
2094         ilt_hw_entry = 0;
2095         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2096         SET_FIELD(ilt_hw_entry,
2097                   ILT_ENTRY_PHY_ADDR,
2098                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2099
2100 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2101
2102         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2103                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2104                             0 /* no flags */);
2105
2106         if (elem_type == ECORE_ELEM_CXT) {
2107                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2108                                          elems_per_p;
2109
2110                 /* Update the relevant register in the parser */
2111                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2112                          last_cid_allocated - 1);
2113
2114                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2115                         /* Enable RoCE search */
2116                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2117                         p_hwfn->b_rdma_enabled_in_prs = true;
2118                 }
2119         }
2120
2121 out1:
2122         ecore_ptt_release(p_hwfn, p_ptt);
2123 out0:
2124         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2125
2126         return rc;
2127 }
2128
2129 /* This function is very RoCE oriented, if another protocol in the future
2130  * will want this feature we'll need to modify the function to be more generic
2131  */
2132 static enum _ecore_status_t
2133 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2134                          enum ecore_cxt_elem_type elem_type,
2135                          u32 start_iid, u32 count)
2136 {
2137         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2138         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2139         struct ecore_ilt_client_cfg *p_cli;
2140         struct ecore_ilt_cli_blk *p_blk;
2141         u32 end_iid = start_iid + count;
2142         struct ecore_ptt *p_ptt;
2143         u64 ilt_hw_entry = 0;
2144         u32 i;
2145
2146         switch (elem_type) {
2147         case ECORE_ELEM_CXT:
2148                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2149                 elem_size = CONN_CXT_SIZE(p_hwfn);
2150                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2151                 break;
2152         case ECORE_ELEM_SRQ:
2153                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2154                 elem_size = SRQ_CXT_SIZE;
2155                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2156                 break;
2157         case ECORE_ELEM_TASK:
2158                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2159                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2160                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2161                 break;
2162         default:
2163                 DP_NOTICE(p_hwfn, false,
2164                           "ECORE_INVALID elem type = %d", elem_type);
2165                 return ECORE_INVAL;
2166         }
2167
2168         /* Calculate line in ilt */
2169         hw_p_size = p_cli->p_size.val;
2170         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2171         start_line = p_blk->start_line + (start_iid / elems_per_p);
2172         end_line = p_blk->start_line + (end_iid / elems_per_p);
2173         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2174                 end_line--;
2175
2176         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2177         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2178
2179         p_ptt = ecore_ptt_acquire(p_hwfn);
2180         if (!p_ptt) {
2181                 DP_NOTICE(p_hwfn, false,
2182                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2183                 return ECORE_TIMEOUT;
2184         }
2185
2186         for (i = shadow_start_line; i < shadow_end_line; i++) {
2187                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2188                         continue;
2189
2190                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2191                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2192                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2193                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2194
2195                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2196                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2197                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2198
2199                 /* compute absolute offset */
2200                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2201                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2202                      ILT_ENTRY_IN_REGS);
2203
2204                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2205                  * wide-bus.
2206                  */
2207                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2208                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2209                                     reg_offset,
2210                                     sizeof(ilt_hw_entry) / sizeof(u32),
2211                                     0 /* no flags */);
2212         }
2213
2214         ecore_ptt_release(p_hwfn, p_ptt);
2215
2216         return ECORE_SUCCESS;
2217 }
2218
2219 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2220                                               enum protocol_type proto)
2221 {
2222         enum _ecore_status_t rc;
2223         u32 cid;
2224
2225         /* Free Connection CXT */
2226         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2227                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2228                                                                     proto),
2229                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2230                                                                     proto,
2231                                                                     &cid));
2232
2233         if (rc)
2234                 return rc;
2235
2236         /* Free Task CXT */
2237         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2238                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2239                                                                     proto));
2240         if (rc)
2241                 return rc;
2242
2243         /* Free TSDM CXT */
2244         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2245                                       ecore_cxt_get_srq_count(p_hwfn));
2246
2247         return rc;
2248 }