drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "common_hsi.h"
  12 #include "ecore_hsi_common.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_status.h"
  16 #include "ecore.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_init_fw_funcs.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_hw.h"
  21 #include "ecore_dev_api.h"
  22 #include "ecore_sriov.h"
  23 #include "ecore_mcp.h"
  24
  25 /* Max number of connection types in HW (DQ/CDU etc.) */
  26 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  27 #define NUM_TASK_TYPES          2
  28 #define NUM_TASK_PF_SEGMENTS    4
  29 #define NUM_TASK_VF_SEGMENTS    1
  30
  31 /* Doorbell-Queue constants */
  32 #define DQ_RANGE_SHIFT  4
  33 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  34
  35 /* Searcher constants */
  36 #define SRC_MIN_NUM_ELEMS 256
  37
  38 /* Timers constants */
  39 #define TM_SHIFT        7
  40 #define TM_ALIGN        (1 << TM_SHIFT)
  41 #define TM_ELEM_SIZE    4
  42
  43 /* ILT constants */
  44 /* If for some reason, HW P size is modified to be less than 32K,
  45  * special handling needs to be made for CDU initialization
  46  */
  47 #define ILT_DEFAULT_HW_P_SIZE   3
  48
  49 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  50 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  51
  52 /* ILT entry structure */
  53 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  54 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  55 #define ILT_ENTRY_VALID_MASK            0x1ULL
  56 #define ILT_ENTRY_VALID_SHIFT           52
  57 #define ILT_ENTRY_IN_REGS               2
  58 #define ILT_REG_SIZE_IN_BYTES           4
  59
  60 /* connection context union */
  61 union conn_context {
  62         struct core_conn_context core_ctx;
  63         struct eth_conn_context eth_ctx;
  64 };
  65
  66 /* TYPE-0 task context - iSCSI, FCOE */
  67 union type0_task_context {
  68 };
  69
  70 /* TYPE-1 task context - ROCE */
  71 union type1_task_context {
  72 };
  73
  74 struct src_ent {
  75         u8 opaque[56];
  76         u64 next;
  77 };
  78
  79 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  80 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  81
  82 #define CONN_CXT_SIZE(p_hwfn) \
  83         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  84
  85 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  86
  87 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  88         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  89
  90 /* Alignment is inherent to the type1_task_context structure */
  91 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  92
  93 /* PF per protocl configuration object */
  94 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  95 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  96
  97 struct ecore_tid_seg {
  98         u32 count;
  99         u8 type;
 100         bool has_fl_mem;
 101 };
 102
 103 struct ecore_conn_type_cfg {
 104         u32 cid_count;
 105         u32 cids_per_vf;
 106         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 107 };
 108
 109 /* ILT Client configuration,
 110  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 111  * 1 - for connection context (CDUC) and for each task context we need two
 112  * values, for regular task context and for force load memory
 113  */
 114 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 115 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 116 #define CDUC_BLK                (0)
 117 #define SRQ_BLK                 (0)
 118 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 119 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 120
 121 enum ilt_clients {
 122         ILT_CLI_CDUC,
 123         ILT_CLI_CDUT,
 124         ILT_CLI_QM,
 125         ILT_CLI_TM,
 126         ILT_CLI_SRC,
 127         ILT_CLI_TSDM,
 128         ILT_CLI_MAX
 129 };
 130
 131 struct ilt_cfg_pair {
 132         u32 reg;
 133         u32 val;
 134 };
 135
 136 struct ecore_ilt_cli_blk {
 137         u32 total_size;         /* 0 means not active */
 138         u32 real_size_in_page;
 139         u32 start_line;
 140         u32 dynamic_line_cnt;
 141 };
 142
 143 struct ecore_ilt_client_cfg {
 144         bool active;
 145
 146         /* ILT boundaries */
 147         struct ilt_cfg_pair first;
 148         struct ilt_cfg_pair last;
 149         struct ilt_cfg_pair p_size;
 150
 151         /* ILT client blocks for PF */
 152         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 153         u32 pf_total_lines;
 154
 155         /* ILT client blocks for VFs */
 156         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 157         u32 vf_total_lines;
 158 };
 159
 160 /* Per Path -
 161  *      ILT shadow table
 162  *      Protocol acquired CID lists
 163  *      PF start line in ILT
 164  */
 165 struct ecore_dma_mem {
 166         dma_addr_t p_phys;
 167         void *p_virt;
 168         osal_size_t size;
 169 };
 170
 171 #define MAP_WORD_SIZE           sizeof(unsigned long)
 172 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 173
 174 struct ecore_cid_acquired_map {
 175         u32 start_cid;
 176         u32 max_count;
 177         unsigned long *cid_map;
 178 };
 179
 180 struct ecore_cxt_mngr {
 181         /* Per protocl configuration */
 182         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 183
 184         /* computed ILT structure */
 185         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 186
 187         /* Task type sizes */
 188         u32 task_type_size[NUM_TASK_TYPES];
 189
 190         /* total number of VFs for this hwfn -
 191          * ALL VFs are symmetric in terms of HW resources
 192          */
 193         u32 vf_count;
 194
 195         /* Acquired CIDs */
 196         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 197         /* TBD - do we want this allocated to reserve space? */
 198         struct ecore_cid_acquired_map
 199                 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
 200
 201         /* ILT  shadow table */
 202         struct ecore_dma_mem *ilt_shadow;
 203         u32 pf_start_line;
 204
 205         /* Mutex for a dynamic ILT allocation */
 206         osal_mutex_t mutex;
 207
 208         /* SRC T2 */
 209         struct ecore_dma_mem *t2;
 210         u32 t2_num_pages;
 211         u64 first_free;
 212         u64 last_free;
 213
 214         /* The infrastructure originally was very generic and context/task
 215          * oriented - per connection-type we would set how many of those
 216          * are needed, and later when determining how much memory we're
 217          * needing for a given block we'd iterate over all the relevant
 218          * connection-types.
 219          * But since then we've had some additional resources, some of which
 220          * require memory which is indepent of the general context/task
 221          * scheme. We add those here explicitly per-feature.
 222          */
 223
 224         /* total number of SRQ's for this hwfn */
 225         u32                             srq_count;
 226
 227         /* Maximal number of L2 steering filters */
 228         u32                             arfs_count;
 229
 230         /* TODO - VF arfs filters ? */
 231 };
 232
 233 /* check if resources/configuration is required according to protocol type */
 234 static OSAL_INLINE bool src_proto(struct ecore_hwfn *p_hwfn,
 235                                   enum protocol_type type)
 236 {
 237         return type == PROTOCOLID_TOE;
 238 }
 239
 240 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 241 {
 242         return type == PROTOCOLID_TOE;
 243 }
 244
 245 static bool tm_tid_proto(enum protocol_type type)
 246 {
 247         return type == PROTOCOLID_FCOE;
 248 }
 249
 250 /* counts the iids for the CDU/CDUC ILT client configuration */
 251 struct ecore_cdu_iids {
 252         u32 pf_cids;
 253         u32 per_vf_cids;
 254 };
 255
 256 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 257                                struct ecore_cdu_iids *iids)
 258 {
 259         u32 type;
 260
 261         for (type = 0; type < MAX_CONN_TYPES; type++) {
 262                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 263                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 264         }
 265 }
 266
 267 /* counts the iids for the Searcher block configuration */
 268 struct ecore_src_iids {
 269         u32 pf_cids;
 270         u32 per_vf_cids;
 271 };
 272
 273 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_hwfn *p_hwfn,
 274                                            struct ecore_cxt_mngr *p_mngr,
 275                                            struct ecore_src_iids *iids)
 276 {
 277         u32 i;
 278
 279         for (i = 0; i < MAX_CONN_TYPES; i++) {
 280                 if (!src_proto(p_hwfn, i))
 281                         continue;
 282
 283                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 284                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 285         }
 286
 287         /* Add L2 filtering filters in addition */
 288         iids->pf_cids += p_mngr->arfs_count;
 289 }
 290
 291 /* counts the iids for the Timers block configuration */
 292 struct ecore_tm_iids {
 293         u32 pf_cids;
 294         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 295         u32 pf_tids_total;
 296         u32 per_vf_cids;
 297         u32 per_vf_tids;
 298 };
 299
 300 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 301                                           struct ecore_tm_iids *iids)
 302 {
 303         bool tm_vf_required = false;
 304         bool tm_required = false;
 305         u32 i, j;
 306
 307         for (i = 0; i < MAX_CONN_TYPES; i++) {
 308                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 309
 310                 if (tm_cid_proto(i) || tm_required) {
 311                         if (p_cfg->cid_count)
 312                                 tm_required = true;
 313
 314                         iids->pf_cids += p_cfg->cid_count;
 315                 }
 316
 317                 if (tm_cid_proto(i) || tm_vf_required) {
 318                         if (p_cfg->cids_per_vf)
 319                                 tm_vf_required = true;
 320
 321                 }
 322
 323                 if (tm_tid_proto(i)) {
 324                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 325
 326                         /* for each segment there is at most one
 327                          * protocol for which count is not 0.
 328                          */
 329                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 330                                 iids->pf_tids[j] += segs[j].count;
 331
 332                         /* The last array elelment is for the VFs. As for PF
 333                          * segments there can be only one protocol for
 334                          * which this value is not 0.
 335                          */
 336                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 337                 }
 338         }
 339
 340         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 341         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 342         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 343
 344         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 345                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 346                 iids->pf_tids_total += iids->pf_tids[j];
 347         }
 348 }
 349
 350 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
 351                               struct ecore_qm_iids *iids)
 352 {
 353         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 354         struct ecore_tid_seg *segs;
 355         u32 vf_cids = 0, type, j;
 356         u32 vf_tids = 0;
 357
 358         for (type = 0; type < MAX_CONN_TYPES; type++) {
 359                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 360                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 361
 362                 segs = p_mngr->conn_cfg[type].tid_seg;
 363                 /* for each segment there is at most one
 364                  * protocol for which count is not 0.
 365                  */
 366                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 367                         iids->tids += segs[j].count;
 368
 369                 /* The last array elelment is for the VFs. As for PF
 370                  * segments there can be only one protocol for
 371                  * which this value is not 0.
 372                  */
 373                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 374         }
 375
 376         iids->vf_cids += vf_cids * p_mngr->vf_count;
 377         iids->tids += vf_tids * p_mngr->vf_count;
 378
 379         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 380                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 381                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 382 }
 383
 384 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 385                                                     u32 seg)
 386 {
 387         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 388         u32 i;
 389
 390         /* Find the protocol with tid count > 0 for this segment.
 391          * Note: there can only be one and this is already validated.
 392          */
 393         for (i = 0; i < MAX_CONN_TYPES; i++) {
 394                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 395                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 396         }
 397         return OSAL_NULL;
 398 }
 399
 400 /* set the iids (cid/tid) count per protocol */
 401 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 402                                    enum protocol_type type,
 403                                    u32 cid_count, u32 vf_cid_cnt)
 404 {
 405         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 406         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 407
 408         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 409         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 410 }
 411
 412 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 413                                   enum protocol_type type, u32 *vf_cid)
 414 {
 415         if (vf_cid)
 416                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 417
 418         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 419 }
 420
 421 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 422                                   enum protocol_type type)
 423 {
 424         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 425 }
 426
 427 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 428                                          enum protocol_type type)
 429 {
 430         u32 cnt = 0;
 431         int i;
 432
 433         for (i = 0; i < TASK_SEGMENTS; i++)
 434                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 435
 436         return cnt;
 437 }
 438
 439 static OSAL_INLINE void
 440 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 441                               enum protocol_type proto,
 442                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 443 {
 444         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 445         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 446
 447         p_seg->count = count;
 448         p_seg->has_fl_mem = has_fl;
 449         p_seg->type = seg_type;
 450 }
 451
 452 /* the *p_line parameter must be either 0 for the first invocation or the
 453  * value returned in the previous invocation.
 454  */
 455 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 456                                    struct ecore_ilt_cli_blk *p_blk,
 457                                    u32 start_line,
 458                                    u32 total_size, u32 elem_size)
 459 {
 460         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 461
 462         /* verify that it's called once for each block */
 463         if (p_blk->total_size)
 464                 return;
 465
 466         p_blk->total_size = total_size;
 467         p_blk->real_size_in_page = 0;
 468         if (elem_size)
 469                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 470         p_blk->start_line = start_line;
 471 }
 472
 473 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 474                                    struct ecore_ilt_client_cfg *p_cli,
 475                                    struct ecore_ilt_cli_blk *p_blk,
 476                                    u32 *p_line, enum ilt_clients client_id)
 477 {
 478         if (!p_blk->total_size)
 479                 return;
 480
 481         if (!p_cli->active)
 482                 p_cli->first.val = *p_line;
 483
 484         p_cli->active = true;
 485         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 486         p_cli->last.val = *p_line - 1;
 487
 488         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 489                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 490                    " [Real %08x] Start line %d\n",
 491                    client_id, p_cli->first.val, p_cli->last.val,
 492                    p_blk->total_size, p_blk->real_size_in_page,
 493                    p_blk->start_line);
 494 }
 495
 496 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 497                                           enum ilt_clients ilt_client)
 498 {
 499         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 500         struct ecore_ilt_client_cfg *p_cli;
 501         u32 lines_to_skip = 0;
 502         u32 cxts_per_p;
 503
 504         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 505
 506         if (ilt_client == ILT_CLI_CDUC) {
 507                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 508
 509                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 510                     (u32)CONN_CXT_SIZE(p_hwfn);
 511
 512                 lines_to_skip = cid_count / cxts_per_p;
 513         }
 514
 515         return lines_to_skip;
 516 }
 517
 518 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 519 {
 520         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 521         u32 curr_line, total, i, task_size, line;
 522         struct ecore_ilt_client_cfg *p_cli;
 523         struct ecore_ilt_cli_blk *p_blk;
 524         struct ecore_cdu_iids cdu_iids;
 525         struct ecore_src_iids src_iids;
 526         struct ecore_qm_iids qm_iids;
 527         struct ecore_tm_iids tm_iids;
 528         struct ecore_tid_seg *p_seg;
 529
 530         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 531         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 532         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 533         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 534
 535         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 536
 537         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 538                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 539                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 540
 541         /* CDUC */
 542         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 543
 544         curr_line = p_mngr->pf_start_line;
 545
 546         /* CDUC PF */
 547         p_cli->pf_total_lines = 0;
 548
 549         /* get the counters for the CDUC,CDUC and QM clients  */
 550         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 551
 552         p_blk = &p_cli->pf_blks[CDUC_BLK];
 553
 554         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 555
 556         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 557                                total, CONN_CXT_SIZE(p_hwfn));
 558
 559         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 560         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 561
 562         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 563                                                                  ILT_CLI_CDUC);
 564
 565         /* CDUC VF */
 566         p_blk = &p_cli->vf_blks[CDUC_BLK];
 567         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 568
 569         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 570                                total, CONN_CXT_SIZE(p_hwfn));
 571
 572         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 573         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 574
 575         for (i = 1; i < p_mngr->vf_count; i++)
 576                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 577                                        ILT_CLI_CDUC);
 578
 579         /* CDUT PF */
 580         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 581         p_cli->first.val = curr_line;
 582
 583         /* first the 'working' task memory */
 584         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 585                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 586                 if (!p_seg || p_seg->count == 0)
 587                         continue;
 588
 589                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 590                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 591                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 592                                        p_mngr->task_type_size[p_seg->type]);
 593
 594                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 595                                        ILT_CLI_CDUT);
 596         }
 597
 598         /* next the 'init' task memory (forced load memory) */
 599         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 600                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 601                 if (!p_seg || p_seg->count == 0)
 602                         continue;
 603
 604                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 605
 606                 if (!p_seg->has_fl_mem) {
 607                         /* The segment is active (total size pf 'working'
 608                          * memory is > 0) but has no FL (forced-load, Init)
 609                          * memory. Thus:
 610                          *
 611                          * 1.   The total-size in the corrsponding FL block of
 612                          *      the ILT client is set to 0 - No ILT line are
 613                          *      provisioned and no ILT memory allocated.
 614                          *
 615                          * 2.   The start-line of said block is set to the
 616                          *      start line of the matching working memory
 617                          *      block in the ILT client. This is later used to
 618                          *      configure the CDU segment offset registers and
 619                          *      results in an FL command for TIDs of this
 620                          *      segment behaves as regular load commands
 621                          *      (loading TIDs from the working memory).
 622                          */
 623                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 624
 625                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 626                         continue;
 627                 }
 628                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 629
 630                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 631                                        curr_line, total,
 632                                        p_mngr->task_type_size[p_seg->type]);
 633
 634                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 635                                        ILT_CLI_CDUT);
 636         }
 637         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 638
 639         /* CDUT VF */
 640         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 641         if (p_seg && p_seg->count) {
 642                 /* Stricly speaking we need to iterate over all VF
 643                  * task segment types, but a VF has only 1 segment
 644                  */
 645
 646                 /* 'working' memory */
 647                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 648
 649                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 650                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 651                                        curr_line, total,
 652                                        p_mngr->task_type_size[p_seg->type]);
 653
 654                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 655                                        ILT_CLI_CDUT);
 656
 657                 /* 'init' memory */
 658                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 659                 if (!p_seg->has_fl_mem) {
 660                         /* see comment above */
 661                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 662                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 663                 } else {
 664                         task_size = p_mngr->task_type_size[p_seg->type];
 665                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 666                                                curr_line, total, task_size);
 667                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 668                                                ILT_CLI_CDUT);
 669                 }
 670                 p_cli->vf_total_lines = curr_line -
 671                     p_cli->vf_blks[0].start_line;
 672
 673                 /* Now for the rest of the VFs */
 674                 for (i = 1; i < p_mngr->vf_count; i++) {
 675                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 676                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 677                                                ILT_CLI_CDUT);
 678
 679                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 680                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 681                                                ILT_CLI_CDUT);
 682                 }
 683         }
 684
 685         /* QM */
 686         p_cli = &p_mngr->clients[ILT_CLI_QM];
 687         p_blk = &p_cli->pf_blks[0];
 688
 689         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 690         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 691                                      qm_iids.vf_cids, qm_iids.tids,
 692                                      p_hwfn->qm_info.num_pqs,
 693                                      p_hwfn->qm_info.num_vf_pqs);
 694
 695         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 696                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 697                    " num_vf_pqs=%d, memory_size=%d)\n",
 698                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 699                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 700
 701         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 702                                QM_PQ_ELEMENT_SIZE);
 703
 704         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 705         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 706
 707         /* SRC */
 708         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 709         ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
 710
 711         /* Both the PF and VFs searcher connections are stored in the per PF
 712          * database. Thus sum the PF searcher cids and all the VFs searcher
 713          * cids.
 714          */
 715         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 716         if (total) {
 717                 u32 local_max = OSAL_MAX_T(u32, total,
 718                                            SRC_MIN_NUM_ELEMS);
 719
 720                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 721
 722                 p_blk = &p_cli->pf_blks[0];
 723                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 724                                        total * sizeof(struct src_ent),
 725                                        sizeof(struct src_ent));
 726
 727                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 728                                        ILT_CLI_SRC);
 729                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 730         }
 731
 732         /* TM PF */
 733         p_cli = &p_mngr->clients[ILT_CLI_TM];
 734         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 735         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 736         if (total) {
 737                 p_blk = &p_cli->pf_blks[0];
 738                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 739                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 740
 741                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 742                                        ILT_CLI_TM);
 743                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 744         }
 745
 746         /* TM VF */
 747         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 748         if (total) {
 749                 p_blk = &p_cli->vf_blks[0];
 750                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 751                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 752
 753                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 754                                        ILT_CLI_TM);
 755
 756                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 757                 for (i = 1; i < p_mngr->vf_count; i++) {
 758                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 759                                                ILT_CLI_TM);
 760                 }
 761         }
 762
 763         /* TSDM (SRQ CONTEXT) */
 764         total = ecore_cxt_get_srq_count(p_hwfn);
 765
 766         if (total) {
 767                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 768                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 769                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 770                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 771
 772                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 773                                        ILT_CLI_TSDM);
 774                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 775         }
 776
 777         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 778             RESC_NUM(p_hwfn, ECORE_ILT)) {
 779                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 780                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 781                 return ECORE_INVAL;
 782         }
 783
 784         return ECORE_SUCCESS;
 785 }
 786
 787 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 788 {
 789         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 790         u32 i;
 791
 792         if (!p_mngr->t2)
 793                 return;
 794
 795         for (i = 0; i < p_mngr->t2_num_pages; i++)
 796                 if (p_mngr->t2[i].p_virt)
 797                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 798                                                p_mngr->t2[i].p_virt,
 799                                                p_mngr->t2[i].p_phys,
 800                                                p_mngr->t2[i].size);
 801
 802         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 803 }
 804
 805 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 806 {
 807         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 808         u32 conn_num, total_size, ent_per_page, psz, i;
 809         struct ecore_ilt_client_cfg *p_src;
 810         struct ecore_src_iids src_iids;
 811         struct ecore_dma_mem *p_t2;
 812         enum _ecore_status_t rc;
 813
 814         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 815
 816         /* if the SRC ILT client is inactive - there are no connection
 817          * requiring the searcer, leave.
 818          */
 819         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 820         if (!p_src->active)
 821                 return ECORE_SUCCESS;
 822
 823         ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
 824         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 825         total_size = conn_num * sizeof(struct src_ent);
 826
 827         /* use the same page size as the SRC ILT client */
 828         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 829         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 830
 831         /* allocate t2 */
 832         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 833                                  p_mngr->t2_num_pages *
 834                                  sizeof(struct ecore_dma_mem));
 835         if (!p_mngr->t2) {
 836                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 837                 rc = ECORE_NOMEM;
 838                 goto t2_fail;
 839         }
 840
 841         /* allocate t2 pages */
 842         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 843                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 844                 void **p_virt = &p_mngr->t2[i].p_virt;
 845
 846                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 847                                                   &p_mngr->t2[i].p_phys, size);
 848                 if (!p_mngr->t2[i].p_virt) {
 849                         rc = ECORE_NOMEM;
 850                         goto t2_fail;
 851                 }
 852                 OSAL_MEM_ZERO(*p_virt, size);
 853                 p_mngr->t2[i].size = size;
 854                 total_size -= size;
 855         }
 856
 857         /* Set the t2 pointers */
 858
 859         /* entries per page - must be a power of two */
 860         ent_per_page = psz / sizeof(struct src_ent);
 861
 862         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 863
 864         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 865         p_mngr->last_free = (u64)p_t2->p_phys +
 866             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 867
 868         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 869                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 870                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 871                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 872                 u32 j;
 873
 874                 for (j = 0; j < ent_num - 1; j++) {
 875                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 876                         entries[j].next = OSAL_CPU_TO_BE64(val);
 877                 }
 878
 879                 if (i < p_mngr->t2_num_pages - 1)
 880                         val = (u64)p_mngr->t2[i + 1].p_phys;
 881                 else
 882                         val = 0;
 883                 entries[j].next = OSAL_CPU_TO_BE64(val);
 884
 885                 conn_num -= ent_num;
 886         }
 887
 888         return ECORE_SUCCESS;
 889
 890 t2_fail:
 891         ecore_cxt_src_t2_free(p_hwfn);
 892         return rc;
 893 }
 894
 895 #define for_each_ilt_valid_client(pos, clients)         \
 896         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 897                 if (!clients[pos].active) {             \
 898                         continue;                       \
 899                 } else                                  \
 900
 901
 902 /* Total number of ILT lines used by this PF */
 903 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 904 {
 905         u32 size = 0;
 906         u32 i;
 907
 908         for_each_ilt_valid_client(i, ilt_clients)
 909                 size += (ilt_clients[i].last.val -
 910                          ilt_clients[i].first.val + 1);
 911
 912         return size;
 913 }
 914
 915 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 916 {
 917         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 918         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 919         u32 ilt_size, i;
 920
 921         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 922
 923         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 924                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 925
 926                 if (p_dma->p_virt)
 927                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 928                                                p_dma->p_virt,
 929                                                p_dma->p_phys, p_dma->size);
 930                 p_dma->p_virt = OSAL_NULL;
 931         }
 932         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 933 }
 934
 935 static enum _ecore_status_t
 936 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 937                     struct ecore_ilt_cli_blk *p_blk,
 938                     enum ilt_clients ilt_client, u32 start_line_offset)
 939 {
 940         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 941         u32 lines, line, sz_left, lines_to_skip = 0;
 942
 943         /* Special handling for RoCE that supports dynamic allocation */
 944         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 945                 return ECORE_SUCCESS;
 946
 947         lines_to_skip = p_blk->dynamic_line_cnt;
 948
 949         if (!p_blk->total_size)
 950                 return ECORE_SUCCESS;
 951
 952         sz_left = p_blk->total_size;
 953         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 954         line = p_blk->start_line + start_line_offset -
 955             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 956
 957         for (; lines; lines--) {
 958                 dma_addr_t p_phys;
 959                 void *p_virt;
 960                 u32 size;
 961
 962                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 963
 964 /* @DPDK */
 965 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 966                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 967                                                          &p_phys, size,
 968                                                          ILT_BLOCK_ALIGN_SIZE);
 969                 if (!p_virt)
 970                         return ECORE_NOMEM;
 971                 OSAL_MEM_ZERO(p_virt, size);
 972
 973                 ilt_shadow[line].p_phys = p_phys;
 974                 ilt_shadow[line].p_virt = p_virt;
 975                 ilt_shadow[line].size = size;
 976
 977                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 978                            "ILT shadow: Line [%d] Physical 0x%lx"
 979                            " Virtual %p Size %d\n",
 980                            line, (unsigned long)p_phys, p_virt, size);
 981
 982                 sz_left -= size;
 983                 line++;
 984         }
 985
 986         return ECORE_SUCCESS;
 987 }
 988
 989 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 990 {
 991         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 992         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 993         struct ecore_ilt_cli_blk *p_blk;
 994         u32 size, i, j, k;
 995         enum _ecore_status_t rc;
 996
 997         size = ecore_cxt_ilt_shadow_size(clients);
 998         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 999                                          size * sizeof(struct ecore_dma_mem));
1000
1001         if (!p_mngr->ilt_shadow) {
1002                 DP_NOTICE(p_hwfn, true,
1003                           "Failed to allocate ilt shadow table\n");
1004                 rc = ECORE_NOMEM;
1005                 goto ilt_shadow_fail;
1006         }
1007
1008         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1009                    "Allocated 0x%x bytes for ilt shadow\n",
1010                    (u32)(size * sizeof(struct ecore_dma_mem)));
1011
1012         for_each_ilt_valid_client(i, clients) {
1013                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1014                         p_blk = &clients[i].pf_blks[j];
1015                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1016                         if (rc != ECORE_SUCCESS)
1017                                 goto ilt_shadow_fail;
1018                 }
1019                 for (k = 0; k < p_mngr->vf_count; k++) {
1020                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1021                                 u32 lines = clients[i].vf_total_lines * k;
1022
1023                                 p_blk = &clients[i].vf_blks[j];
1024                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1025                                                          i, lines);
1026                                 if (rc != ECORE_SUCCESS)
1027                                         goto ilt_shadow_fail;
1028                         }
1029                 }
1030         }
1031
1032         return ECORE_SUCCESS;
1033
1034 ilt_shadow_fail:
1035         ecore_ilt_shadow_free(p_hwfn);
1036         return rc;
1037 }
1038
1039 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1040 {
1041         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1042         u32 type, vf;
1043
1044         for (type = 0; type < MAX_CONN_TYPES; type++) {
1045                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1046                 p_mngr->acquired[type].max_count = 0;
1047                 p_mngr->acquired[type].start_cid = 0;
1048
1049                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1050                         OSAL_FREE(p_hwfn->p_dev,
1051                                   p_mngr->acquired_vf[type][vf].cid_map);
1052                         p_mngr->acquired_vf[type][vf].max_count = 0;
1053                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1054                 }
1055         }
1056 }
1057
1058 static enum _ecore_status_t
1059 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1060                            u32 cid_start, u32 cid_count,
1061                            struct ecore_cid_acquired_map *p_map)
1062 {
1063         u32 size;
1064
1065         if (!cid_count)
1066                 return ECORE_SUCCESS;
1067
1068         size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1069         p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1070         if (p_map->cid_map == OSAL_NULL)
1071                 return ECORE_NOMEM;
1072
1073         p_map->max_count = cid_count;
1074         p_map->start_cid = cid_start;
1075
1076         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1077                    "Type %08x start: %08x count %08x\n",
1078                    type, p_map->start_cid, p_map->max_count);
1079
1080         return ECORE_SUCCESS;
1081 }
1082
1083 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1084 {
1085         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1086         u32 start_cid = 0, vf_start_cid = 0;
1087         u32 type, vf;
1088
1089         for (type = 0; type < MAX_CONN_TYPES; type++) {
1090                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1091                 struct ecore_cid_acquired_map *p_map;
1092
1093                 /* Handle PF maps */
1094                 p_map = &p_mngr->acquired[type];
1095                 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1096                                                p_cfg->cid_count, p_map))
1097                         goto cid_map_fail;
1098
1099                 /* Handle VF maps */
1100                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1101                         p_map = &p_mngr->acquired_vf[type][vf];
1102                         if (ecore_cid_map_alloc_single(p_hwfn, type,
1103                                                        vf_start_cid,
1104                                                        p_cfg->cids_per_vf,
1105                                                        p_map))
1106                                 goto cid_map_fail;
1107                 }
1108
1109                 start_cid += p_cfg->cid_count;
1110                 vf_start_cid += p_cfg->cids_per_vf;
1111         }
1112
1113         return ECORE_SUCCESS;
1114
1115 cid_map_fail:
1116         ecore_cid_map_free(p_hwfn);
1117         return ECORE_NOMEM;
1118 }
1119
1120 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1121 {
1122         struct ecore_ilt_client_cfg *clients;
1123         struct ecore_cxt_mngr *p_mngr;
1124         u32 i;
1125
1126         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1127         if (!p_mngr) {
1128                 DP_NOTICE(p_hwfn, true,
1129                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1130                 return ECORE_NOMEM;
1131         }
1132
1133         /* Initialize ILT client registers */
1134         clients = p_mngr->clients;
1135         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1136         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1137         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1138
1139         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1140         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1141         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1142
1143         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1144         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1145         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1146
1147         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1148         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1149         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1150
1151         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1152         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1153         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1154
1155         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1156         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1157         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1158
1159         /* default ILT page size for all clients is 32K */
1160         for (i = 0; i < ILT_CLI_MAX; i++)
1161                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1162
1163         /* due to removal of ISCSI/FCoE files union type0_task_context
1164          * task_type_size will be 0. So hardcoded for now.
1165          */
1166         p_mngr->task_type_size[0] = 512; /* @DPDK */
1167         p_mngr->task_type_size[1] = 128; /* @DPDK */
1168
1169         if (p_hwfn->p_dev->p_iov_info)
1170                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1171
1172         /* Initialize the dynamic ILT allocation mutex */
1173 #ifdef CONFIG_ECORE_LOCK_ALLOC
1174         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1175 #endif
1176         OSAL_MUTEX_INIT(&p_mngr->mutex);
1177
1178         /* Set the cxt mangr pointer priori to further allocations */
1179         p_hwfn->p_cxt_mngr = p_mngr;
1180
1181         return ECORE_SUCCESS;
1182 }
1183
1184 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1185 {
1186         enum _ecore_status_t rc;
1187
1188         /* Allocate the ILT shadow table */
1189         rc = ecore_ilt_shadow_alloc(p_hwfn);
1190         if (rc) {
1191                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1192                 goto tables_alloc_fail;
1193         }
1194
1195         /* Allocate the T2  table */
1196         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1197         if (rc) {
1198                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1199                 goto tables_alloc_fail;
1200         }
1201
1202         /* Allocate and initialize the acquired cids bitmaps */
1203         rc = ecore_cid_map_alloc(p_hwfn);
1204         if (rc) {
1205                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1206                 goto tables_alloc_fail;
1207         }
1208
1209         return ECORE_SUCCESS;
1210
1211 tables_alloc_fail:
1212         ecore_cxt_mngr_free(p_hwfn);
1213         return rc;
1214 }
1215
1216 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1217 {
1218         if (!p_hwfn->p_cxt_mngr)
1219                 return;
1220
1221         ecore_cid_map_free(p_hwfn);
1222         ecore_cxt_src_t2_free(p_hwfn);
1223         ecore_ilt_shadow_free(p_hwfn);
1224 #ifdef CONFIG_ECORE_LOCK_ALLOC
1225         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1226 #endif
1227         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1228 }
1229
1230 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1231 {
1232         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1233         struct ecore_cid_acquired_map *p_map;
1234         struct ecore_conn_type_cfg *p_cfg;
1235         int type;
1236         u32 len;
1237
1238         /* Reset acquired cids */
1239         for (type = 0; type < MAX_CONN_TYPES; type++) {
1240                 u32 vf;
1241
1242                 p_cfg = &p_mngr->conn_cfg[type];
1243                 if (p_cfg->cid_count) {
1244                         p_map = &p_mngr->acquired[type];
1245                         len = DIV_ROUND_UP(p_map->max_count,
1246                                            BITS_PER_MAP_WORD) *
1247                               MAP_WORD_SIZE;
1248                         OSAL_MEM_ZERO(p_map->cid_map, len);
1249                 }
1250
1251                 if (!p_cfg->cids_per_vf)
1252                         continue;
1253
1254                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1255                         p_map = &p_mngr->acquired_vf[type][vf];
1256                         len = DIV_ROUND_UP(p_map->max_count,
1257                                            BITS_PER_MAP_WORD) *
1258                               MAP_WORD_SIZE;
1259                         OSAL_MEM_ZERO(p_map->cid_map, len);
1260                 }
1261         }
1262 }
1263
1264 /* HW initialization helper (per Block, per phase) */
1265
1266 /* CDU Common */
1267 #define CDUC_CXT_SIZE_SHIFT                                             \
1268         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1269
1270 #define CDUC_CXT_SIZE_MASK                                              \
1271         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1272
1273 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1274         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1275
1276 #define CDUC_BLOCK_WASTE_MASK                                           \
1277         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1278
1279 #define CDUC_NCIB_SHIFT                                                 \
1280         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1281
1282 #define CDUC_NCIB_MASK                                                  \
1283         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1284
1285 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1286         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1287
1288 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1289         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1290         CDUT_TYPE0_CXT_SIZE_SHIFT)
1291
1292 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1293         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1294
1295 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1296         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1297         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1298
1299 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1300         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1301
1302 #define CDUT_TYPE0_NCIB_MASK                                            \
1303         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1304         CDUT_TYPE0_NCIB_SHIFT)
1305
1306 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1307         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1308
1309 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1310         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1311         CDUT_TYPE1_CXT_SIZE_SHIFT)
1312
1313 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1314         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1315
1316 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1317         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1318         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1319
1320 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1321         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1322
1323 #define CDUT_TYPE1_NCIB_MASK                                            \
1324         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1325         CDUT_TYPE1_NCIB_SHIFT)
1326
1327 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1328 {
1329         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1330
1331         /* CDUC - connection configuration */
1332         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1333         cxt_size = CONN_CXT_SIZE(p_hwfn);
1334         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1335         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1336
1337         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1338         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1339         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1340         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1341
1342         /* CDUT - type-0 tasks configuration */
1343         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1344         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1345         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1346         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1347
1348         /* cxt size and block-waste are multipes of 8 */
1349         cdu_params = 0;
1350         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1351         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1352         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1353         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1354
1355         /* CDUT - type-1 tasks configuration */
1356         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1357         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1358         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1359
1360         /* cxt size and block-waste are multipes of 8 */
1361         cdu_params = 0;
1362         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1363         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1364         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1365         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1366 }
1367
1368 /* CDU PF */
1369 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1370 #define CDU_SEG_REG_TYPE_MASK           0x1
1371 #define CDU_SEG_REG_OFFSET_SHIFT        0
1372 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1373
1374 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1375 {
1376         struct ecore_ilt_client_cfg *p_cli;
1377         struct ecore_tid_seg *p_seg;
1378         u32 cdu_seg_params, offset;
1379         int i;
1380
1381         static const u32 rt_type_offset_arr[] = {
1382                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1383                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1384                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1385                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1386         };
1387
1388         static const u32 rt_type_offset_fl_arr[] = {
1389                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1390                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1391                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1392                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1393         };
1394
1395         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1396
1397         /* There are initializations only for CDUT during pf Phase */
1398         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1399                 /* Segment 0 */
1400                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1401                 if (!p_seg)
1402                         continue;
1403
1404                 /* Note: start_line is already adjusted for the CDU
1405                  * segment register granularity, so we just need to
1406                  * divide. Adjustment is implicit as we assume ILT
1407                  * Page size is larger than 32K!
1408                  */
1409                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1410                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1411                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1412
1413                 cdu_seg_params = 0;
1414                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1415                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1416                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1417
1418                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1419                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1420                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1421
1422                 cdu_seg_params = 0;
1423                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1424                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1425                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1426         }
1427 }
1428
1429 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1430 {
1431         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1432         struct ecore_qm_iids iids;
1433
1434         OSAL_MEM_ZERO(&iids, sizeof(iids));
1435         ecore_cxt_qm_iids(p_hwfn, &iids);
1436
1437         ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id,
1438                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1439                             p_hwfn->first_on_engine,
1440                             iids.cids, iids.vf_cids, iids.tids,
1441                             qm_info->start_pq,
1442                             qm_info->num_pqs - qm_info->num_vf_pqs,
1443                             qm_info->num_vf_pqs,
1444                             qm_info->start_vport,
1445                             qm_info->num_vports, qm_info->pf_wfq,
1446                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1447                             p_hwfn->qm_info.qm_vport_params);
1448 }
1449
1450 /* CM PF */
1451 void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1452 {
1453         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1454                      ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1455 }
1456
1457 /* DQ PF */
1458 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1459 {
1460         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1461         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1462
1463         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1464         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1465
1466         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1467         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1468
1469         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1470         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1471
1472         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1473         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1474
1475         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1476         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1477
1478         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1479         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1480
1481         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1482         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1483
1484         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1485         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1486
1487         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1488         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1489
1490         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1491         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1492
1493         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1494         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1495
1496         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1497         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1498
1499         /* Connection types 6 & 7 are not in use, yet they must be configured
1500          * as the highest possible connection. Not configuring them means the
1501          * defaults will be  used, and with a large number of cids a bug may
1502          * occur, if the defaults will be smaller than dq_pf_max_cid /
1503          * dq_vf_max_cid.
1504          */
1505         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1506         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1507
1508         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1509         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1510 }
1511
1512 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1513 {
1514         struct ecore_ilt_client_cfg *ilt_clients;
1515         int i;
1516
1517         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1518         for_each_ilt_valid_client(i, ilt_clients) {
1519                 STORE_RT_REG(p_hwfn,
1520                              ilt_clients[i].first.reg,
1521                              ilt_clients[i].first.val);
1522                 STORE_RT_REG(p_hwfn,
1523                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1524                 STORE_RT_REG(p_hwfn,
1525                              ilt_clients[i].p_size.reg,
1526                              ilt_clients[i].p_size.val);
1527         }
1528 }
1529
1530 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1531 {
1532         struct ecore_ilt_client_cfg *p_cli;
1533         u32 blk_factor;
1534
1535         /* For simplicty  we set the 'block' to be an ILT page */
1536         if (p_hwfn->p_dev->p_iov_info) {
1537                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1538
1539                 STORE_RT_REG(p_hwfn,
1540                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1541                              p_iov->first_vf_in_pf);
1542                 STORE_RT_REG(p_hwfn,
1543                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1544                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1545         }
1546
1547         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1548         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1549         if (p_cli->active) {
1550                 STORE_RT_REG(p_hwfn,
1551                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1552                              blk_factor);
1553                 STORE_RT_REG(p_hwfn,
1554                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1555                              p_cli->pf_total_lines);
1556                 STORE_RT_REG(p_hwfn,
1557                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1558                              p_cli->vf_total_lines);
1559         }
1560
1561         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1562         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1563         if (p_cli->active) {
1564                 STORE_RT_REG(p_hwfn,
1565                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1566                              blk_factor);
1567                 STORE_RT_REG(p_hwfn,
1568                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1569                              p_cli->pf_total_lines);
1570                 STORE_RT_REG(p_hwfn,
1571                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1572                              p_cli->vf_total_lines);
1573         }
1574
1575         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1576         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1577         if (p_cli->active) {
1578                 STORE_RT_REG(p_hwfn,
1579                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1580                 STORE_RT_REG(p_hwfn,
1581                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1582                              p_cli->pf_total_lines);
1583                 STORE_RT_REG(p_hwfn,
1584                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1585                              p_cli->vf_total_lines);
1586         }
1587 }
1588
1589 /* ILT (PSWRQ2) PF */
1590 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1591 {
1592         struct ecore_ilt_client_cfg *clients;
1593         struct ecore_cxt_mngr *p_mngr;
1594         struct ecore_dma_mem *p_shdw;
1595         u32 line, rt_offst, i;
1596
1597         ecore_ilt_bounds_init(p_hwfn);
1598         ecore_ilt_vf_bounds_init(p_hwfn);
1599
1600         p_mngr = p_hwfn->p_cxt_mngr;
1601         p_shdw = p_mngr->ilt_shadow;
1602         clients = p_hwfn->p_cxt_mngr->clients;
1603
1604         for_each_ilt_valid_client(i, clients) {
1605                 /* Client's 1st val and RT array are absolute, ILT shadows'
1606                  * lines are relative.
1607                  */
1608                 line = clients[i].first.val - p_mngr->pf_start_line;
1609                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1610                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1611
1612                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1613                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1614                         u64 ilt_hw_entry = 0;
1615
1616                         /** p_virt could be OSAL_NULL incase of dynamic
1617                          *  allocation
1618                          */
1619                         if (p_shdw[line].p_virt != OSAL_NULL) {
1620                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1621                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1622                                           (p_shdw[line].p_phys >> 12));
1623
1624                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1625                                         "Setting RT[0x%08x] from"
1626                                         " ILT[0x%08x] [Client is %d] to"
1627                                         " Physical addr: 0x%lx\n",
1628                                         rt_offst, line, i,
1629                                         (unsigned long)(p_shdw[line].
1630                                                         p_phys >> 12));
1631                         }
1632
1633                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1634                 }
1635         }
1636 }
1637
1638 /* SRC (Searcher) PF */
1639 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1640 {
1641         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1642         u32 rounded_conn_num, conn_num, conn_max;
1643         struct ecore_src_iids src_iids;
1644
1645         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1646         ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
1647         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1648         if (!conn_num)
1649                 return;
1650
1651         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1652         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1653
1654         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1655         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1656                      OSAL_LOG2(rounded_conn_num));
1657
1658         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1659                          p_hwfn->p_cxt_mngr->first_free);
1660         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1661                          p_hwfn->p_cxt_mngr->last_free);
1662         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1663                    "Configured SEARCHER for 0x%08x connections\n",
1664                    conn_num);
1665 }
1666
1667 /* Timers PF */
1668 #define TM_CFG_NUM_IDS_SHIFT            0
1669 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1670 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1671 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1672 #define TM_CFG_PARENT_PF_SHIFT          25
1673 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1674
1675 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1676 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1677
1678 #define TM_CFG_TID_OFFSET_SHIFT         30
1679 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1680 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1681 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1682
1683 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1684 {
1685         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1686         u32 active_seg_mask = 0, tm_offset, rt_reg;
1687         struct ecore_tm_iids tm_iids;
1688         u64 cfg_word;
1689         u8 i;
1690
1691         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1692         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1693
1694         /* @@@TBD No pre-scan for now */
1695
1696         /* Note: We assume consecutive VFs for a PF */
1697         for (i = 0; i < p_mngr->vf_count; i++) {
1698                 cfg_word = 0;
1699                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1700                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1701                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1702                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1703
1704                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1705                     (sizeof(cfg_word) / sizeof(u32)) *
1706                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1707                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1708         }
1709
1710         cfg_word = 0;
1711         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1712         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1713         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1714         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1715
1716         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1717             (sizeof(cfg_word) / sizeof(u32)) *
1718             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1719         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1720
1721         /* enale scan */
1722         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1723                      tm_iids.pf_cids ? 0x1 : 0x0);
1724
1725         /* @@@TBD how to enable the scan for the VFs */
1726
1727         tm_offset = tm_iids.per_vf_cids;
1728
1729         /* Note: We assume consecutive VFs for a PF */
1730         for (i = 0; i < p_mngr->vf_count; i++) {
1731                 cfg_word = 0;
1732                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1733                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1734                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1735                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1736                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1737
1738                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1739                     (sizeof(cfg_word) / sizeof(u32)) *
1740                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1741
1742                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1743         }
1744
1745         tm_offset = tm_iids.pf_cids;
1746         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1747                 cfg_word = 0;
1748                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1749                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1750                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1751                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1752                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1753
1754                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1755                     (sizeof(cfg_word) / sizeof(u32)) *
1756                     (NUM_OF_VFS(p_hwfn->p_dev) +
1757                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1758
1759                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1760                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1761
1762                 tm_offset += tm_iids.pf_tids[i];
1763         }
1764
1765         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1766
1767         /* @@@TBD how to enable the scan for the VFs */
1768 }
1769
1770 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1771 {
1772         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1773         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1774         struct ecore_tid_seg *p_tid;
1775
1776         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1777         if (!p_fcoe->cid_count)
1778                 return;
1779
1780         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1781         STORE_RT_REG_AGG(p_hwfn,
1782                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1783                         p_tid->count);
1784 }
1785
1786 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1787 {
1788         /* CDU configuration */
1789         ecore_cdu_init_common(p_hwfn);
1790 }
1791
1792 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1793 {
1794         ecore_qm_init_pf(p_hwfn, p_ptt);
1795         ecore_cm_init_pf(p_hwfn);
1796         ecore_dq_init_pf(p_hwfn);
1797         ecore_cdu_init_pf(p_hwfn);
1798         ecore_ilt_init_pf(p_hwfn);
1799         ecore_src_init_pf(p_hwfn);
1800         ecore_tm_init_pf(p_hwfn);
1801         ecore_prs_init_pf(p_hwfn);
1802 }
1803
1804 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1805                                             enum protocol_type type,
1806                                             u32 *p_cid, u8 vfid)
1807 {
1808         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1809         struct ecore_cid_acquired_map *p_map;
1810         u32 rel_cid;
1811
1812         if (type >= MAX_CONN_TYPES) {
1813                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1814                 return ECORE_INVAL;
1815         }
1816
1817         if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1818                 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1819                 return ECORE_INVAL;
1820         }
1821
1822         /* Determine the right map to take this CID from */
1823         if (vfid == ECORE_CXT_PF_CID)
1824                 p_map = &p_mngr->acquired[type];
1825         else
1826                 p_map = &p_mngr->acquired_vf[type][vfid];
1827
1828         if (p_map->cid_map == OSAL_NULL) {
1829                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1830                 return ECORE_INVAL;
1831         }
1832
1833         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1834                                            p_map->max_count);
1835
1836         if (rel_cid >= p_map->max_count) {
1837                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1838                           type);
1839                 return ECORE_NORESOURCES;
1840         }
1841
1842         OSAL_SET_BIT(rel_cid, p_map->cid_map);
1843
1844         *p_cid = rel_cid + p_map->start_cid;
1845
1846         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1847                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1848                    *p_cid, rel_cid, vfid, type);
1849
1850         return ECORE_SUCCESS;
1851 }
1852
1853 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1854                                            enum protocol_type type,
1855                                            u32 *p_cid)
1856 {
1857         return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1858 }
1859
1860 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1861                                         u32 cid, u8 vfid,
1862                                         enum protocol_type *p_type,
1863                                         struct ecore_cid_acquired_map **pp_map)
1864 {
1865         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1866         u32 rel_cid;
1867
1868         /* Iterate over protocols and find matching cid range */
1869         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1870                 if (vfid == ECORE_CXT_PF_CID)
1871                         *pp_map = &p_mngr->acquired[*p_type];
1872                 else
1873                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1874
1875                 if (!((*pp_map)->cid_map))
1876                         continue;
1877                 if (cid >= (*pp_map)->start_cid &&
1878                     cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1879                         break;
1880                 }
1881         }
1882         if (*p_type == MAX_CONN_TYPES) {
1883                 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1884                 goto fail;
1885         }
1886
1887         rel_cid = cid - (*pp_map)->start_cid;
1888         if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1889                 DP_NOTICE(p_hwfn, true,
1890                           "CID %d [vifd %02x] not acquired", cid, vfid);
1891                 goto fail;
1892         }
1893
1894         return true;
1895 fail:
1896         *p_type = MAX_CONN_TYPES;
1897         *pp_map = OSAL_NULL;
1898         return false;
1899 }
1900
1901 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1902 {
1903         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1904         enum protocol_type type;
1905         bool b_acquired;
1906         u32 rel_cid;
1907
1908         if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1909                 DP_NOTICE(p_hwfn, true,
1910                           "Trying to return incorrect CID belonging to VF %02x\n",
1911                           vfid);
1912                 return;
1913         }
1914
1915         /* Test acquired and find matching per-protocol map */
1916         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1917                                                  &type, &p_map);
1918
1919         if (!b_acquired)
1920                 return;
1921
1922         rel_cid = cid - p_map->start_cid;
1923         OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1924
1925         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1926                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1927                    cid, rel_cid, vfid, type);
1928 }
1929
1930 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1931 {
1932         _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1933 }
1934
1935 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1936                                             struct ecore_cxt_info *p_info)
1937 {
1938         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1939         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1940         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1941         enum protocol_type type;
1942         bool b_acquired;
1943
1944         /* Test acquired and find matching per-protocol map */
1945         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1946                                                  ECORE_CXT_PF_CID,
1947                                                  &type, &p_map);
1948
1949         if (!b_acquired)
1950                 return ECORE_INVAL;
1951
1952         /* set the protocl type */
1953         p_info->type = type;
1954
1955         /* compute context virtual pointer */
1956         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1957
1958         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1959         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1960         line = p_info->iid / cxts_per_p;
1961
1962         /* Make sure context is allocated (dynamic allocation) */
1963         if (!p_mngr->ilt_shadow[line].p_virt)
1964                 return ECORE_INVAL;
1965
1966         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1967             p_info->iid % cxts_per_p * conn_cxt_size;
1968
1969         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1970                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1971                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1972
1973         return ECORE_SUCCESS;
1974 }
1975
1976 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1977 {
1978         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1979
1980         p_mgr->srq_count = num_srqs;
1981 }
1982
1983 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1984 {
1985         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1986
1987         return p_mgr->srq_count;
1988 }
1989
1990 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1991 {
1992         /* Set the number of required CORE connections */
1993         u32 core_cids = 1;      /* SPQ */
1994
1995         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1996
1997         switch (p_hwfn->hw_info.personality) {
1998         case ECORE_PCI_ETH:
1999                 {
2000                 struct ecore_eth_pf_params *p_params =
2001                             &p_hwfn->pf_params.eth_pf_params;
2002
2003                 if (!p_params->num_vf_cons)
2004                         p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
2005                 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2006                                               p_params->num_cons,
2007                                               p_params->num_vf_cons);
2008                 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2009                 break;
2010                 }
2011         default:
2012                 return ECORE_INVAL;
2013         }
2014
2015         return ECORE_SUCCESS;
2016 }
2017
2018 /* This function is very RoCE oriented, if another protocol in the future
2019  * will want this feature we'll need to modify the function to be more generic
2020  */
2021 enum _ecore_status_t
2022 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2023                             enum ecore_cxt_elem_type elem_type,
2024                             u32 iid)
2025 {
2026         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2027         struct ecore_ilt_client_cfg *p_cli;
2028         struct ecore_ilt_cli_blk *p_blk;
2029         struct ecore_ptt *p_ptt;
2030         dma_addr_t p_phys;
2031         u64 ilt_hw_entry;
2032         void *p_virt;
2033         enum _ecore_status_t rc = ECORE_SUCCESS;
2034
2035         switch (elem_type) {
2036         case ECORE_ELEM_CXT:
2037                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2038                 elem_size = CONN_CXT_SIZE(p_hwfn);
2039                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2040                 break;
2041         case ECORE_ELEM_SRQ:
2042                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2043                 elem_size = SRQ_CXT_SIZE;
2044                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2045                 break;
2046         case ECORE_ELEM_TASK:
2047                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2048                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2049                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2050                 break;
2051         default:
2052                 DP_NOTICE(p_hwfn, false,
2053                           "ECORE_INVALID elem type = %d", elem_type);
2054                 return ECORE_INVAL;
2055         }
2056
2057         /* Calculate line in ilt */
2058         hw_p_size = p_cli->p_size.val;
2059         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2060         line = p_blk->start_line + (iid / elems_per_p);
2061         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2062
2063         /* If line is already allocated, do nothing, otherwise allocate it and
2064          * write it to the PSWRQ2 registers.
2065          * This section can be run in parallel from different contexts and thus
2066          * a mutex protection is needed.
2067          */
2068
2069         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2070
2071         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2072                 goto out0;
2073
2074         p_ptt = ecore_ptt_acquire(p_hwfn);
2075         if (!p_ptt) {
2076                 DP_NOTICE(p_hwfn, false,
2077                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2078                 rc = ECORE_TIMEOUT;
2079                 goto out0;
2080         }
2081
2082         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2083                                          &p_phys,
2084                                          p_blk->real_size_in_page);
2085         if (!p_virt) {
2086                 rc = ECORE_NOMEM;
2087                 goto out1;
2088         }
2089         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2090
2091         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2092         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2093         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2094                 p_blk->real_size_in_page;
2095
2096         /* compute absolute offset */
2097         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2098                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2099
2100         ilt_hw_entry = 0;
2101         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2102         SET_FIELD(ilt_hw_entry,
2103                   ILT_ENTRY_PHY_ADDR,
2104                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2105
2106 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2107
2108         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2109                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2110                             0 /* no flags */);
2111
2112         if (elem_type == ECORE_ELEM_CXT) {
2113                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2114                                          elems_per_p;
2115
2116                 /* Update the relevant register in the parser */
2117                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2118                          last_cid_allocated - 1);
2119
2120                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2121                         /* Enable RoCE search */
2122                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2123                         p_hwfn->b_rdma_enabled_in_prs = true;
2124                 }
2125         }
2126
2127 out1:
2128         ecore_ptt_release(p_hwfn, p_ptt);
2129 out0:
2130         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2131
2132         return rc;
2133 }
2134
2135 /* This function is very RoCE oriented, if another protocol in the future
2136  * will want this feature we'll need to modify the function to be more generic
2137  */
2138 static enum _ecore_status_t
2139 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2140                          enum ecore_cxt_elem_type elem_type,
2141                          u32 start_iid, u32 count)
2142 {
2143         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2144         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2145         struct ecore_ilt_client_cfg *p_cli;
2146         struct ecore_ilt_cli_blk *p_blk;
2147         u32 end_iid = start_iid + count;
2148         struct ecore_ptt *p_ptt;
2149         u64 ilt_hw_entry = 0;
2150         u32 i;
2151
2152         switch (elem_type) {
2153         case ECORE_ELEM_CXT:
2154                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2155                 elem_size = CONN_CXT_SIZE(p_hwfn);
2156                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2157                 break;
2158         case ECORE_ELEM_SRQ:
2159                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2160                 elem_size = SRQ_CXT_SIZE;
2161                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2162                 break;
2163         case ECORE_ELEM_TASK:
2164                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2165                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2166                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2167                 break;
2168         default:
2169                 DP_NOTICE(p_hwfn, false,
2170                           "ECORE_INVALID elem type = %d", elem_type);
2171                 return ECORE_INVAL;
2172         }
2173
2174         /* Calculate line in ilt */
2175         hw_p_size = p_cli->p_size.val;
2176         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2177         start_line = p_blk->start_line + (start_iid / elems_per_p);
2178         end_line = p_blk->start_line + (end_iid / elems_per_p);
2179         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2180                 end_line--;
2181
2182         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2183         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2184
2185         p_ptt = ecore_ptt_acquire(p_hwfn);
2186         if (!p_ptt) {
2187                 DP_NOTICE(p_hwfn, false,
2188                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2189                 return ECORE_TIMEOUT;
2190         }
2191
2192         for (i = shadow_start_line; i < shadow_end_line; i++) {
2193                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2194                         continue;
2195
2196                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2197                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2198                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2199                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2200
2201                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2202                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2203                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2204
2205                 /* compute absolute offset */
2206                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2207                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2208                      ILT_ENTRY_IN_REGS);
2209
2210                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2211                  * wide-bus.
2212                  */
2213                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2214                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2215                                     reg_offset,
2216                                     sizeof(ilt_hw_entry) / sizeof(u32),
2217                                     0 /* no flags */);
2218         }
2219
2220         ecore_ptt_release(p_hwfn, p_ptt);
2221
2222         return ECORE_SUCCESS;
2223 }
2224
2225 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2226                                               enum protocol_type proto)
2227 {
2228         enum _ecore_status_t rc;
2229         u32 cid;
2230
2231         /* Free Connection CXT */
2232         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2233                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2234                                                                     proto),
2235                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2236                                                                     proto,
2237                                                                     &cid));
2238
2239         if (rc)
2240                 return rc;
2241
2242         /* Free Task CXT */
2243         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2244                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2245                                                                     proto));
2246         if (rc)
2247                 return rc;
2248
2249         /* Free TSDM CXT */
2250         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2251                                       ecore_cxt_get_srq_count(p_hwfn));
2252
2253         return rc;
2254 }