drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 ecore_cxt_mngr_free(p_hwfn);
 159                 ecore_qm_info_free(p_hwfn);
 160                 ecore_spq_free(p_hwfn);
 161                 ecore_eq_free(p_hwfn);
 162                 ecore_consq_free(p_hwfn);
 163                 ecore_int_free(p_hwfn);
 164                 ecore_iov_free(p_hwfn);
 165                 ecore_dmae_info_free(p_hwfn);
 166                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 167                 /* @@@TBD Flush work-queue ? */
 168         }
 169 }
 170
 171 /******************** QM initialization *******************/
 172
 173 /* bitmaps for indicating active traffic classes.
 174  * Special case for Arrowhead 4 port
 175  */
 176 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 177 #define ACTIVE_TCS_BMAP 0x9f
 178 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 179 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 180
 181 /* determines the physical queue flags for a given PF. */
 182 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 183 {
 184         u32 flags;
 185
 186         /* common flags */
 187         flags = PQ_FLAGS_LB;
 188
 189         /* feature flags */
 190         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 191                 flags |= PQ_FLAGS_VFS;
 192
 193         /* protocol flags */
 194         switch (p_hwfn->hw_info.personality) {
 195         case ECORE_PCI_ETH:
 196                 flags |= PQ_FLAGS_MCOS;
 197                 break;
 198         case ECORE_PCI_FCOE:
 199                 flags |= PQ_FLAGS_OFLD;
 200                 break;
 201         case ECORE_PCI_ISCSI:
 202                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 203                 break;
 204         case ECORE_PCI_ETH_ROCE:
 205                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 206                 break;
 207         case ECORE_PCI_ETH_IWARP:
 208                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 209                          PQ_FLAGS_OFLD;
 210                 break;
 211         default:
 212                 DP_ERR(p_hwfn, "unknown personality %d\n",
 213                        p_hwfn->hw_info.personality);
 214                 return 0;
 215         }
 216         return flags;
 217 }
 218
 219 /* Getters for resource amounts necessary for qm initialization */
 220 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 221 {
 222         return p_hwfn->hw_info.num_hw_tc;
 223 }
 224
 225 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 226 {
 227         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 228                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 229 }
 230
 231 #define NUM_DEFAULT_RLS 1
 232
 233 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 234 {
 235         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 236
 237         /* @DPDK */
 238         /* num RLs can't exceed resource amount of rls or vports or the
 239          * dcqcn qps
 240          */
 241         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 242                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 243
 244         /* make sure after we reserve the default and VF rls we'll have
 245          * something left
 246          */
 247         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 248                 DP_NOTICE(p_hwfn, false,
 249                           "no rate limiters left for PF rate limiting"
 250                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 251                 return 0;
 252         }
 253
 254         /* subtract rls necessary for VFs and one default one for the PF */
 255         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 256
 257         return num_pf_rls;
 258 }
 259
 260 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 261 {
 262         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 263
 264         /* all pqs share the same vport (hence the 1 below), except for vfs
 265          * and pf_rl pqs
 266          */
 267         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 268                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 269                (!!(PQ_FLAGS_VFS & pq_flags)) *
 270                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 271 }
 272
 273 /* calc amount of PQs according to the requested flags */
 274 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 275 {
 276         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 277
 278         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 279                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 280                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 281                 ecore_init_qm_get_num_tcs(p_hwfn) +
 282                (!!(PQ_FLAGS_LB & pq_flags)) +
 283                (!!(PQ_FLAGS_OOO & pq_flags)) +
 284                (!!(PQ_FLAGS_ACK & pq_flags)) +
 285                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 286                (!!(PQ_FLAGS_VFS & pq_flags)) *
 287                 ecore_init_qm_get_num_vfs(p_hwfn);
 288 }
 289
 290 /* initialize the top level QM params */
 291 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 292 {
 293         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 294
 295         /* pq and vport bases for this PF */
 296         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 297         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 298
 299         /* rate limiting and weighted fair queueing are always enabled */
 300         qm_info->vport_rl_en = 1;
 301         qm_info->vport_wfq_en = 1;
 302
 303         /* in AH 4 port we have fewer TCs per port */
 304         qm_info->max_phys_tcs_per_port =
 305                 p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2 ?
 306                         NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
 307 }
 308
 309 /* initialize qm vport params */
 310 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 311 {
 312         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 313         u8 i;
 314
 315         /* all vports participate in weighted fair queueing */
 316         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 317                 qm_info->qm_vport_params[i].vport_wfq = 1;
 318 }
 319
 320 /* initialize qm port params */
 321 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 322 {
 323         /* Initialize qm port parameters */
 324         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 325
 326         /* indicate how ooo and high pri traffic is dealt with */
 327         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 328                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 329
 330         for (i = 0; i < num_ports; i++) {
 331                 struct init_qm_port_params *p_qm_port =
 332                         &p_hwfn->qm_info.qm_port_params[i];
 333
 334                 p_qm_port->active = 1;
 335                 p_qm_port->active_phys_tcs = active_phys_tcs;
 336                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 337                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 338         }
 339 }
 340
 341 /* Reset the params which must be reset for qm init. QM init may be called as
 342  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 343  * params may be affected by the init but would simply recalculate to the same
 344  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 345  * affected as these amounts stay the same.
 346  */
 347 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 348 {
 349         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 350
 351         qm_info->num_pqs = 0;
 352         qm_info->num_vports = 0;
 353         qm_info->num_pf_rls = 0;
 354         qm_info->num_vf_pqs = 0;
 355         qm_info->first_vf_pq = 0;
 356         qm_info->first_mcos_pq = 0;
 357         qm_info->first_rl_pq = 0;
 358 }
 359
 360 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 361 {
 362         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 363
 364         qm_info->num_vports++;
 365
 366         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 367                 DP_ERR(p_hwfn,
 368                        "vport overflow! qm_info->num_vports %d,"
 369                        " qm_init_get_num_vports() %d\n",
 370                        qm_info->num_vports,
 371                        ecore_init_qm_get_num_vports(p_hwfn));
 372 }
 373
 374 /* initialize a single pq and manage qm_info resources accounting.
 375  * The pq_init_flags param determines whether the PQ is rate limited
 376  * (for VF or PF)
 377  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 378  * shared)
 379  */
 380
 381 /* flags for pq init */
 382 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 383 #define PQ_INIT_PF_RL           (1 << 1)
 384 #define PQ_INIT_VF_RL           (1 << 2)
 385
 386 /* defines for pq init */
 387 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 388 #define PQ_INIT_DEFAULT_TC              0
 389 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 390
 391 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 392                              struct ecore_qm_info *qm_info,
 393                              u8 tc, u32 pq_init_flags)
 394 {
 395         u16 pq_idx = qm_info->num_pqs, max_pq =
 396                                         ecore_init_qm_get_num_pqs(p_hwfn);
 397
 398         if (pq_idx > max_pq)
 399                 DP_ERR(p_hwfn,
 400                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 401
 402         /* init pq params */
 403         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 404                                                  qm_info->num_vports;
 405         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 406         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 407         qm_info->qm_pq_params[pq_idx].rl_valid =
 408                 (pq_init_flags & PQ_INIT_PF_RL ||
 409                  pq_init_flags & PQ_INIT_VF_RL);
 410
 411         /* qm params accounting */
 412         qm_info->num_pqs++;
 413         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 414                 qm_info->num_vports++;
 415
 416         if (pq_init_flags & PQ_INIT_PF_RL)
 417                 qm_info->num_pf_rls++;
 418
 419         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 420                 DP_ERR(p_hwfn,
 421                        "vport overflow! qm_info->num_vports %d,"
 422                        " qm_init_get_num_vports() %d\n",
 423                        qm_info->num_vports,
 424                        ecore_init_qm_get_num_vports(p_hwfn));
 425
 426         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 427                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 428                        " qm_init_get_num_pf_rls() %d\n",
 429                        qm_info->num_pf_rls,
 430                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 431 }
 432
 433 /* get pq index according to PQ_FLAGS */
 434 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 435                                              u32 pq_flags)
 436 {
 437         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 438
 439         /* Can't have multiple flags set here */
 440         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 441                                 sizeof(pq_flags)) > 1)
 442                 goto err;
 443
 444         switch (pq_flags) {
 445         case PQ_FLAGS_RLS:
 446                 return &qm_info->first_rl_pq;
 447         case PQ_FLAGS_MCOS:
 448                 return &qm_info->first_mcos_pq;
 449         case PQ_FLAGS_LB:
 450                 return &qm_info->pure_lb_pq;
 451         case PQ_FLAGS_OOO:
 452                 return &qm_info->ooo_pq;
 453         case PQ_FLAGS_ACK:
 454                 return &qm_info->pure_ack_pq;
 455         case PQ_FLAGS_OFLD:
 456                 return &qm_info->offload_pq;
 457         case PQ_FLAGS_VFS:
 458                 return &qm_info->first_vf_pq;
 459         default:
 460                 goto err;
 461         }
 462
 463 err:
 464         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 465         return OSAL_NULL;
 466 }
 467
 468 /* save pq index in qm info */
 469 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 470                                   u32 pq_flags, u16 pq_val)
 471 {
 472         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 473
 474         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 475 }
 476
 477 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 478 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 479 {
 480         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 481
 482         return *base_pq_idx + CM_TX_PQ_BASE;
 483 }
 484
 485 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 486 {
 487         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 488
 489         if (tc > max_tc)
 490                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 491
 492         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 493 }
 494
 495 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 496 {
 497         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 498
 499         if (vf > max_vf)
 500                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 501
 502         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 503 }
 504
 505 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 506 {
 507         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 508
 509         if (rl > max_rl)
 510                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 511
 512         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 513 }
 514
 515 /* Functions for creating specific types of pqs */
 516 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 517 {
 518         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 519
 520         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 521                 return;
 522
 523         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 524         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 525 }
 526
 527 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 528 {
 529         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 530
 531         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 532                 return;
 533
 534         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 535         ecore_init_qm_pq(p_hwfn, qm_info, DCBX_ISCSI_OOO_TC,
 536                          PQ_INIT_SHARE_VPORT);
 537 }
 538
 539 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 540 {
 541         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 542
 543         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 544                 return;
 545
 546         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 547         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 548 }
 549
 550 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 551 {
 552         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 553
 554         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 555                 return;
 556
 557         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 558         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 559 }
 560
 561 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 562 {
 563         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 564         u8 tc_idx;
 565
 566         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 567                 return;
 568
 569         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 570         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 571                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 572 }
 573
 574 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 575 {
 576         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 577         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 578
 579         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 580                 return;
 581
 582         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 583
 584         qm_info->num_vf_pqs = num_vfs;
 585         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 586                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 587                                  PQ_INIT_VF_RL);
 588 }
 589
 590 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 591 {
 592         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 593         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 594
 595         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 596                 return;
 597
 598         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 599         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 600                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 601                                  PQ_INIT_PF_RL);
 602 }
 603
 604 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 605 {
 606         /* rate limited pqs, must come first (FW assumption) */
 607         ecore_init_qm_rl_pqs(p_hwfn);
 608
 609         /* pqs for multi cos */
 610         ecore_init_qm_mcos_pqs(p_hwfn);
 611
 612         /* pure loopback pq */
 613         ecore_init_qm_lb_pq(p_hwfn);
 614
 615         /* out of order pq */
 616         ecore_init_qm_ooo_pq(p_hwfn);
 617
 618         /* pure ack pq */
 619         ecore_init_qm_pure_ack_pq(p_hwfn);
 620
 621         /* pq for offloaded protocol */
 622         ecore_init_qm_offload_pq(p_hwfn);
 623
 624         /* done sharing vports */
 625         ecore_init_qm_advance_vport(p_hwfn);
 626
 627         /* pqs for vfs */
 628         ecore_init_qm_vf_pqs(p_hwfn);
 629 }
 630
 631 /* compare values of getters against resources amounts */
 632 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 633 {
 634         if (ecore_init_qm_get_num_vports(p_hwfn) >
 635             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 636                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 637                 return ECORE_INVAL;
 638         }
 639
 640         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 641                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 642                 return ECORE_INVAL;
 643         }
 644
 645         return ECORE_SUCCESS;
 646 }
 647
 648 /*
 649  * Function for verbose printing of the qm initialization results
 650  */
 651 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 652 {
 653         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 654         struct init_qm_vport_params *vport;
 655         struct init_qm_port_params *port;
 656         struct init_qm_pq_params *pq;
 657         int i, tc;
 658
 659         /* top level params */
 660         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 661                    "qm init top level params: start_pq %d, start_vport %d,"
 662                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 663                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 664                    qm_info->offload_pq, qm_info->pure_ack_pq);
 665         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 666                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 667                    " num_vports %d, max_phys_tcs_per_port %d\n",
 668                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 669                    qm_info->num_vf_pqs, qm_info->num_vports,
 670                    qm_info->max_phys_tcs_per_port);
 671         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 672                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 673                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 674                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 675                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 676                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 677
 678         /* port table */
 679         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 680                 port = &qm_info->qm_port_params[i];
 681                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 682                            "port idx %d, active %d, active_phys_tcs %d,"
 683                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 684                            " reserved %d\n",
 685                            i, port->active, port->active_phys_tcs,
 686                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 687                            port->reserved);
 688         }
 689
 690         /* vport table */
 691         for (i = 0; i < qm_info->num_vports; i++) {
 692                 vport = &qm_info->qm_vport_params[i];
 693                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 694                            "vport idx %d, vport_rl %d, wfq %d,"
 695                            " first_tx_pq_id [ ",
 696                            qm_info->start_vport + i, vport->vport_rl,
 697                            vport->vport_wfq);
 698                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 699                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 700                                    vport->first_tx_pq_id[tc]);
 701                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 702         }
 703
 704         /* pq table */
 705         for (i = 0; i < qm_info->num_pqs; i++) {
 706                 pq = &qm_info->qm_pq_params[i];
 707                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 708                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 709                            " rl_valid %d\n",
 710                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 711                            pq->wrr_group, pq->rl_valid);
 712         }
 713 }
 714
 715 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 716 {
 717         /* reset params required for init run */
 718         ecore_init_qm_reset_params(p_hwfn);
 719
 720         /* init QM top level params */
 721         ecore_init_qm_params(p_hwfn);
 722
 723         /* init QM port params */
 724         ecore_init_qm_port_params(p_hwfn);
 725
 726         /* init QM vport params */
 727         ecore_init_qm_vport_params(p_hwfn);
 728
 729         /* init QM physical queue params */
 730         ecore_init_qm_pq_params(p_hwfn);
 731
 732         /* display all that init */
 733         ecore_dp_init_qm_params(p_hwfn);
 734 }
 735
 736 /* This function reconfigures the QM pf on the fly.
 737  * For this purpose we:
 738  * 1. reconfigure the QM database
 739  * 2. set new values to runtime array
 740  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 741  * 4. activate init tool in QM_PF stage
 742  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 743  */
 744 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 745                                      struct ecore_ptt *p_ptt)
 746 {
 747         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 748         enum _ecore_status_t rc;
 749         bool b_rc;
 750
 751         /* initialize ecore's qm data structure */
 752         ecore_init_qm_info(p_hwfn);
 753
 754         /* stop PF's qm queues */
 755         OSAL_SPIN_LOCK(&qm_lock);
 756         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 757                                       qm_info->start_pq, qm_info->num_pqs);
 758         OSAL_SPIN_UNLOCK(&qm_lock);
 759         if (!b_rc)
 760                 return ECORE_INVAL;
 761
 762         /* clear the QM_PF runtime phase leftovers from previous init */
 763         ecore_init_clear_rt_data(p_hwfn);
 764
 765         /* prepare QM portion of runtime array */
 766         ecore_qm_init_pf(p_hwfn);
 767
 768         /* activate init tool on runtime array */
 769         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 770                             p_hwfn->hw_info.hw_mode);
 771         if (rc != ECORE_SUCCESS)
 772                 return rc;
 773
 774         /* start PF's qm queues */
 775         OSAL_SPIN_LOCK(&qm_lock);
 776         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 777                                       qm_info->start_pq, qm_info->num_pqs);
 778         OSAL_SPIN_UNLOCK(&qm_lock);
 779         if (!b_rc)
 780                 return ECORE_INVAL;
 781
 782         return ECORE_SUCCESS;
 783 }
 784
 785 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 786 {
 787         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 788         enum _ecore_status_t rc;
 789
 790         rc = ecore_init_qm_sanity(p_hwfn);
 791         if (rc != ECORE_SUCCESS)
 792                 goto alloc_err;
 793
 794         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 795                                             sizeof(struct init_qm_pq_params) *
 796                                             ecore_init_qm_get_num_pqs(p_hwfn));
 797         if (!qm_info->qm_pq_params)
 798                 goto alloc_err;
 799
 800         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 801                                        sizeof(struct init_qm_vport_params) *
 802                                        ecore_init_qm_get_num_vports(p_hwfn));
 803         if (!qm_info->qm_vport_params)
 804                 goto alloc_err;
 805
 806         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 807                                       sizeof(struct init_qm_port_params) *
 808                                       p_hwfn->p_dev->num_ports_in_engines);
 809         if (!qm_info->qm_port_params)
 810                 goto alloc_err;
 811
 812         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 813                                         sizeof(struct ecore_wfq_data) *
 814                                         ecore_init_qm_get_num_vports(p_hwfn));
 815         if (!qm_info->wfq_data)
 816                 goto alloc_err;
 817
 818         return ECORE_SUCCESS;
 819
 820 alloc_err:
 821         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 822         ecore_qm_info_free(p_hwfn);
 823         return ECORE_NOMEM;
 824 }
 825 /******************** End QM initialization ***************/
 826
 827 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 828 {
 829         enum _ecore_status_t rc = ECORE_SUCCESS;
 830         int i;
 831
 832         if (IS_VF(p_dev))
 833                 return rc;
 834
 835         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 836                                      sizeof(*p_dev->fw_data));
 837         if (!p_dev->fw_data)
 838                 return ECORE_NOMEM;
 839
 840         for_each_hwfn(p_dev, i) {
 841                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 842                 u32 n_eqes, num_cons;
 843
 844                 /* First allocate the context manager structure */
 845                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 846                 if (rc)
 847                         goto alloc_err;
 848
 849                 /* Set the HW cid/tid numbers (in the contest manager)
 850                  * Must be done prior to any further computations.
 851                  */
 852                 rc = ecore_cxt_set_pf_params(p_hwfn);
 853                 if (rc)
 854                         goto alloc_err;
 855
 856                 rc = ecore_alloc_qm_data(p_hwfn);
 857                 if (rc)
 858                         goto alloc_err;
 859
 860                 /* init qm info */
 861                 ecore_init_qm_info(p_hwfn);
 862
 863                 /* Compute the ILT client partition */
 864                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 865                 if (rc)
 866                         goto alloc_err;
 867
 868                 /* CID map / ILT shadow table / T2
 869                  * The talbes sizes are determined by the computations above
 870                  */
 871                 rc = ecore_cxt_tables_alloc(p_hwfn);
 872                 if (rc)
 873                         goto alloc_err;
 874
 875                 /* SPQ, must follow ILT because initializes SPQ context */
 876                 rc = ecore_spq_alloc(p_hwfn);
 877                 if (rc)
 878                         goto alloc_err;
 879
 880                 /* SP status block allocation */
 881                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 882                                                            RESERVED_PTT_DPC);
 883
 884                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 rc = ecore_iov_alloc(p_hwfn);
 889                 if (rc)
 890                         goto alloc_err;
 891
 892                 /* EQ */
 893                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 894                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 895                         /* Calculate the EQ size
 896                          * ---------------------
 897                          * Each ICID may generate up to one event at a time i.e.
 898                          * the event must be handled/cleared before a new one
 899                          * can be generated. We calculate the sum of events per
 900                          * protocol and create an EQ deep enough to handle the
 901                          * worst case:
 902                          * - Core - according to SPQ.
 903                          * - RoCE - per QP there are a couple of ICIDs, one
 904                          *        responder and one requester, each can
 905                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 906                          *        Each CQ can generate an EQE. There are 2 CQs
 907                          *        per QP => n_eqes_cq = 2 * n_qp.
 908                          *        Hence the RoCE total is 4 * n_qp or
 909                          *        2 * num_cons.
 910                          * - ENet - There can be up to two events per VF. One
 911                          *        for VF-PF channel and another for VF FLR
 912                          *        initial cleanup. The number of VFs is
 913                          *        bounded by MAX_NUM_VFS_BB, and is much
 914                          *        smaller than RoCE's so we avoid exact
 915                          *        calculation.
 916                          */
 917                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 918                                 num_cons =
 919                                     ecore_cxt_get_proto_cid_count(
 920                                                 p_hwfn,
 921                                                 PROTOCOLID_ROCE,
 922                                                 OSAL_NULL);
 923                                 num_cons *= 2;
 924                         } else {
 925                                 num_cons = ecore_cxt_get_proto_cid_count(
 926                                                 p_hwfn,
 927                                                 PROTOCOLID_IWARP,
 928                                                 OSAL_NULL);
 929                         }
 930                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 931                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 932                         num_cons =
 933                             ecore_cxt_get_proto_cid_count(p_hwfn,
 934                                                           PROTOCOLID_ISCSI,
 935                                                           OSAL_NULL);
 936                         n_eqes += 2 * num_cons;
 937                 }
 938
 939                 if (n_eqes > 0xFFFF) {
 940                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 941                                        "The maximum of a u16 chain is 0x%x\n",
 942                                n_eqes, 0xFFFF);
 943                         goto alloc_no_mem;
 944                 }
 945
 946                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 947                 if (rc)
 948                         goto alloc_err;
 949
 950                 rc = ecore_consq_alloc(p_hwfn);
 951                 if (rc)
 952                         goto alloc_err;
 953
 954                 /* DMA info initialization */
 955                 rc = ecore_dmae_info_alloc(p_hwfn);
 956                 if (rc) {
 957                         DP_NOTICE(p_hwfn, true,
 958                                   "Failed to allocate memory for dmae_info"
 959                                   " structure\n");
 960                         goto alloc_err;
 961                 }
 962
 963                 /* DCBX initialization */
 964                 rc = ecore_dcbx_info_alloc(p_hwfn);
 965                 if (rc) {
 966                         DP_NOTICE(p_hwfn, true,
 967                                   "Failed to allocate memory for dcbx structure\n");
 968                         goto alloc_err;
 969                 }
 970         }
 971
 972         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 973                                          sizeof(*p_dev->reset_stats));
 974         if (!p_dev->reset_stats) {
 975                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 976                 goto alloc_no_mem;
 977         }
 978
 979         return ECORE_SUCCESS;
 980
 981 alloc_no_mem:
 982         rc = ECORE_NOMEM;
 983 alloc_err:
 984         ecore_resc_free(p_dev);
 985         return rc;
 986 }
 987
 988 void ecore_resc_setup(struct ecore_dev *p_dev)
 989 {
 990         int i;
 991
 992         if (IS_VF(p_dev))
 993                 return;
 994
 995         for_each_hwfn(p_dev, i) {
 996                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 997
 998                 ecore_cxt_mngr_setup(p_hwfn);
 999                 ecore_spq_setup(p_hwfn);
1000                 ecore_eq_setup(p_hwfn);
1001                 ecore_consq_setup(p_hwfn);
1002
1003                 /* Read shadow of current MFW mailbox */
1004                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1005                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1006                             p_hwfn->mcp_info->mfw_mb_cur,
1007                             p_hwfn->mcp_info->mfw_mb_length);
1008
1009                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1010
1011                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1012         }
1013 }
1014
1015 #define FINAL_CLEANUP_POLL_CNT  (100)
1016 #define FINAL_CLEANUP_POLL_TIME (10)
1017 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1018                                          struct ecore_ptt *p_ptt,
1019                                          u16 id, bool is_vf)
1020 {
1021         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1022         enum _ecore_status_t rc = ECORE_TIMEOUT;
1023
1024 #ifndef ASIC_ONLY
1025         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1026             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1027                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1028                 return ECORE_SUCCESS;
1029         }
1030 #endif
1031
1032         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1033             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1034
1035         if (is_vf)
1036                 id += 0x10;
1037
1038         command |= X_FINAL_CLEANUP_AGG_INT <<
1039             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1040         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1041         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1042         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1043
1044 /* Make sure notification is not set before initiating final cleanup */
1045
1046         if (REG_RD(p_hwfn, addr)) {
1047                 DP_NOTICE(p_hwfn, false,
1048                           "Unexpected; Found final cleanup notification");
1049                 DP_NOTICE(p_hwfn, false,
1050                           " before initiating final cleanup\n");
1051                 REG_WR(p_hwfn, addr, 0);
1052         }
1053
1054         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1055                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1056                    id, command);
1057
1058         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1059
1060         /* Poll until completion */
1061         while (!REG_RD(p_hwfn, addr) && count--)
1062                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1063
1064         if (REG_RD(p_hwfn, addr))
1065                 rc = ECORE_SUCCESS;
1066         else
1067                 DP_NOTICE(p_hwfn, true,
1068                           "Failed to receive FW final cleanup notification\n");
1069
1070         /* Cleanup afterwards */
1071         REG_WR(p_hwfn, addr, 0);
1072
1073         return rc;
1074 }
1075
1076 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1077 {
1078         int hw_mode = 0;
1079
1080         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1081                 hw_mode |= 1 << MODE_BB;
1082         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1083                 hw_mode |= 1 << MODE_K2;
1084         } else {
1085                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1086                           p_hwfn->p_dev->type);
1087                 return ECORE_INVAL;
1088         }
1089
1090         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1091         switch (p_hwfn->p_dev->num_ports_in_engines) {
1092         case 1:
1093                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1094                 break;
1095         case 2:
1096                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1097                 break;
1098         case 4:
1099                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1100                 break;
1101         default:
1102                 DP_NOTICE(p_hwfn, true,
1103                           "num_ports_in_engine = %d not supported\n",
1104                           p_hwfn->p_dev->num_ports_in_engines);
1105                 return ECORE_INVAL;
1106         }
1107
1108         switch (p_hwfn->p_dev->mf_mode) {
1109         case ECORE_MF_DEFAULT:
1110         case ECORE_MF_NPAR:
1111                 hw_mode |= 1 << MODE_MF_SI;
1112                 break;
1113         case ECORE_MF_OVLAN:
1114                 hw_mode |= 1 << MODE_MF_SD;
1115                 break;
1116         default:
1117                 DP_NOTICE(p_hwfn, true,
1118                           "Unsupported MF mode, init as DEFAULT\n");
1119                 hw_mode |= 1 << MODE_MF_SI;
1120         }
1121
1122 #ifndef ASIC_ONLY
1123         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1124                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1125                         hw_mode |= 1 << MODE_FPGA;
1126                 } else {
1127                         if (p_hwfn->p_dev->b_is_emul_full)
1128                                 hw_mode |= 1 << MODE_EMUL_FULL;
1129                         else
1130                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1131                 }
1132         } else
1133 #endif
1134                 hw_mode |= 1 << MODE_ASIC;
1135
1136         if (p_hwfn->p_dev->num_hwfns > 1)
1137                 hw_mode |= 1 << MODE_100G;
1138
1139         p_hwfn->hw_info.hw_mode = hw_mode;
1140
1141         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1142                    "Configuring function for hw_mode: 0x%08x\n",
1143                    p_hwfn->hw_info.hw_mode);
1144
1145         return ECORE_SUCCESS;
1146 }
1147
1148 #ifndef ASIC_ONLY
1149 /* MFW-replacement initializations for non-ASIC */
1150 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1151                                                struct ecore_ptt *p_ptt)
1152 {
1153         struct ecore_dev *p_dev = p_hwfn->p_dev;
1154         u32 pl_hv = 1;
1155         int i;
1156
1157         if (CHIP_REV_IS_EMUL(p_dev)) {
1158                 if (ECORE_IS_AH(p_dev))
1159                         pl_hv |= 0x600;
1160         }
1161
1162         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1163
1164         if (CHIP_REV_IS_EMUL(p_dev) &&
1165             (ECORE_IS_AH(p_dev)))
1166                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1167                          0x3ffffff);
1168
1169         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1170         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1171         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1172                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1173
1174         if (CHIP_REV_IS_EMUL(p_dev)) {
1175                 if (ECORE_IS_AH(p_dev)) {
1176                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1177                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1178                                  (p_dev->num_ports_in_engines >> 1));
1179
1180                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1181                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1182                 }
1183         }
1184
1185         /* Poll on RBC */
1186         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1187         for (i = 0; i < 100; i++) {
1188                 OSAL_UDELAY(50);
1189                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1190                         break;
1191         }
1192         if (i == 100)
1193                 DP_NOTICE(p_hwfn, true,
1194                           "RBC done failed to complete in PSWRQ2\n");
1195
1196         return ECORE_SUCCESS;
1197 }
1198 #endif
1199
1200 /* Init run time data for all PFs and their VFs on an engine.
1201  * TBD - for VFs - Once we have parent PF info for each VF in
1202  * shmem available as CAU requires knowledge of parent PF for each VF.
1203  */
1204 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1205 {
1206         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1207         int i, sb_id;
1208
1209         for_each_hwfn(p_dev, i) {
1210                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1211                 struct ecore_igu_info *p_igu_info;
1212                 struct ecore_igu_block *p_block;
1213                 struct cau_sb_entry sb_entry;
1214
1215                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1216
1217                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1218                      sb_id++) {
1219                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1220
1221                         if (!p_block->is_pf)
1222                                 continue;
1223
1224                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1225                                                 p_block->function_id, 0, 0);
1226                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1227                 }
1228         }
1229 }
1230
1231 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1232                                                  struct ecore_ptt *p_ptt,
1233                                                  int hw_mode)
1234 {
1235         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1236         struct ecore_dev *p_dev = p_hwfn->p_dev;
1237         u8 vf_id, max_num_vfs;
1238         u16 num_pfs, pf_id;
1239         u32 concrete_fid;
1240         enum _ecore_status_t rc = ECORE_SUCCESS;
1241
1242         ecore_init_cau_rt_data(p_dev);
1243
1244         /* Program GTT windows */
1245         ecore_gtt_init(p_hwfn);
1246
1247 #ifndef ASIC_ONLY
1248         if (CHIP_REV_IS_EMUL(p_dev)) {
1249                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1250                 if (rc != ECORE_SUCCESS)
1251                         return rc;
1252         }
1253 #endif
1254
1255         if (p_hwfn->mcp_info) {
1256                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1257                         qm_info->pf_rl_en = 1;
1258                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1259                         qm_info->pf_wfq_en = 1;
1260         }
1261
1262         ecore_qm_common_rt_init(p_hwfn,
1263                                 p_dev->num_ports_in_engines,
1264                                 qm_info->max_phys_tcs_per_port,
1265                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1266                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1267                                 qm_info->qm_port_params);
1268
1269         ecore_cxt_hw_init_common(p_hwfn);
1270
1271         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1272         if (rc != ECORE_SUCCESS)
1273                 return rc;
1274
1275         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1276          * need to decide with which value, maybe runtime
1277          */
1278         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1279         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1280
1281         if (ECORE_IS_BB(p_dev)) {
1282                 /* Workaround clears ROCE search for all functions to prevent
1283                  * involving non initialized function in processing ROCE packet.
1284                  */
1285                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1286                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1287                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1288                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1289                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1290                 }
1291                 /* pretend to original PF */
1292                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1293         }
1294
1295         /* Workaround for avoiding CCFC execution error when getting packets
1296          * with CRC errors, and allowing instead the invoking of the FW error
1297          * handler.
1298          * This is not done inside the init tool since it currently can't
1299          * perform a pretending to VFs.
1300          */
1301         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1302         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1303                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1304                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1305                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1306                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1307                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1308                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1309         }
1310         /* pretend to original PF */
1311         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1312
1313         return rc;
1314 }
1315
1316 #ifndef ASIC_ONLY
1317 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1318 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1319
1320 #define PMEG_IF_BYTE_COUNT      8
1321
1322 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1323                              struct ecore_ptt *p_ptt,
1324                              u32 addr, u64 data, u8 reg_type, u8 port)
1325 {
1326         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1327                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1328                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1329                    (8 << PMEG_IF_BYTE_COUNT),
1330                    (reg_type << 25) | (addr << 8) | port,
1331                    (u32)((data >> 32) & 0xffffffff),
1332                    (u32)(data & 0xffffffff));
1333
1334         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1335                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1336                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1337         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1338                  (reg_type << 25) | (addr << 8) | port);
1339         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1340         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1341                  (data >> 32) & 0xffffffff);
1342 }
1343
1344 #define XLPORT_MODE_REG (0x20a)
1345 #define XLPORT_MAC_CONTROL (0x210)
1346 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1347 #define XLPORT_ENABLE_REG (0x20b)
1348
1349 #define XLMAC_CTRL (0x600)
1350 #define XLMAC_MODE (0x601)
1351 #define XLMAC_RX_MAX_SIZE (0x608)
1352 #define XLMAC_TX_CTRL (0x604)
1353 #define XLMAC_PAUSE_CTRL (0x60d)
1354 #define XLMAC_PFC_CTRL (0x60e)
1355
1356 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1357                                     struct ecore_ptt *p_ptt)
1358 {
1359         u8 loopback = 0, port = p_hwfn->port_id * 2;
1360
1361         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1362
1363         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1364         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1365                          port);
1366         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1367         /* XLMAC: SOFT RESET */
1368         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1369         /* XLMAC: Port Speed >= 10Gbps */
1370         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1371         /* XLMAC: Max Size */
1372         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1373         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1374                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1375                          0, port);
1376         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1377         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1378                          0x30ffffc000ULL, 0, port);
1379         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1380                          port); /* XLMAC: TX_EN, RX_EN */
1381         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1382         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1383                          0x1003 | (loopback << 2), 0, port);
1384         /* Enabled Parallel PFC interface */
1385         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1386
1387         /* XLPORT port enable */
1388         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1389 }
1390
1391 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1392                                        struct ecore_ptt *p_ptt)
1393 {
1394         u8 port = p_hwfn->port_id;
1395         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1396
1397         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1398
1399         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1400                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1401                  (port <<
1402                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1403                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1404
1405         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1406                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1407
1408         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1409                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1410
1411         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1412                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1413
1414         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1415                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1416
1417         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1418                  (0xA <<
1419                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1420                  (8 <<
1421                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1422
1423         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1424                  0xa853);
1425 }
1426
1427 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1428                                  struct ecore_ptt *p_ptt)
1429 {
1430         if (ECORE_IS_AH(p_hwfn->p_dev))
1431                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1432         else /* BB */
1433                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1434 }
1435
1436 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1437                                struct ecore_ptt *p_ptt,  u8 port)
1438 {
1439         int port_offset = port ? 0x800 : 0;
1440         u32 xmac_rxctrl = 0;
1441
1442         /* Reset of XMAC */
1443         /* FIXME: move to common start */
1444         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1445                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1446         OSAL_MSLEEP(1);
1447         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1448                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1449
1450         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1451
1452         /* Set the number of ports on the Warp Core to 10G */
1453         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1454
1455         /* Soft reset of XMAC */
1456         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1457                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1458         OSAL_MSLEEP(1);
1459         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1460                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1461
1462         /* FIXME: move to common end */
1463         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1464                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1465
1466         /* Set Max packet size: initialize XMAC block register for port 0 */
1467         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1468
1469         /* CRC append for Tx packets: init XMAC block register for port 1 */
1470         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1471
1472         /* Enable TX and RX: initialize XMAC block register for port 1 */
1473         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1474                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1475         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1476                                XMAC_REG_RX_CTRL_BB + port_offset);
1477         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1478         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1479 }
1480 #endif
1481
1482 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1483                                                struct ecore_ptt *p_ptt,
1484                                                int hw_mode)
1485 {
1486         enum _ecore_status_t rc = ECORE_SUCCESS;
1487
1488         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1489                             hw_mode);
1490         if (rc != ECORE_SUCCESS)
1491                 return rc;
1492 #ifndef ASIC_ONLY
1493         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1494                 return ECORE_SUCCESS;
1495
1496         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1497                 if (ECORE_IS_AH(p_hwfn->p_dev))
1498                         return ECORE_SUCCESS;
1499                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1500                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1501         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1502                 if (p_hwfn->p_dev->num_hwfns > 1) {
1503                         /* Activate OPTE in CMT */
1504                         u32 val;
1505
1506                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1507                         val |= 0x10;
1508                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1509                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1510                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1511                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1512                         ecore_wr(p_hwfn, p_ptt,
1513                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1514                         ecore_wr(p_hwfn, p_ptt,
1515                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1516                         ecore_wr(p_hwfn, p_ptt,
1517                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1518                                  0x55555555);
1519                 }
1520
1521                 ecore_emul_link_init(p_hwfn, p_ptt);
1522         } else {
1523                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1524         }
1525 #endif
1526
1527         return rc;
1528 }
1529
1530 static enum _ecore_status_t
1531 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1532                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1533 {
1534         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1535         u32 dpi_bit_shift, dpi_count;
1536         u32 min_dpis;
1537
1538         /* Calculate DPI size
1539          * ------------------
1540          * The PWM region contains Doorbell Pages. The first is reserverd for
1541          * the kernel for, e.g, L2. The others are free to be used by non-
1542          * trusted applications, typically from user space. Each page, called a
1543          * doorbell page is sectioned into windows that allow doorbells to be
1544          * issued in parallel by the kernel/application. The size of such a
1545          * window (a.k.a. WID) is 1kB.
1546          * Summary:
1547          *    1kB WID x N WIDS = DPI page size
1548          *    DPI page size x N DPIs = PWM region size
1549          * Notes:
1550          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1551          * in order to ensure that two applications won't share the same page.
1552          * It also must contain at least one WID per CPU to allow parallelism.
1553          * It also must be a power of 2, since it is stored as a bit shift.
1554          *
1555          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1556          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1557          * containing 4 WIDs.
1558          */
1559         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1560         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1561         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1562         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1563         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1564
1565         dpi_count = pwm_region_size / dpi_page_size;
1566
1567         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1568         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1569
1570         /* Update hwfn */
1571         p_hwfn->dpi_size = dpi_page_size;
1572         p_hwfn->dpi_count = dpi_count;
1573
1574         /* Update registers */
1575         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1576
1577         if (dpi_count < min_dpis)
1578                 return ECORE_NORESOURCES;
1579
1580         return ECORE_SUCCESS;
1581 }
1582
1583 enum ECORE_ROCE_EDPM_MODE {
1584         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1585         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1586         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1587 };
1588
1589 static enum _ecore_status_t
1590 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1591                               struct ecore_ptt *p_ptt)
1592 {
1593         u32 pwm_regsize, norm_regsize;
1594         u32 non_pwm_conn, min_addr_reg1;
1595         u32 db_bar_size, n_cpus;
1596         u32 roce_edpm_mode;
1597         u32 pf_dems_shift;
1598         int rc = ECORE_SUCCESS;
1599         u8 cond;
1600
1601         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1602         if (p_hwfn->p_dev->num_hwfns > 1)
1603                 db_bar_size /= 2;
1604
1605         /* Calculate doorbell regions
1606          * -----------------------------------
1607          * The doorbell BAR is made of two regions. The first is called normal
1608          * region and the second is called PWM region. In the normal region
1609          * each ICID has its own set of addresses so that writing to that
1610          * specific address identifies the ICID. In the Process Window Mode
1611          * region the ICID is given in the data written to the doorbell. The
1612          * above per PF register denotes the offset in the doorbell BAR in which
1613          * the PWM region begins.
1614          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1615          * non-PWM connection. The calculation below computes the total non-PWM
1616          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1617          * in units of 4,096 bytes.
1618          */
1619         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1620             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1621                                           OSAL_NULL) +
1622             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1623         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1624         min_addr_reg1 = norm_regsize / 4096;
1625         pwm_regsize = db_bar_size - norm_regsize;
1626
1627         /* Check that the normal and PWM sizes are valid */
1628         if (db_bar_size < norm_regsize) {
1629                 DP_ERR(p_hwfn->p_dev,
1630                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1631                        db_bar_size, norm_regsize);
1632                 return ECORE_NORESOURCES;
1633         }
1634         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1635                 DP_ERR(p_hwfn->p_dev,
1636                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1637                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1638                        norm_regsize);
1639                 return ECORE_NORESOURCES;
1640         }
1641
1642         /* Calculate number of DPIs */
1643         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1644         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1645             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1646                 /* Either EDPM is mandatory, or we are attempting to allocate a
1647                  * WID per CPU.
1648                  */
1649                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1650                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1651         }
1652
1653         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1654             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1655         if (cond || p_hwfn->dcbx_no_edpm) {
1656                 /* Either EDPM is disabled from user configuration, or it is
1657                  * disabled via DCBx, or it is not mandatory and we failed to
1658                  * allocated a WID per CPU.
1659                  */
1660                 n_cpus = 1;
1661                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1662
1663                 /* If we entered this flow due to DCBX then the DPM register is
1664                  * already configured.
1665                  */
1666         }
1667
1668         DP_INFO(p_hwfn,
1669                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1670                 norm_regsize, pwm_regsize);
1671         DP_INFO(p_hwfn,
1672                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1673                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1674                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1675                 "disabled" : "enabled");
1676
1677         /* Check return codes from above calls */
1678         if (rc) {
1679                 DP_ERR(p_hwfn,
1680                        "Failed to allocate enough DPIs\n");
1681                 return ECORE_NORESOURCES;
1682         }
1683
1684         /* Update hwfn */
1685         p_hwfn->dpi_start_offset = norm_regsize;
1686
1687         /* Update registers */
1688         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1689         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1690         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1691         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1692
1693         return ECORE_SUCCESS;
1694 }
1695
1696 static enum _ecore_status_t
1697 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1698                  struct ecore_ptt *p_ptt,
1699                  struct ecore_tunn_start_params *p_tunn,
1700                  int hw_mode,
1701                  bool b_hw_start,
1702                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1703 {
1704         u8 rel_pf_id = p_hwfn->rel_pf_id;
1705         u32 prs_reg;
1706         enum _ecore_status_t rc = ECORE_SUCCESS;
1707         u16 ctrl;
1708         int pos;
1709
1710         if (p_hwfn->mcp_info) {
1711                 struct ecore_mcp_function_info *p_info;
1712
1713                 p_info = &p_hwfn->mcp_info->func_info;
1714                 if (p_info->bandwidth_min)
1715                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1716
1717                 /* Update rate limit once we'll actually have a link */
1718                 p_hwfn->qm_info.pf_rl = 100000;
1719         }
1720         ecore_cxt_hw_init_pf(p_hwfn);
1721
1722         ecore_int_igu_init_rt(p_hwfn);
1723
1724         /* Set VLAN in NIG if needed */
1725         if (hw_mode & (1 << MODE_MF_SD)) {
1726                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1727                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1728                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1729                              p_hwfn->hw_info.ovlan);
1730         }
1731
1732         /* Enable classification by MAC if needed */
1733         if (hw_mode & (1 << MODE_MF_SI)) {
1734                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1735                            "Configuring TAGMAC_CLS_TYPE\n");
1736                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1737                              1);
1738         }
1739
1740         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1741         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1742                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1743         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1744                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1745         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1746
1747         /* perform debug configuration when chip is out of reset */
1748         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1749
1750         /* Cleanup chip from previous driver if such remains exist */
1751         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1752         if (rc != ECORE_SUCCESS) {
1753                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1754                 return rc;
1755         }
1756
1757         /* PF Init sequence */
1758         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1759         if (rc)
1760                 return rc;
1761
1762         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1763         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1764         if (rc)
1765                 return rc;
1766
1767         /* Pure runtime initializations - directly to the HW  */
1768         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1769
1770         /* PCI relaxed ordering causes a decrease in the performance on some
1771          * systems. Till a root cause is found, disable this attribute in the
1772          * PCI config space.
1773          */
1774         /* Not in use @DPDK
1775         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1776         * if (!pos) {
1777         *       DP_NOTICE(p_hwfn, true,
1778         *                 "Failed to find the PCIe Cap\n");
1779         *       return ECORE_IO;
1780         * }
1781         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1782         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1783         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1784         */
1785
1786         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1787         if (rc)
1788                 return rc;
1789         if (b_hw_start) {
1790                 /* enable interrupts */
1791                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1792                 if (rc != ECORE_SUCCESS)
1793                         return rc;
1794
1795                 /* send function start command */
1796                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1797                                        allow_npar_tx_switch);
1798                 if (rc) {
1799                         DP_NOTICE(p_hwfn, true,
1800                                   "Function start ramrod failed\n");
1801                 } else {
1802                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1803                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1804                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1805
1806                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1807                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1808                                          (1 << 2));
1809                                 ecore_wr(p_hwfn, p_ptt,
1810                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1811                                     0x100);
1812                         }
1813                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1814                                    "PRS_REG_SEARCH registers after start PFn\n");
1815                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1816                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1817                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1818                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1819                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1820                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1821                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1822                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1823                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1824                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1825                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1826                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1827                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1828                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1829                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1830                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1831                                    prs_reg);
1832                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1833                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1834                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1835                 }
1836         }
1837         return rc;
1838 }
1839
1840 static enum _ecore_status_t
1841 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1842                       struct ecore_ptt *p_ptt, u8 enable)
1843 {
1844         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1845
1846         /* Change PF in PXP */
1847         ecore_wr(p_hwfn, p_ptt,
1848                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1849
1850         /* wait until value is set - try for 1 second every 50us */
1851         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1852                 val = ecore_rd(p_hwfn, p_ptt,
1853                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1854                 if (val == set_val)
1855                         break;
1856
1857                 OSAL_UDELAY(50);
1858         }
1859
1860         if (val != set_val) {
1861                 DP_NOTICE(p_hwfn, true,
1862                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1863                 return ECORE_UNKNOWN_ERROR;
1864         }
1865
1866         return ECORE_SUCCESS;
1867 }
1868
1869 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1870                                   struct ecore_ptt *p_main_ptt)
1871 {
1872         /* Read shadow of current MFW mailbox */
1873         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1874         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1875                     p_hwfn->mcp_info->mfw_mb_cur,
1876                     p_hwfn->mcp_info->mfw_mb_length);
1877 }
1878
1879 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1880                                    struct ecore_hw_init_params *p_params)
1881 {
1882         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1883         u32 load_code, param, drv_mb_param;
1884         bool b_default_mtu = true;
1885         struct ecore_hwfn *p_hwfn;
1886         int i;
1887
1888         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1889             (p_dev->num_hwfns > 1)) {
1890                 DP_NOTICE(p_dev, false,
1891                           "MSI mode is not supported for CMT devices\n");
1892                 return ECORE_INVAL;
1893         }
1894
1895         if (IS_PF(p_dev)) {
1896                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1897                 if (rc != ECORE_SUCCESS)
1898                         return rc;
1899         }
1900
1901         for_each_hwfn(p_dev, i) {
1902                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1903
1904                 /* If management didn't provide a default, set one of our own */
1905                 if (!p_hwfn->hw_info.mtu) {
1906                         p_hwfn->hw_info.mtu = 1500;
1907                         b_default_mtu = false;
1908                 }
1909
1910                 if (IS_VF(p_dev)) {
1911                         p_hwfn->b_int_enabled = 1;
1912                         continue;
1913                 }
1914
1915                 /* Enable DMAE in PXP */
1916                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1917                 if (rc != ECORE_SUCCESS)
1918                         return rc;
1919
1920                 rc = ecore_calc_hw_mode(p_hwfn);
1921                 if (rc != ECORE_SUCCESS)
1922                         return rc;
1923
1924                 /* @@@TBD need to add here:
1925                  * Check for fan failure
1926                  * Prev_unload
1927                  */
1928                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1929                 if (rc) {
1930                         DP_NOTICE(p_hwfn, true,
1931                                   "Failed sending LOAD_REQ command\n");
1932                         return rc;
1933                 }
1934
1935                 /* CQ75580:
1936                  * When coming back from hiberbate state, the registers from
1937                  * which shadow is read initially are not initialized. It turns
1938                  * out that these registers get initialized during the call to
1939                  * ecore_mcp_load_req request. So we need to reread them here
1940                  * to get the proper shadow register value.
1941                  * Note: This is a workaround for the missing MFW
1942                  * initialization. It may be removed once the implementation
1943                  * is done.
1944                  */
1945                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1946
1947                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1948                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1949                            rc, load_code);
1950
1951                 /* Only relevant for recovery:
1952                  * Clear the indication after the LOAD_REQ command is responded
1953                  * by the MFW.
1954                  */
1955                 p_dev->recov_in_prog = false;
1956
1957                 p_hwfn->first_on_engine = (load_code ==
1958                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1959
1960                 if (!qm_lock_init) {
1961                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1962                         qm_lock_init = true;
1963                 }
1964
1965                 switch (load_code) {
1966                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1967                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1968                                                   p_hwfn->hw_info.hw_mode);
1969                         if (rc)
1970                                 break;
1971                         /* Fall into */
1972                 case FW_MSG_CODE_DRV_LOAD_PORT:
1973                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1974                                                 p_hwfn->hw_info.hw_mode);
1975                         if (rc)
1976                                 break;
1977                         /* Fall into */
1978                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1979                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1980                                               p_params->p_tunn,
1981                                               p_hwfn->hw_info.hw_mode,
1982                                               p_params->b_hw_start,
1983                                               p_params->int_mode,
1984                                               p_params->allow_npar_tx_switch);
1985                         break;
1986                 default:
1987                         rc = ECORE_NOTIMPL;
1988                         break;
1989                 }
1990
1991                 if (rc != ECORE_SUCCESS)
1992                         DP_NOTICE(p_hwfn, true,
1993                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1994                                   load_code, rc);
1995
1996                 /* ACK mfw regardless of success or failure of initialization */
1997                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1998                                        DRV_MSG_CODE_LOAD_DONE,
1999                                        0, &load_code, &param);
2000                 if (rc != ECORE_SUCCESS)
2001                         return rc;
2002                 if (mfw_rc != ECORE_SUCCESS) {
2003                         DP_NOTICE(p_hwfn, true,
2004                                   "Failed sending LOAD_DONE command\n");
2005                         return mfw_rc;
2006                 }
2007
2008                 /* send DCBX attention request command */
2009                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2010                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2011                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2012                                        DRV_MSG_CODE_SET_DCBX,
2013                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2014                                        &load_code, &param);
2015                 if (mfw_rc != ECORE_SUCCESS) {
2016                         DP_NOTICE(p_hwfn, true,
2017                                   "Failed to send DCBX attention request\n");
2018                         return mfw_rc;
2019                 }
2020
2021                 p_hwfn->hw_init_done = true;
2022         }
2023
2024         if (IS_PF(p_dev)) {
2025                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2026                 drv_mb_param = (FW_MAJOR_VERSION << 24) |
2027                                (FW_MINOR_VERSION << 16) |
2028                                (FW_REVISION_VERSION << 8) |
2029                                (FW_ENGINEERING_VERSION);
2030                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2031                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2032                                    drv_mb_param, &load_code, &param);
2033                 if (rc != ECORE_SUCCESS)
2034                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2035
2036                 if (!b_default_mtu)
2037                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2038                                                       p_hwfn->hw_info.mtu);
2039                 if (rc != ECORE_SUCCESS)
2040                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2041
2042                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2043                                                       p_hwfn->p_main_ptt,
2044                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2045                 if (rc != ECORE_SUCCESS)
2046                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2047         }
2048
2049         return rc;
2050 }
2051
2052 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2053 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2054                                  struct ecore_hwfn *p_hwfn,
2055                                  struct ecore_ptt *p_ptt)
2056 {
2057         int i;
2058
2059         /* close timers */
2060         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2061         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2062         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2063                                                                         i++) {
2064                 if ((!ecore_rd(p_hwfn, p_ptt,
2065                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2066                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2067                         break;
2068
2069                 /* Dependent on number of connection/tasks, possibly
2070                  * 1ms sleep is required between polls
2071                  */
2072                 OSAL_MSLEEP(1);
2073         }
2074
2075         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2076                 return;
2077
2078         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2079                   " [Connection %02x Tasks %02x]\n",
2080                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2081                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2082 }
2083
2084 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2085 {
2086         int j;
2087
2088         for_each_hwfn(p_dev, j) {
2089                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2090                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2091
2092                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2093         }
2094 }
2095
2096 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2097 {
2098         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2099         int j;
2100
2101         for_each_hwfn(p_dev, j) {
2102                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2103                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2104
2105                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2106
2107                 if (IS_VF(p_dev)) {
2108                         ecore_vf_pf_int_cleanup(p_hwfn);
2109                         continue;
2110                 }
2111
2112                 /* mark the hw as uninitialized... */
2113                 p_hwfn->hw_init_done = false;
2114
2115                 rc = ecore_sp_pf_stop(p_hwfn);
2116                 if (rc)
2117                         DP_NOTICE(p_hwfn, true,
2118                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2119
2120                 /* perform debug action after PF stop was sent */
2121                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2122
2123                 /* close NIG to BRB gate */
2124                 ecore_wr(p_hwfn, p_ptt,
2125                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2126
2127                 /* close parser */
2128                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2129                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2130                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2131                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2132                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2133
2134                 /* @@@TBD - clean transmission queues (5.b) */
2135                 /* @@@TBD - clean BTB (5.c) */
2136
2137                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2138
2139                 /* @@@TBD - verify DMAE requests are done (8) */
2140
2141                 /* Disable Attention Generation */
2142                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2143                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2144                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2145                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2146                 /* Need to wait 1ms to guarantee SBs are cleared */
2147                 OSAL_MSLEEP(1);
2148         }
2149
2150         if (IS_PF(p_dev)) {
2151                 /* Disable DMAE in PXP - in CMT, this should only be done for
2152                  * first hw-function, and only after all transactions have
2153                  * stopped for all active hw-functions.
2154                  */
2155                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2156                                              p_dev->hwfns[0].p_main_ptt, false);
2157                 if (t_rc != ECORE_SUCCESS)
2158                         rc = t_rc;
2159         }
2160
2161         return rc;
2162 }
2163
2164 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2165 {
2166         int j;
2167
2168         for_each_hwfn(p_dev, j) {
2169                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2170                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2171
2172                 if (IS_VF(p_dev)) {
2173                         ecore_vf_pf_int_cleanup(p_hwfn);
2174                         continue;
2175                 }
2176
2177                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2178                            "Shutting down the fastpath\n");
2179
2180                 ecore_wr(p_hwfn, p_ptt,
2181                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2182
2183                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2184                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2185                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2186                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2187                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2188
2189                 /* @@@TBD - clean transmission queues (5.b) */
2190                 /* @@@TBD - clean BTB (5.c) */
2191
2192                 /* @@@TBD - verify DMAE requests are done (8) */
2193
2194                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2195                 /* Need to wait 1ms to guarantee SBs are cleared */
2196                 OSAL_MSLEEP(1);
2197         }
2198 }
2199
2200 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2201 {
2202         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2203
2204         if (IS_VF(p_hwfn->p_dev))
2205                 return;
2206
2207         /* If roce info is allocated it means roce is initialized and should
2208          * be enabled in searcher.
2209          */
2210         if (p_hwfn->p_rdma_info) {
2211                 if (p_hwfn->b_rdma_enabled_in_prs)
2212                         ecore_wr(p_hwfn, p_ptt,
2213                                  p_hwfn->rdma_prs_search_reg, 0x1);
2214                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2215         }
2216
2217         /* Re-open incoming traffic */
2218         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2219                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2220 }
2221
2222 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2223                                              struct ecore_ptt *p_ptt, u32 reg,
2224                                              bool expected)
2225 {
2226         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2227
2228         if (assert_val != expected) {
2229                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2230                           reg, expected);
2231                 return ECORE_UNKNOWN_ERROR;
2232         }
2233
2234         return 0;
2235 }
2236
2237 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2238 {
2239         enum _ecore_status_t rc = ECORE_SUCCESS;
2240         u32 unload_resp, unload_param;
2241         int i;
2242
2243         for_each_hwfn(p_dev, i) {
2244                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2245
2246                 if (IS_VF(p_dev)) {
2247                         rc = ecore_vf_pf_reset(p_hwfn);
2248                         if (rc)
2249                                 return rc;
2250                         continue;
2251                 }
2252
2253                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2254
2255                 /* Check for incorrect states */
2256                 if (!p_dev->recov_in_prog) {
2257                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2258                                          QM_REG_USG_CNT_PF_TX, 0);
2259                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2260                                          QM_REG_USG_CNT_PF_OTHER, 0);
2261                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2262                 }
2263
2264                 /* Disable PF in HW blocks */
2265                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2266                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2267
2268                 if (p_dev->recov_in_prog) {
2269                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2270                                    "Recovery is in progress -> skip sending unload_req/done\n");
2271                         break;
2272                 }
2273
2274                 /* Send unload command to MCP */
2275                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2276                                    DRV_MSG_CODE_UNLOAD_REQ,
2277                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2278                                    &unload_resp, &unload_param);
2279                 if (rc != ECORE_SUCCESS) {
2280                         DP_NOTICE(p_hwfn, true,
2281                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2282                         /* @@TBD - what to do? for now, assume ENG. */
2283                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2284                 }
2285
2286                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2287                                    DRV_MSG_CODE_UNLOAD_DONE,
2288                                    0, &unload_resp, &unload_param);
2289                 if (rc != ECORE_SUCCESS) {
2290                         DP_NOTICE(p_hwfn,
2291                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2292                         /* @@@TBD - Should it really ASSERT here ? */
2293                         return rc;
2294                 }
2295         }
2296
2297         return rc;
2298 }
2299
2300 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2301 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2302 {
2303         ecore_ptt_pool_free(p_hwfn);
2304         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2305 }
2306
2307 /* Setup bar access */
2308 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2309 {
2310         /* clear indirect access */
2311         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2312                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2313                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2314                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2315                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2316                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2317                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2318                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2319                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2320         } else {
2321                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2322                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2323                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2324                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2325                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2326                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2327                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2328                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2329         }
2330
2331         /* Clean Previous errors if such exist */
2332         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2333                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2334
2335         /* enable internal target-read */
2336         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2337                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2338 }
2339
2340 static void get_function_id(struct ecore_hwfn *p_hwfn)
2341 {
2342         /* ME Register */
2343         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2344                                                   PXP_PF_ME_OPAQUE_ADDR);
2345
2346         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2347
2348         /* Bits 16-19 from the ME registers are the pf_num */
2349         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2350         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2351                                       PXP_CONCRETE_FID_PFID);
2352         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2353                                     PXP_CONCRETE_FID_PORT);
2354
2355         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2356                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2357                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2358 }
2359
2360 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2361 {
2362         u32 *feat_num = p_hwfn->hw_info.feat_num;
2363         struct ecore_sb_cnt_info sb_cnt_info;
2364         int num_features = 1;
2365
2366         /* L2 Queues require each: 1 status block. 1 L2 queue */
2367         feat_num[ECORE_PF_L2_QUE] =
2368             OSAL_MIN_T(u32,
2369                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2370                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2371
2372         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2373         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2374         feat_num[ECORE_VF_L2_QUE] =
2375                 OSAL_MIN_T(u32,
2376                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2377                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2378                            sb_cnt_info.sb_iov_cnt);
2379
2380         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2381                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2382         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2383                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2384
2385         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2386                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2387                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2388                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2389                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2390                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2391                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2392                    RESC_NUM(p_hwfn, ECORE_SB));
2393 }
2394
2395 static enum resource_id_enum
2396 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2397 {
2398         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2399
2400         switch (res_id) {
2401         case ECORE_SB:
2402                 mfw_res_id = RESOURCE_NUM_SB_E;
2403                 break;
2404         case ECORE_L2_QUEUE:
2405                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2406                 break;
2407         case ECORE_VPORT:
2408                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2409                 break;
2410         case ECORE_RSS_ENG:
2411                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2412                 break;
2413         case ECORE_PQ:
2414                 mfw_res_id = RESOURCE_NUM_PQ_E;
2415                 break;
2416         case ECORE_RL:
2417                 mfw_res_id = RESOURCE_NUM_RL_E;
2418                 break;
2419         case ECORE_MAC:
2420         case ECORE_VLAN:
2421                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2422                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2423                 break;
2424         case ECORE_ILT:
2425                 mfw_res_id = RESOURCE_ILT_E;
2426                 break;
2427         case ECORE_LL2_QUEUE:
2428                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2429                 break;
2430         case ECORE_RDMA_CNQ_RAM:
2431         case ECORE_CMDQS_CQS:
2432                 /* CNQ/CMDQS are the same resource */
2433                 mfw_res_id = RESOURCE_CQS_E;
2434                 break;
2435         case ECORE_RDMA_STATS_QUEUE:
2436                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2437                 break;
2438         default:
2439                 break;
2440         }
2441
2442         return mfw_res_id;
2443 }
2444
2445 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2446                                       enum ecore_resources res_id)
2447 {
2448         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2449         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2450         struct ecore_sb_cnt_info sb_cnt_info;
2451         u32 dflt_resc_num = 0;
2452
2453         switch (res_id) {
2454         case ECORE_SB:
2455                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2456                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2457                 dflt_resc_num = sb_cnt_info.sb_cnt;
2458                 break;
2459         case ECORE_L2_QUEUE:
2460                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2461                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2462                 break;
2463         case ECORE_VPORT:
2464                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2465                                  MAX_NUM_VPORTS_BB) / num_funcs;
2466                 break;
2467         case ECORE_RSS_ENG:
2468                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2469                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2470                 break;
2471         case ECORE_PQ:
2472                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2473                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2474                 break;
2475         case ECORE_RL:
2476                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2477                 break;
2478         case ECORE_MAC:
2479         case ECORE_VLAN:
2480                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2481                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2482                 break;
2483         case ECORE_ILT:
2484                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2485                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2486                 break;
2487         case ECORE_LL2_QUEUE:
2488                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2489                 break;
2490         case ECORE_RDMA_CNQ_RAM:
2491         case ECORE_CMDQS_CQS:
2492                 /* CNQ/CMDQS are the same resource */
2493                 /* @DPDK */
2494                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2495                 break;
2496         case ECORE_RDMA_STATS_QUEUE:
2497                 /* @DPDK */
2498                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2499                                  MAX_NUM_VPORTS_BB) / num_funcs;
2500                 break;
2501         default:
2502                 break;
2503         }
2504
2505         return dflt_resc_num;
2506 }
2507
2508 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2509 {
2510         switch (res_id) {
2511         case ECORE_SB:
2512                 return "SB";
2513         case ECORE_L2_QUEUE:
2514                 return "L2_QUEUE";
2515         case ECORE_VPORT:
2516                 return "VPORT";
2517         case ECORE_RSS_ENG:
2518                 return "RSS_ENG";
2519         case ECORE_PQ:
2520                 return "PQ";
2521         case ECORE_RL:
2522                 return "RL";
2523         case ECORE_MAC:
2524                 return "MAC";
2525         case ECORE_VLAN:
2526                 return "VLAN";
2527         case ECORE_RDMA_CNQ_RAM:
2528                 return "RDMA_CNQ_RAM";
2529         case ECORE_ILT:
2530                 return "ILT";
2531         case ECORE_LL2_QUEUE:
2532                 return "LL2_QUEUE";
2533         case ECORE_CMDQS_CQS:
2534                 return "CMDQS_CQS";
2535         case ECORE_RDMA_STATS_QUEUE:
2536                 return "RDMA_STATS_QUEUE";
2537         default:
2538                 return "UNKNOWN_RESOURCE";
2539         }
2540 }
2541
2542 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2543                                                    enum ecore_resources res_id,
2544                                                    bool drv_resc_alloc)
2545 {
2546         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2547         u32 *p_resc_num, *p_resc_start;
2548         struct resource_info resc_info;
2549         enum _ecore_status_t rc;
2550
2551         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2552         p_resc_start = &RESC_START(p_hwfn, res_id);
2553
2554         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2555         if (!dflt_resc_num) {
2556                 DP_ERR(p_hwfn,
2557                        "Failed to get default amount for resource %d [%s]\n",
2558                         res_id, ecore_hw_get_resc_name(res_id));
2559                 return ECORE_INVAL;
2560         }
2561         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2562
2563 #ifndef ASIC_ONLY
2564         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2565                 *p_resc_num = dflt_resc_num;
2566                 *p_resc_start = dflt_resc_start;
2567                 goto out;
2568         }
2569 #endif
2570
2571         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2572         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2573         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2574                 DP_ERR(p_hwfn,
2575                        "Failed to match resource %d with MFW resources\n",
2576                        res_id);
2577                 return ECORE_INVAL;
2578         }
2579
2580         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2581                                      &mcp_resp, &mcp_param);
2582         if (rc != ECORE_SUCCESS) {
2583                 DP_NOTICE(p_hwfn, true,
2584                           "MFW response failure for an allocation request for"
2585                           " resource %d [%s]\n",
2586                           res_id, ecore_hw_get_resc_name(res_id));
2587                 return rc;
2588         }
2589
2590         /* Default driver values are applied in the following cases:
2591          * - The resource allocation MB command is not supported by the MFW
2592          * - There is an internal error in the MFW while processing the request
2593          * - The resource ID is unknown to the MFW
2594          */
2595         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2596             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2597                 /* @DPDK */
2598                 DP_INFO(p_hwfn,
2599                         "Resource %d [%s]: No allocation info was received"
2600                         " [mcp_resp 0x%x]. Applying default values"
2601                         " [num %d, start %d].\n",
2602                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2603                         dflt_resc_num, dflt_resc_start);
2604
2605                 *p_resc_num = dflt_resc_num;
2606                 *p_resc_start = dflt_resc_start;
2607                 goto out;
2608         }
2609
2610         /* TBD - remove this when revising the handling of the SB resource */
2611         if (res_id == ECORE_SB) {
2612                 /* Excluding the slowpath SB */
2613                 resc_info.size -= 1;
2614                 resc_info.offset -= p_hwfn->enabled_func_idx;
2615         }
2616
2617         *p_resc_num = resc_info.size;
2618         *p_resc_start = resc_info.offset;
2619
2620         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2621                 DP_INFO(p_hwfn,
2622                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2623                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2624                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2625                         drv_resc_alloc ? " - Applying default values" : "");
2626                 if (drv_resc_alloc) {
2627                         *p_resc_num = dflt_resc_num;
2628                         *p_resc_start = dflt_resc_start;
2629                 }
2630         }
2631 out:
2632         return ECORE_SUCCESS;
2633 }
2634
2635 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2636                                               bool drv_resc_alloc)
2637 {
2638         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2639         enum _ecore_status_t rc;
2640         u8 res_id;
2641 #ifndef ASIC_ONLY
2642         u32 *resc_start = p_hwfn->hw_info.resc_start;
2643         u32 *resc_num = p_hwfn->hw_info.resc_num;
2644         /* For AH, an equal share of the ILT lines between the maximal number of
2645          * PFs is not enough for RoCE. This would be solved by the future
2646          * resource allocation scheme, but isn't currently present for
2647          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2648          * to work - the BB number of ILT lines divided by its max PFs number.
2649          */
2650         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2651 #endif
2652
2653         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2654                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2655                 if (rc != ECORE_SUCCESS)
2656                         return rc;
2657         }
2658
2659 #ifndef ASIC_ONLY
2660         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2661                 /* Reduced build contains less PQs */
2662                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2663                         resc_num[ECORE_PQ] = 32;
2664                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2665                             p_hwfn->enabled_func_idx;
2666                 }
2667
2668                 /* For AH emulation, since we have a possible maximal number of
2669                  * 16 enabled PFs, in case there are not enough ILT lines -
2670                  * allocate only first PF as RoCE and have all the other ETH
2671                  * only with less ILT lines.
2672                  */
2673                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2674                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2675                                                          resc_num[ECORE_ILT],
2676                                                          roce_min_ilt_lines);
2677         }
2678
2679         /* Correct the common ILT calculation if PF0 has more */
2680         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2681             p_hwfn->p_dev->b_is_emul_full &&
2682             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2683                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2684                     resc_num[ECORE_ILT];
2685 #endif
2686
2687         /* Sanity for ILT */
2688         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2689             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2690                 DP_NOTICE(p_hwfn, true,
2691                           "Can't assign ILT pages [%08x,...,%08x]\n",
2692                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2693                                                                   ECORE_ILT) -
2694                           1);
2695                 return ECORE_INVAL;
2696         }
2697
2698         ecore_hw_set_feat(p_hwfn);
2699
2700         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2701                    "The numbers for each resource are:\n");
2702         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2703                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2704                            ecore_hw_get_resc_name(res_id),
2705                            RESC_NUM(p_hwfn, res_id),
2706                            RESC_START(p_hwfn, res_id));
2707
2708         return ECORE_SUCCESS;
2709 }
2710
2711 static enum _ecore_status_t
2712 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2713                       struct ecore_ptt *p_ptt,
2714                       struct ecore_hw_prepare_params *p_params)
2715 {
2716         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2717         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2718         struct ecore_mcp_link_params *link;
2719         enum _ecore_status_t rc;
2720
2721         /* Read global nvm_cfg address */
2722         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2723
2724         /* Verify MCP has initialized it */
2725         if (!nvm_cfg_addr) {
2726                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2727                 if (p_params->b_relaxed_probe)
2728                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2729                 return ECORE_INVAL;
2730         }
2731
2732 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2733
2734         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2735
2736         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2737             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2738                                                        core_cfg);
2739
2740         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2741
2742         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2743                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2744         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2745                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2746                 break;
2747         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2748                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2749                 break;
2750         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2751                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2752                 break;
2753         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2754                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2755                 break;
2756         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2757                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2758                 break;
2759         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2760                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2761                 break;
2762         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2763                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2764                 break;
2765         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2766                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2767                 break;
2768         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2769                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2770                 break;
2771         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2772                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2773                 break;
2774         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2775                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2776                 break;
2777         default:
2778                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2779                           core_cfg);
2780                 break;
2781         }
2782
2783         /* Read DCBX configuration */
2784         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2785                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2786         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2787                              port_cfg_addr +
2788                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2789         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2790                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2791         switch (dcbx_mode) {
2792         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2793                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2794                 break;
2795         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2796                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2797                 break;
2798         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2799                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2800                 break;
2801         default:
2802                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2803         }
2804
2805         /* Read default link configuration */
2806         link = &p_hwfn->mcp_info->link_input;
2807         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2808             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2809         link_temp = ecore_rd(p_hwfn, p_ptt,
2810                              port_cfg_addr +
2811                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2812         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2813         link->speed.advertised_speeds = link_temp;
2814
2815         link_temp = link->speed.advertised_speeds;
2816         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2817
2818         link_temp = ecore_rd(p_hwfn, p_ptt,
2819                              port_cfg_addr +
2820                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2821         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2822                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2823         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2824                 link->speed.autoneg = true;
2825                 break;
2826         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2827                 link->speed.forced_speed = 1000;
2828                 break;
2829         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2830                 link->speed.forced_speed = 10000;
2831                 break;
2832         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2833                 link->speed.forced_speed = 25000;
2834                 break;
2835         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2836                 link->speed.forced_speed = 40000;
2837                 break;
2838         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2839                 link->speed.forced_speed = 50000;
2840                 break;
2841         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2842                 link->speed.forced_speed = 100000;
2843                 break;
2844         default:
2845                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2846         }
2847
2848         p_hwfn->mcp_info->link_capabilities.default_speed =
2849             link->speed.forced_speed;
2850         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2851             link->speed.autoneg;
2852
2853         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2854         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2855         link->pause.autoneg = !!(link_temp &
2856                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2857         link->pause.forced_rx = !!(link_temp &
2858                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2859         link->pause.forced_tx = !!(link_temp &
2860                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2861         link->loopback_mode = 0;
2862
2863         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2864                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2865                    link->speed.forced_speed, link->speed.advertised_speeds,
2866                    link->speed.autoneg, link->pause.autoneg);
2867
2868         /* Read Multi-function information from shmem */
2869         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2870             OFFSETOF(struct nvm_cfg1, glob) +
2871             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2872
2873         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2874
2875         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2876             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2877
2878         switch (mf_mode) {
2879         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2880                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2881                 break;
2882         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2883                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2884                 break;
2885         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2886                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2887                 break;
2888         }
2889         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2890                 p_hwfn->p_dev->mf_mode);
2891
2892         /* Read Multi-function information from shmem */
2893         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2894             OFFSETOF(struct nvm_cfg1, glob) +
2895             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2896
2897         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2898         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2899                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2900                              &p_hwfn->hw_info.device_capabilities);
2901         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2902                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2903                              &p_hwfn->hw_info.device_capabilities);
2904         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2905                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2906                              &p_hwfn->hw_info.device_capabilities);
2907         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2908                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2909                              &p_hwfn->hw_info.device_capabilities);
2910         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2911                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2912                              &p_hwfn->hw_info.device_capabilities);
2913
2914         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2915         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2916                 rc = ECORE_SUCCESS;
2917                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2918         }
2919
2920         return rc;
2921 }
2922
2923 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2924                                 struct ecore_ptt *p_ptt)
2925 {
2926         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2927         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2928         struct ecore_dev *p_dev = p_hwfn->p_dev;
2929
2930         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2931
2932         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2933          * in the other bits are selected.
2934          * Bits 1-15 are for functions 1-15, respectively, and their value is
2935          * '0' only for enabled functions (function 0 always exists and
2936          * enabled).
2937          * In case of CMT in BB, only the "even" functions are enabled, and thus
2938          * the number of functions for both hwfns is learnt from the same bits.
2939          */
2940         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2941                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2942                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
2943         } else { /* E5 */
2944                 reg_function_hide = 0;
2945         }
2946
2947         if (reg_function_hide & 0x1) {
2948                 if (ECORE_IS_BB(p_dev)) {
2949                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2950                                 num_funcs = 0;
2951                                 eng_mask = 0xaaaa;
2952                         } else {
2953                                 num_funcs = 1;
2954                                 eng_mask = 0x5554;
2955                         }
2956                 } else {
2957                         num_funcs = 1;
2958                         eng_mask = 0xfffe;
2959                 }
2960
2961                 /* Get the number of the enabled functions on the engine */
2962                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2963                 while (tmp) {
2964                         if (tmp & 0x1)
2965                                 num_funcs++;
2966                         tmp >>= 0x1;
2967                 }
2968
2969                 /* Get the PF index within the enabled functions */
2970                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2971                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2972                 while (tmp) {
2973                         if (tmp & 0x1)
2974                                 enabled_func_idx--;
2975                         tmp >>= 0x1;
2976                 }
2977         }
2978
2979         p_hwfn->num_funcs_on_engine = num_funcs;
2980         p_hwfn->enabled_func_idx = enabled_func_idx;
2981
2982 #ifndef ASIC_ONLY
2983         if (CHIP_REV_IS_FPGA(p_dev)) {
2984                 DP_NOTICE(p_hwfn, false,
2985                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2986                 p_hwfn->num_funcs_on_engine = 4;
2987         }
2988 #endif
2989
2990         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2991                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2992                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2993                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2994 }
2995
2996 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2997                                       struct ecore_ptt *p_ptt)
2998 {
2999         u32 port_mode;
3000
3001 #ifndef ASIC_ONLY
3002         /* Read the port mode */
3003         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3004                 port_mode = 4;
3005         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3006                  (p_hwfn->p_dev->num_hwfns > 1))
3007                 /* In CMT on emulation, assume 1 port */
3008                 port_mode = 1;
3009         else
3010 #endif
3011         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3012
3013         if (port_mode < 3) {
3014                 p_hwfn->p_dev->num_ports_in_engines = 1;
3015         } else if (port_mode <= 5) {
3016                 p_hwfn->p_dev->num_ports_in_engines = 2;
3017         } else {
3018                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3019                           p_hwfn->p_dev->num_ports_in_engines);
3020
3021                 /* Default num_ports_in_engines to something */
3022                 p_hwfn->p_dev->num_ports_in_engines = 1;
3023         }
3024 }
3025
3026 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3027                                          struct ecore_ptt *p_ptt)
3028 {
3029         u32 port;
3030         int i;
3031
3032         p_hwfn->p_dev->num_ports_in_engines = 0;
3033
3034 #ifndef ASIC_ONLY
3035         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3036                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3037                 switch ((port & 0xf000) >> 12) {
3038                 case 1:
3039                         p_hwfn->p_dev->num_ports_in_engines = 1;
3040                         break;
3041                 case 3:
3042                         p_hwfn->p_dev->num_ports_in_engines = 2;
3043                         break;
3044                 case 0xf:
3045                         p_hwfn->p_dev->num_ports_in_engines = 4;
3046                         break;
3047                 default:
3048                         DP_NOTICE(p_hwfn, false,
3049                                   "Unknown port mode in ECO_RESERVED %08x\n",
3050                                   port);
3051                 }
3052         } else
3053 #endif
3054                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3055                         port = ecore_rd(p_hwfn, p_ptt,
3056                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3057                                         (i * 4));
3058                         if (port & 1)
3059                                 p_hwfn->p_dev->num_ports_in_engines++;
3060                 }
3061 }
3062
3063 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3064                                    struct ecore_ptt *p_ptt)
3065 {
3066         if (ECORE_IS_BB(p_hwfn->p_dev))
3067                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3068         else
3069                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3070 }
3071
3072 static enum _ecore_status_t
3073 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3074                   enum ecore_pci_personality personality,
3075                   struct ecore_hw_prepare_params *p_params)
3076 {
3077         bool drv_resc_alloc = p_params->drv_resc_alloc;
3078         enum _ecore_status_t rc;
3079
3080         /* Since all information is common, only first hwfns should do this */
3081         if (IS_LEAD_HWFN(p_hwfn)) {
3082                 rc = ecore_iov_hw_info(p_hwfn);
3083                 if (rc != ECORE_SUCCESS) {
3084                         if (p_params->b_relaxed_probe)
3085                                 p_params->p_relaxed_res =
3086                                                 ECORE_HW_PREPARE_BAD_IOV;
3087                         else
3088                                 return rc;
3089                 }
3090         }
3091
3092         /* TODO In get_hw_info, amoungst others:
3093          * Get MCP FW revision and determine according to it the supported
3094          * featrues (e.g. DCB)
3095          * Get boot mode
3096          * ecore_get_pcie_width_speed, WOL capability.
3097          * Number of global CQ-s (for storage
3098          */
3099         ecore_hw_info_port_num(p_hwfn, p_ptt);
3100
3101 #ifndef ASIC_ONLY
3102         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3103 #endif
3104         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3105         if (rc != ECORE_SUCCESS)
3106                 return rc;
3107 #ifndef ASIC_ONLY
3108         }
3109 #endif
3110
3111         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3112         if (rc != ECORE_SUCCESS) {
3113                 if (p_params->b_relaxed_probe)
3114                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3115                 else
3116                         return rc;
3117         }
3118
3119 #ifndef ASIC_ONLY
3120         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3121 #endif
3122                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3123                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3124 #ifndef ASIC_ONLY
3125         } else {
3126                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3127
3128                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3129                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3130         }
3131 #endif
3132
3133         if (ecore_mcp_is_init(p_hwfn)) {
3134                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3135                         p_hwfn->hw_info.ovlan =
3136                             p_hwfn->mcp_info->func_info.ovlan;
3137
3138                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3139         }
3140
3141         if (personality != ECORE_PCI_DEFAULT) {
3142                 p_hwfn->hw_info.personality = personality;
3143         } else if (ecore_mcp_is_init(p_hwfn)) {
3144                 enum ecore_pci_personality protocol;
3145
3146                 protocol = p_hwfn->mcp_info->func_info.protocol;
3147                 p_hwfn->hw_info.personality = protocol;
3148         }
3149
3150 #ifndef ASIC_ONLY
3151         /* To overcome ILT lack for emulation, until at least until we'll have
3152          * a definite answer from system about it, allow only PF0 to be RoCE.
3153          */
3154         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3155                 if (!p_hwfn->rel_pf_id)
3156                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3157                 else
3158                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3159         }
3160 #endif
3161
3162         /* although in BB some constellations may support more than 4 tcs,
3163          * that can result in performance penalty in some cases. 4
3164          * represents a good tradeoff between performance and flexibility.
3165          */
3166         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3167
3168         /* start out with a single active tc. This can be increased either
3169          * by dcbx negotiation or by upper layer driver
3170          */
3171         p_hwfn->hw_info.num_active_tc = 1;
3172
3173         ecore_get_num_funcs(p_hwfn, p_ptt);
3174
3175         if (ecore_mcp_is_init(p_hwfn))
3176                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3177
3178         /* In case of forcing the driver's default resource allocation, calling
3179          * ecore_hw_get_resc() should come after initializing the personality
3180          * and after getting the number of functions, since the calculation of
3181          * the resources/features depends on them.
3182          * This order is not harmful if not forcing.
3183          */
3184         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3185         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3186                 rc = ECORE_SUCCESS;
3187                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3188         }
3189
3190         return rc;
3191 }
3192
3193 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3194 {
3195         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3196         u32 tmp;
3197
3198         /* Read Vendor Id / Device Id */
3199         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3200                                   &p_dev->vendor_id);
3201         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3202                                   &p_dev->device_id);
3203
3204         /* Determine type */
3205         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3206                 p_dev->type = ECORE_DEV_TYPE_AH;
3207         else
3208                 p_dev->type = ECORE_DEV_TYPE_BB;
3209
3210         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3211                                          MISCS_REG_CHIP_NUM);
3212         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3213                                          MISCS_REG_CHIP_REV);
3214
3215         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3216
3217         /* Learn number of HW-functions */
3218         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3219                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3220
3221         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3222                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3223                 p_dev->num_hwfns = 2;
3224         } else {
3225                 p_dev->num_hwfns = 1;
3226         }
3227
3228 #ifndef ASIC_ONLY
3229         if (CHIP_REV_IS_EMUL(p_dev)) {
3230                 /* For some reason we have problems with this register
3231                  * in B0 emulation; Simply assume no CMT
3232                  */
3233                 DP_NOTICE(p_dev->hwfns, false,
3234                           "device on emul - assume no CMT\n");
3235                 p_dev->num_hwfns = 1;
3236         }
3237 #endif
3238
3239         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3240                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3241         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3242         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3243                                            MISCS_REG_CHIP_METAL);
3244         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3245         DP_INFO(p_dev->hwfns,
3246                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3247                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3248                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3249                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3250                 p_dev->chip_metal);
3251
3252         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3253                 DP_NOTICE(p_dev->hwfns, false,
3254                           "The chip type/rev (BB A0) is not supported!\n");
3255                 return ECORE_ABORTED;
3256         }
3257 #ifndef ASIC_ONLY
3258         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3259                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3260                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3261
3262         if (CHIP_REV_IS_EMUL(p_dev)) {
3263                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3264                                MISCS_REG_ECO_RESERVED);
3265                 if (tmp & (1 << 29)) {
3266                         DP_NOTICE(p_hwfn, false,
3267                                   "Emulation: Running on a FULL build\n");
3268                         p_dev->b_is_emul_full = true;
3269                 } else {
3270                         DP_NOTICE(p_hwfn, false,
3271                                   "Emulation: Running on a REDUCED build\n");
3272                 }
3273         }
3274 #endif
3275
3276         return ECORE_SUCCESS;
3277 }
3278
3279 #ifndef LINUX_REMOVE
3280 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3281 {
3282         int j;
3283
3284         if (IS_VF(p_dev))
3285                 return;
3286
3287         for_each_hwfn(p_dev, j) {
3288                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3289
3290                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3291                            "Mark hw/fw uninitialized\n");
3292
3293                 p_hwfn->hw_init_done = false;
3294                 p_hwfn->first_on_engine = false;
3295
3296                 ecore_ptt_invalidate(p_hwfn);
3297         }
3298 }
3299 #endif
3300
3301 static enum _ecore_status_t
3302 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3303                         void OSAL_IOMEM * p_regview,
3304                         void OSAL_IOMEM * p_doorbells,
3305                         struct ecore_hw_prepare_params *p_params)
3306 {
3307         struct ecore_dev *p_dev = p_hwfn->p_dev;
3308         struct ecore_mdump_info mdump_info;
3309         enum _ecore_status_t rc = ECORE_SUCCESS;
3310
3311         /* Split PCI bars evenly between hwfns */
3312         p_hwfn->regview = p_regview;
3313         p_hwfn->doorbells = p_doorbells;
3314
3315         if (IS_VF(p_dev))
3316                 return ecore_vf_hw_prepare(p_hwfn);
3317
3318         /* Validate that chip access is feasible */
3319         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3320                 DP_ERR(p_hwfn,
3321                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3322                 if (p_params->b_relaxed_probe)
3323                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3324                 return ECORE_INVAL;
3325         }
3326
3327         get_function_id(p_hwfn);
3328
3329         /* Allocate PTT pool */
3330         rc = ecore_ptt_pool_alloc(p_hwfn);
3331         if (rc) {
3332                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3333                 if (p_params->b_relaxed_probe)
3334                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3335                 goto err0;
3336         }
3337
3338         /* Allocate the main PTT */
3339         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3340
3341         /* First hwfn learns basic information, e.g., number of hwfns */
3342         if (!p_hwfn->my_id) {
3343                 rc = ecore_get_dev_info(p_dev);
3344                 if (rc != ECORE_SUCCESS) {
3345                         if (p_params->b_relaxed_probe)
3346                                 p_params->p_relaxed_res =
3347                                         ECORE_HW_PREPARE_FAILED_DEV;
3348                         goto err1;
3349                 }
3350         }
3351
3352         ecore_hw_hwfn_prepare(p_hwfn);
3353
3354         /* Initialize MCP structure */
3355         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3356         if (rc) {
3357                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3358                 if (p_params->b_relaxed_probe)
3359                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3360                 goto err1;
3361         }
3362
3363         /* Read the device configuration information from the HW and SHMEM */
3364         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3365                                p_params->personality, p_params);
3366         if (rc) {
3367                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3368                 goto err2;
3369         }
3370
3371         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3372          * called, since among others it sets the ports number in an engine.
3373          */
3374         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3375             !p_dev->recov_in_prog) {
3376                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3377                 if (rc != ECORE_SUCCESS)
3378                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3379         }
3380
3381         /* Check if mdump logs are present and update the epoch value */
3382         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3383                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3384                                               &mdump_info);
3385                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3386                         DP_NOTICE(p_hwfn, false,
3387                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3388                 }
3389
3390                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3391                                            p_params->epoch);
3392         }
3393
3394         /* Allocate the init RT array and initialize the init-ops engine */
3395         rc = ecore_init_alloc(p_hwfn);
3396         if (rc) {
3397                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3398                 if (p_params->b_relaxed_probe)
3399                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3400                 goto err2;
3401         }
3402 #ifndef ASIC_ONLY
3403         if (CHIP_REV_IS_FPGA(p_dev)) {
3404                 DP_NOTICE(p_hwfn, false,
3405                           "FPGA: workaround; Prevent DMAE parities\n");
3406                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3407                          7);
3408
3409                 DP_NOTICE(p_hwfn, false,
3410                           "FPGA: workaround: Set VF bar0 size\n");
3411                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3412                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3413         }
3414 #endif
3415
3416         return rc;
3417 err2:
3418         if (IS_LEAD_HWFN(p_hwfn))
3419                 ecore_iov_free_hw_info(p_dev);
3420         ecore_mcp_free(p_hwfn);
3421 err1:
3422         ecore_hw_hwfn_free(p_hwfn);
3423 err0:
3424         return rc;
3425 }
3426
3427 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3428                                       struct ecore_hw_prepare_params *p_params)
3429 {
3430         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3431         enum _ecore_status_t rc;
3432
3433         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3434
3435         if (p_params->b_relaxed_probe)
3436                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3437
3438         /* Store the precompiled init data ptrs */
3439         if (IS_PF(p_dev))
3440                 ecore_init_iro_array(p_dev);
3441
3442         /* Initialize the first hwfn - will learn number of hwfns */
3443         rc = ecore_hw_prepare_single(p_hwfn,
3444                                      p_dev->regview,
3445                                      p_dev->doorbells, p_params);
3446         if (rc != ECORE_SUCCESS)
3447                 return rc;
3448
3449         p_params->personality = p_hwfn->hw_info.personality;
3450
3451         /* initilalize 2nd hwfn if necessary */
3452         if (p_dev->num_hwfns > 1) {
3453                 void OSAL_IOMEM *p_regview, *p_doorbell;
3454                 u8 OSAL_IOMEM *addr;
3455
3456                 /* adjust bar offset for second engine */
3457                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3458                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3459                 p_regview = (void OSAL_IOMEM *)addr;
3460
3461                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3462                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3463                 p_doorbell = (void OSAL_IOMEM *)addr;
3464
3465                 /* prepare second hw function */
3466                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3467                                              p_doorbell, p_params);
3468
3469                 /* in case of error, need to free the previously
3470                  * initiliazed hwfn 0.
3471                  */
3472                 if (rc != ECORE_SUCCESS) {
3473                         if (p_params->b_relaxed_probe)
3474                                 p_params->p_relaxed_res =
3475                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3476
3477                         if (IS_PF(p_dev)) {
3478                                 ecore_init_free(p_hwfn);
3479                                 ecore_mcp_free(p_hwfn);
3480                                 ecore_hw_hwfn_free(p_hwfn);
3481                         } else {
3482                                 DP_NOTICE(p_dev, true,
3483                                           "What do we need to free when VF hwfn1 init fails\n");
3484                         }
3485                         return rc;
3486                 }
3487         }
3488
3489         return rc;
3490 }
3491
3492 void ecore_hw_remove(struct ecore_dev *p_dev)
3493 {
3494         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3495         int i;
3496
3497         if (IS_PF(p_dev))
3498                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3499                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3500
3501         for_each_hwfn(p_dev, i) {
3502                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3503
3504                 if (IS_VF(p_dev)) {
3505                         ecore_vf_pf_release(p_hwfn);
3506                         continue;
3507                 }
3508
3509                 ecore_init_free(p_hwfn);
3510                 ecore_hw_hwfn_free(p_hwfn);
3511                 ecore_mcp_free(p_hwfn);
3512
3513                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3514         }
3515
3516         ecore_iov_free_hw_info(p_dev);
3517 }
3518
3519 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3520                                       struct ecore_chain *p_chain)
3521 {
3522         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3523         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3524         struct ecore_chain_next *p_next;
3525         u32 size, i;
3526
3527         if (!p_virt)
3528                 return;
3529
3530         size = p_chain->elem_size * p_chain->usable_per_page;
3531
3532         for (i = 0; i < p_chain->page_cnt; i++) {
3533                 if (!p_virt)
3534                         break;
3535
3536                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3537                 p_virt_next = p_next->next_virt;
3538                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3539
3540                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3541                                        ECORE_CHAIN_PAGE_SIZE);
3542
3543                 p_virt = p_virt_next;
3544                 p_phys = p_phys_next;
3545         }
3546 }
3547
3548 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3549                                     struct ecore_chain *p_chain)
3550 {
3551         if (!p_chain->p_virt_addr)
3552                 return;
3553
3554         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3555                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3556 }
3557
3558 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3559                                  struct ecore_chain *p_chain)
3560 {
3561         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3562         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3563         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3564
3565         if (!pp_virt_addr_tbl)
3566                 return;
3567
3568         if (!p_pbl_virt)
3569                 goto out;
3570
3571         for (i = 0; i < page_cnt; i++) {
3572                 if (!pp_virt_addr_tbl[i])
3573                         break;
3574
3575                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3576                                        *(dma_addr_t *)p_pbl_virt,
3577                                        ECORE_CHAIN_PAGE_SIZE);
3578
3579                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3580         }
3581
3582         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3583
3584         if (!p_chain->b_external_pbl)
3585                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3586                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3587  out:
3588         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3589 }
3590
3591 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3592 {
3593         switch (p_chain->mode) {
3594         case ECORE_CHAIN_MODE_NEXT_PTR:
3595                 ecore_chain_free_next_ptr(p_dev, p_chain);
3596                 break;
3597         case ECORE_CHAIN_MODE_SINGLE:
3598                 ecore_chain_free_single(p_dev, p_chain);
3599                 break;
3600         case ECORE_CHAIN_MODE_PBL:
3601                 ecore_chain_free_pbl(p_dev, p_chain);
3602                 break;
3603         }
3604 }
3605
3606 static enum _ecore_status_t
3607 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3608                                enum ecore_chain_cnt_type cnt_type,
3609                                osal_size_t elem_size, u32 page_cnt)
3610 {
3611         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3612
3613         /* The actual chain size can be larger than the maximal possible value
3614          * after rounding up the requested elements number to pages, and after
3615          * taking into acount the unusuable elements (next-ptr elements).
3616          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3617          * size/capacity fields are of a u32 type.
3618          */
3619         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3620              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3621             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3622              chain_size > ECORE_U32_MAX)) {
3623                 DP_NOTICE(p_dev, true,
3624                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3625                           (unsigned long)chain_size);
3626                 return ECORE_INVAL;
3627         }
3628
3629         return ECORE_SUCCESS;
3630 }
3631
3632 static enum _ecore_status_t
3633 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3634 {
3635         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3636         dma_addr_t p_phys = 0;
3637         u32 i;
3638
3639         for (i = 0; i < p_chain->page_cnt; i++) {
3640                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3641                                                  ECORE_CHAIN_PAGE_SIZE);
3642                 if (!p_virt) {
3643                         DP_NOTICE(p_dev, true,
3644                                   "Failed to allocate chain memory\n");
3645                         return ECORE_NOMEM;
3646                 }
3647
3648                 if (i == 0) {
3649                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3650                         ecore_chain_reset(p_chain);
3651                 } else {
3652                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3653                                                        p_virt, p_phys);
3654                 }
3655
3656                 p_virt_prev = p_virt;
3657         }
3658         /* Last page's next element should point to the beginning of the
3659          * chain.
3660          */
3661         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3662                                        p_chain->p_virt_addr,
3663                                        p_chain->p_phys_addr);
3664
3665         return ECORE_SUCCESS;
3666 }
3667
3668 static enum _ecore_status_t
3669 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3670 {
3671         dma_addr_t p_phys = 0;
3672         void *p_virt = OSAL_NULL;
3673
3674         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3675         if (!p_virt) {
3676                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3677                 return ECORE_NOMEM;
3678         }
3679
3680         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3681         ecore_chain_reset(p_chain);
3682
3683         return ECORE_SUCCESS;
3684 }
3685
3686 static enum _ecore_status_t
3687 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3688                       struct ecore_chain *p_chain,
3689                       struct ecore_chain_ext_pbl *ext_pbl)
3690 {
3691         void *p_virt = OSAL_NULL;
3692         u8 *p_pbl_virt = OSAL_NULL;
3693         void **pp_virt_addr_tbl = OSAL_NULL;
3694         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3695         u32 page_cnt = p_chain->page_cnt, size, i;
3696
3697         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3698         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3699         if (!pp_virt_addr_tbl) {
3700                 DP_NOTICE(p_dev, true,
3701                           "Failed to allocate memory for the chain virtual addresses table\n");
3702                 return ECORE_NOMEM;
3703         }
3704         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3705
3706         /* The allocation of the PBL table is done with its full size, since it
3707          * is expected to be successive.
3708          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3709          * failure, since pp_virt_addr_tbl was previously allocated, and it
3710          * should be saved to allow its freeing during the error flow.
3711          */
3712         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3713
3714         if (ext_pbl == OSAL_NULL) {
3715                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3716         } else {
3717                 p_pbl_virt = ext_pbl->p_pbl_virt;
3718                 p_pbl_phys = ext_pbl->p_pbl_phys;
3719                 p_chain->b_external_pbl = true;
3720         }
3721
3722         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3723                                  pp_virt_addr_tbl);
3724         if (!p_pbl_virt) {
3725                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3726                 return ECORE_NOMEM;
3727         }
3728
3729         for (i = 0; i < page_cnt; i++) {
3730                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3731                                                  ECORE_CHAIN_PAGE_SIZE);
3732                 if (!p_virt) {
3733                         DP_NOTICE(p_dev, true,
3734                                   "Failed to allocate chain memory\n");
3735                         return ECORE_NOMEM;
3736                 }
3737
3738                 if (i == 0) {
3739                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3740                         ecore_chain_reset(p_chain);
3741                 }
3742
3743                 /* Fill the PBL table with the physical address of the page */
3744                 *(dma_addr_t *)p_pbl_virt = p_phys;
3745                 /* Keep the virtual address of the page */
3746                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3747
3748                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3749         }
3750
3751         return ECORE_SUCCESS;
3752 }
3753
3754 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3755                                        enum ecore_chain_use_mode intended_use,
3756                                        enum ecore_chain_mode mode,
3757                                        enum ecore_chain_cnt_type cnt_type,
3758                                        u32 num_elems, osal_size_t elem_size,
3759                                        struct ecore_chain *p_chain,
3760                                        struct ecore_chain_ext_pbl *ext_pbl)
3761 {
3762         u32 page_cnt;
3763         enum _ecore_status_t rc = ECORE_SUCCESS;
3764
3765         if (mode == ECORE_CHAIN_MODE_SINGLE)
3766                 page_cnt = 1;
3767         else
3768                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3769
3770         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3771                                             page_cnt);
3772         if (rc) {
3773                 DP_NOTICE(p_dev, true,
3774                           "Cannot allocate a chain with the given arguments:\n"
3775                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3776                           intended_use, mode, cnt_type, num_elems, elem_size);
3777                 return rc;
3778         }
3779
3780         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3781                                 mode, cnt_type, p_dev->dp_ctx);
3782
3783         switch (mode) {
3784         case ECORE_CHAIN_MODE_NEXT_PTR:
3785                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3786                 break;
3787         case ECORE_CHAIN_MODE_SINGLE:
3788                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3789                 break;
3790         case ECORE_CHAIN_MODE_PBL:
3791                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3792                 break;
3793         }
3794         if (rc)
3795                 goto nomem;
3796
3797         return ECORE_SUCCESS;
3798
3799 nomem:
3800         ecore_chain_free(p_dev, p_chain);
3801         return rc;
3802 }
3803
3804 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3805                                        u16 src_id, u16 *dst_id)
3806 {
3807         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3808                 u16 min, max;
3809
3810                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3811                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3812                 DP_NOTICE(p_hwfn, true,
3813                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3814                           src_id, min, max);
3815
3816                 return ECORE_INVAL;
3817         }
3818
3819         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3820
3821         return ECORE_SUCCESS;
3822 }
3823
3824 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3825                                     u8 src_id, u8 *dst_id)
3826 {
3827         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3828                 u8 min, max;
3829
3830                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3831                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3832                 DP_NOTICE(p_hwfn, true,
3833                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3834                           src_id, min, max);
3835
3836                 return ECORE_INVAL;
3837         }
3838
3839         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3840
3841         return ECORE_SUCCESS;
3842 }
3843
3844 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3845                                       u8 src_id, u8 *dst_id)
3846 {
3847         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3848                 u8 min, max;
3849
3850                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3851                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3852                 DP_NOTICE(p_hwfn, true,
3853                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3854                           src_id, min, max);
3855
3856                 return ECORE_INVAL;
3857         }
3858
3859         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3860
3861         return ECORE_SUCCESS;
3862 }
3863
3864 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3865                                               struct ecore_ptt *p_ptt,
3866                                               u8 *p_filter)
3867 {
3868         u32 high, low, en;
3869         int i;
3870
3871         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3872                 return ECORE_SUCCESS;
3873
3874         high = p_filter[1] | (p_filter[0] << 8);
3875         low = p_filter[5] | (p_filter[4] << 8) |
3876             (p_filter[3] << 16) | (p_filter[2] << 24);
3877
3878         /* Find a free entry and utilize it */
3879         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3880                 en = ecore_rd(p_hwfn, p_ptt,
3881                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3882                 if (en)
3883                         continue;
3884                 ecore_wr(p_hwfn, p_ptt,
3885                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3886                          2 * i * sizeof(u32), low);
3887                 ecore_wr(p_hwfn, p_ptt,
3888                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3889                          (2 * i + 1) * sizeof(u32), high);
3890                 ecore_wr(p_hwfn, p_ptt,
3891                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3892                 ecore_wr(p_hwfn, p_ptt,
3893                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3894                          i * sizeof(u32), 0);
3895                 ecore_wr(p_hwfn, p_ptt,
3896                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3897                 break;
3898         }
3899         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3900                 DP_NOTICE(p_hwfn, false,
3901                           "Failed to find an empty LLH filter to utilize\n");
3902                 return ECORE_INVAL;
3903         }
3904
3905         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3906                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3907                    p_filter[0], p_filter[1], p_filter[2],
3908                    p_filter[3], p_filter[4], p_filter[5], i);
3909
3910         return ECORE_SUCCESS;
3911 }
3912
3913 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3914                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3915 {
3916         u32 high, low;
3917         int i;
3918
3919         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3920                 return;
3921
3922         high = p_filter[1] | (p_filter[0] << 8);
3923         low = p_filter[5] | (p_filter[4] << 8) |
3924             (p_filter[3] << 16) | (p_filter[2] << 24);
3925
3926         /* Find the entry and clean it */
3927         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3928                 if (ecore_rd(p_hwfn, p_ptt,
3929                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3930                              2 * i * sizeof(u32)) != low)
3931                         continue;
3932                 if (ecore_rd(p_hwfn, p_ptt,
3933                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3934                              (2 * i + 1) * sizeof(u32)) != high)
3935                         continue;
3936
3937                 ecore_wr(p_hwfn, p_ptt,
3938                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3939                 ecore_wr(p_hwfn, p_ptt,
3940                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3941                          2 * i * sizeof(u32), 0);
3942                 ecore_wr(p_hwfn, p_ptt,
3943                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3944                          (2 * i + 1) * sizeof(u32), 0);
3945                 break;
3946         }
3947         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3948                 DP_NOTICE(p_hwfn, false,
3949                           "Tried to remove a non-configured filter\n");
3950 }
3951
3952 enum _ecore_status_t
3953 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3954                               struct ecore_ptt *p_ptt,
3955                               u16 source_port_or_eth_type,
3956                               u16 dest_port,
3957                               enum ecore_llh_port_filter_type_t type)
3958 {
3959         u32 high, low, en;
3960         int i;
3961
3962         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3963                 return ECORE_SUCCESS;
3964
3965         high = 0;
3966         low = 0;
3967         switch (type) {
3968         case ECORE_LLH_FILTER_ETHERTYPE:
3969                 high = source_port_or_eth_type;
3970                 break;
3971         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3972         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3973                 low = source_port_or_eth_type << 16;
3974                 break;
3975         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3976         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3977                 low = dest_port;
3978                 break;
3979         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3980         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3981                 low = (source_port_or_eth_type << 16) | dest_port;
3982                 break;
3983         default:
3984                 DP_NOTICE(p_hwfn, true,
3985                           "Non valid LLH protocol filter type %d\n", type);
3986                 return ECORE_INVAL;
3987         }
3988         /* Find a free entry and utilize it */
3989         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3990                 en = ecore_rd(p_hwfn, p_ptt,
3991                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3992                 if (en)
3993                         continue;
3994                 ecore_wr(p_hwfn, p_ptt,
3995                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3996                          2 * i * sizeof(u32), low);
3997                 ecore_wr(p_hwfn, p_ptt,
3998                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3999                          (2 * i + 1) * sizeof(u32), high);
4000                 ecore_wr(p_hwfn, p_ptt,
4001                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4002                 ecore_wr(p_hwfn, p_ptt,
4003                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4004                          i * sizeof(u32), 1 << type);
4005                 ecore_wr(p_hwfn, p_ptt,
4006                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4007                 break;
4008         }
4009         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4010                 DP_NOTICE(p_hwfn, false,
4011                           "Failed to find an empty LLH filter to utilize\n");
4012                 return ECORE_NORESOURCES;
4013         }
4014         switch (type) {
4015         case ECORE_LLH_FILTER_ETHERTYPE:
4016                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4017                            "ETH type %x is added at %d\n",
4018                            source_port_or_eth_type, i);
4019                 break;
4020         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4021                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4022                            "TCP src port %x is added at %d\n",
4023                            source_port_or_eth_type, i);
4024                 break;
4025         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4026                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4027                            "UDP src port %x is added at %d\n",
4028                            source_port_or_eth_type, i);
4029                 break;
4030         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4031                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4032                            "TCP dst port %x is added at %d\n", dest_port, i);
4033                 break;
4034         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4035                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4036                            "UDP dst port %x is added at %d\n", dest_port, i);
4037                 break;
4038         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4039                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4040                            "TCP src/dst ports %x/%x are added at %d\n",
4041                            source_port_or_eth_type, dest_port, i);
4042                 break;
4043         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4044                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4045                            "UDP src/dst ports %x/%x are added at %d\n",
4046                            source_port_or_eth_type, dest_port, i);
4047                 break;
4048         }
4049         return ECORE_SUCCESS;
4050 }
4051
4052 void
4053 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4054                                  struct ecore_ptt *p_ptt,
4055                                  u16 source_port_or_eth_type,
4056                                  u16 dest_port,
4057                                  enum ecore_llh_port_filter_type_t type)
4058 {
4059         u32 high, low;
4060         int i;
4061
4062         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4063                 return;
4064
4065         high = 0;
4066         low = 0;
4067         switch (type) {
4068         case ECORE_LLH_FILTER_ETHERTYPE:
4069                 high = source_port_or_eth_type;
4070                 break;
4071         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4072         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4073                 low = source_port_or_eth_type << 16;
4074                 break;
4075         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4076         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4077                 low = dest_port;
4078                 break;
4079         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4080         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4081                 low = (source_port_or_eth_type << 16) | dest_port;
4082                 break;
4083         default:
4084                 DP_NOTICE(p_hwfn, true,
4085                           "Non valid LLH protocol filter type %d\n", type);
4086                 return;
4087         }
4088
4089         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4090                 if (!ecore_rd(p_hwfn, p_ptt,
4091                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4092                         continue;
4093                 if (!ecore_rd(p_hwfn, p_ptt,
4094                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4095                         continue;
4096                 if (!(ecore_rd(p_hwfn, p_ptt,
4097                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4098                                i * sizeof(u32)) & (1 << type)))
4099                         continue;
4100                 if (ecore_rd(p_hwfn, p_ptt,
4101                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4102                              2 * i * sizeof(u32)) != low)
4103                         continue;
4104                 if (ecore_rd(p_hwfn, p_ptt,
4105                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4106                              (2 * i + 1) * sizeof(u32)) != high)
4107                         continue;
4108
4109                 ecore_wr(p_hwfn, p_ptt,
4110                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4111                 ecore_wr(p_hwfn, p_ptt,
4112                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4113                 ecore_wr(p_hwfn, p_ptt,
4114                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4115                          i * sizeof(u32), 0);
4116                 ecore_wr(p_hwfn, p_ptt,
4117                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4118                          2 * i * sizeof(u32), 0);
4119                 ecore_wr(p_hwfn, p_ptt,
4120                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4121                          (2 * i + 1) * sizeof(u32), 0);
4122                 break;
4123         }
4124
4125         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4126                 DP_NOTICE(p_hwfn, false,
4127                           "Tried to remove a non-configured filter\n");
4128 }
4129
4130 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4131                                  struct ecore_ptt *p_ptt)
4132 {
4133         int i;
4134
4135         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4136                 return;
4137
4138         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4139                 ecore_wr(p_hwfn, p_ptt,
4140                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4141                 ecore_wr(p_hwfn, p_ptt,
4142                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4143                          2 * i * sizeof(u32), 0);
4144                 ecore_wr(p_hwfn, p_ptt,
4145                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4146                          (2 * i + 1) * sizeof(u32), 0);
4147         }
4148 }
4149
4150 enum _ecore_status_t
4151 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4152                                   struct ecore_ptt *p_ptt)
4153 {
4154         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4155                 ecore_wr(p_hwfn, p_ptt,
4156                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4157                          1 << p_hwfn->abs_pf_id / 2);
4158                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4159                 return ECORE_SUCCESS;
4160         }
4161
4162         DP_NOTICE(p_hwfn, false,
4163                   "This function can't be set as default\n");
4164         return ECORE_INVAL;
4165 }
4166
4167 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4168                                                struct ecore_ptt *p_ptt,
4169                                                u32 hw_addr, void *p_eth_qzone,
4170                                                osal_size_t eth_qzone_size,
4171                                                u8 timeset)
4172 {
4173         struct coalescing_timeset *p_coal_timeset;
4174
4175         if (IS_VF(p_hwfn->p_dev)) {
4176                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
4177                 return ECORE_INVAL;
4178         }
4179
4180         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4181                 DP_NOTICE(p_hwfn, true,
4182                           "Coalescing configuration not enabled\n");
4183                 return ECORE_INVAL;
4184         }
4185
4186         p_coal_timeset = p_eth_qzone;
4187         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4188         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4189         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4190         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4191
4192         return ECORE_SUCCESS;
4193 }
4194
4195 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4196                                             struct ecore_ptt *p_ptt,
4197                                             u16 coalesce, u16 qid, u16 sb_id)
4198 {
4199         struct ustorm_eth_queue_zone eth_qzone;
4200         u8 timeset, timer_res;
4201         u16 fw_qid = 0;
4202         u32 address;
4203         enum _ecore_status_t rc;
4204
4205         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4206         if (coalesce <= 0x7F) {
4207                 timer_res = 0;
4208         } else if (coalesce <= 0xFF) {
4209                 timer_res = 1;
4210         } else if (coalesce <= 0x1FF) {
4211                 timer_res = 2;
4212         } else {
4213                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4214                 return ECORE_INVAL;
4215         }
4216         timeset = (u8)(coalesce >> timer_res);
4217
4218         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4219         if (rc != ECORE_SUCCESS)
4220                 return rc;
4221
4222         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
4223         if (rc != ECORE_SUCCESS)
4224                 goto out;
4225
4226         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4227
4228         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4229                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4230         if (rc != ECORE_SUCCESS)
4231                 goto out;
4232
4233         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
4234 out:
4235         return rc;
4236 }
4237
4238 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4239                                             struct ecore_ptt *p_ptt,
4240                                             u16 coalesce, u16 qid, u16 sb_id)
4241 {
4242         struct xstorm_eth_queue_zone eth_qzone;
4243         u8 timeset, timer_res;
4244         u16 fw_qid = 0;
4245         u32 address;
4246         enum _ecore_status_t rc;
4247
4248         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4249         if (coalesce <= 0x7F) {
4250                 timer_res = 0;
4251         } else if (coalesce <= 0xFF) {
4252                 timer_res = 1;
4253         } else if (coalesce <= 0x1FF) {
4254                 timer_res = 2;
4255         } else {
4256                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4257                 return ECORE_INVAL;
4258         }
4259
4260         timeset = (u8)(coalesce >> timer_res);
4261
4262         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4263         if (rc != ECORE_SUCCESS)
4264                 return rc;
4265
4266         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
4267         if (rc != ECORE_SUCCESS)
4268                 goto out;
4269
4270         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4271
4272         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4273                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4274         if (rc != ECORE_SUCCESS)
4275                 goto out;
4276
4277         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4278 out:
4279         return rc;
4280 }
4281
4282 /* Calculate final WFQ values for all vports and configure it.
4283  * After this configuration each vport must have
4284  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4285  */
4286 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4287                                                struct ecore_ptt *p_ptt,
4288                                                u32 min_pf_rate)
4289 {
4290         struct init_qm_vport_params *vport_params;
4291         int i;
4292
4293         vport_params = p_hwfn->qm_info.qm_vport_params;
4294
4295         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4296                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4297
4298                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4299                     min_pf_rate;
4300                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4301                                      vport_params[i].first_tx_pq_id,
4302                                      vport_params[i].vport_wfq);
4303         }
4304 }
4305
4306 static void
4307 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4308 {
4309         int i;
4310
4311         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4312                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4313 }
4314
4315 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4316                                              struct ecore_ptt *p_ptt,
4317                                              u32 min_pf_rate)
4318 {
4319         struct init_qm_vport_params *vport_params;
4320         int i;
4321
4322         vport_params = p_hwfn->qm_info.qm_vport_params;
4323
4324         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4325                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4326                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4327                                      vport_params[i].first_tx_pq_id,
4328                                      vport_params[i].vport_wfq);
4329         }
4330 }
4331
4332 /* This function performs several validations for WFQ
4333  * configuration and required min rate for a given vport
4334  * 1. req_rate must be greater than one percent of min_pf_rate.
4335  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4336  *    rates to get less than one percent of min_pf_rate.
4337  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4338  */
4339 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4340                                                  u16 vport_id, u32 req_rate,
4341                                                  u32 min_pf_rate)
4342 {
4343         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4344         int non_requested_count = 0, req_count = 0, i, num_vports;
4345
4346         num_vports = p_hwfn->qm_info.num_vports;
4347
4348 /* Accounting for the vports which are configured for WFQ explicitly */
4349
4350         for (i = 0; i < num_vports; i++) {
4351                 u32 tmp_speed;
4352
4353                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4354                         req_count++;
4355                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4356                         total_req_min_rate += tmp_speed;
4357                 }
4358         }
4359
4360         /* Include current vport data as well */
4361         req_count++;
4362         total_req_min_rate += req_rate;
4363         non_requested_count = num_vports - req_count;
4364
4365         /* validate possible error cases */
4366         if (req_rate > min_pf_rate) {
4367                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4368                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4369                            vport_id, req_rate, min_pf_rate);
4370                 return ECORE_INVAL;
4371         }
4372
4373         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4374                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4375                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4376                            vport_id, req_rate, min_pf_rate);
4377                 return ECORE_INVAL;
4378         }
4379
4380         /* TBD - for number of vports greater than 100 */
4381         if (num_vports > ECORE_WFQ_UNIT) {
4382                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4383                            "Number of vports is greater than %d\n",
4384                            ECORE_WFQ_UNIT);
4385                 return ECORE_INVAL;
4386         }
4387
4388         if (total_req_min_rate > min_pf_rate) {
4389                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4390                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4391                            total_req_min_rate, min_pf_rate);
4392                 return ECORE_INVAL;
4393         }
4394
4395         /* Data left for non requested vports */
4396         total_left_rate = min_pf_rate - total_req_min_rate;
4397         left_rate_per_vp = total_left_rate / non_requested_count;
4398
4399         /* validate if non requested get < 1% of min bw */
4400         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4401                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4402                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4403                            left_rate_per_vp, min_pf_rate);
4404                 return ECORE_INVAL;
4405         }
4406
4407         /* now req_rate for given vport passes all scenarios.
4408          * assign final wfq rates to all vports.
4409          */
4410         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4411         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4412
4413         for (i = 0; i < num_vports; i++) {
4414                 if (p_hwfn->qm_info.wfq_data[i].configured)
4415                         continue;
4416
4417                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4418         }
4419
4420         return ECORE_SUCCESS;
4421 }
4422
4423 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4424                                        struct ecore_ptt *p_ptt,
4425                                        u16 vp_id, u32 rate)
4426 {
4427         struct ecore_mcp_link_state *p_link;
4428         int rc = ECORE_SUCCESS;
4429
4430         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4431
4432         if (!p_link->min_pf_rate) {
4433                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4434                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4435                 return rc;
4436         }
4437
4438         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4439
4440         if (rc == ECORE_SUCCESS)
4441                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4442                                                    p_link->min_pf_rate);
4443         else
4444                 DP_NOTICE(p_hwfn, false,
4445                           "Validation failed while configuring min rate\n");
4446
4447         return rc;
4448 }
4449
4450 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4451                                                    struct ecore_ptt *p_ptt,
4452                                                    u32 min_pf_rate)
4453 {
4454         bool use_wfq = false;
4455         int rc = ECORE_SUCCESS;
4456         u16 i;
4457
4458         /* Validate all pre configured vports for wfq */
4459         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4460                 u32 rate;
4461
4462                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4463                         continue;
4464
4465                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4466                 use_wfq = true;
4467
4468                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4469                 if (rc != ECORE_SUCCESS) {
4470                         DP_NOTICE(p_hwfn, false,
4471                                   "WFQ validation failed while configuring min rate\n");
4472                         break;
4473                 }
4474         }
4475
4476         if (rc == ECORE_SUCCESS && use_wfq)
4477                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4478         else
4479                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4480
4481         return rc;
4482 }
4483
4484 /* Main API for ecore clients to configure vport min rate.
4485  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4486  * rate - Speed in Mbps needs to be assigned to a given vport.
4487  */
4488 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4489 {
4490         int i, rc = ECORE_INVAL;
4491
4492         /* TBD - for multiple hardware functions - that is 100 gig */
4493         if (p_dev->num_hwfns > 1) {
4494                 DP_NOTICE(p_dev, false,
4495                           "WFQ configuration is not supported for this device\n");
4496                 return rc;
4497         }
4498
4499         for_each_hwfn(p_dev, i) {
4500                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4501                 struct ecore_ptt *p_ptt;
4502
4503                 p_ptt = ecore_ptt_acquire(p_hwfn);
4504                 if (!p_ptt)
4505                         return ECORE_TIMEOUT;
4506
4507                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4508
4509                 if (rc != ECORE_SUCCESS) {
4510                         ecore_ptt_release(p_hwfn, p_ptt);
4511                         return rc;
4512                 }
4513
4514                 ecore_ptt_release(p_hwfn, p_ptt);
4515         }
4516
4517         return rc;
4518 }
4519
4520 /* API to configure WFQ from mcp link change */
4521 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4522                                            u32 min_pf_rate)
4523 {
4524         int i;
4525
4526         /* TBD - for multiple hardware functions - that is 100 gig */
4527         if (p_dev->num_hwfns > 1) {
4528                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4529                            "WFQ configuration is not supported for this device\n");
4530                 return;
4531         }
4532
4533         for_each_hwfn(p_dev, i) {
4534                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4535
4536                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4537                                                         p_hwfn->p_dpc_ptt,
4538                                                         min_pf_rate);
4539         }
4540 }
4541
4542 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4543                                        struct ecore_ptt *p_ptt,
4544                                        struct ecore_mcp_link_state *p_link,
4545                                        u8 max_bw)
4546 {
4547         int rc = ECORE_SUCCESS;
4548
4549         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4550
4551         if (!p_link->line_speed && (max_bw != 100))
4552                 return rc;
4553
4554         p_link->speed = (p_link->line_speed * max_bw) / 100;
4555         p_hwfn->qm_info.pf_rl = p_link->speed;
4556
4557         /* Since the limiter also affects Tx-switched traffic, we don't want it
4558          * to limit such traffic in case there's no actual limit.
4559          * In that case, set limit to imaginary high boundary.
4560          */
4561         if (max_bw == 100)
4562                 p_hwfn->qm_info.pf_rl = 100000;
4563
4564         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4565                               p_hwfn->qm_info.pf_rl);
4566
4567         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4568                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4569                    p_link->speed);
4570
4571         return rc;
4572 }
4573
4574 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4575 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4576 {
4577         int i, rc = ECORE_INVAL;
4578
4579         if (max_bw < 1 || max_bw > 100) {
4580                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4581                 return rc;
4582         }
4583
4584         for_each_hwfn(p_dev, i) {
4585                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4586                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4587                 struct ecore_mcp_link_state *p_link;
4588                 struct ecore_ptt *p_ptt;
4589
4590                 p_link = &p_lead->mcp_info->link_output;
4591
4592                 p_ptt = ecore_ptt_acquire(p_hwfn);
4593                 if (!p_ptt)
4594                         return ECORE_TIMEOUT;
4595
4596                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4597                                                         p_link, max_bw);
4598
4599                 ecore_ptt_release(p_hwfn, p_ptt);
4600
4601                 if (rc != ECORE_SUCCESS)
4602                         break;
4603         }
4604
4605         return rc;
4606 }
4607
4608 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4609                                        struct ecore_ptt *p_ptt,
4610                                        struct ecore_mcp_link_state *p_link,
4611                                        u8 min_bw)
4612 {
4613         int rc = ECORE_SUCCESS;
4614
4615         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4616         p_hwfn->qm_info.pf_wfq = min_bw;
4617
4618         if (!p_link->line_speed)
4619                 return rc;
4620
4621         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4622
4623         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4624
4625         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4626                    "Configured MIN bandwidth to be %d Mb/sec\n",
4627                    p_link->min_pf_rate);
4628
4629         return rc;
4630 }
4631
4632 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4633 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4634 {
4635         int i, rc = ECORE_INVAL;
4636
4637         if (min_bw < 1 || min_bw > 100) {
4638                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4639                 return rc;
4640         }
4641
4642         for_each_hwfn(p_dev, i) {
4643                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4644                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4645                 struct ecore_mcp_link_state *p_link;
4646                 struct ecore_ptt *p_ptt;
4647
4648                 p_link = &p_lead->mcp_info->link_output;
4649
4650                 p_ptt = ecore_ptt_acquire(p_hwfn);
4651                 if (!p_ptt)
4652                         return ECORE_TIMEOUT;
4653
4654                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4655                                                         p_link, min_bw);
4656                 if (rc != ECORE_SUCCESS) {
4657                         ecore_ptt_release(p_hwfn, p_ptt);
4658                         return rc;
4659                 }
4660
4661                 if (p_link->min_pf_rate) {
4662                         u32 min_rate = p_link->min_pf_rate;
4663
4664                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4665                                                                      p_ptt,
4666                                                                      min_rate);
4667                 }
4668
4669                 ecore_ptt_release(p_hwfn, p_ptt);
4670         }
4671
4672         return rc;
4673 }
4674
4675 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4676 {
4677         struct ecore_mcp_link_state *p_link;
4678
4679         p_link = &p_hwfn->mcp_info->link_output;
4680
4681         if (p_link->min_pf_rate)
4682                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4683                                                  p_link->min_pf_rate);
4684
4685         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4686                     sizeof(*p_hwfn->qm_info.wfq_data) *
4687                     p_hwfn->qm_info.num_vports);
4688 }
4689
4690 int ecore_device_num_engines(struct ecore_dev *p_dev)
4691 {
4692         return ECORE_IS_BB(p_dev) ? 2 : 1;
4693 }
4694
4695 int ecore_device_num_ports(struct ecore_dev *p_dev)
4696 {
4697         /* in CMT always only one port */
4698         if (p_dev->num_hwfns > 1)
4699                 return 1;
4700
4701         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4702 }
4703
4704 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4705                           __le16 *fw_mid,
4706                           __le16 *fw_lsb,
4707                           u8 *mac)
4708 {
4709         ((u8 *)fw_msb)[0] = mac[1];
4710         ((u8 *)fw_msb)[1] = mac[0];
4711         ((u8 *)fw_mid)[0] = mac[3];
4712         ((u8 *)fw_mid)[1] = mac[2];
4713         ((u8 *)fw_lsb)[0] = mac[5];
4714         ((u8 *)fw_lsb)[1] = mac[4];
4715 }