drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 ecore_cxt_mngr_free(p_hwfn);
 159                 ecore_qm_info_free(p_hwfn);
 160                 ecore_spq_free(p_hwfn);
 161                 ecore_eq_free(p_hwfn);
 162                 ecore_consq_free(p_hwfn);
 163                 ecore_int_free(p_hwfn);
 164                 ecore_iov_free(p_hwfn);
 165                 ecore_dmae_info_free(p_hwfn);
 166                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 167                 /* @@@TBD Flush work-queue ? */
 168         }
 169 }
 170
 171 /******************** QM initialization *******************/
 172
 173 /* bitmaps for indicating active traffic classes.
 174  * Special case for Arrowhead 4 port
 175  */
 176 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 177 #define ACTIVE_TCS_BMAP 0x9f
 178 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 179 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 180
 181 /* determines the physical queue flags for a given PF. */
 182 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 183 {
 184         u32 flags;
 185
 186         /* common flags */
 187         flags = PQ_FLAGS_LB;
 188
 189         /* feature flags */
 190         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 191                 flags |= PQ_FLAGS_VFS;
 192
 193         /* protocol flags */
 194         switch (p_hwfn->hw_info.personality) {
 195         case ECORE_PCI_ETH:
 196                 flags |= PQ_FLAGS_MCOS;
 197                 break;
 198         case ECORE_PCI_FCOE:
 199                 flags |= PQ_FLAGS_OFLD;
 200                 break;
 201         case ECORE_PCI_ISCSI:
 202                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 203                 break;
 204         case ECORE_PCI_ETH_ROCE:
 205                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 206                 break;
 207         case ECORE_PCI_ETH_IWARP:
 208                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 209                          PQ_FLAGS_OFLD;
 210                 break;
 211         default:
 212                 DP_ERR(p_hwfn, "unknown personality %d\n",
 213                        p_hwfn->hw_info.personality);
 214                 return 0;
 215         }
 216         return flags;
 217 }
 218
 219 /* Getters for resource amounts necessary for qm initialization */
 220 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 221 {
 222         return p_hwfn->hw_info.num_hw_tc;
 223 }
 224
 225 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 226 {
 227         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 228                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 229 }
 230
 231 #define NUM_DEFAULT_RLS 1
 232
 233 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 234 {
 235         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 236
 237         /* @DPDK */
 238         /* num RLs can't exceed resource amount of rls or vports or the
 239          * dcqcn qps
 240          */
 241         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 242                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 243
 244         /* make sure after we reserve the default and VF rls we'll have
 245          * something left
 246          */
 247         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 248                 DP_NOTICE(p_hwfn, false,
 249                           "no rate limiters left for PF rate limiting"
 250                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 251                 return 0;
 252         }
 253
 254         /* subtract rls necessary for VFs and one default one for the PF */
 255         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 256
 257         return num_pf_rls;
 258 }
 259
 260 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 261 {
 262         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 263
 264         /* all pqs share the same vport (hence the 1 below), except for vfs
 265          * and pf_rl pqs
 266          */
 267         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 268                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 269                (!!(PQ_FLAGS_VFS & pq_flags)) *
 270                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 271 }
 272
 273 /* calc amount of PQs according to the requested flags */
 274 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 275 {
 276         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 277
 278         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 279                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 280                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 281                 ecore_init_qm_get_num_tcs(p_hwfn) +
 282                (!!(PQ_FLAGS_LB & pq_flags)) +
 283                (!!(PQ_FLAGS_OOO & pq_flags)) +
 284                (!!(PQ_FLAGS_ACK & pq_flags)) +
 285                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 286                (!!(PQ_FLAGS_VFS & pq_flags)) *
 287                 ecore_init_qm_get_num_vfs(p_hwfn);
 288 }
 289
 290 /* initialize the top level QM params */
 291 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 292 {
 293         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 294
 295         /* pq and vport bases for this PF */
 296         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 297         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 298
 299         /* rate limiting and weighted fair queueing are always enabled */
 300         qm_info->vport_rl_en = 1;
 301         qm_info->vport_wfq_en = 1;
 302
 303         /* in AH 4 port we have fewer TCs per port */
 304         qm_info->max_phys_tcs_per_port =
 305                 p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2 ?
 306                         NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
 307 }
 308
 309 /* initialize qm vport params */
 310 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 311 {
 312         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 313         u8 i;
 314
 315         /* all vports participate in weighted fair queueing */
 316         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 317                 qm_info->qm_vport_params[i].vport_wfq = 1;
 318 }
 319
 320 /* initialize qm port params */
 321 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 322 {
 323         /* Initialize qm port parameters */
 324         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 325
 326         /* indicate how ooo and high pri traffic is dealt with */
 327         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 328                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 329
 330         for (i = 0; i < num_ports; i++) {
 331                 struct init_qm_port_params *p_qm_port =
 332                         &p_hwfn->qm_info.qm_port_params[i];
 333
 334                 p_qm_port->active = 1;
 335                 p_qm_port->active_phys_tcs = active_phys_tcs;
 336                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 337                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 338         }
 339 }
 340
 341 /* Reset the params which must be reset for qm init. QM init may be called as
 342  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 343  * params may be affected by the init but would simply recalculate to the same
 344  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 345  * affected as these amounts stay the same.
 346  */
 347 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 348 {
 349         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 350
 351         qm_info->num_pqs = 0;
 352         qm_info->num_vports = 0;
 353         qm_info->num_pf_rls = 0;
 354         qm_info->num_vf_pqs = 0;
 355         qm_info->first_vf_pq = 0;
 356         qm_info->first_mcos_pq = 0;
 357         qm_info->first_rl_pq = 0;
 358 }
 359
 360 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 361 {
 362         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 363
 364         qm_info->num_vports++;
 365
 366         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 367                 DP_ERR(p_hwfn,
 368                        "vport overflow! qm_info->num_vports %d,"
 369                        " qm_init_get_num_vports() %d\n",
 370                        qm_info->num_vports,
 371                        ecore_init_qm_get_num_vports(p_hwfn));
 372 }
 373
 374 /* initialize a single pq and manage qm_info resources accounting.
 375  * The pq_init_flags param determines whether the PQ is rate limited
 376  * (for VF or PF)
 377  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 378  * shared)
 379  */
 380
 381 /* flags for pq init */
 382 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 383 #define PQ_INIT_PF_RL           (1 << 1)
 384 #define PQ_INIT_VF_RL           (1 << 2)
 385
 386 /* defines for pq init */
 387 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 388 #define PQ_INIT_DEFAULT_TC              0
 389 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 390
 391 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 392                              struct ecore_qm_info *qm_info,
 393                              u8 tc, u32 pq_init_flags)
 394 {
 395         u16 pq_idx = qm_info->num_pqs, max_pq =
 396                                         ecore_init_qm_get_num_pqs(p_hwfn);
 397
 398         if (pq_idx > max_pq)
 399                 DP_ERR(p_hwfn,
 400                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 401
 402         /* init pq params */
 403         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 404                                                  qm_info->num_vports;
 405         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 406         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 407         qm_info->qm_pq_params[pq_idx].rl_valid =
 408                 (pq_init_flags & PQ_INIT_PF_RL ||
 409                  pq_init_flags & PQ_INIT_VF_RL);
 410
 411         /* qm params accounting */
 412         qm_info->num_pqs++;
 413         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 414                 qm_info->num_vports++;
 415
 416         if (pq_init_flags & PQ_INIT_PF_RL)
 417                 qm_info->num_pf_rls++;
 418
 419         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 420                 DP_ERR(p_hwfn,
 421                        "vport overflow! qm_info->num_vports %d,"
 422                        " qm_init_get_num_vports() %d\n",
 423                        qm_info->num_vports,
 424                        ecore_init_qm_get_num_vports(p_hwfn));
 425
 426         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 427                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 428                        " qm_init_get_num_pf_rls() %d\n",
 429                        qm_info->num_pf_rls,
 430                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 431 }
 432
 433 /* get pq index according to PQ_FLAGS */
 434 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 435                                              u32 pq_flags)
 436 {
 437         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 438
 439         /* Can't have multiple flags set here */
 440         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 441                                 sizeof(pq_flags)) > 1)
 442                 goto err;
 443
 444         switch (pq_flags) {
 445         case PQ_FLAGS_RLS:
 446                 return &qm_info->first_rl_pq;
 447         case PQ_FLAGS_MCOS:
 448                 return &qm_info->first_mcos_pq;
 449         case PQ_FLAGS_LB:
 450                 return &qm_info->pure_lb_pq;
 451         case PQ_FLAGS_OOO:
 452                 return &qm_info->ooo_pq;
 453         case PQ_FLAGS_ACK:
 454                 return &qm_info->pure_ack_pq;
 455         case PQ_FLAGS_OFLD:
 456                 return &qm_info->offload_pq;
 457         case PQ_FLAGS_VFS:
 458                 return &qm_info->first_vf_pq;
 459         default:
 460                 goto err;
 461         }
 462
 463 err:
 464         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 465         return OSAL_NULL;
 466 }
 467
 468 /* save pq index in qm info */
 469 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 470                                   u32 pq_flags, u16 pq_val)
 471 {
 472         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 473
 474         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 475 }
 476
 477 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 478 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 479 {
 480         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 481
 482         return *base_pq_idx + CM_TX_PQ_BASE;
 483 }
 484
 485 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 486 {
 487         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 488
 489         if (tc > max_tc)
 490                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 491
 492         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 493 }
 494
 495 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 496 {
 497         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 498
 499         if (vf > max_vf)
 500                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 501
 502         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 503 }
 504
 505 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 506 {
 507         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 508
 509         if (rl > max_rl)
 510                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 511
 512         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 513 }
 514
 515 /* Functions for creating specific types of pqs */
 516 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 517 {
 518         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 519
 520         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 521                 return;
 522
 523         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 524         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 525 }
 526
 527 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 528 {
 529         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 530
 531         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 532                 return;
 533
 534         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 535         ecore_init_qm_pq(p_hwfn, qm_info, DCBX_ISCSI_OOO_TC,
 536                          PQ_INIT_SHARE_VPORT);
 537 }
 538
 539 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 540 {
 541         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 542
 543         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 544                 return;
 545
 546         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 547         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 548 }
 549
 550 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 551 {
 552         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 553
 554         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 555                 return;
 556
 557         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 558         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 559 }
 560
 561 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 562 {
 563         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 564         u8 tc_idx;
 565
 566         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 567                 return;
 568
 569         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 570         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 571                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 572 }
 573
 574 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 575 {
 576         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 577         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 578
 579         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 580                 return;
 581
 582         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 583
 584         qm_info->num_vf_pqs = num_vfs;
 585         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 586                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 587                                  PQ_INIT_VF_RL);
 588 }
 589
 590 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 591 {
 592         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 593         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 594
 595         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 596                 return;
 597
 598         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 599         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 600                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 601                                  PQ_INIT_PF_RL);
 602 }
 603
 604 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 605 {
 606         /* rate limited pqs, must come first (FW assumption) */
 607         ecore_init_qm_rl_pqs(p_hwfn);
 608
 609         /* pqs for multi cos */
 610         ecore_init_qm_mcos_pqs(p_hwfn);
 611
 612         /* pure loopback pq */
 613         ecore_init_qm_lb_pq(p_hwfn);
 614
 615         /* out of order pq */
 616         ecore_init_qm_ooo_pq(p_hwfn);
 617
 618         /* pure ack pq */
 619         ecore_init_qm_pure_ack_pq(p_hwfn);
 620
 621         /* pq for offloaded protocol */
 622         ecore_init_qm_offload_pq(p_hwfn);
 623
 624         /* done sharing vports */
 625         ecore_init_qm_advance_vport(p_hwfn);
 626
 627         /* pqs for vfs */
 628         ecore_init_qm_vf_pqs(p_hwfn);
 629 }
 630
 631 /* compare values of getters against resources amounts */
 632 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 633 {
 634         if (ecore_init_qm_get_num_vports(p_hwfn) >
 635             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 636                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 637                 return ECORE_INVAL;
 638         }
 639
 640         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 641                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 642                 return ECORE_INVAL;
 643         }
 644
 645         return ECORE_SUCCESS;
 646 }
 647
 648 /*
 649  * Function for verbose printing of the qm initialization results
 650  */
 651 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 652 {
 653         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 654         struct init_qm_vport_params *vport;
 655         struct init_qm_port_params *port;
 656         struct init_qm_pq_params *pq;
 657         int i, tc;
 658
 659         /* top level params */
 660         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 661                    "qm init top level params: start_pq %d, start_vport %d,"
 662                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 663                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 664                    qm_info->offload_pq, qm_info->pure_ack_pq);
 665         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 666                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 667                    " num_vports %d, max_phys_tcs_per_port %d\n",
 668                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 669                    qm_info->num_vf_pqs, qm_info->num_vports,
 670                    qm_info->max_phys_tcs_per_port);
 671         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 672                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 673                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 674                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 675                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 676                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 677
 678         /* port table */
 679         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 680                 port = &qm_info->qm_port_params[i];
 681                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 682                            "port idx %d, active %d, active_phys_tcs %d,"
 683                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 684                            " reserved %d\n",
 685                            i, port->active, port->active_phys_tcs,
 686                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 687                            port->reserved);
 688         }
 689
 690         /* vport table */
 691         for (i = 0; i < qm_info->num_vports; i++) {
 692                 vport = &qm_info->qm_vport_params[i];
 693                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 694                            "vport idx %d, vport_rl %d, wfq %d,"
 695                            " first_tx_pq_id [ ",
 696                            qm_info->start_vport + i, vport->vport_rl,
 697                            vport->vport_wfq);
 698                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 699                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 700                                    vport->first_tx_pq_id[tc]);
 701                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 702         }
 703
 704         /* pq table */
 705         for (i = 0; i < qm_info->num_pqs; i++) {
 706                 pq = &qm_info->qm_pq_params[i];
 707                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 708                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 709                            " rl_valid %d\n",
 710                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 711                            pq->wrr_group, pq->rl_valid);
 712         }
 713 }
 714
 715 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 716 {
 717         /* reset params required for init run */
 718         ecore_init_qm_reset_params(p_hwfn);
 719
 720         /* init QM top level params */
 721         ecore_init_qm_params(p_hwfn);
 722
 723         /* init QM port params */
 724         ecore_init_qm_port_params(p_hwfn);
 725
 726         /* init QM vport params */
 727         ecore_init_qm_vport_params(p_hwfn);
 728
 729         /* init QM physical queue params */
 730         ecore_init_qm_pq_params(p_hwfn);
 731
 732         /* display all that init */
 733         ecore_dp_init_qm_params(p_hwfn);
 734 }
 735
 736 /* This function reconfigures the QM pf on the fly.
 737  * For this purpose we:
 738  * 1. reconfigure the QM database
 739  * 2. set new values to runtime array
 740  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 741  * 4. activate init tool in QM_PF stage
 742  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 743  */
 744 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 745                                      struct ecore_ptt *p_ptt)
 746 {
 747         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 748         enum _ecore_status_t rc;
 749         bool b_rc;
 750
 751         /* initialize ecore's qm data structure */
 752         ecore_init_qm_info(p_hwfn);
 753
 754         /* stop PF's qm queues */
 755         OSAL_SPIN_LOCK(&qm_lock);
 756         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 757                                       qm_info->start_pq, qm_info->num_pqs);
 758         OSAL_SPIN_UNLOCK(&qm_lock);
 759         if (!b_rc)
 760                 return ECORE_INVAL;
 761
 762         /* clear the QM_PF runtime phase leftovers from previous init */
 763         ecore_init_clear_rt_data(p_hwfn);
 764
 765         /* prepare QM portion of runtime array */
 766         ecore_qm_init_pf(p_hwfn);
 767
 768         /* activate init tool on runtime array */
 769         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 770                             p_hwfn->hw_info.hw_mode);
 771         if (rc != ECORE_SUCCESS)
 772                 return rc;
 773
 774         /* start PF's qm queues */
 775         OSAL_SPIN_LOCK(&qm_lock);
 776         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 777                                       qm_info->start_pq, qm_info->num_pqs);
 778         OSAL_SPIN_UNLOCK(&qm_lock);
 779         if (!b_rc)
 780                 return ECORE_INVAL;
 781
 782         return ECORE_SUCCESS;
 783 }
 784
 785 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 786 {
 787         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 788         enum _ecore_status_t rc;
 789
 790         rc = ecore_init_qm_sanity(p_hwfn);
 791         if (rc != ECORE_SUCCESS)
 792                 goto alloc_err;
 793
 794         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 795                                             sizeof(struct init_qm_pq_params) *
 796                                             ecore_init_qm_get_num_pqs(p_hwfn));
 797         if (!qm_info->qm_pq_params)
 798                 goto alloc_err;
 799
 800         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 801                                        sizeof(struct init_qm_vport_params) *
 802                                        ecore_init_qm_get_num_vports(p_hwfn));
 803         if (!qm_info->qm_vport_params)
 804                 goto alloc_err;
 805
 806         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 807                                       sizeof(struct init_qm_port_params) *
 808                                       p_hwfn->p_dev->num_ports_in_engines);
 809         if (!qm_info->qm_port_params)
 810                 goto alloc_err;
 811
 812         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 813                                         sizeof(struct ecore_wfq_data) *
 814                                         ecore_init_qm_get_num_vports(p_hwfn));
 815         if (!qm_info->wfq_data)
 816                 goto alloc_err;
 817
 818         return ECORE_SUCCESS;
 819
 820 alloc_err:
 821         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 822         ecore_qm_info_free(p_hwfn);
 823         return ECORE_NOMEM;
 824 }
 825 /******************** End QM initialization ***************/
 826
 827 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 828 {
 829         enum _ecore_status_t rc = ECORE_SUCCESS;
 830         int i;
 831
 832         if (IS_VF(p_dev))
 833                 return rc;
 834
 835         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 836                                      sizeof(*p_dev->fw_data));
 837         if (!p_dev->fw_data)
 838                 return ECORE_NOMEM;
 839
 840         for_each_hwfn(p_dev, i) {
 841                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 842                 u32 n_eqes, num_cons;
 843
 844                 /* First allocate the context manager structure */
 845                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 846                 if (rc)
 847                         goto alloc_err;
 848
 849                 /* Set the HW cid/tid numbers (in the contest manager)
 850                  * Must be done prior to any further computations.
 851                  */
 852                 rc = ecore_cxt_set_pf_params(p_hwfn);
 853                 if (rc)
 854                         goto alloc_err;
 855
 856                 rc = ecore_alloc_qm_data(p_hwfn);
 857                 if (rc)
 858                         goto alloc_err;
 859
 860                 /* init qm info */
 861                 ecore_init_qm_info(p_hwfn);
 862
 863                 /* Compute the ILT client partition */
 864                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 865                 if (rc)
 866                         goto alloc_err;
 867
 868                 /* CID map / ILT shadow table / T2
 869                  * The talbes sizes are determined by the computations above
 870                  */
 871                 rc = ecore_cxt_tables_alloc(p_hwfn);
 872                 if (rc)
 873                         goto alloc_err;
 874
 875                 /* SPQ, must follow ILT because initializes SPQ context */
 876                 rc = ecore_spq_alloc(p_hwfn);
 877                 if (rc)
 878                         goto alloc_err;
 879
 880                 /* SP status block allocation */
 881                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 882                                                            RESERVED_PTT_DPC);
 883
 884                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 rc = ecore_iov_alloc(p_hwfn);
 889                 if (rc)
 890                         goto alloc_err;
 891
 892                 /* EQ */
 893                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 894                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 895                         /* Calculate the EQ size
 896                          * ---------------------
 897                          * Each ICID may generate up to one event at a time i.e.
 898                          * the event must be handled/cleared before a new one
 899                          * can be generated. We calculate the sum of events per
 900                          * protocol and create an EQ deep enough to handle the
 901                          * worst case:
 902                          * - Core - according to SPQ.
 903                          * - RoCE - per QP there are a couple of ICIDs, one
 904                          *        responder and one requester, each can
 905                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 906                          *        Each CQ can generate an EQE. There are 2 CQs
 907                          *        per QP => n_eqes_cq = 2 * n_qp.
 908                          *        Hence the RoCE total is 4 * n_qp or
 909                          *        2 * num_cons.
 910                          * - ENet - There can be up to two events per VF. One
 911                          *        for VF-PF channel and another for VF FLR
 912                          *        initial cleanup. The number of VFs is
 913                          *        bounded by MAX_NUM_VFS_BB, and is much
 914                          *        smaller than RoCE's so we avoid exact
 915                          *        calculation.
 916                          */
 917                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 918                                 num_cons =
 919                                     ecore_cxt_get_proto_cid_count(
 920                                                 p_hwfn,
 921                                                 PROTOCOLID_ROCE,
 922                                                 OSAL_NULL);
 923                                 num_cons *= 2;
 924                         } else {
 925                                 num_cons = ecore_cxt_get_proto_cid_count(
 926                                                 p_hwfn,
 927                                                 PROTOCOLID_IWARP,
 928                                                 OSAL_NULL);
 929                         }
 930                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 931                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 932                         num_cons =
 933                             ecore_cxt_get_proto_cid_count(p_hwfn,
 934                                                           PROTOCOLID_ISCSI,
 935                                                           OSAL_NULL);
 936                         n_eqes += 2 * num_cons;
 937                 }
 938
 939                 if (n_eqes > 0xFFFF) {
 940                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 941                                        "The maximum of a u16 chain is 0x%x\n",
 942                                n_eqes, 0xFFFF);
 943                         goto alloc_no_mem;
 944                 }
 945
 946                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 947                 if (rc)
 948                         goto alloc_err;
 949
 950                 rc = ecore_consq_alloc(p_hwfn);
 951                 if (rc)
 952                         goto alloc_err;
 953
 954                 /* DMA info initialization */
 955                 rc = ecore_dmae_info_alloc(p_hwfn);
 956                 if (rc) {
 957                         DP_NOTICE(p_hwfn, true,
 958                                   "Failed to allocate memory for dmae_info"
 959                                   " structure\n");
 960                         goto alloc_err;
 961                 }
 962
 963                 /* DCBX initialization */
 964                 rc = ecore_dcbx_info_alloc(p_hwfn);
 965                 if (rc) {
 966                         DP_NOTICE(p_hwfn, true,
 967                                   "Failed to allocate memory for dcbx structure\n");
 968                         goto alloc_err;
 969                 }
 970         }
 971
 972         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 973                                          sizeof(*p_dev->reset_stats));
 974         if (!p_dev->reset_stats) {
 975                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 976                 goto alloc_no_mem;
 977         }
 978
 979         return ECORE_SUCCESS;
 980
 981 alloc_no_mem:
 982         rc = ECORE_NOMEM;
 983 alloc_err:
 984         ecore_resc_free(p_dev);
 985         return rc;
 986 }
 987
 988 void ecore_resc_setup(struct ecore_dev *p_dev)
 989 {
 990         int i;
 991
 992         if (IS_VF(p_dev))
 993                 return;
 994
 995         for_each_hwfn(p_dev, i) {
 996                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 997
 998                 ecore_cxt_mngr_setup(p_hwfn);
 999                 ecore_spq_setup(p_hwfn);
1000                 ecore_eq_setup(p_hwfn);
1001                 ecore_consq_setup(p_hwfn);
1002
1003                 /* Read shadow of current MFW mailbox */
1004                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1005                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1006                             p_hwfn->mcp_info->mfw_mb_cur,
1007                             p_hwfn->mcp_info->mfw_mb_length);
1008
1009                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1010
1011                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1012         }
1013 }
1014
1015 #define FINAL_CLEANUP_POLL_CNT  (100)
1016 #define FINAL_CLEANUP_POLL_TIME (10)
1017 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1018                                          struct ecore_ptt *p_ptt,
1019                                          u16 id, bool is_vf)
1020 {
1021         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1022         enum _ecore_status_t rc = ECORE_TIMEOUT;
1023
1024 #ifndef ASIC_ONLY
1025         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1026             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1027                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1028                 return ECORE_SUCCESS;
1029         }
1030 #endif
1031
1032         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1033             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1034
1035         if (is_vf)
1036                 id += 0x10;
1037
1038         command |= X_FINAL_CLEANUP_AGG_INT <<
1039             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1040         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1041         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1042         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1043
1044 /* Make sure notification is not set before initiating final cleanup */
1045
1046         if (REG_RD(p_hwfn, addr)) {
1047                 DP_NOTICE(p_hwfn, false,
1048                           "Unexpected; Found final cleanup notification");
1049                 DP_NOTICE(p_hwfn, false,
1050                           " before initiating final cleanup\n");
1051                 REG_WR(p_hwfn, addr, 0);
1052         }
1053
1054         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1055                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1056                    id, command);
1057
1058         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1059
1060         /* Poll until completion */
1061         while (!REG_RD(p_hwfn, addr) && count--)
1062                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1063
1064         if (REG_RD(p_hwfn, addr))
1065                 rc = ECORE_SUCCESS;
1066         else
1067                 DP_NOTICE(p_hwfn, true,
1068                           "Failed to receive FW final cleanup notification\n");
1069
1070         /* Cleanup afterwards */
1071         REG_WR(p_hwfn, addr, 0);
1072
1073         return rc;
1074 }
1075
1076 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1077 {
1078         int hw_mode = 0;
1079
1080         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1081                 hw_mode |= 1 << MODE_BB;
1082         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1083                 hw_mode |= 1 << MODE_K2;
1084         } else {
1085                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1086                           p_hwfn->p_dev->type);
1087                 return ECORE_INVAL;
1088         }
1089
1090         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1091         switch (p_hwfn->p_dev->num_ports_in_engines) {
1092         case 1:
1093                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1094                 break;
1095         case 2:
1096                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1097                 break;
1098         case 4:
1099                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1100                 break;
1101         default:
1102                 DP_NOTICE(p_hwfn, true,
1103                           "num_ports_in_engine = %d not supported\n",
1104                           p_hwfn->p_dev->num_ports_in_engines);
1105                 return ECORE_INVAL;
1106         }
1107
1108         switch (p_hwfn->p_dev->mf_mode) {
1109         case ECORE_MF_DEFAULT:
1110         case ECORE_MF_NPAR:
1111                 hw_mode |= 1 << MODE_MF_SI;
1112                 break;
1113         case ECORE_MF_OVLAN:
1114                 hw_mode |= 1 << MODE_MF_SD;
1115                 break;
1116         default:
1117                 DP_NOTICE(p_hwfn, true,
1118                           "Unsupported MF mode, init as DEFAULT\n");
1119                 hw_mode |= 1 << MODE_MF_SI;
1120         }
1121
1122 #ifndef ASIC_ONLY
1123         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1124                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1125                         hw_mode |= 1 << MODE_FPGA;
1126                 } else {
1127                         if (p_hwfn->p_dev->b_is_emul_full)
1128                                 hw_mode |= 1 << MODE_EMUL_FULL;
1129                         else
1130                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1131                 }
1132         } else
1133 #endif
1134                 hw_mode |= 1 << MODE_ASIC;
1135
1136         if (p_hwfn->p_dev->num_hwfns > 1)
1137                 hw_mode |= 1 << MODE_100G;
1138
1139         p_hwfn->hw_info.hw_mode = hw_mode;
1140
1141         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1142                    "Configuring function for hw_mode: 0x%08x\n",
1143                    p_hwfn->hw_info.hw_mode);
1144
1145         return ECORE_SUCCESS;
1146 }
1147
1148 #ifndef ASIC_ONLY
1149 /* MFW-replacement initializations for non-ASIC */
1150 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1151                                                struct ecore_ptt *p_ptt)
1152 {
1153         struct ecore_dev *p_dev = p_hwfn->p_dev;
1154         u32 pl_hv = 1;
1155         int i;
1156
1157         if (CHIP_REV_IS_EMUL(p_dev)) {
1158                 if (ECORE_IS_AH(p_dev))
1159                         pl_hv |= 0x600;
1160         }
1161
1162         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1163
1164         if (CHIP_REV_IS_EMUL(p_dev) &&
1165             (ECORE_IS_AH(p_dev)))
1166                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1167                          0x3ffffff);
1168
1169         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1170         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1171         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1172                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1173
1174         if (CHIP_REV_IS_EMUL(p_dev)) {
1175                 if (ECORE_IS_AH(p_dev)) {
1176                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1177                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1178                                  (p_dev->num_ports_in_engines >> 1));
1179
1180                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1181                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1182                 }
1183         }
1184
1185         /* Poll on RBC */
1186         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1187         for (i = 0; i < 100; i++) {
1188                 OSAL_UDELAY(50);
1189                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1190                         break;
1191         }
1192         if (i == 100)
1193                 DP_NOTICE(p_hwfn, true,
1194                           "RBC done failed to complete in PSWRQ2\n");
1195
1196         return ECORE_SUCCESS;
1197 }
1198 #endif
1199
1200 /* Init run time data for all PFs and their VFs on an engine.
1201  * TBD - for VFs - Once we have parent PF info for each VF in
1202  * shmem available as CAU requires knowledge of parent PF for each VF.
1203  */
1204 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1205 {
1206         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1207         int i, sb_id;
1208
1209         for_each_hwfn(p_dev, i) {
1210                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1211                 struct ecore_igu_info *p_igu_info;
1212                 struct ecore_igu_block *p_block;
1213                 struct cau_sb_entry sb_entry;
1214
1215                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1216
1217                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1218                      sb_id++) {
1219                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1220
1221                         if (!p_block->is_pf)
1222                                 continue;
1223
1224                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1225                                                 p_block->function_id, 0, 0);
1226                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1227                 }
1228         }
1229 }
1230
1231 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1232                                                  struct ecore_ptt *p_ptt,
1233                                                  int hw_mode)
1234 {
1235         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1236         struct ecore_dev *p_dev = p_hwfn->p_dev;
1237         u8 vf_id, max_num_vfs;
1238         u16 num_pfs, pf_id;
1239         u32 concrete_fid;
1240         enum _ecore_status_t rc = ECORE_SUCCESS;
1241
1242         ecore_init_cau_rt_data(p_dev);
1243
1244         /* Program GTT windows */
1245         ecore_gtt_init(p_hwfn);
1246
1247 #ifndef ASIC_ONLY
1248         if (CHIP_REV_IS_EMUL(p_dev)) {
1249                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1250                 if (rc != ECORE_SUCCESS)
1251                         return rc;
1252         }
1253 #endif
1254
1255         if (p_hwfn->mcp_info) {
1256                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1257                         qm_info->pf_rl_en = 1;
1258                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1259                         qm_info->pf_wfq_en = 1;
1260         }
1261
1262         ecore_qm_common_rt_init(p_hwfn,
1263                                 p_dev->num_ports_in_engines,
1264                                 qm_info->max_phys_tcs_per_port,
1265                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1266                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1267                                 qm_info->qm_port_params);
1268
1269         ecore_cxt_hw_init_common(p_hwfn);
1270
1271         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1272         if (rc != ECORE_SUCCESS)
1273                 return rc;
1274
1275         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1276          * need to decide with which value, maybe runtime
1277          */
1278         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1279         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1280
1281         if (ECORE_IS_BB(p_dev)) {
1282                 /* Workaround clears ROCE search for all functions to prevent
1283                  * involving non initialized function in processing ROCE packet.
1284                  */
1285                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1286                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1287                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1288                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1289                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1290                 }
1291                 /* pretend to original PF */
1292                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1293         }
1294
1295         /* Workaround for avoiding CCFC execution error when getting packets
1296          * with CRC errors, and allowing instead the invoking of the FW error
1297          * handler.
1298          * This is not done inside the init tool since it currently can't
1299          * perform a pretending to VFs.
1300          */
1301         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1302         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1303                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1304                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1305                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1306                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1307                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1308                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1309         }
1310         /* pretend to original PF */
1311         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1312
1313         return rc;
1314 }
1315
1316 #ifndef ASIC_ONLY
1317 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1318 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1319
1320 #define PMEG_IF_BYTE_COUNT      8
1321
1322 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1323                              struct ecore_ptt *p_ptt,
1324                              u32 addr, u64 data, u8 reg_type, u8 port)
1325 {
1326         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1327                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1328                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1329                    (8 << PMEG_IF_BYTE_COUNT),
1330                    (reg_type << 25) | (addr << 8) | port,
1331                    (u32)((data >> 32) & 0xffffffff),
1332                    (u32)(data & 0xffffffff));
1333
1334         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1335                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1336                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1337         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1338                  (reg_type << 25) | (addr << 8) | port);
1339         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1340         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1341                  (data >> 32) & 0xffffffff);
1342 }
1343
1344 #define XLPORT_MODE_REG (0x20a)
1345 #define XLPORT_MAC_CONTROL (0x210)
1346 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1347 #define XLPORT_ENABLE_REG (0x20b)
1348
1349 #define XLMAC_CTRL (0x600)
1350 #define XLMAC_MODE (0x601)
1351 #define XLMAC_RX_MAX_SIZE (0x608)
1352 #define XLMAC_TX_CTRL (0x604)
1353 #define XLMAC_PAUSE_CTRL (0x60d)
1354 #define XLMAC_PFC_CTRL (0x60e)
1355
1356 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1357                                     struct ecore_ptt *p_ptt)
1358 {
1359         u8 loopback = 0, port = p_hwfn->port_id * 2;
1360
1361         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1362
1363         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1364         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1365                          port);
1366         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1367         /* XLMAC: SOFT RESET */
1368         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1369         /* XLMAC: Port Speed >= 10Gbps */
1370         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1371         /* XLMAC: Max Size */
1372         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1373         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1374                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1375                          0, port);
1376         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1377         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1378                          0x30ffffc000ULL, 0, port);
1379         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1380                          port); /* XLMAC: TX_EN, RX_EN */
1381         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1382         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1383                          0x1003 | (loopback << 2), 0, port);
1384         /* Enabled Parallel PFC interface */
1385         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1386
1387         /* XLPORT port enable */
1388         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1389 }
1390
1391 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1392                                        struct ecore_ptt *p_ptt)
1393 {
1394         u8 port = p_hwfn->port_id;
1395         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1396
1397         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1398
1399         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1400                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1401                  (port <<
1402                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1403                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1404
1405         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1406                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1407
1408         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1409                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1410
1411         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1412                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1413
1414         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1415                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1416
1417         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1418                  (0xA <<
1419                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1420                  (8 <<
1421                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1422
1423         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1424                  0xa853);
1425 }
1426
1427 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1428                                  struct ecore_ptt *p_ptt)
1429 {
1430         if (ECORE_IS_AH(p_hwfn->p_dev))
1431                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1432         else /* BB */
1433                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1434 }
1435
1436 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1437                                struct ecore_ptt *p_ptt,  u8 port)
1438 {
1439         int port_offset = port ? 0x800 : 0;
1440         u32 xmac_rxctrl = 0;
1441
1442         /* Reset of XMAC */
1443         /* FIXME: move to common start */
1444         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1445                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1446         OSAL_MSLEEP(1);
1447         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1448                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1449
1450         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1451
1452         /* Set the number of ports on the Warp Core to 10G */
1453         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1454
1455         /* Soft reset of XMAC */
1456         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1457                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1458         OSAL_MSLEEP(1);
1459         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1460                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1461
1462         /* FIXME: move to common end */
1463         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1464                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1465
1466         /* Set Max packet size: initialize XMAC block register for port 0 */
1467         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1468
1469         /* CRC append for Tx packets: init XMAC block register for port 1 */
1470         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1471
1472         /* Enable TX and RX: initialize XMAC block register for port 1 */
1473         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1474                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1475         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1476                                XMAC_REG_RX_CTRL_BB + port_offset);
1477         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1478         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1479 }
1480 #endif
1481
1482 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1483                                                struct ecore_ptt *p_ptt,
1484                                                int hw_mode)
1485 {
1486         enum _ecore_status_t rc = ECORE_SUCCESS;
1487
1488         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1489                             hw_mode);
1490         if (rc != ECORE_SUCCESS)
1491                 return rc;
1492 #ifndef ASIC_ONLY
1493         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1494                 return ECORE_SUCCESS;
1495
1496         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1497                 if (ECORE_IS_AH(p_hwfn->p_dev))
1498                         return ECORE_SUCCESS;
1499                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1500                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1501         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1502                 if (p_hwfn->p_dev->num_hwfns > 1) {
1503                         /* Activate OPTE in CMT */
1504                         u32 val;
1505
1506                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1507                         val |= 0x10;
1508                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1509                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1510                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1511                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1512                         ecore_wr(p_hwfn, p_ptt,
1513                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1514                         ecore_wr(p_hwfn, p_ptt,
1515                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1516                         ecore_wr(p_hwfn, p_ptt,
1517                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1518                                  0x55555555);
1519                 }
1520
1521                 ecore_emul_link_init(p_hwfn, p_ptt);
1522         } else {
1523                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1524         }
1525 #endif
1526
1527         return rc;
1528 }
1529
1530 static enum _ecore_status_t
1531 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1532                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1533 {
1534         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1535         u32 dpi_bit_shift, dpi_count;
1536         u32 min_dpis;
1537
1538         /* Calculate DPI size
1539          * ------------------
1540          * The PWM region contains Doorbell Pages. The first is reserverd for
1541          * the kernel for, e.g, L2. The others are free to be used by non-
1542          * trusted applications, typically from user space. Each page, called a
1543          * doorbell page is sectioned into windows that allow doorbells to be
1544          * issued in parallel by the kernel/application. The size of such a
1545          * window (a.k.a. WID) is 1kB.
1546          * Summary:
1547          *    1kB WID x N WIDS = DPI page size
1548          *    DPI page size x N DPIs = PWM region size
1549          * Notes:
1550          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1551          * in order to ensure that two applications won't share the same page.
1552          * It also must contain at least one WID per CPU to allow parallelism.
1553          * It also must be a power of 2, since it is stored as a bit shift.
1554          *
1555          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1556          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1557          * containing 4 WIDs.
1558          */
1559         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1560         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1561         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1562         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1563         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1564
1565         dpi_count = pwm_region_size / dpi_page_size;
1566
1567         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1568         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1569
1570         /* Update hwfn */
1571         p_hwfn->dpi_size = dpi_page_size;
1572         p_hwfn->dpi_count = dpi_count;
1573
1574         /* Update registers */
1575         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1576
1577         if (dpi_count < min_dpis)
1578                 return ECORE_NORESOURCES;
1579
1580         return ECORE_SUCCESS;
1581 }
1582
1583 enum ECORE_ROCE_EDPM_MODE {
1584         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1585         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1586         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1587 };
1588
1589 static enum _ecore_status_t
1590 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1591                               struct ecore_ptt *p_ptt)
1592 {
1593         u32 pwm_regsize, norm_regsize;
1594         u32 non_pwm_conn, min_addr_reg1;
1595         u32 db_bar_size, n_cpus;
1596         u32 roce_edpm_mode;
1597         u32 pf_dems_shift;
1598         int rc = ECORE_SUCCESS;
1599         u8 cond;
1600
1601         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1602         if (p_hwfn->p_dev->num_hwfns > 1)
1603                 db_bar_size /= 2;
1604
1605         /* Calculate doorbell regions
1606          * -----------------------------------
1607          * The doorbell BAR is made of two regions. The first is called normal
1608          * region and the second is called PWM region. In the normal region
1609          * each ICID has its own set of addresses so that writing to that
1610          * specific address identifies the ICID. In the Process Window Mode
1611          * region the ICID is given in the data written to the doorbell. The
1612          * above per PF register denotes the offset in the doorbell BAR in which
1613          * the PWM region begins.
1614          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1615          * non-PWM connection. The calculation below computes the total non-PWM
1616          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1617          * in units of 4,096 bytes.
1618          */
1619         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1620             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1621                                           OSAL_NULL) +
1622             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1623         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1624         min_addr_reg1 = norm_regsize / 4096;
1625         pwm_regsize = db_bar_size - norm_regsize;
1626
1627         /* Check that the normal and PWM sizes are valid */
1628         if (db_bar_size < norm_regsize) {
1629                 DP_ERR(p_hwfn->p_dev,
1630                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1631                        db_bar_size, norm_regsize);
1632                 return ECORE_NORESOURCES;
1633         }
1634         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1635                 DP_ERR(p_hwfn->p_dev,
1636                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1637                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1638                        norm_regsize);
1639                 return ECORE_NORESOURCES;
1640         }
1641
1642         /* Calculate number of DPIs */
1643         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1644         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1645             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1646                 /* Either EDPM is mandatory, or we are attempting to allocate a
1647                  * WID per CPU.
1648                  */
1649                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1650                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1651         }
1652
1653         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1654             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1655         if (cond || p_hwfn->dcbx_no_edpm) {
1656                 /* Either EDPM is disabled from user configuration, or it is
1657                  * disabled via DCBx, or it is not mandatory and we failed to
1658                  * allocated a WID per CPU.
1659                  */
1660                 n_cpus = 1;
1661                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1662
1663                 /* If we entered this flow due to DCBX then the DPM register is
1664                  * already configured.
1665                  */
1666         }
1667
1668         DP_INFO(p_hwfn,
1669                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1670                 norm_regsize, pwm_regsize);
1671         DP_INFO(p_hwfn,
1672                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1673                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1674                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1675                 "disabled" : "enabled");
1676
1677         /* Check return codes from above calls */
1678         if (rc) {
1679                 DP_ERR(p_hwfn,
1680                        "Failed to allocate enough DPIs\n");
1681                 return ECORE_NORESOURCES;
1682         }
1683
1684         /* Update hwfn */
1685         p_hwfn->dpi_start_offset = norm_regsize;
1686
1687         /* Update registers */
1688         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1689         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1690         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1691         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1692
1693         return ECORE_SUCCESS;
1694 }
1695
1696 static enum _ecore_status_t
1697 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1698                  struct ecore_ptt *p_ptt,
1699                  struct ecore_tunnel_info *p_tunn,
1700                  int hw_mode,
1701                  bool b_hw_start,
1702                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1703 {
1704         u8 rel_pf_id = p_hwfn->rel_pf_id;
1705         u32 prs_reg;
1706         enum _ecore_status_t rc = ECORE_SUCCESS;
1707         u16 ctrl;
1708         int pos;
1709
1710         if (p_hwfn->mcp_info) {
1711                 struct ecore_mcp_function_info *p_info;
1712
1713                 p_info = &p_hwfn->mcp_info->func_info;
1714                 if (p_info->bandwidth_min)
1715                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1716
1717                 /* Update rate limit once we'll actually have a link */
1718                 p_hwfn->qm_info.pf_rl = 100000;
1719         }
1720         ecore_cxt_hw_init_pf(p_hwfn);
1721
1722         ecore_int_igu_init_rt(p_hwfn);
1723
1724         /* Set VLAN in NIG if needed */
1725         if (hw_mode & (1 << MODE_MF_SD)) {
1726                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1727                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1728                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1729                              p_hwfn->hw_info.ovlan);
1730         }
1731
1732         /* Enable classification by MAC if needed */
1733         if (hw_mode & (1 << MODE_MF_SI)) {
1734                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1735                            "Configuring TAGMAC_CLS_TYPE\n");
1736                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1737                              1);
1738         }
1739
1740         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1741         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1742                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1743         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1744                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1745         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1746
1747         /* perform debug configuration when chip is out of reset */
1748         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1749
1750         /* Cleanup chip from previous driver if such remains exist */
1751         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1752         if (rc != ECORE_SUCCESS) {
1753                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1754                 return rc;
1755         }
1756
1757         /* PF Init sequence */
1758         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1759         if (rc)
1760                 return rc;
1761
1762         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1763         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1764         if (rc)
1765                 return rc;
1766
1767         /* Pure runtime initializations - directly to the HW  */
1768         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1769
1770         /* PCI relaxed ordering causes a decrease in the performance on some
1771          * systems. Till a root cause is found, disable this attribute in the
1772          * PCI config space.
1773          */
1774         /* Not in use @DPDK
1775         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1776         * if (!pos) {
1777         *       DP_NOTICE(p_hwfn, true,
1778         *                 "Failed to find the PCIe Cap\n");
1779         *       return ECORE_IO;
1780         * }
1781         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1782         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1783         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1784         */
1785
1786         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1787         if (rc)
1788                 return rc;
1789         if (b_hw_start) {
1790                 /* enable interrupts */
1791                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1792                 if (rc != ECORE_SUCCESS)
1793                         return rc;
1794
1795                 /* send function start command */
1796                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1797                                        allow_npar_tx_switch);
1798                 if (rc) {
1799                         DP_NOTICE(p_hwfn, true,
1800                                   "Function start ramrod failed\n");
1801                 } else {
1802                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1803                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1804                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1805
1806                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1807                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1808                                          (1 << 2));
1809                                 ecore_wr(p_hwfn, p_ptt,
1810                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1811                                     0x100);
1812                         }
1813                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1814                                    "PRS_REG_SEARCH registers after start PFn\n");
1815                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1816                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1817                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1818                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1819                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1820                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1821                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1822                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1823                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1824                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1825                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1826                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1827                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1828                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1829                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1830                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1831                                    prs_reg);
1832                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1833                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1834                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1835                 }
1836         }
1837         return rc;
1838 }
1839
1840 static enum _ecore_status_t
1841 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1842                       struct ecore_ptt *p_ptt, u8 enable)
1843 {
1844         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1845
1846         /* Change PF in PXP */
1847         ecore_wr(p_hwfn, p_ptt,
1848                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1849
1850         /* wait until value is set - try for 1 second every 50us */
1851         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1852                 val = ecore_rd(p_hwfn, p_ptt,
1853                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1854                 if (val == set_val)
1855                         break;
1856
1857                 OSAL_UDELAY(50);
1858         }
1859
1860         if (val != set_val) {
1861                 DP_NOTICE(p_hwfn, true,
1862                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1863                 return ECORE_UNKNOWN_ERROR;
1864         }
1865
1866         return ECORE_SUCCESS;
1867 }
1868
1869 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1870                                   struct ecore_ptt *p_main_ptt)
1871 {
1872         /* Read shadow of current MFW mailbox */
1873         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1874         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1875                     p_hwfn->mcp_info->mfw_mb_cur,
1876                     p_hwfn->mcp_info->mfw_mb_length);
1877 }
1878
1879 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1880                                     struct ecore_hw_init_params *p_params)
1881 {
1882         if (p_params->p_tunn) {
1883                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1884                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1885         }
1886
1887         p_hwfn->b_int_enabled = 1;
1888
1889         return ECORE_SUCCESS;
1890 }
1891
1892 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1893                                    struct ecore_hw_init_params *p_params)
1894 {
1895         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1896         u32 load_code, param, drv_mb_param;
1897         bool b_default_mtu = true;
1898         struct ecore_hwfn *p_hwfn;
1899         int i;
1900
1901         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1902             (p_dev->num_hwfns > 1)) {
1903                 DP_NOTICE(p_dev, false,
1904                           "MSI mode is not supported for CMT devices\n");
1905                 return ECORE_INVAL;
1906         }
1907
1908         if (IS_PF(p_dev)) {
1909                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1910                 if (rc != ECORE_SUCCESS)
1911                         return rc;
1912         }
1913
1914         for_each_hwfn(p_dev, i) {
1915                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1916
1917                 /* If management didn't provide a default, set one of our own */
1918                 if (!p_hwfn->hw_info.mtu) {
1919                         p_hwfn->hw_info.mtu = 1500;
1920                         b_default_mtu = false;
1921                 }
1922
1923                 if (IS_VF(p_dev)) {
1924                         ecore_vf_start(p_hwfn, p_params);
1925                         continue;
1926                 }
1927
1928                 /* Enable DMAE in PXP */
1929                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1930                 if (rc != ECORE_SUCCESS)
1931                         return rc;
1932
1933                 rc = ecore_calc_hw_mode(p_hwfn);
1934                 if (rc != ECORE_SUCCESS)
1935                         return rc;
1936
1937                 /* @@@TBD need to add here:
1938                  * Check for fan failure
1939                  * Prev_unload
1940                  */
1941                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1942                 if (rc) {
1943                         DP_NOTICE(p_hwfn, true,
1944                                   "Failed sending LOAD_REQ command\n");
1945                         return rc;
1946                 }
1947
1948                 /* CQ75580:
1949                  * When coming back from hiberbate state, the registers from
1950                  * which shadow is read initially are not initialized. It turns
1951                  * out that these registers get initialized during the call to
1952                  * ecore_mcp_load_req request. So we need to reread them here
1953                  * to get the proper shadow register value.
1954                  * Note: This is a workaround for the missing MFW
1955                  * initialization. It may be removed once the implementation
1956                  * is done.
1957                  */
1958                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1959
1960                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1961                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1962                            rc, load_code);
1963
1964                 /* Only relevant for recovery:
1965                  * Clear the indication after the LOAD_REQ command is responded
1966                  * by the MFW.
1967                  */
1968                 p_dev->recov_in_prog = false;
1969
1970                 p_hwfn->first_on_engine = (load_code ==
1971                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1972
1973                 if (!qm_lock_init) {
1974                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1975                         qm_lock_init = true;
1976                 }
1977
1978                 switch (load_code) {
1979                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1980                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1981                                                   p_hwfn->hw_info.hw_mode);
1982                         if (rc)
1983                                 break;
1984                         /* Fall into */
1985                 case FW_MSG_CODE_DRV_LOAD_PORT:
1986                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1987                                                 p_hwfn->hw_info.hw_mode);
1988                         if (rc)
1989                                 break;
1990                         /* Fall into */
1991                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1992                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1993                                               p_params->p_tunn,
1994                                               p_hwfn->hw_info.hw_mode,
1995                                               p_params->b_hw_start,
1996                                               p_params->int_mode,
1997                                               p_params->allow_npar_tx_switch);
1998                         break;
1999                 default:
2000                         rc = ECORE_NOTIMPL;
2001                         break;
2002                 }
2003
2004                 if (rc != ECORE_SUCCESS)
2005                         DP_NOTICE(p_hwfn, true,
2006                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2007                                   load_code, rc);
2008
2009                 /* ACK mfw regardless of success or failure of initialization */
2010                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2011                                        DRV_MSG_CODE_LOAD_DONE,
2012                                        0, &load_code, &param);
2013                 if (rc != ECORE_SUCCESS)
2014                         return rc;
2015                 if (mfw_rc != ECORE_SUCCESS) {
2016                         DP_NOTICE(p_hwfn, true,
2017                                   "Failed sending LOAD_DONE command\n");
2018                         return mfw_rc;
2019                 }
2020
2021                 /* send DCBX attention request command */
2022                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2023                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2024                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2025                                        DRV_MSG_CODE_SET_DCBX,
2026                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2027                                        &load_code, &param);
2028                 if (mfw_rc != ECORE_SUCCESS) {
2029                         DP_NOTICE(p_hwfn, true,
2030                                   "Failed to send DCBX attention request\n");
2031                         return mfw_rc;
2032                 }
2033
2034                 p_hwfn->hw_init_done = true;
2035         }
2036
2037         if (IS_PF(p_dev)) {
2038                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2039                 drv_mb_param = (FW_MAJOR_VERSION << 24) |
2040                                (FW_MINOR_VERSION << 16) |
2041                                (FW_REVISION_VERSION << 8) |
2042                                (FW_ENGINEERING_VERSION);
2043                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2044                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2045                                    drv_mb_param, &load_code, &param);
2046                 if (rc != ECORE_SUCCESS)
2047                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2048
2049                 if (!b_default_mtu)
2050                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2051                                                       p_hwfn->hw_info.mtu);
2052                 if (rc != ECORE_SUCCESS)
2053                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2054
2055                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2056                                                       p_hwfn->p_main_ptt,
2057                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2058                 if (rc != ECORE_SUCCESS)
2059                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2060         }
2061
2062         return rc;
2063 }
2064
2065 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2066 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2067                                  struct ecore_hwfn *p_hwfn,
2068                                  struct ecore_ptt *p_ptt)
2069 {
2070         int i;
2071
2072         /* close timers */
2073         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2074         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2075         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2076                                                                         i++) {
2077                 if ((!ecore_rd(p_hwfn, p_ptt,
2078                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2079                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2080                         break;
2081
2082                 /* Dependent on number of connection/tasks, possibly
2083                  * 1ms sleep is required between polls
2084                  */
2085                 OSAL_MSLEEP(1);
2086         }
2087
2088         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2089                 return;
2090
2091         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2092                   " [Connection %02x Tasks %02x]\n",
2093                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2094                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2095 }
2096
2097 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2098 {
2099         int j;
2100
2101         for_each_hwfn(p_dev, j) {
2102                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2103                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2104
2105                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2106         }
2107 }
2108
2109 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2110 {
2111         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2112         int j;
2113
2114         for_each_hwfn(p_dev, j) {
2115                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2116                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2117
2118                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2119
2120                 if (IS_VF(p_dev)) {
2121                         ecore_vf_pf_int_cleanup(p_hwfn);
2122                         continue;
2123                 }
2124
2125                 /* mark the hw as uninitialized... */
2126                 p_hwfn->hw_init_done = false;
2127
2128                 rc = ecore_sp_pf_stop(p_hwfn);
2129                 if (rc)
2130                         DP_NOTICE(p_hwfn, true,
2131                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2132
2133                 /* perform debug action after PF stop was sent */
2134                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2135
2136                 /* close NIG to BRB gate */
2137                 ecore_wr(p_hwfn, p_ptt,
2138                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2139
2140                 /* close parser */
2141                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2142                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2143                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2144                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2145                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2146
2147                 /* @@@TBD - clean transmission queues (5.b) */
2148                 /* @@@TBD - clean BTB (5.c) */
2149
2150                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2151
2152                 /* @@@TBD - verify DMAE requests are done (8) */
2153
2154                 /* Disable Attention Generation */
2155                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2156                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2157                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2158                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2159                 /* Need to wait 1ms to guarantee SBs are cleared */
2160                 OSAL_MSLEEP(1);
2161         }
2162
2163         if (IS_PF(p_dev)) {
2164                 /* Disable DMAE in PXP - in CMT, this should only be done for
2165                  * first hw-function, and only after all transactions have
2166                  * stopped for all active hw-functions.
2167                  */
2168                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2169                                              p_dev->hwfns[0].p_main_ptt, false);
2170                 if (t_rc != ECORE_SUCCESS)
2171                         rc = t_rc;
2172         }
2173
2174         return rc;
2175 }
2176
2177 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2178 {
2179         int j;
2180
2181         for_each_hwfn(p_dev, j) {
2182                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2183                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2184
2185                 if (IS_VF(p_dev)) {
2186                         ecore_vf_pf_int_cleanup(p_hwfn);
2187                         continue;
2188                 }
2189
2190                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2191                            "Shutting down the fastpath\n");
2192
2193                 ecore_wr(p_hwfn, p_ptt,
2194                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2195
2196                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2197                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2198                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2199                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2200                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2201
2202                 /* @@@TBD - clean transmission queues (5.b) */
2203                 /* @@@TBD - clean BTB (5.c) */
2204
2205                 /* @@@TBD - verify DMAE requests are done (8) */
2206
2207                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2208                 /* Need to wait 1ms to guarantee SBs are cleared */
2209                 OSAL_MSLEEP(1);
2210         }
2211 }
2212
2213 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2214 {
2215         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2216
2217         if (IS_VF(p_hwfn->p_dev))
2218                 return;
2219
2220         /* If roce info is allocated it means roce is initialized and should
2221          * be enabled in searcher.
2222          */
2223         if (p_hwfn->p_rdma_info) {
2224                 if (p_hwfn->b_rdma_enabled_in_prs)
2225                         ecore_wr(p_hwfn, p_ptt,
2226                                  p_hwfn->rdma_prs_search_reg, 0x1);
2227                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2228         }
2229
2230         /* Re-open incoming traffic */
2231         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2232                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2233 }
2234
2235 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2236                                              struct ecore_ptt *p_ptt, u32 reg,
2237                                              bool expected)
2238 {
2239         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2240
2241         if (assert_val != expected) {
2242                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2243                           reg, expected);
2244                 return ECORE_UNKNOWN_ERROR;
2245         }
2246
2247         return 0;
2248 }
2249
2250 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2251 {
2252         enum _ecore_status_t rc = ECORE_SUCCESS;
2253         u32 unload_resp, unload_param;
2254         int i;
2255
2256         for_each_hwfn(p_dev, i) {
2257                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2258
2259                 if (IS_VF(p_dev)) {
2260                         rc = ecore_vf_pf_reset(p_hwfn);
2261                         if (rc)
2262                                 return rc;
2263                         continue;
2264                 }
2265
2266                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2267
2268                 /* Check for incorrect states */
2269                 if (!p_dev->recov_in_prog) {
2270                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2271                                          QM_REG_USG_CNT_PF_TX, 0);
2272                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2273                                          QM_REG_USG_CNT_PF_OTHER, 0);
2274                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2275                 }
2276
2277                 /* Disable PF in HW blocks */
2278                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2279                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2280
2281                 if (p_dev->recov_in_prog) {
2282                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2283                                    "Recovery is in progress -> skip sending unload_req/done\n");
2284                         break;
2285                 }
2286
2287                 /* Send unload command to MCP */
2288                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2289                                    DRV_MSG_CODE_UNLOAD_REQ,
2290                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2291                                    &unload_resp, &unload_param);
2292                 if (rc != ECORE_SUCCESS) {
2293                         DP_NOTICE(p_hwfn, true,
2294                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2295                         /* @@TBD - what to do? for now, assume ENG. */
2296                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2297                 }
2298
2299                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2300                                    DRV_MSG_CODE_UNLOAD_DONE,
2301                                    0, &unload_resp, &unload_param);
2302                 if (rc != ECORE_SUCCESS) {
2303                         DP_NOTICE(p_hwfn,
2304                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2305                         /* @@@TBD - Should it really ASSERT here ? */
2306                         return rc;
2307                 }
2308         }
2309
2310         return rc;
2311 }
2312
2313 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2314 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2315 {
2316         ecore_ptt_pool_free(p_hwfn);
2317         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2318 }
2319
2320 /* Setup bar access */
2321 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2322 {
2323         /* clear indirect access */
2324         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2325                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2326                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2327                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2328                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2329                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2330                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2331                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2332                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2333         } else {
2334                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2335                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2336                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2337                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2338                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2339                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2340                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2341                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2342         }
2343
2344         /* Clean Previous errors if such exist */
2345         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2346                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2347
2348         /* enable internal target-read */
2349         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2350                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2351 }
2352
2353 static void get_function_id(struct ecore_hwfn *p_hwfn)
2354 {
2355         /* ME Register */
2356         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2357                                                   PXP_PF_ME_OPAQUE_ADDR);
2358
2359         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2360
2361         /* Bits 16-19 from the ME registers are the pf_num */
2362         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2363         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2364                                       PXP_CONCRETE_FID_PFID);
2365         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2366                                     PXP_CONCRETE_FID_PORT);
2367
2368         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2369                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2370                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2371 }
2372
2373 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2374 {
2375         u32 *feat_num = p_hwfn->hw_info.feat_num;
2376         struct ecore_sb_cnt_info sb_cnt_info;
2377         int num_features = 1;
2378
2379         /* L2 Queues require each: 1 status block. 1 L2 queue */
2380         feat_num[ECORE_PF_L2_QUE] =
2381             OSAL_MIN_T(u32,
2382                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2383                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2384
2385         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2386         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2387         feat_num[ECORE_VF_L2_QUE] =
2388                 OSAL_MIN_T(u32,
2389                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2390                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2391                            sb_cnt_info.sb_iov_cnt);
2392
2393         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2394                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2395         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2396                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2397
2398         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2399                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2400                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2401                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2402                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2403                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2404                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2405                    RESC_NUM(p_hwfn, ECORE_SB));
2406 }
2407
2408 static enum resource_id_enum
2409 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2410 {
2411         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2412
2413         switch (res_id) {
2414         case ECORE_SB:
2415                 mfw_res_id = RESOURCE_NUM_SB_E;
2416                 break;
2417         case ECORE_L2_QUEUE:
2418                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2419                 break;
2420         case ECORE_VPORT:
2421                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2422                 break;
2423         case ECORE_RSS_ENG:
2424                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2425                 break;
2426         case ECORE_PQ:
2427                 mfw_res_id = RESOURCE_NUM_PQ_E;
2428                 break;
2429         case ECORE_RL:
2430                 mfw_res_id = RESOURCE_NUM_RL_E;
2431                 break;
2432         case ECORE_MAC:
2433         case ECORE_VLAN:
2434                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2435                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2436                 break;
2437         case ECORE_ILT:
2438                 mfw_res_id = RESOURCE_ILT_E;
2439                 break;
2440         case ECORE_LL2_QUEUE:
2441                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2442                 break;
2443         case ECORE_RDMA_CNQ_RAM:
2444         case ECORE_CMDQS_CQS:
2445                 /* CNQ/CMDQS are the same resource */
2446                 mfw_res_id = RESOURCE_CQS_E;
2447                 break;
2448         case ECORE_RDMA_STATS_QUEUE:
2449                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2450                 break;
2451         default:
2452                 break;
2453         }
2454
2455         return mfw_res_id;
2456 }
2457
2458 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2459                                       enum ecore_resources res_id)
2460 {
2461         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2462         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2463         struct ecore_sb_cnt_info sb_cnt_info;
2464         u32 dflt_resc_num = 0;
2465
2466         switch (res_id) {
2467         case ECORE_SB:
2468                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2469                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2470                 dflt_resc_num = sb_cnt_info.sb_cnt;
2471                 break;
2472         case ECORE_L2_QUEUE:
2473                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2474                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2475                 break;
2476         case ECORE_VPORT:
2477                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2478                                  MAX_NUM_VPORTS_BB) / num_funcs;
2479                 break;
2480         case ECORE_RSS_ENG:
2481                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2482                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2483                 break;
2484         case ECORE_PQ:
2485                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2486                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2487                 break;
2488         case ECORE_RL:
2489                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2490                 break;
2491         case ECORE_MAC:
2492         case ECORE_VLAN:
2493                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2494                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2495                 break;
2496         case ECORE_ILT:
2497                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2498                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2499                 break;
2500         case ECORE_LL2_QUEUE:
2501                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2502                 break;
2503         case ECORE_RDMA_CNQ_RAM:
2504         case ECORE_CMDQS_CQS:
2505                 /* CNQ/CMDQS are the same resource */
2506                 /* @DPDK */
2507                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2508                 break;
2509         case ECORE_RDMA_STATS_QUEUE:
2510                 /* @DPDK */
2511                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2512                                  MAX_NUM_VPORTS_BB) / num_funcs;
2513                 break;
2514         default:
2515                 break;
2516         }
2517
2518         return dflt_resc_num;
2519 }
2520
2521 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2522 {
2523         switch (res_id) {
2524         case ECORE_SB:
2525                 return "SB";
2526         case ECORE_L2_QUEUE:
2527                 return "L2_QUEUE";
2528         case ECORE_VPORT:
2529                 return "VPORT";
2530         case ECORE_RSS_ENG:
2531                 return "RSS_ENG";
2532         case ECORE_PQ:
2533                 return "PQ";
2534         case ECORE_RL:
2535                 return "RL";
2536         case ECORE_MAC:
2537                 return "MAC";
2538         case ECORE_VLAN:
2539                 return "VLAN";
2540         case ECORE_RDMA_CNQ_RAM:
2541                 return "RDMA_CNQ_RAM";
2542         case ECORE_ILT:
2543                 return "ILT";
2544         case ECORE_LL2_QUEUE:
2545                 return "LL2_QUEUE";
2546         case ECORE_CMDQS_CQS:
2547                 return "CMDQS_CQS";
2548         case ECORE_RDMA_STATS_QUEUE:
2549                 return "RDMA_STATS_QUEUE";
2550         default:
2551                 return "UNKNOWN_RESOURCE";
2552         }
2553 }
2554
2555 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2556                                                    enum ecore_resources res_id,
2557                                                    bool drv_resc_alloc)
2558 {
2559         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2560         u32 *p_resc_num, *p_resc_start;
2561         struct resource_info resc_info;
2562         enum _ecore_status_t rc;
2563
2564         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2565         p_resc_start = &RESC_START(p_hwfn, res_id);
2566
2567         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2568         if (!dflt_resc_num) {
2569                 DP_ERR(p_hwfn,
2570                        "Failed to get default amount for resource %d [%s]\n",
2571                         res_id, ecore_hw_get_resc_name(res_id));
2572                 return ECORE_INVAL;
2573         }
2574         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2575
2576 #ifndef ASIC_ONLY
2577         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2578                 *p_resc_num = dflt_resc_num;
2579                 *p_resc_start = dflt_resc_start;
2580                 goto out;
2581         }
2582 #endif
2583
2584         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2585         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2586         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2587                 DP_ERR(p_hwfn,
2588                        "Failed to match resource %d with MFW resources\n",
2589                        res_id);
2590                 return ECORE_INVAL;
2591         }
2592
2593         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2594                                      &mcp_resp, &mcp_param);
2595         if (rc != ECORE_SUCCESS) {
2596                 DP_NOTICE(p_hwfn, true,
2597                           "MFW response failure for an allocation request for"
2598                           " resource %d [%s]\n",
2599                           res_id, ecore_hw_get_resc_name(res_id));
2600                 return rc;
2601         }
2602
2603         /* Default driver values are applied in the following cases:
2604          * - The resource allocation MB command is not supported by the MFW
2605          * - There is an internal error in the MFW while processing the request
2606          * - The resource ID is unknown to the MFW
2607          */
2608         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2609             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2610                 /* @DPDK */
2611                 DP_INFO(p_hwfn,
2612                         "Resource %d [%s]: No allocation info was received"
2613                         " [mcp_resp 0x%x]. Applying default values"
2614                         " [num %d, start %d].\n",
2615                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2616                         dflt_resc_num, dflt_resc_start);
2617
2618                 *p_resc_num = dflt_resc_num;
2619                 *p_resc_start = dflt_resc_start;
2620                 goto out;
2621         }
2622
2623         /* TBD - remove this when revising the handling of the SB resource */
2624         if (res_id == ECORE_SB) {
2625                 /* Excluding the slowpath SB */
2626                 resc_info.size -= 1;
2627                 resc_info.offset -= p_hwfn->enabled_func_idx;
2628         }
2629
2630         *p_resc_num = resc_info.size;
2631         *p_resc_start = resc_info.offset;
2632
2633         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2634                 DP_INFO(p_hwfn,
2635                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2636                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2637                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2638                         drv_resc_alloc ? " - Applying default values" : "");
2639                 if (drv_resc_alloc) {
2640                         *p_resc_num = dflt_resc_num;
2641                         *p_resc_start = dflt_resc_start;
2642                 }
2643         }
2644 out:
2645         return ECORE_SUCCESS;
2646 }
2647
2648 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2649                                               bool drv_resc_alloc)
2650 {
2651         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2652         enum _ecore_status_t rc;
2653         u8 res_id;
2654 #ifndef ASIC_ONLY
2655         u32 *resc_start = p_hwfn->hw_info.resc_start;
2656         u32 *resc_num = p_hwfn->hw_info.resc_num;
2657         /* For AH, an equal share of the ILT lines between the maximal number of
2658          * PFs is not enough for RoCE. This would be solved by the future
2659          * resource allocation scheme, but isn't currently present for
2660          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2661          * to work - the BB number of ILT lines divided by its max PFs number.
2662          */
2663         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2664 #endif
2665
2666         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2667                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2668                 if (rc != ECORE_SUCCESS)
2669                         return rc;
2670         }
2671
2672 #ifndef ASIC_ONLY
2673         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2674                 /* Reduced build contains less PQs */
2675                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2676                         resc_num[ECORE_PQ] = 32;
2677                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2678                             p_hwfn->enabled_func_idx;
2679                 }
2680
2681                 /* For AH emulation, since we have a possible maximal number of
2682                  * 16 enabled PFs, in case there are not enough ILT lines -
2683                  * allocate only first PF as RoCE and have all the other ETH
2684                  * only with less ILT lines.
2685                  */
2686                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2687                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2688                                                          resc_num[ECORE_ILT],
2689                                                          roce_min_ilt_lines);
2690         }
2691
2692         /* Correct the common ILT calculation if PF0 has more */
2693         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2694             p_hwfn->p_dev->b_is_emul_full &&
2695             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2696                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2697                     resc_num[ECORE_ILT];
2698 #endif
2699
2700         /* Sanity for ILT */
2701         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2702             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2703                 DP_NOTICE(p_hwfn, true,
2704                           "Can't assign ILT pages [%08x,...,%08x]\n",
2705                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2706                                                                   ECORE_ILT) -
2707                           1);
2708                 return ECORE_INVAL;
2709         }
2710
2711         ecore_hw_set_feat(p_hwfn);
2712
2713         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2714                    "The numbers for each resource are:\n");
2715         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2716                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2717                            ecore_hw_get_resc_name(res_id),
2718                            RESC_NUM(p_hwfn, res_id),
2719                            RESC_START(p_hwfn, res_id));
2720
2721         return ECORE_SUCCESS;
2722 }
2723
2724 static enum _ecore_status_t
2725 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2726                       struct ecore_ptt *p_ptt,
2727                       struct ecore_hw_prepare_params *p_params)
2728 {
2729         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2730         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2731         struct ecore_mcp_link_params *link;
2732         enum _ecore_status_t rc;
2733
2734         /* Read global nvm_cfg address */
2735         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2736
2737         /* Verify MCP has initialized it */
2738         if (!nvm_cfg_addr) {
2739                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2740                 if (p_params->b_relaxed_probe)
2741                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2742                 return ECORE_INVAL;
2743         }
2744
2745 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2746
2747         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2748
2749         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2750             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2751                                                        core_cfg);
2752
2753         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2754
2755         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2756                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2757         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2758                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2759                 break;
2760         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2761                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2762                 break;
2763         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2764                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2765                 break;
2766         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2767                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2768                 break;
2769         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2770                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2771                 break;
2772         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2773                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2774                 break;
2775         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2776                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2777                 break;
2778         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2779                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2780                 break;
2781         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2782                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2783                 break;
2784         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2785                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2786                 break;
2787         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2788                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2789                 break;
2790         default:
2791                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2792                           core_cfg);
2793                 break;
2794         }
2795
2796         /* Read DCBX configuration */
2797         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2798                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2799         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2800                              port_cfg_addr +
2801                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2802         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2803                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2804         switch (dcbx_mode) {
2805         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2806                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2807                 break;
2808         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2809                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2810                 break;
2811         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2812                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2813                 break;
2814         default:
2815                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2816         }
2817
2818         /* Read default link configuration */
2819         link = &p_hwfn->mcp_info->link_input;
2820         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2821             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2822         link_temp = ecore_rd(p_hwfn, p_ptt,
2823                              port_cfg_addr +
2824                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2825         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2826         link->speed.advertised_speeds = link_temp;
2827
2828         link_temp = link->speed.advertised_speeds;
2829         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2830
2831         link_temp = ecore_rd(p_hwfn, p_ptt,
2832                              port_cfg_addr +
2833                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2834         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2835                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2836         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2837                 link->speed.autoneg = true;
2838                 break;
2839         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2840                 link->speed.forced_speed = 1000;
2841                 break;
2842         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2843                 link->speed.forced_speed = 10000;
2844                 break;
2845         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2846                 link->speed.forced_speed = 25000;
2847                 break;
2848         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2849                 link->speed.forced_speed = 40000;
2850                 break;
2851         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2852                 link->speed.forced_speed = 50000;
2853                 break;
2854         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2855                 link->speed.forced_speed = 100000;
2856                 break;
2857         default:
2858                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2859         }
2860
2861         p_hwfn->mcp_info->link_capabilities.default_speed =
2862             link->speed.forced_speed;
2863         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2864             link->speed.autoneg;
2865
2866         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2867         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2868         link->pause.autoneg = !!(link_temp &
2869                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2870         link->pause.forced_rx = !!(link_temp &
2871                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2872         link->pause.forced_tx = !!(link_temp &
2873                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2874         link->loopback_mode = 0;
2875
2876         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2877                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2878                    link->speed.forced_speed, link->speed.advertised_speeds,
2879                    link->speed.autoneg, link->pause.autoneg);
2880
2881         /* Read Multi-function information from shmem */
2882         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2883             OFFSETOF(struct nvm_cfg1, glob) +
2884             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2885
2886         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2887
2888         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2889             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2890
2891         switch (mf_mode) {
2892         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2893                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2894                 break;
2895         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2896                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2897                 break;
2898         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2899                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2900                 break;
2901         }
2902         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2903                 p_hwfn->p_dev->mf_mode);
2904
2905         /* Read Multi-function information from shmem */
2906         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2907             OFFSETOF(struct nvm_cfg1, glob) +
2908             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2909
2910         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2911         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2912                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2913                              &p_hwfn->hw_info.device_capabilities);
2914         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2915                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2916                              &p_hwfn->hw_info.device_capabilities);
2917         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2918                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2919                              &p_hwfn->hw_info.device_capabilities);
2920         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2921                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2922                              &p_hwfn->hw_info.device_capabilities);
2923         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2924                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2925                              &p_hwfn->hw_info.device_capabilities);
2926
2927         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2928         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2929                 rc = ECORE_SUCCESS;
2930                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2931         }
2932
2933         return rc;
2934 }
2935
2936 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2937                                 struct ecore_ptt *p_ptt)
2938 {
2939         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2940         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2941         struct ecore_dev *p_dev = p_hwfn->p_dev;
2942
2943         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2944
2945         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2946          * in the other bits are selected.
2947          * Bits 1-15 are for functions 1-15, respectively, and their value is
2948          * '0' only for enabled functions (function 0 always exists and
2949          * enabled).
2950          * In case of CMT in BB, only the "even" functions are enabled, and thus
2951          * the number of functions for both hwfns is learnt from the same bits.
2952          */
2953         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2954                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2955                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
2956         } else { /* E5 */
2957                 reg_function_hide = 0;
2958         }
2959
2960         if (reg_function_hide & 0x1) {
2961                 if (ECORE_IS_BB(p_dev)) {
2962                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2963                                 num_funcs = 0;
2964                                 eng_mask = 0xaaaa;
2965                         } else {
2966                                 num_funcs = 1;
2967                                 eng_mask = 0x5554;
2968                         }
2969                 } else {
2970                         num_funcs = 1;
2971                         eng_mask = 0xfffe;
2972                 }
2973
2974                 /* Get the number of the enabled functions on the engine */
2975                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2976                 while (tmp) {
2977                         if (tmp & 0x1)
2978                                 num_funcs++;
2979                         tmp >>= 0x1;
2980                 }
2981
2982                 /* Get the PF index within the enabled functions */
2983                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2984                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2985                 while (tmp) {
2986                         if (tmp & 0x1)
2987                                 enabled_func_idx--;
2988                         tmp >>= 0x1;
2989                 }
2990         }
2991
2992         p_hwfn->num_funcs_on_engine = num_funcs;
2993         p_hwfn->enabled_func_idx = enabled_func_idx;
2994
2995 #ifndef ASIC_ONLY
2996         if (CHIP_REV_IS_FPGA(p_dev)) {
2997                 DP_NOTICE(p_hwfn, false,
2998                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2999                 p_hwfn->num_funcs_on_engine = 4;
3000         }
3001 #endif
3002
3003         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3004                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3005                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3006                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3007 }
3008
3009 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3010                                       struct ecore_ptt *p_ptt)
3011 {
3012         u32 port_mode;
3013
3014 #ifndef ASIC_ONLY
3015         /* Read the port mode */
3016         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3017                 port_mode = 4;
3018         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3019                  (p_hwfn->p_dev->num_hwfns > 1))
3020                 /* In CMT on emulation, assume 1 port */
3021                 port_mode = 1;
3022         else
3023 #endif
3024         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3025
3026         if (port_mode < 3) {
3027                 p_hwfn->p_dev->num_ports_in_engines = 1;
3028         } else if (port_mode <= 5) {
3029                 p_hwfn->p_dev->num_ports_in_engines = 2;
3030         } else {
3031                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3032                           p_hwfn->p_dev->num_ports_in_engines);
3033
3034                 /* Default num_ports_in_engines to something */
3035                 p_hwfn->p_dev->num_ports_in_engines = 1;
3036         }
3037 }
3038
3039 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3040                                          struct ecore_ptt *p_ptt)
3041 {
3042         u32 port;
3043         int i;
3044
3045         p_hwfn->p_dev->num_ports_in_engines = 0;
3046
3047 #ifndef ASIC_ONLY
3048         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3049                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3050                 switch ((port & 0xf000) >> 12) {
3051                 case 1:
3052                         p_hwfn->p_dev->num_ports_in_engines = 1;
3053                         break;
3054                 case 3:
3055                         p_hwfn->p_dev->num_ports_in_engines = 2;
3056                         break;
3057                 case 0xf:
3058                         p_hwfn->p_dev->num_ports_in_engines = 4;
3059                         break;
3060                 default:
3061                         DP_NOTICE(p_hwfn, false,
3062                                   "Unknown port mode in ECO_RESERVED %08x\n",
3063                                   port);
3064                 }
3065         } else
3066 #endif
3067                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3068                         port = ecore_rd(p_hwfn, p_ptt,
3069                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3070                                         (i * 4));
3071                         if (port & 1)
3072                                 p_hwfn->p_dev->num_ports_in_engines++;
3073                 }
3074 }
3075
3076 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3077                                    struct ecore_ptt *p_ptt)
3078 {
3079         if (ECORE_IS_BB(p_hwfn->p_dev))
3080                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3081         else
3082                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3083 }
3084
3085 static enum _ecore_status_t
3086 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3087                   enum ecore_pci_personality personality,
3088                   struct ecore_hw_prepare_params *p_params)
3089 {
3090         bool drv_resc_alloc = p_params->drv_resc_alloc;
3091         enum _ecore_status_t rc;
3092
3093         /* Since all information is common, only first hwfns should do this */
3094         if (IS_LEAD_HWFN(p_hwfn)) {
3095                 rc = ecore_iov_hw_info(p_hwfn);
3096                 if (rc != ECORE_SUCCESS) {
3097                         if (p_params->b_relaxed_probe)
3098                                 p_params->p_relaxed_res =
3099                                                 ECORE_HW_PREPARE_BAD_IOV;
3100                         else
3101                                 return rc;
3102                 }
3103         }
3104
3105         /* TODO In get_hw_info, amoungst others:
3106          * Get MCP FW revision and determine according to it the supported
3107          * featrues (e.g. DCB)
3108          * Get boot mode
3109          * ecore_get_pcie_width_speed, WOL capability.
3110          * Number of global CQ-s (for storage
3111          */
3112         ecore_hw_info_port_num(p_hwfn, p_ptt);
3113
3114 #ifndef ASIC_ONLY
3115         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3116 #endif
3117         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3118         if (rc != ECORE_SUCCESS)
3119                 return rc;
3120 #ifndef ASIC_ONLY
3121         }
3122 #endif
3123
3124         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3125         if (rc != ECORE_SUCCESS) {
3126                 if (p_params->b_relaxed_probe)
3127                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3128                 else
3129                         return rc;
3130         }
3131
3132 #ifndef ASIC_ONLY
3133         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3134 #endif
3135                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3136                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3137 #ifndef ASIC_ONLY
3138         } else {
3139                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3140
3141                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3142                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3143         }
3144 #endif
3145
3146         if (ecore_mcp_is_init(p_hwfn)) {
3147                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3148                         p_hwfn->hw_info.ovlan =
3149                             p_hwfn->mcp_info->func_info.ovlan;
3150
3151                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3152         }
3153
3154         if (personality != ECORE_PCI_DEFAULT) {
3155                 p_hwfn->hw_info.personality = personality;
3156         } else if (ecore_mcp_is_init(p_hwfn)) {
3157                 enum ecore_pci_personality protocol;
3158
3159                 protocol = p_hwfn->mcp_info->func_info.protocol;
3160                 p_hwfn->hw_info.personality = protocol;
3161         }
3162
3163 #ifndef ASIC_ONLY
3164         /* To overcome ILT lack for emulation, until at least until we'll have
3165          * a definite answer from system about it, allow only PF0 to be RoCE.
3166          */
3167         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3168                 if (!p_hwfn->rel_pf_id)
3169                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3170                 else
3171                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3172         }
3173 #endif
3174
3175         /* although in BB some constellations may support more than 4 tcs,
3176          * that can result in performance penalty in some cases. 4
3177          * represents a good tradeoff between performance and flexibility.
3178          */
3179         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3180
3181         /* start out with a single active tc. This can be increased either
3182          * by dcbx negotiation or by upper layer driver
3183          */
3184         p_hwfn->hw_info.num_active_tc = 1;
3185
3186         ecore_get_num_funcs(p_hwfn, p_ptt);
3187
3188         if (ecore_mcp_is_init(p_hwfn))
3189                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3190
3191         /* In case of forcing the driver's default resource allocation, calling
3192          * ecore_hw_get_resc() should come after initializing the personality
3193          * and after getting the number of functions, since the calculation of
3194          * the resources/features depends on them.
3195          * This order is not harmful if not forcing.
3196          */
3197         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3198         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3199                 rc = ECORE_SUCCESS;
3200                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3201         }
3202
3203         return rc;
3204 }
3205
3206 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3207 {
3208         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3209         u32 tmp;
3210
3211         /* Read Vendor Id / Device Id */
3212         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3213                                   &p_dev->vendor_id);
3214         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3215                                   &p_dev->device_id);
3216
3217         /* Determine type */
3218         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3219                 p_dev->type = ECORE_DEV_TYPE_AH;
3220         else
3221                 p_dev->type = ECORE_DEV_TYPE_BB;
3222
3223         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3224                                          MISCS_REG_CHIP_NUM);
3225         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3226                                          MISCS_REG_CHIP_REV);
3227
3228         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3229
3230         /* Learn number of HW-functions */
3231         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3232                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3233
3234         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3235                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3236                 p_dev->num_hwfns = 2;
3237         } else {
3238                 p_dev->num_hwfns = 1;
3239         }
3240
3241 #ifndef ASIC_ONLY
3242         if (CHIP_REV_IS_EMUL(p_dev)) {
3243                 /* For some reason we have problems with this register
3244                  * in B0 emulation; Simply assume no CMT
3245                  */
3246                 DP_NOTICE(p_dev->hwfns, false,
3247                           "device on emul - assume no CMT\n");
3248                 p_dev->num_hwfns = 1;
3249         }
3250 #endif
3251
3252         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3253                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3254         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3255         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3256                                            MISCS_REG_CHIP_METAL);
3257         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3258         DP_INFO(p_dev->hwfns,
3259                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3260                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3261                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3262                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3263                 p_dev->chip_metal);
3264
3265         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3266                 DP_NOTICE(p_dev->hwfns, false,
3267                           "The chip type/rev (BB A0) is not supported!\n");
3268                 return ECORE_ABORTED;
3269         }
3270 #ifndef ASIC_ONLY
3271         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3272                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3273                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3274
3275         if (CHIP_REV_IS_EMUL(p_dev)) {
3276                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3277                                MISCS_REG_ECO_RESERVED);
3278                 if (tmp & (1 << 29)) {
3279                         DP_NOTICE(p_hwfn, false,
3280                                   "Emulation: Running on a FULL build\n");
3281                         p_dev->b_is_emul_full = true;
3282                 } else {
3283                         DP_NOTICE(p_hwfn, false,
3284                                   "Emulation: Running on a REDUCED build\n");
3285                 }
3286         }
3287 #endif
3288
3289         return ECORE_SUCCESS;
3290 }
3291
3292 #ifndef LINUX_REMOVE
3293 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3294 {
3295         int j;
3296
3297         if (IS_VF(p_dev))
3298                 return;
3299
3300         for_each_hwfn(p_dev, j) {
3301                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3302
3303                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3304                            "Mark hw/fw uninitialized\n");
3305
3306                 p_hwfn->hw_init_done = false;
3307                 p_hwfn->first_on_engine = false;
3308
3309                 ecore_ptt_invalidate(p_hwfn);
3310         }
3311 }
3312 #endif
3313
3314 static enum _ecore_status_t
3315 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3316                         void OSAL_IOMEM * p_regview,
3317                         void OSAL_IOMEM * p_doorbells,
3318                         struct ecore_hw_prepare_params *p_params)
3319 {
3320         struct ecore_dev *p_dev = p_hwfn->p_dev;
3321         struct ecore_mdump_info mdump_info;
3322         enum _ecore_status_t rc = ECORE_SUCCESS;
3323
3324         /* Split PCI bars evenly between hwfns */
3325         p_hwfn->regview = p_regview;
3326         p_hwfn->doorbells = p_doorbells;
3327
3328         if (IS_VF(p_dev))
3329                 return ecore_vf_hw_prepare(p_hwfn);
3330
3331         /* Validate that chip access is feasible */
3332         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3333                 DP_ERR(p_hwfn,
3334                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3335                 if (p_params->b_relaxed_probe)
3336                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3337                 return ECORE_INVAL;
3338         }
3339
3340         get_function_id(p_hwfn);
3341
3342         /* Allocate PTT pool */
3343         rc = ecore_ptt_pool_alloc(p_hwfn);
3344         if (rc) {
3345                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3346                 if (p_params->b_relaxed_probe)
3347                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3348                 goto err0;
3349         }
3350
3351         /* Allocate the main PTT */
3352         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3353
3354         /* First hwfn learns basic information, e.g., number of hwfns */
3355         if (!p_hwfn->my_id) {
3356                 rc = ecore_get_dev_info(p_dev);
3357                 if (rc != ECORE_SUCCESS) {
3358                         if (p_params->b_relaxed_probe)
3359                                 p_params->p_relaxed_res =
3360                                         ECORE_HW_PREPARE_FAILED_DEV;
3361                         goto err1;
3362                 }
3363         }
3364
3365         ecore_hw_hwfn_prepare(p_hwfn);
3366
3367         /* Initialize MCP structure */
3368         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3369         if (rc) {
3370                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3371                 if (p_params->b_relaxed_probe)
3372                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3373                 goto err1;
3374         }
3375
3376         /* Read the device configuration information from the HW and SHMEM */
3377         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3378                                p_params->personality, p_params);
3379         if (rc) {
3380                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3381                 goto err2;
3382         }
3383
3384         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3385          * called, since among others it sets the ports number in an engine.
3386          */
3387         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3388             !p_dev->recov_in_prog) {
3389                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3390                 if (rc != ECORE_SUCCESS)
3391                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3392         }
3393
3394         /* Check if mdump logs are present and update the epoch value */
3395         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3396                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3397                                               &mdump_info);
3398                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3399                         DP_NOTICE(p_hwfn, false,
3400                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3401                 }
3402
3403                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3404                                            p_params->epoch);
3405         }
3406
3407         /* Allocate the init RT array and initialize the init-ops engine */
3408         rc = ecore_init_alloc(p_hwfn);
3409         if (rc) {
3410                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3411                 if (p_params->b_relaxed_probe)
3412                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3413                 goto err2;
3414         }
3415 #ifndef ASIC_ONLY
3416         if (CHIP_REV_IS_FPGA(p_dev)) {
3417                 DP_NOTICE(p_hwfn, false,
3418                           "FPGA: workaround; Prevent DMAE parities\n");
3419                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3420                          7);
3421
3422                 DP_NOTICE(p_hwfn, false,
3423                           "FPGA: workaround: Set VF bar0 size\n");
3424                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3425                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3426         }
3427 #endif
3428
3429         return rc;
3430 err2:
3431         if (IS_LEAD_HWFN(p_hwfn))
3432                 ecore_iov_free_hw_info(p_dev);
3433         ecore_mcp_free(p_hwfn);
3434 err1:
3435         ecore_hw_hwfn_free(p_hwfn);
3436 err0:
3437         return rc;
3438 }
3439
3440 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3441                                       struct ecore_hw_prepare_params *p_params)
3442 {
3443         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3444         enum _ecore_status_t rc;
3445
3446         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3447
3448         if (p_params->b_relaxed_probe)
3449                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3450
3451         /* Store the precompiled init data ptrs */
3452         if (IS_PF(p_dev))
3453                 ecore_init_iro_array(p_dev);
3454
3455         /* Initialize the first hwfn - will learn number of hwfns */
3456         rc = ecore_hw_prepare_single(p_hwfn,
3457                                      p_dev->regview,
3458                                      p_dev->doorbells, p_params);
3459         if (rc != ECORE_SUCCESS)
3460                 return rc;
3461
3462         p_params->personality = p_hwfn->hw_info.personality;
3463
3464         /* initilalize 2nd hwfn if necessary */
3465         if (p_dev->num_hwfns > 1) {
3466                 void OSAL_IOMEM *p_regview, *p_doorbell;
3467                 u8 OSAL_IOMEM *addr;
3468
3469                 /* adjust bar offset for second engine */
3470                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3471                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3472                 p_regview = (void OSAL_IOMEM *)addr;
3473
3474                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3475                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3476                 p_doorbell = (void OSAL_IOMEM *)addr;
3477
3478                 /* prepare second hw function */
3479                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3480                                              p_doorbell, p_params);
3481
3482                 /* in case of error, need to free the previously
3483                  * initiliazed hwfn 0.
3484                  */
3485                 if (rc != ECORE_SUCCESS) {
3486                         if (p_params->b_relaxed_probe)
3487                                 p_params->p_relaxed_res =
3488                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3489
3490                         if (IS_PF(p_dev)) {
3491                                 ecore_init_free(p_hwfn);
3492                                 ecore_mcp_free(p_hwfn);
3493                                 ecore_hw_hwfn_free(p_hwfn);
3494                         } else {
3495                                 DP_NOTICE(p_dev, true,
3496                                           "What do we need to free when VF hwfn1 init fails\n");
3497                         }
3498                         return rc;
3499                 }
3500         }
3501
3502         return rc;
3503 }
3504
3505 void ecore_hw_remove(struct ecore_dev *p_dev)
3506 {
3507         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3508         int i;
3509
3510         if (IS_PF(p_dev))
3511                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3512                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3513
3514         for_each_hwfn(p_dev, i) {
3515                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3516
3517                 if (IS_VF(p_dev)) {
3518                         ecore_vf_pf_release(p_hwfn);
3519                         continue;
3520                 }
3521
3522                 ecore_init_free(p_hwfn);
3523                 ecore_hw_hwfn_free(p_hwfn);
3524                 ecore_mcp_free(p_hwfn);
3525
3526                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3527         }
3528
3529         ecore_iov_free_hw_info(p_dev);
3530 }
3531
3532 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3533                                       struct ecore_chain *p_chain)
3534 {
3535         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3536         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3537         struct ecore_chain_next *p_next;
3538         u32 size, i;
3539
3540         if (!p_virt)
3541                 return;
3542
3543         size = p_chain->elem_size * p_chain->usable_per_page;
3544
3545         for (i = 0; i < p_chain->page_cnt; i++) {
3546                 if (!p_virt)
3547                         break;
3548
3549                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3550                 p_virt_next = p_next->next_virt;
3551                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3552
3553                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3554                                        ECORE_CHAIN_PAGE_SIZE);
3555
3556                 p_virt = p_virt_next;
3557                 p_phys = p_phys_next;
3558         }
3559 }
3560
3561 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3562                                     struct ecore_chain *p_chain)
3563 {
3564         if (!p_chain->p_virt_addr)
3565                 return;
3566
3567         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3568                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3569 }
3570
3571 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3572                                  struct ecore_chain *p_chain)
3573 {
3574         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3575         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3576         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3577
3578         if (!pp_virt_addr_tbl)
3579                 return;
3580
3581         if (!p_pbl_virt)
3582                 goto out;
3583
3584         for (i = 0; i < page_cnt; i++) {
3585                 if (!pp_virt_addr_tbl[i])
3586                         break;
3587
3588                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3589                                        *(dma_addr_t *)p_pbl_virt,
3590                                        ECORE_CHAIN_PAGE_SIZE);
3591
3592                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3593         }
3594
3595         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3596
3597         if (!p_chain->b_external_pbl)
3598                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3599                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3600  out:
3601         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3602 }
3603
3604 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3605 {
3606         switch (p_chain->mode) {
3607         case ECORE_CHAIN_MODE_NEXT_PTR:
3608                 ecore_chain_free_next_ptr(p_dev, p_chain);
3609                 break;
3610         case ECORE_CHAIN_MODE_SINGLE:
3611                 ecore_chain_free_single(p_dev, p_chain);
3612                 break;
3613         case ECORE_CHAIN_MODE_PBL:
3614                 ecore_chain_free_pbl(p_dev, p_chain);
3615                 break;
3616         }
3617 }
3618
3619 static enum _ecore_status_t
3620 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3621                                enum ecore_chain_cnt_type cnt_type,
3622                                osal_size_t elem_size, u32 page_cnt)
3623 {
3624         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3625
3626         /* The actual chain size can be larger than the maximal possible value
3627          * after rounding up the requested elements number to pages, and after
3628          * taking into acount the unusuable elements (next-ptr elements).
3629          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3630          * size/capacity fields are of a u32 type.
3631          */
3632         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3633              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3634             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3635              chain_size > ECORE_U32_MAX)) {
3636                 DP_NOTICE(p_dev, true,
3637                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3638                           (unsigned long)chain_size);
3639                 return ECORE_INVAL;
3640         }
3641
3642         return ECORE_SUCCESS;
3643 }
3644
3645 static enum _ecore_status_t
3646 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3647 {
3648         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3649         dma_addr_t p_phys = 0;
3650         u32 i;
3651
3652         for (i = 0; i < p_chain->page_cnt; i++) {
3653                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3654                                                  ECORE_CHAIN_PAGE_SIZE);
3655                 if (!p_virt) {
3656                         DP_NOTICE(p_dev, true,
3657                                   "Failed to allocate chain memory\n");
3658                         return ECORE_NOMEM;
3659                 }
3660
3661                 if (i == 0) {
3662                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3663                         ecore_chain_reset(p_chain);
3664                 } else {
3665                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3666                                                        p_virt, p_phys);
3667                 }
3668
3669                 p_virt_prev = p_virt;
3670         }
3671         /* Last page's next element should point to the beginning of the
3672          * chain.
3673          */
3674         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3675                                        p_chain->p_virt_addr,
3676                                        p_chain->p_phys_addr);
3677
3678         return ECORE_SUCCESS;
3679 }
3680
3681 static enum _ecore_status_t
3682 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3683 {
3684         dma_addr_t p_phys = 0;
3685         void *p_virt = OSAL_NULL;
3686
3687         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3688         if (!p_virt) {
3689                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3690                 return ECORE_NOMEM;
3691         }
3692
3693         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3694         ecore_chain_reset(p_chain);
3695
3696         return ECORE_SUCCESS;
3697 }
3698
3699 static enum _ecore_status_t
3700 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3701                       struct ecore_chain *p_chain,
3702                       struct ecore_chain_ext_pbl *ext_pbl)
3703 {
3704         void *p_virt = OSAL_NULL;
3705         u8 *p_pbl_virt = OSAL_NULL;
3706         void **pp_virt_addr_tbl = OSAL_NULL;
3707         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3708         u32 page_cnt = p_chain->page_cnt, size, i;
3709
3710         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3711         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3712         if (!pp_virt_addr_tbl) {
3713                 DP_NOTICE(p_dev, true,
3714                           "Failed to allocate memory for the chain virtual addresses table\n");
3715                 return ECORE_NOMEM;
3716         }
3717         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3718
3719         /* The allocation of the PBL table is done with its full size, since it
3720          * is expected to be successive.
3721          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3722          * failure, since pp_virt_addr_tbl was previously allocated, and it
3723          * should be saved to allow its freeing during the error flow.
3724          */
3725         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3726
3727         if (ext_pbl == OSAL_NULL) {
3728                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3729         } else {
3730                 p_pbl_virt = ext_pbl->p_pbl_virt;
3731                 p_pbl_phys = ext_pbl->p_pbl_phys;
3732                 p_chain->b_external_pbl = true;
3733         }
3734
3735         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3736                                  pp_virt_addr_tbl);
3737         if (!p_pbl_virt) {
3738                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3739                 return ECORE_NOMEM;
3740         }
3741
3742         for (i = 0; i < page_cnt; i++) {
3743                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3744                                                  ECORE_CHAIN_PAGE_SIZE);
3745                 if (!p_virt) {
3746                         DP_NOTICE(p_dev, true,
3747                                   "Failed to allocate chain memory\n");
3748                         return ECORE_NOMEM;
3749                 }
3750
3751                 if (i == 0) {
3752                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3753                         ecore_chain_reset(p_chain);
3754                 }
3755
3756                 /* Fill the PBL table with the physical address of the page */
3757                 *(dma_addr_t *)p_pbl_virt = p_phys;
3758                 /* Keep the virtual address of the page */
3759                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3760
3761                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3762         }
3763
3764         return ECORE_SUCCESS;
3765 }
3766
3767 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3768                                        enum ecore_chain_use_mode intended_use,
3769                                        enum ecore_chain_mode mode,
3770                                        enum ecore_chain_cnt_type cnt_type,
3771                                        u32 num_elems, osal_size_t elem_size,
3772                                        struct ecore_chain *p_chain,
3773                                        struct ecore_chain_ext_pbl *ext_pbl)
3774 {
3775         u32 page_cnt;
3776         enum _ecore_status_t rc = ECORE_SUCCESS;
3777
3778         if (mode == ECORE_CHAIN_MODE_SINGLE)
3779                 page_cnt = 1;
3780         else
3781                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3782
3783         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3784                                             page_cnt);
3785         if (rc) {
3786                 DP_NOTICE(p_dev, true,
3787                           "Cannot allocate a chain with the given arguments:\n"
3788                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3789                           intended_use, mode, cnt_type, num_elems, elem_size);
3790                 return rc;
3791         }
3792
3793         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3794                                 mode, cnt_type, p_dev->dp_ctx);
3795
3796         switch (mode) {
3797         case ECORE_CHAIN_MODE_NEXT_PTR:
3798                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3799                 break;
3800         case ECORE_CHAIN_MODE_SINGLE:
3801                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3802                 break;
3803         case ECORE_CHAIN_MODE_PBL:
3804                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3805                 break;
3806         }
3807         if (rc)
3808                 goto nomem;
3809
3810         return ECORE_SUCCESS;
3811
3812 nomem:
3813         ecore_chain_free(p_dev, p_chain);
3814         return rc;
3815 }
3816
3817 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3818                                        u16 src_id, u16 *dst_id)
3819 {
3820         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3821                 u16 min, max;
3822
3823                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3824                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3825                 DP_NOTICE(p_hwfn, true,
3826                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3827                           src_id, min, max);
3828
3829                 return ECORE_INVAL;
3830         }
3831
3832         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3833
3834         return ECORE_SUCCESS;
3835 }
3836
3837 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3838                                     u8 src_id, u8 *dst_id)
3839 {
3840         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3841                 u8 min, max;
3842
3843                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3844                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3845                 DP_NOTICE(p_hwfn, true,
3846                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3847                           src_id, min, max);
3848
3849                 return ECORE_INVAL;
3850         }
3851
3852         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3853
3854         return ECORE_SUCCESS;
3855 }
3856
3857 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3858                                       u8 src_id, u8 *dst_id)
3859 {
3860         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3861                 u8 min, max;
3862
3863                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3864                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3865                 DP_NOTICE(p_hwfn, true,
3866                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3867                           src_id, min, max);
3868
3869                 return ECORE_INVAL;
3870         }
3871
3872         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3873
3874         return ECORE_SUCCESS;
3875 }
3876
3877 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3878                                               struct ecore_ptt *p_ptt,
3879                                               u8 *p_filter)
3880 {
3881         u32 high, low, en;
3882         int i;
3883
3884         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3885                 return ECORE_SUCCESS;
3886
3887         high = p_filter[1] | (p_filter[0] << 8);
3888         low = p_filter[5] | (p_filter[4] << 8) |
3889             (p_filter[3] << 16) | (p_filter[2] << 24);
3890
3891         /* Find a free entry and utilize it */
3892         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3893                 en = ecore_rd(p_hwfn, p_ptt,
3894                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3895                 if (en)
3896                         continue;
3897                 ecore_wr(p_hwfn, p_ptt,
3898                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3899                          2 * i * sizeof(u32), low);
3900                 ecore_wr(p_hwfn, p_ptt,
3901                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3902                          (2 * i + 1) * sizeof(u32), high);
3903                 ecore_wr(p_hwfn, p_ptt,
3904                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3905                 ecore_wr(p_hwfn, p_ptt,
3906                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3907                          i * sizeof(u32), 0);
3908                 ecore_wr(p_hwfn, p_ptt,
3909                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3910                 break;
3911         }
3912         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3913                 DP_NOTICE(p_hwfn, false,
3914                           "Failed to find an empty LLH filter to utilize\n");
3915                 return ECORE_INVAL;
3916         }
3917
3918         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3919                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3920                    p_filter[0], p_filter[1], p_filter[2],
3921                    p_filter[3], p_filter[4], p_filter[5], i);
3922
3923         return ECORE_SUCCESS;
3924 }
3925
3926 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3927                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3928 {
3929         u32 high, low;
3930         int i;
3931
3932         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3933                 return;
3934
3935         high = p_filter[1] | (p_filter[0] << 8);
3936         low = p_filter[5] | (p_filter[4] << 8) |
3937             (p_filter[3] << 16) | (p_filter[2] << 24);
3938
3939         /* Find the entry and clean it */
3940         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3941                 if (ecore_rd(p_hwfn, p_ptt,
3942                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3943                              2 * i * sizeof(u32)) != low)
3944                         continue;
3945                 if (ecore_rd(p_hwfn, p_ptt,
3946                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3947                              (2 * i + 1) * sizeof(u32)) != high)
3948                         continue;
3949
3950                 ecore_wr(p_hwfn, p_ptt,
3951                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3952                 ecore_wr(p_hwfn, p_ptt,
3953                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3954                          2 * i * sizeof(u32), 0);
3955                 ecore_wr(p_hwfn, p_ptt,
3956                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3957                          (2 * i + 1) * sizeof(u32), 0);
3958                 break;
3959         }
3960         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3961                 DP_NOTICE(p_hwfn, false,
3962                           "Tried to remove a non-configured filter\n");
3963 }
3964
3965 enum _ecore_status_t
3966 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3967                               struct ecore_ptt *p_ptt,
3968                               u16 source_port_or_eth_type,
3969                               u16 dest_port,
3970                               enum ecore_llh_port_filter_type_t type)
3971 {
3972         u32 high, low, en;
3973         int i;
3974
3975         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3976                 return ECORE_SUCCESS;
3977
3978         high = 0;
3979         low = 0;
3980         switch (type) {
3981         case ECORE_LLH_FILTER_ETHERTYPE:
3982                 high = source_port_or_eth_type;
3983                 break;
3984         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3985         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3986                 low = source_port_or_eth_type << 16;
3987                 break;
3988         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3989         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3990                 low = dest_port;
3991                 break;
3992         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3993         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3994                 low = (source_port_or_eth_type << 16) | dest_port;
3995                 break;
3996         default:
3997                 DP_NOTICE(p_hwfn, true,
3998                           "Non valid LLH protocol filter type %d\n", type);
3999                 return ECORE_INVAL;
4000         }
4001         /* Find a free entry and utilize it */
4002         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4003                 en = ecore_rd(p_hwfn, p_ptt,
4004                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4005                 if (en)
4006                         continue;
4007                 ecore_wr(p_hwfn, p_ptt,
4008                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4009                          2 * i * sizeof(u32), low);
4010                 ecore_wr(p_hwfn, p_ptt,
4011                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4012                          (2 * i + 1) * sizeof(u32), high);
4013                 ecore_wr(p_hwfn, p_ptt,
4014                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4015                 ecore_wr(p_hwfn, p_ptt,
4016                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4017                          i * sizeof(u32), 1 << type);
4018                 ecore_wr(p_hwfn, p_ptt,
4019                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4020                 break;
4021         }
4022         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4023                 DP_NOTICE(p_hwfn, false,
4024                           "Failed to find an empty LLH filter to utilize\n");
4025                 return ECORE_NORESOURCES;
4026         }
4027         switch (type) {
4028         case ECORE_LLH_FILTER_ETHERTYPE:
4029                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4030                            "ETH type %x is added at %d\n",
4031                            source_port_or_eth_type, i);
4032                 break;
4033         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4034                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4035                            "TCP src port %x is added at %d\n",
4036                            source_port_or_eth_type, i);
4037                 break;
4038         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4039                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4040                            "UDP src port %x is added at %d\n",
4041                            source_port_or_eth_type, i);
4042                 break;
4043         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4044                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4045                            "TCP dst port %x is added at %d\n", dest_port, i);
4046                 break;
4047         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4048                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4049                            "UDP dst port %x is added at %d\n", dest_port, i);
4050                 break;
4051         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4052                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4053                            "TCP src/dst ports %x/%x are added at %d\n",
4054                            source_port_or_eth_type, dest_port, i);
4055                 break;
4056         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4057                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4058                            "UDP src/dst ports %x/%x are added at %d\n",
4059                            source_port_or_eth_type, dest_port, i);
4060                 break;
4061         }
4062         return ECORE_SUCCESS;
4063 }
4064
4065 void
4066 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4067                                  struct ecore_ptt *p_ptt,
4068                                  u16 source_port_or_eth_type,
4069                                  u16 dest_port,
4070                                  enum ecore_llh_port_filter_type_t type)
4071 {
4072         u32 high, low;
4073         int i;
4074
4075         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4076                 return;
4077
4078         high = 0;
4079         low = 0;
4080         switch (type) {
4081         case ECORE_LLH_FILTER_ETHERTYPE:
4082                 high = source_port_or_eth_type;
4083                 break;
4084         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4085         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4086                 low = source_port_or_eth_type << 16;
4087                 break;
4088         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4089         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4090                 low = dest_port;
4091                 break;
4092         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4093         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4094                 low = (source_port_or_eth_type << 16) | dest_port;
4095                 break;
4096         default:
4097                 DP_NOTICE(p_hwfn, true,
4098                           "Non valid LLH protocol filter type %d\n", type);
4099                 return;
4100         }
4101
4102         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4103                 if (!ecore_rd(p_hwfn, p_ptt,
4104                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4105                         continue;
4106                 if (!ecore_rd(p_hwfn, p_ptt,
4107                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4108                         continue;
4109                 if (!(ecore_rd(p_hwfn, p_ptt,
4110                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4111                                i * sizeof(u32)) & (1 << type)))
4112                         continue;
4113                 if (ecore_rd(p_hwfn, p_ptt,
4114                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4115                              2 * i * sizeof(u32)) != low)
4116                         continue;
4117                 if (ecore_rd(p_hwfn, p_ptt,
4118                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4119                              (2 * i + 1) * sizeof(u32)) != high)
4120                         continue;
4121
4122                 ecore_wr(p_hwfn, p_ptt,
4123                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4124                 ecore_wr(p_hwfn, p_ptt,
4125                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4126                 ecore_wr(p_hwfn, p_ptt,
4127                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4128                          i * sizeof(u32), 0);
4129                 ecore_wr(p_hwfn, p_ptt,
4130                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4131                          2 * i * sizeof(u32), 0);
4132                 ecore_wr(p_hwfn, p_ptt,
4133                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4134                          (2 * i + 1) * sizeof(u32), 0);
4135                 break;
4136         }
4137
4138         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4139                 DP_NOTICE(p_hwfn, false,
4140                           "Tried to remove a non-configured filter\n");
4141 }
4142
4143 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4144                                  struct ecore_ptt *p_ptt)
4145 {
4146         int i;
4147
4148         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4149                 return;
4150
4151         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4152                 ecore_wr(p_hwfn, p_ptt,
4153                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4154                 ecore_wr(p_hwfn, p_ptt,
4155                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4156                          2 * i * sizeof(u32), 0);
4157                 ecore_wr(p_hwfn, p_ptt,
4158                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4159                          (2 * i + 1) * sizeof(u32), 0);
4160         }
4161 }
4162
4163 enum _ecore_status_t
4164 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4165                                   struct ecore_ptt *p_ptt)
4166 {
4167         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4168                 ecore_wr(p_hwfn, p_ptt,
4169                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4170                          1 << p_hwfn->abs_pf_id / 2);
4171                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4172                 return ECORE_SUCCESS;
4173         }
4174
4175         DP_NOTICE(p_hwfn, false,
4176                   "This function can't be set as default\n");
4177         return ECORE_INVAL;
4178 }
4179
4180 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4181                                                struct ecore_ptt *p_ptt,
4182                                                u32 hw_addr, void *p_eth_qzone,
4183                                                osal_size_t eth_qzone_size,
4184                                                u8 timeset)
4185 {
4186         struct coalescing_timeset *p_coal_timeset;
4187
4188         if (IS_VF(p_hwfn->p_dev)) {
4189                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
4190                 return ECORE_INVAL;
4191         }
4192
4193         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4194                 DP_NOTICE(p_hwfn, true,
4195                           "Coalescing configuration not enabled\n");
4196                 return ECORE_INVAL;
4197         }
4198
4199         p_coal_timeset = p_eth_qzone;
4200         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4201         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4202         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4203         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4204
4205         return ECORE_SUCCESS;
4206 }
4207
4208 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4209                                             struct ecore_ptt *p_ptt,
4210                                             u16 coalesce, u16 qid, u16 sb_id)
4211 {
4212         struct ustorm_eth_queue_zone eth_qzone;
4213         u8 timeset, timer_res;
4214         u16 fw_qid = 0;
4215         u32 address;
4216         enum _ecore_status_t rc;
4217
4218         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4219         if (coalesce <= 0x7F) {
4220                 timer_res = 0;
4221         } else if (coalesce <= 0xFF) {
4222                 timer_res = 1;
4223         } else if (coalesce <= 0x1FF) {
4224                 timer_res = 2;
4225         } else {
4226                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4227                 return ECORE_INVAL;
4228         }
4229         timeset = (u8)(coalesce >> timer_res);
4230
4231         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4232         if (rc != ECORE_SUCCESS)
4233                 return rc;
4234
4235         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
4236         if (rc != ECORE_SUCCESS)
4237                 goto out;
4238
4239         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4240
4241         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4242                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4243         if (rc != ECORE_SUCCESS)
4244                 goto out;
4245
4246         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
4247 out:
4248         return rc;
4249 }
4250
4251 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4252                                             struct ecore_ptt *p_ptt,
4253                                             u16 coalesce, u16 qid, u16 sb_id)
4254 {
4255         struct xstorm_eth_queue_zone eth_qzone;
4256         u8 timeset, timer_res;
4257         u16 fw_qid = 0;
4258         u32 address;
4259         enum _ecore_status_t rc;
4260
4261         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4262         if (coalesce <= 0x7F) {
4263                 timer_res = 0;
4264         } else if (coalesce <= 0xFF) {
4265                 timer_res = 1;
4266         } else if (coalesce <= 0x1FF) {
4267                 timer_res = 2;
4268         } else {
4269                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4270                 return ECORE_INVAL;
4271         }
4272
4273         timeset = (u8)(coalesce >> timer_res);
4274
4275         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4276         if (rc != ECORE_SUCCESS)
4277                 return rc;
4278
4279         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
4280         if (rc != ECORE_SUCCESS)
4281                 goto out;
4282
4283         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4284
4285         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4286                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4287         if (rc != ECORE_SUCCESS)
4288                 goto out;
4289
4290         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4291 out:
4292         return rc;
4293 }
4294
4295 /* Calculate final WFQ values for all vports and configure it.
4296  * After this configuration each vport must have
4297  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4298  */
4299 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4300                                                struct ecore_ptt *p_ptt,
4301                                                u32 min_pf_rate)
4302 {
4303         struct init_qm_vport_params *vport_params;
4304         int i;
4305
4306         vport_params = p_hwfn->qm_info.qm_vport_params;
4307
4308         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4309                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4310
4311                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4312                     min_pf_rate;
4313                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4314                                      vport_params[i].first_tx_pq_id,
4315                                      vport_params[i].vport_wfq);
4316         }
4317 }
4318
4319 static void
4320 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4321 {
4322         int i;
4323
4324         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4325                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4326 }
4327
4328 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4329                                              struct ecore_ptt *p_ptt,
4330                                              u32 min_pf_rate)
4331 {
4332         struct init_qm_vport_params *vport_params;
4333         int i;
4334
4335         vport_params = p_hwfn->qm_info.qm_vport_params;
4336
4337         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4338                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4339                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4340                                      vport_params[i].first_tx_pq_id,
4341                                      vport_params[i].vport_wfq);
4342         }
4343 }
4344
4345 /* This function performs several validations for WFQ
4346  * configuration and required min rate for a given vport
4347  * 1. req_rate must be greater than one percent of min_pf_rate.
4348  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4349  *    rates to get less than one percent of min_pf_rate.
4350  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4351  */
4352 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4353                                                  u16 vport_id, u32 req_rate,
4354                                                  u32 min_pf_rate)
4355 {
4356         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4357         int non_requested_count = 0, req_count = 0, i, num_vports;
4358
4359         num_vports = p_hwfn->qm_info.num_vports;
4360
4361 /* Accounting for the vports which are configured for WFQ explicitly */
4362
4363         for (i = 0; i < num_vports; i++) {
4364                 u32 tmp_speed;
4365
4366                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4367                         req_count++;
4368                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4369                         total_req_min_rate += tmp_speed;
4370                 }
4371         }
4372
4373         /* Include current vport data as well */
4374         req_count++;
4375         total_req_min_rate += req_rate;
4376         non_requested_count = num_vports - req_count;
4377
4378         /* validate possible error cases */
4379         if (req_rate > min_pf_rate) {
4380                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4381                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4382                            vport_id, req_rate, min_pf_rate);
4383                 return ECORE_INVAL;
4384         }
4385
4386         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4387                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4388                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4389                            vport_id, req_rate, min_pf_rate);
4390                 return ECORE_INVAL;
4391         }
4392
4393         /* TBD - for number of vports greater than 100 */
4394         if (num_vports > ECORE_WFQ_UNIT) {
4395                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4396                            "Number of vports is greater than %d\n",
4397                            ECORE_WFQ_UNIT);
4398                 return ECORE_INVAL;
4399         }
4400
4401         if (total_req_min_rate > min_pf_rate) {
4402                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4403                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4404                            total_req_min_rate, min_pf_rate);
4405                 return ECORE_INVAL;
4406         }
4407
4408         /* Data left for non requested vports */
4409         total_left_rate = min_pf_rate - total_req_min_rate;
4410         left_rate_per_vp = total_left_rate / non_requested_count;
4411
4412         /* validate if non requested get < 1% of min bw */
4413         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4414                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4415                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4416                            left_rate_per_vp, min_pf_rate);
4417                 return ECORE_INVAL;
4418         }
4419
4420         /* now req_rate for given vport passes all scenarios.
4421          * assign final wfq rates to all vports.
4422          */
4423         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4424         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4425
4426         for (i = 0; i < num_vports; i++) {
4427                 if (p_hwfn->qm_info.wfq_data[i].configured)
4428                         continue;
4429
4430                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4431         }
4432
4433         return ECORE_SUCCESS;
4434 }
4435
4436 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4437                                        struct ecore_ptt *p_ptt,
4438                                        u16 vp_id, u32 rate)
4439 {
4440         struct ecore_mcp_link_state *p_link;
4441         int rc = ECORE_SUCCESS;
4442
4443         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4444
4445         if (!p_link->min_pf_rate) {
4446                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4447                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4448                 return rc;
4449         }
4450
4451         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4452
4453         if (rc == ECORE_SUCCESS)
4454                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4455                                                    p_link->min_pf_rate);
4456         else
4457                 DP_NOTICE(p_hwfn, false,
4458                           "Validation failed while configuring min rate\n");
4459
4460         return rc;
4461 }
4462
4463 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4464                                                    struct ecore_ptt *p_ptt,
4465                                                    u32 min_pf_rate)
4466 {
4467         bool use_wfq = false;
4468         int rc = ECORE_SUCCESS;
4469         u16 i;
4470
4471         /* Validate all pre configured vports for wfq */
4472         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4473                 u32 rate;
4474
4475                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4476                         continue;
4477
4478                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4479                 use_wfq = true;
4480
4481                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4482                 if (rc != ECORE_SUCCESS) {
4483                         DP_NOTICE(p_hwfn, false,
4484                                   "WFQ validation failed while configuring min rate\n");
4485                         break;
4486                 }
4487         }
4488
4489         if (rc == ECORE_SUCCESS && use_wfq)
4490                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4491         else
4492                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4493
4494         return rc;
4495 }
4496
4497 /* Main API for ecore clients to configure vport min rate.
4498  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4499  * rate - Speed in Mbps needs to be assigned to a given vport.
4500  */
4501 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4502 {
4503         int i, rc = ECORE_INVAL;
4504
4505         /* TBD - for multiple hardware functions - that is 100 gig */
4506         if (p_dev->num_hwfns > 1) {
4507                 DP_NOTICE(p_dev, false,
4508                           "WFQ configuration is not supported for this device\n");
4509                 return rc;
4510         }
4511
4512         for_each_hwfn(p_dev, i) {
4513                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4514                 struct ecore_ptt *p_ptt;
4515
4516                 p_ptt = ecore_ptt_acquire(p_hwfn);
4517                 if (!p_ptt)
4518                         return ECORE_TIMEOUT;
4519
4520                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4521
4522                 if (rc != ECORE_SUCCESS) {
4523                         ecore_ptt_release(p_hwfn, p_ptt);
4524                         return rc;
4525                 }
4526
4527                 ecore_ptt_release(p_hwfn, p_ptt);
4528         }
4529
4530         return rc;
4531 }
4532
4533 /* API to configure WFQ from mcp link change */
4534 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4535                                            u32 min_pf_rate)
4536 {
4537         int i;
4538
4539         /* TBD - for multiple hardware functions - that is 100 gig */
4540         if (p_dev->num_hwfns > 1) {
4541                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4542                            "WFQ configuration is not supported for this device\n");
4543                 return;
4544         }
4545
4546         for_each_hwfn(p_dev, i) {
4547                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4548
4549                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4550                                                         p_hwfn->p_dpc_ptt,
4551                                                         min_pf_rate);
4552         }
4553 }
4554
4555 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4556                                        struct ecore_ptt *p_ptt,
4557                                        struct ecore_mcp_link_state *p_link,
4558                                        u8 max_bw)
4559 {
4560         int rc = ECORE_SUCCESS;
4561
4562         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4563
4564         if (!p_link->line_speed && (max_bw != 100))
4565                 return rc;
4566
4567         p_link->speed = (p_link->line_speed * max_bw) / 100;
4568         p_hwfn->qm_info.pf_rl = p_link->speed;
4569
4570         /* Since the limiter also affects Tx-switched traffic, we don't want it
4571          * to limit such traffic in case there's no actual limit.
4572          * In that case, set limit to imaginary high boundary.
4573          */
4574         if (max_bw == 100)
4575                 p_hwfn->qm_info.pf_rl = 100000;
4576
4577         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4578                               p_hwfn->qm_info.pf_rl);
4579
4580         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4581                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4582                    p_link->speed);
4583
4584         return rc;
4585 }
4586
4587 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4588 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4589 {
4590         int i, rc = ECORE_INVAL;
4591
4592         if (max_bw < 1 || max_bw > 100) {
4593                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4594                 return rc;
4595         }
4596
4597         for_each_hwfn(p_dev, i) {
4598                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4599                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4600                 struct ecore_mcp_link_state *p_link;
4601                 struct ecore_ptt *p_ptt;
4602
4603                 p_link = &p_lead->mcp_info->link_output;
4604
4605                 p_ptt = ecore_ptt_acquire(p_hwfn);
4606                 if (!p_ptt)
4607                         return ECORE_TIMEOUT;
4608
4609                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4610                                                         p_link, max_bw);
4611
4612                 ecore_ptt_release(p_hwfn, p_ptt);
4613
4614                 if (rc != ECORE_SUCCESS)
4615                         break;
4616         }
4617
4618         return rc;
4619 }
4620
4621 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4622                                        struct ecore_ptt *p_ptt,
4623                                        struct ecore_mcp_link_state *p_link,
4624                                        u8 min_bw)
4625 {
4626         int rc = ECORE_SUCCESS;
4627
4628         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4629         p_hwfn->qm_info.pf_wfq = min_bw;
4630
4631         if (!p_link->line_speed)
4632                 return rc;
4633
4634         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4635
4636         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4637
4638         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4639                    "Configured MIN bandwidth to be %d Mb/sec\n",
4640                    p_link->min_pf_rate);
4641
4642         return rc;
4643 }
4644
4645 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4646 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4647 {
4648         int i, rc = ECORE_INVAL;
4649
4650         if (min_bw < 1 || min_bw > 100) {
4651                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4652                 return rc;
4653         }
4654
4655         for_each_hwfn(p_dev, i) {
4656                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4657                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4658                 struct ecore_mcp_link_state *p_link;
4659                 struct ecore_ptt *p_ptt;
4660
4661                 p_link = &p_lead->mcp_info->link_output;
4662
4663                 p_ptt = ecore_ptt_acquire(p_hwfn);
4664                 if (!p_ptt)
4665                         return ECORE_TIMEOUT;
4666
4667                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4668                                                         p_link, min_bw);
4669                 if (rc != ECORE_SUCCESS) {
4670                         ecore_ptt_release(p_hwfn, p_ptt);
4671                         return rc;
4672                 }
4673
4674                 if (p_link->min_pf_rate) {
4675                         u32 min_rate = p_link->min_pf_rate;
4676
4677                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4678                                                                      p_ptt,
4679                                                                      min_rate);
4680                 }
4681
4682                 ecore_ptt_release(p_hwfn, p_ptt);
4683         }
4684
4685         return rc;
4686 }
4687
4688 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4689 {
4690         struct ecore_mcp_link_state *p_link;
4691
4692         p_link = &p_hwfn->mcp_info->link_output;
4693
4694         if (p_link->min_pf_rate)
4695                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4696                                                  p_link->min_pf_rate);
4697
4698         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4699                     sizeof(*p_hwfn->qm_info.wfq_data) *
4700                     p_hwfn->qm_info.num_vports);
4701 }
4702
4703 int ecore_device_num_engines(struct ecore_dev *p_dev)
4704 {
4705         return ECORE_IS_BB(p_dev) ? 2 : 1;
4706 }
4707
4708 int ecore_device_num_ports(struct ecore_dev *p_dev)
4709 {
4710         /* in CMT always only one port */
4711         if (p_dev->num_hwfns > 1)
4712                 return 1;
4713
4714         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4715 }
4716
4717 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4718                           __le16 *fw_mid,
4719                           __le16 *fw_lsb,
4720                           u8 *mac)
4721 {
4722         ((u8 *)fw_msb)[0] = mac[1];
4723         ((u8 *)fw_msb)[1] = mac[0];
4724         ((u8 *)fw_mid)[0] = mac[3];
4725         ((u8 *)fw_mid)[1] = mac[2];
4726         ((u8 *)fw_lsb)[0] = mac[5];
4727         ((u8 *)fw_lsb)[1] = mac[4];
4728 }