drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /******************** Doorbell Recovery *******************/
  46 /* The doorbell recovery mechanism consists of a list of entries which represent
  47  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  48  * entity needs to register with the mechanism and provide the parameters
  49  * describing it's doorbell, including a location where last used doorbell data
  50  * can be found. The doorbell execute function will traverse the list and
  51  * doorbell all of the registered entries.
  52  */
  53 struct ecore_db_recovery_entry {
  54         osal_list_entry_t       list_entry;
  55         void OSAL_IOMEM         *db_addr;
  56         void                    *db_data;
  57         enum ecore_db_rec_width db_width;
  58         enum ecore_db_rec_space db_space;
  59         u8                      hwfn_idx;
  60 };
  61
  62 /* display a single doorbell recovery entry */
  63 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  64                                 struct ecore_db_recovery_entry *db_entry,
  65                                 const char *action)
  66 {
  67         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  68                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  69                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  70                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  71                    db_entry->hwfn_idx);
  72 }
  73
  74 /* doorbell address sanity (address within doorbell bar range) */
  75 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  76                          void *db_data)
  77 {
  78         /* make sure doorbell address  is within the doorbell bar */
  79         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  80                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  81                 OSAL_WARN(true,
  82                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  83                           db_addr, p_dev->doorbells,
  84                           (u8 *)p_dev->doorbells + p_dev->db_size);
  85                 return false;
  86         }
  87
  88         /* make sure doorbell data pointer is not null */
  89         if (!db_data) {
  90                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  91                 return false;
  92         }
  93
  94         return true;
  95 }
  96
  97 /* find hwfn according to the doorbell address */
  98 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  99                                           void OSAL_IOMEM *db_addr)
 100 {
 101         struct ecore_hwfn *p_hwfn;
 102
 103         /* In CMT doorbell bar is split down the middle between engine 0 and
 104          * enigne 1
 105          */
 106         if (ECORE_IS_CMT(p_dev))
 107                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 108                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 109         else
 110                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 111
 112         return p_hwfn;
 113 }
 114
 115 /* add a new entry to the doorbell recovery mechanism */
 116 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 117                                            void OSAL_IOMEM *db_addr,
 118                                            void *db_data,
 119                                            enum ecore_db_rec_width db_width,
 120                                            enum ecore_db_rec_space db_space)
 121 {
 122         struct ecore_db_recovery_entry *db_entry;
 123         struct ecore_hwfn *p_hwfn;
 124
 125         /* shortcircuit VFs, for now */
 126         if (IS_VF(p_dev)) {
 127                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 128                 return ECORE_SUCCESS;
 129         }
 130
 131         /* sanitize doorbell address */
 132         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 133                 return ECORE_INVAL;
 134
 135         /* obtain hwfn from doorbell address */
 136         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 137
 138         /* create entry */
 139         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 140         if (!db_entry) {
 141                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 142                 return ECORE_NOMEM;
 143         }
 144
 145         /* populate entry */
 146         db_entry->db_addr = db_addr;
 147         db_entry->db_data = db_data;
 148         db_entry->db_width = db_width;
 149         db_entry->db_space = db_space;
 150         db_entry->hwfn_idx = p_hwfn->my_id;
 151
 152         /* display */
 153         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 154
 155         /* protect the list */
 156         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 157         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 158                             &p_hwfn->db_recovery_info.list);
 159         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 160
 161         return ECORE_SUCCESS;
 162 }
 163
 164 /* remove an entry from the doorbell recovery mechanism */
 165 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 166                                            void OSAL_IOMEM *db_addr,
 167                                            void *db_data)
 168 {
 169         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 170         enum _ecore_status_t rc = ECORE_INVAL;
 171         struct ecore_hwfn *p_hwfn;
 172
 173         /* shortcircuit VFs, for now */
 174         if (IS_VF(p_dev)) {
 175                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 176                 return ECORE_SUCCESS;
 177         }
 178
 179         /* sanitize doorbell address */
 180         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 181                 return ECORE_INVAL;
 182
 183         /* obtain hwfn from doorbell address */
 184         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 185
 186         /* protect the list */
 187         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 188         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 189                                  &p_hwfn->db_recovery_info.list,
 190                                  list_entry,
 191                                  struct ecore_db_recovery_entry) {
 192                 /* search according to db_data addr since db_addr is not unique
 193                  * (roce)
 194                  */
 195                 if (db_entry->db_data == db_data) {
 196                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 197                                                    "Deleting");
 198                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 199                                                &p_hwfn->db_recovery_info.list);
 200                         rc = ECORE_SUCCESS;
 201                         break;
 202                 }
 203         }
 204
 205         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 206
 207         if (rc == ECORE_INVAL)
 208                 /*OSAL_WARN(true,*/
 209                 DP_NOTICE(p_hwfn, false,
 210                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 211                           db_data, db_addr);
 212         else
 213                 OSAL_FREE(p_dev, db_entry);
 214
 215         return rc;
 216 }
 217
 218 /* initialize the doorbell recovery mechanism */
 219 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 220 {
 221         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 222
 223         /* make sure db_size was set in p_dev */
 224         if (!p_hwfn->p_dev->db_size) {
 225                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 226                 return ECORE_INVAL;
 227         }
 228
 229         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 230 #ifdef CONFIG_ECORE_LOCK_ALLOC
 231         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 232 #endif
 233         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 234         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 235
 236         return ECORE_SUCCESS;
 237 }
 238
 239 /* destroy the doorbell recovery mechanism */
 240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 241 {
 242         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 243
 244         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 245         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 247                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 248                         db_entry = OSAL_LIST_FIRST_ENTRY(
 249                                                 &p_hwfn->db_recovery_info.list,
 250                                                 struct ecore_db_recovery_entry,
 251                                                 list_entry);
 252                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 253                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 254                                                &p_hwfn->db_recovery_info.list);
 255                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 256                 }
 257         }
 258 #ifdef CONFIG_ECORE_LOCK_ALLOC
 259         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 260 #endif
 261         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 262 }
 263
 264 /* print the content of the doorbell recovery mechanism */
 265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 266 {
 267         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 268
 269         DP_NOTICE(p_hwfn, false,
 270                   "Dispalying doorbell recovery database. Counter was %d\n",
 271                   p_hwfn->db_recovery_info.db_recovery_counter);
 272
 273         /* protect the list */
 274         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 275         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 276                                  &p_hwfn->db_recovery_info.list,
 277                                  list_entry,
 278                                  struct ecore_db_recovery_entry) {
 279                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 280         }
 281
 282         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 283 }
 284
 285 /* ring the doorbell of a single doorbell recovery entry */
 286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 287                             struct ecore_db_recovery_entry *db_entry,
 288                             enum ecore_db_rec_exec db_exec)
 289 {
 290         /* Print according to width */
 291         if (db_entry->db_width == DB_REC_WIDTH_32B)
 292                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 293                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 294                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 295         else
 296                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 297                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 298                            db_entry->db_addr,
 299                            *(unsigned long *)(db_entry->db_data));
 300
 301         /* Sanity */
 302         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 303                                  db_entry->db_data))
 304                 return;
 305
 306         /* Flush the write combined buffer. Since there are multiple doorbelling
 307          * entities using the same address, if we don't flush, a transaction
 308          * could be lost.
 309          */
 310         OSAL_WMB(p_hwfn->p_dev);
 311
 312         /* Ring the doorbell */
 313         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 314                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 315                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 316                                       *(u32 *)(db_entry->db_data));
 317                 else
 318                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 319                                         *(u64 *)(db_entry->db_data));
 320         }
 321
 322         /* Flush the write combined buffer. Next doorbell may come from a
 323          * different entity to the same address...
 324          */
 325         OSAL_WMB(p_hwfn->p_dev);
 326 }
 327
 328 /* traverse the doorbell recovery entry list and ring all the doorbells */
 329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 330                                enum ecore_db_rec_exec db_exec)
 331 {
 332         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 333
 334         if (db_exec != DB_REC_ONCE) {
 335                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 336                           p_hwfn->db_recovery_info.db_recovery_counter);
 337
 338                 /* track amount of times recovery was executed */
 339                 p_hwfn->db_recovery_info.db_recovery_counter++;
 340         }
 341
 342         /* protect the list */
 343         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 344         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 345                                  &p_hwfn->db_recovery_info.list,
 346                                  list_entry,
 347                                  struct ecore_db_recovery_entry) {
 348                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 349                 if (db_exec == DB_REC_ONCE)
 350                         break;
 351         }
 352
 353         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 354 }
 355 /******************** Doorbell Recovery end ****************/
 356
 357 /* Configurable */
 358 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 359                                          * load the driver. The number was
 360                                          * arbitrarily set.
 361                                          */
 362
 363 /* Derived */
 364 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 365
 366 enum BAR_ID {
 367         BAR_ID_0,               /* used for GRC */
 368         BAR_ID_1                /* Used for doorbells */
 369 };
 370
 371 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 372                              struct ecore_ptt *p_ptt,
 373                              enum BAR_ID bar_id)
 374 {
 375         u32 bar_reg = (bar_id == BAR_ID_0 ?
 376                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 377         u32 val;
 378
 379         if (IS_VF(p_hwfn->p_dev)) {
 380                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
 381                  * read from actual register, but we're currently not using
 382                  * it for actual doorbelling.
 383                  */
 384                 return 1 << 17;
 385         }
 386
 387         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 388         if (val)
 389                 return 1 << (val + 15);
 390
 391         /* The above registers were updated in the past only in CMT mode. Since
 392          * they were found to be useful MFW started updating them from 8.7.7.0.
 393          * In older MFW versions they are set to 0 which means disabled.
 394          */
 395         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 396                 DP_INFO(p_hwfn,
 397                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 398                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 399         } else {
 400                 DP_INFO(p_hwfn,
 401                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 402                 val = 512 * 1024;
 403         }
 404
 405         return val;
 406 }
 407
 408 void ecore_init_dp(struct ecore_dev *p_dev,
 409                    u32 dp_module, u8 dp_level, void *dp_ctx)
 410 {
 411         u32 i;
 412
 413         p_dev->dp_level = dp_level;
 414         p_dev->dp_module = dp_module;
 415         p_dev->dp_ctx = dp_ctx;
 416         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 417                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 418
 419                 p_hwfn->dp_level = dp_level;
 420                 p_hwfn->dp_module = dp_module;
 421                 p_hwfn->dp_ctx = dp_ctx;
 422         }
 423 }
 424
 425 void ecore_init_struct(struct ecore_dev *p_dev)
 426 {
 427         u8 i;
 428
 429         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 430                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 431
 432                 p_hwfn->p_dev = p_dev;
 433                 p_hwfn->my_id = i;
 434                 p_hwfn->b_active = false;
 435
 436 #ifdef CONFIG_ECORE_LOCK_ALLOC
 437                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 438 #endif
 439                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 440         }
 441
 442         /* hwfn 0 is always active */
 443         p_dev->hwfns[0].b_active = true;
 444
 445         /* set the default cache alignment to 128 (may be overridden later) */
 446         p_dev->cache_shift = 7;
 447 }
 448
 449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 450 {
 451         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 452
 453         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 454         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 455         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 456         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 457 }
 458
 459 void ecore_resc_free(struct ecore_dev *p_dev)
 460 {
 461         int i;
 462
 463         if (IS_VF(p_dev)) {
 464                 for_each_hwfn(p_dev, i)
 465                         ecore_l2_free(&p_dev->hwfns[i]);
 466                 return;
 467         }
 468
 469         OSAL_FREE(p_dev, p_dev->fw_data);
 470
 471         OSAL_FREE(p_dev, p_dev->reset_stats);
 472
 473         for_each_hwfn(p_dev, i) {
 474                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 475
 476                 ecore_cxt_mngr_free(p_hwfn);
 477                 ecore_qm_info_free(p_hwfn);
 478                 ecore_spq_free(p_hwfn);
 479                 ecore_eq_free(p_hwfn);
 480                 ecore_consq_free(p_hwfn);
 481                 ecore_int_free(p_hwfn);
 482                 ecore_iov_free(p_hwfn);
 483                 ecore_l2_free(p_hwfn);
 484                 ecore_dmae_info_free(p_hwfn);
 485                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 486                 /* @@@TBD Flush work-queue ? */
 487
 488                 /* destroy doorbell recovery mechanism */
 489                 ecore_db_recovery_teardown(p_hwfn);
 490         }
 491 }
 492
 493 /******************** QM initialization *******************/
 494
 495 /* bitmaps for indicating active traffic classes.
 496  * Special case for Arrowhead 4 port
 497  */
 498 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 499 #define ACTIVE_TCS_BMAP 0x9f
 500 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 501 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 502
 503 /* determines the physical queue flags for a given PF. */
 504 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 505 {
 506         u32 flags;
 507
 508         /* common flags */
 509         flags = PQ_FLAGS_LB;
 510
 511         /* feature flags */
 512         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 513                 flags |= PQ_FLAGS_VFS;
 514
 515         /* protocol flags */
 516         switch (p_hwfn->hw_info.personality) {
 517         case ECORE_PCI_ETH:
 518                 flags |= PQ_FLAGS_MCOS;
 519                 break;
 520         case ECORE_PCI_FCOE:
 521                 flags |= PQ_FLAGS_OFLD;
 522                 break;
 523         case ECORE_PCI_ISCSI:
 524                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 525                 break;
 526         case ECORE_PCI_ETH_ROCE:
 527                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 528                 break;
 529         case ECORE_PCI_ETH_IWARP:
 530                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 531                          PQ_FLAGS_OFLD;
 532                 break;
 533         default:
 534                 DP_ERR(p_hwfn, "unknown personality %d\n",
 535                        p_hwfn->hw_info.personality);
 536                 return 0;
 537         }
 538         return flags;
 539 }
 540
 541 /* Getters for resource amounts necessary for qm initialization */
 542 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 543 {
 544         return p_hwfn->hw_info.num_hw_tc;
 545 }
 546
 547 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 548 {
 549         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 550                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 551 }
 552
 553 #define NUM_DEFAULT_RLS 1
 554
 555 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 556 {
 557         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 558
 559         /* @DPDK */
 560         /* num RLs can't exceed resource amount of rls or vports or the
 561          * dcqcn qps
 562          */
 563         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 564                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 565
 566         /* make sure after we reserve the default and VF rls we'll have
 567          * something left
 568          */
 569         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 570                 DP_NOTICE(p_hwfn, false,
 571                           "no rate limiters left for PF rate limiting"
 572                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 573                 return 0;
 574         }
 575
 576         /* subtract rls necessary for VFs and one default one for the PF */
 577         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 578
 579         return num_pf_rls;
 580 }
 581
 582 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 583 {
 584         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 585
 586         /* all pqs share the same vport (hence the 1 below), except for vfs
 587          * and pf_rl pqs
 588          */
 589         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 590                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 591                (!!(PQ_FLAGS_VFS & pq_flags)) *
 592                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 593 }
 594
 595 /* calc amount of PQs according to the requested flags */
 596 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 597 {
 598         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 599
 600         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 601                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 602                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 603                 ecore_init_qm_get_num_tcs(p_hwfn) +
 604                (!!(PQ_FLAGS_LB & pq_flags)) +
 605                (!!(PQ_FLAGS_OOO & pq_flags)) +
 606                (!!(PQ_FLAGS_ACK & pq_flags)) +
 607                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 608                (!!(PQ_FLAGS_VFS & pq_flags)) *
 609                 ecore_init_qm_get_num_vfs(p_hwfn);
 610 }
 611
 612 /* initialize the top level QM params */
 613 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 614 {
 615         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 616         bool four_port;
 617
 618         /* pq and vport bases for this PF */
 619         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 620         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 621
 622         /* rate limiting and weighted fair queueing are always enabled */
 623         qm_info->vport_rl_en = 1;
 624         qm_info->vport_wfq_en = 1;
 625
 626         /* TC config is different for AH 4 port */
 627         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 628
 629         /* in AH 4 port we have fewer TCs per port */
 630         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 631                                                      NUM_OF_PHYS_TCS;
 632
 633         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 634          * 4 otherwise
 635          */
 636         if (!qm_info->ooo_tc)
 637                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 638                                               DCBX_TCP_OOO_TC;
 639 }
 640
 641 /* initialize qm vport params */
 642 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 643 {
 644         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 645         u8 i;
 646
 647         /* all vports participate in weighted fair queueing */
 648         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 649                 qm_info->qm_vport_params[i].vport_wfq = 1;
 650 }
 651
 652 /* initialize qm port params */
 653 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 654 {
 655         /* Initialize qm port parameters */
 656         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 657
 658         /* indicate how ooo and high pri traffic is dealt with */
 659         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 660                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 661
 662         for (i = 0; i < num_ports; i++) {
 663                 struct init_qm_port_params *p_qm_port =
 664                         &p_hwfn->qm_info.qm_port_params[i];
 665
 666                 p_qm_port->active = 1;
 667                 p_qm_port->active_phys_tcs = active_phys_tcs;
 668                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 669                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 670         }
 671 }
 672
 673 /* Reset the params which must be reset for qm init. QM init may be called as
 674  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 675  * params may be affected by the init but would simply recalculate to the same
 676  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 677  * affected as these amounts stay the same.
 678  */
 679 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 680 {
 681         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 682
 683         qm_info->num_pqs = 0;
 684         qm_info->num_vports = 0;
 685         qm_info->num_pf_rls = 0;
 686         qm_info->num_vf_pqs = 0;
 687         qm_info->first_vf_pq = 0;
 688         qm_info->first_mcos_pq = 0;
 689         qm_info->first_rl_pq = 0;
 690 }
 691
 692 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 693 {
 694         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 695
 696         qm_info->num_vports++;
 697
 698         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 699                 DP_ERR(p_hwfn,
 700                        "vport overflow! qm_info->num_vports %d,"
 701                        " qm_init_get_num_vports() %d\n",
 702                        qm_info->num_vports,
 703                        ecore_init_qm_get_num_vports(p_hwfn));
 704 }
 705
 706 /* initialize a single pq and manage qm_info resources accounting.
 707  * The pq_init_flags param determines whether the PQ is rate limited
 708  * (for VF or PF)
 709  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 710  * shared)
 711  */
 712
 713 /* flags for pq init */
 714 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 715 #define PQ_INIT_PF_RL           (1 << 1)
 716 #define PQ_INIT_VF_RL           (1 << 2)
 717
 718 /* defines for pq init */
 719 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 720 #define PQ_INIT_DEFAULT_TC              0
 721 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 722
 723 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 724                              struct ecore_qm_info *qm_info,
 725                              u8 tc, u32 pq_init_flags)
 726 {
 727         u16 pq_idx = qm_info->num_pqs, max_pq =
 728                                         ecore_init_qm_get_num_pqs(p_hwfn);
 729
 730         if (pq_idx > max_pq)
 731                 DP_ERR(p_hwfn,
 732                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 733
 734         /* init pq params */
 735         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 736                                                  qm_info->num_vports;
 737         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 738         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 739         qm_info->qm_pq_params[pq_idx].rl_valid =
 740                 (pq_init_flags & PQ_INIT_PF_RL ||
 741                  pq_init_flags & PQ_INIT_VF_RL);
 742
 743         /* qm params accounting */
 744         qm_info->num_pqs++;
 745         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 746                 qm_info->num_vports++;
 747
 748         if (pq_init_flags & PQ_INIT_PF_RL)
 749                 qm_info->num_pf_rls++;
 750
 751         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 752                 DP_ERR(p_hwfn,
 753                        "vport overflow! qm_info->num_vports %d,"
 754                        " qm_init_get_num_vports() %d\n",
 755                        qm_info->num_vports,
 756                        ecore_init_qm_get_num_vports(p_hwfn));
 757
 758         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 759                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 760                        " qm_init_get_num_pf_rls() %d\n",
 761                        qm_info->num_pf_rls,
 762                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 763 }
 764
 765 /* get pq index according to PQ_FLAGS */
 766 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 767                                              u32 pq_flags)
 768 {
 769         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 770
 771         /* Can't have multiple flags set here */
 772         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 773                                 sizeof(pq_flags)) > 1)
 774                 goto err;
 775
 776         switch (pq_flags) {
 777         case PQ_FLAGS_RLS:
 778                 return &qm_info->first_rl_pq;
 779         case PQ_FLAGS_MCOS:
 780                 return &qm_info->first_mcos_pq;
 781         case PQ_FLAGS_LB:
 782                 return &qm_info->pure_lb_pq;
 783         case PQ_FLAGS_OOO:
 784                 return &qm_info->ooo_pq;
 785         case PQ_FLAGS_ACK:
 786                 return &qm_info->pure_ack_pq;
 787         case PQ_FLAGS_OFLD:
 788                 return &qm_info->offload_pq;
 789         case PQ_FLAGS_VFS:
 790                 return &qm_info->first_vf_pq;
 791         default:
 792                 goto err;
 793         }
 794
 795 err:
 796         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 797         return OSAL_NULL;
 798 }
 799
 800 /* save pq index in qm info */
 801 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 802                                   u32 pq_flags, u16 pq_val)
 803 {
 804         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 805
 806         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 807 }
 808
 809 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 810 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 811 {
 812         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 813
 814         return *base_pq_idx + CM_TX_PQ_BASE;
 815 }
 816
 817 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 818 {
 819         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 820
 821         if (tc > max_tc)
 822                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 823
 824         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 825 }
 826
 827 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 828 {
 829         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 830
 831         if (vf > max_vf)
 832                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 833
 834         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 835 }
 836
 837 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 838 {
 839         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 840
 841         if (rl > max_rl)
 842                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 843
 844         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 845 }
 846
 847 /* Functions for creating specific types of pqs */
 848 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 849 {
 850         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 851
 852         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 853                 return;
 854
 855         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 856         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 857 }
 858
 859 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 860 {
 861         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 862
 863         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 864                 return;
 865
 866         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 867         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 868 }
 869
 870 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 871 {
 872         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 873
 874         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 875                 return;
 876
 877         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 878         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 879 }
 880
 881 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 882 {
 883         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 884
 885         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 886                 return;
 887
 888         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 889         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 890 }
 891
 892 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 893 {
 894         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 895         u8 tc_idx;
 896
 897         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 898                 return;
 899
 900         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 901         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 902                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 903 }
 904
 905 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 906 {
 907         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 908         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 909
 910         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 911                 return;
 912
 913         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 914
 915         qm_info->num_vf_pqs = num_vfs;
 916         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 917                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 918                                  PQ_INIT_VF_RL);
 919 }
 920
 921 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 922 {
 923         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 924         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 925
 926         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 927                 return;
 928
 929         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 930         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 931                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 932                                  PQ_INIT_PF_RL);
 933 }
 934
 935 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 936 {
 937         /* rate limited pqs, must come first (FW assumption) */
 938         ecore_init_qm_rl_pqs(p_hwfn);
 939
 940         /* pqs for multi cos */
 941         ecore_init_qm_mcos_pqs(p_hwfn);
 942
 943         /* pure loopback pq */
 944         ecore_init_qm_lb_pq(p_hwfn);
 945
 946         /* out of order pq */
 947         ecore_init_qm_ooo_pq(p_hwfn);
 948
 949         /* pure ack pq */
 950         ecore_init_qm_pure_ack_pq(p_hwfn);
 951
 952         /* pq for offloaded protocol */
 953         ecore_init_qm_offload_pq(p_hwfn);
 954
 955         /* done sharing vports */
 956         ecore_init_qm_advance_vport(p_hwfn);
 957
 958         /* pqs for vfs */
 959         ecore_init_qm_vf_pqs(p_hwfn);
 960 }
 961
 962 /* compare values of getters against resources amounts */
 963 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 964 {
 965         if (ecore_init_qm_get_num_vports(p_hwfn) >
 966             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 967                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 968                 return ECORE_INVAL;
 969         }
 970
 971         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 972                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 973                 return ECORE_INVAL;
 974         }
 975
 976         return ECORE_SUCCESS;
 977 }
 978
 979 /*
 980  * Function for verbose printing of the qm initialization results
 981  */
 982 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 983 {
 984         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 985         struct init_qm_vport_params *vport;
 986         struct init_qm_port_params *port;
 987         struct init_qm_pq_params *pq;
 988         int i, tc;
 989
 990         /* top level params */
 991         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 992                    "qm init top level params: start_pq %d, start_vport %d,"
 993                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 994                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 995                    qm_info->offload_pq, qm_info->pure_ack_pq);
 996         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 997                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 998                    " num_vports %d, max_phys_tcs_per_port %d\n",
 999                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1000                    qm_info->num_vf_pqs, qm_info->num_vports,
1001                    qm_info->max_phys_tcs_per_port);
1002         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1004                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1005                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1006                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1007                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1008
1009         /* port table */
1010         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1011                 port = &qm_info->qm_port_params[i];
1012                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1013                            "port idx %d, active %d, active_phys_tcs %d,"
1014                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1015                            " reserved %d\n",
1016                            i, port->active, port->active_phys_tcs,
1017                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1018                            port->reserved);
1019         }
1020
1021         /* vport table */
1022         for (i = 0; i < qm_info->num_vports; i++) {
1023                 vport = &qm_info->qm_vport_params[i];
1024                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1025                            "vport idx %d, vport_rl %d, wfq %d,"
1026                            " first_tx_pq_id [ ",
1027                            qm_info->start_vport + i, vport->vport_rl,
1028                            vport->vport_wfq);
1029                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1030                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1031                                    vport->first_tx_pq_id[tc]);
1032                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1033         }
1034
1035         /* pq table */
1036         for (i = 0; i < qm_info->num_pqs; i++) {
1037                 pq = &qm_info->qm_pq_params[i];
1038                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1039                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1040                            " rl_valid %d\n",
1041                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1042                            pq->wrr_group, pq->rl_valid);
1043         }
1044 }
1045
1046 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1047 {
1048         /* reset params required for init run */
1049         ecore_init_qm_reset_params(p_hwfn);
1050
1051         /* init QM top level params */
1052         ecore_init_qm_params(p_hwfn);
1053
1054         /* init QM port params */
1055         ecore_init_qm_port_params(p_hwfn);
1056
1057         /* init QM vport params */
1058         ecore_init_qm_vport_params(p_hwfn);
1059
1060         /* init QM physical queue params */
1061         ecore_init_qm_pq_params(p_hwfn);
1062
1063         /* display all that init */
1064         ecore_dp_init_qm_params(p_hwfn);
1065 }
1066
1067 /* This function reconfigures the QM pf on the fly.
1068  * For this purpose we:
1069  * 1. reconfigure the QM database
1070  * 2. set new values to runtime array
1071  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1072  * 4. activate init tool in QM_PF stage
1073  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1074  */
1075 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1076                                      struct ecore_ptt *p_ptt)
1077 {
1078         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1079         bool b_rc;
1080         enum _ecore_status_t rc;
1081
1082         /* initialize ecore's qm data structure */
1083         ecore_init_qm_info(p_hwfn);
1084
1085         /* stop PF's qm queues */
1086         OSAL_SPIN_LOCK(&qm_lock);
1087         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1088                                       qm_info->start_pq, qm_info->num_pqs);
1089         OSAL_SPIN_UNLOCK(&qm_lock);
1090         if (!b_rc)
1091                 return ECORE_INVAL;
1092
1093         /* clear the QM_PF runtime phase leftovers from previous init */
1094         ecore_init_clear_rt_data(p_hwfn);
1095
1096         /* prepare QM portion of runtime array */
1097         ecore_qm_init_pf(p_hwfn, p_ptt);
1098
1099         /* activate init tool on runtime array */
1100         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1101                             p_hwfn->hw_info.hw_mode);
1102         if (rc != ECORE_SUCCESS)
1103                 return rc;
1104
1105         /* start PF's qm queues */
1106         OSAL_SPIN_LOCK(&qm_lock);
1107         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1108                                       qm_info->start_pq, qm_info->num_pqs);
1109         OSAL_SPIN_UNLOCK(&qm_lock);
1110         if (!b_rc)
1111                 return ECORE_INVAL;
1112
1113         return ECORE_SUCCESS;
1114 }
1115
1116 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1117 {
1118         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1119         enum _ecore_status_t rc;
1120
1121         rc = ecore_init_qm_sanity(p_hwfn);
1122         if (rc != ECORE_SUCCESS)
1123                 goto alloc_err;
1124
1125         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1126                                             sizeof(struct init_qm_pq_params) *
1127                                             ecore_init_qm_get_num_pqs(p_hwfn));
1128         if (!qm_info->qm_pq_params)
1129                 goto alloc_err;
1130
1131         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1132                                        sizeof(struct init_qm_vport_params) *
1133                                        ecore_init_qm_get_num_vports(p_hwfn));
1134         if (!qm_info->qm_vport_params)
1135                 goto alloc_err;
1136
1137         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1138                                       sizeof(struct init_qm_port_params) *
1139                                       p_hwfn->p_dev->num_ports_in_engine);
1140         if (!qm_info->qm_port_params)
1141                 goto alloc_err;
1142
1143         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1144                                         sizeof(struct ecore_wfq_data) *
1145                                         ecore_init_qm_get_num_vports(p_hwfn));
1146         if (!qm_info->wfq_data)
1147                 goto alloc_err;
1148
1149         return ECORE_SUCCESS;
1150
1151 alloc_err:
1152         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1153         ecore_qm_info_free(p_hwfn);
1154         return ECORE_NOMEM;
1155 }
1156 /******************** End QM initialization ***************/
1157
1158 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1159 {
1160         enum _ecore_status_t rc = ECORE_SUCCESS;
1161         int i;
1162
1163         if (IS_VF(p_dev)) {
1164                 for_each_hwfn(p_dev, i) {
1165                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1166                         if (rc != ECORE_SUCCESS)
1167                                 return rc;
1168                 }
1169                 return rc;
1170         }
1171
1172         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1173                                      sizeof(*p_dev->fw_data));
1174         if (!p_dev->fw_data)
1175                 return ECORE_NOMEM;
1176
1177         for_each_hwfn(p_dev, i) {
1178                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1179                 u32 n_eqes, num_cons;
1180
1181                 /* initialize the doorbell recovery mechanism */
1182                 rc = ecore_db_recovery_setup(p_hwfn);
1183                 if (rc)
1184                         goto alloc_err;
1185
1186                 /* First allocate the context manager structure */
1187                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1188                 if (rc)
1189                         goto alloc_err;
1190
1191                 /* Set the HW cid/tid numbers (in the context manager)
1192                  * Must be done prior to any further computations.
1193                  */
1194                 rc = ecore_cxt_set_pf_params(p_hwfn);
1195                 if (rc)
1196                         goto alloc_err;
1197
1198                 rc = ecore_alloc_qm_data(p_hwfn);
1199                 if (rc)
1200                         goto alloc_err;
1201
1202                 /* init qm info */
1203                 ecore_init_qm_info(p_hwfn);
1204
1205                 /* Compute the ILT client partition */
1206                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1207                 if (rc)
1208                         goto alloc_err;
1209
1210                 /* CID map / ILT shadow table / T2
1211                  * The talbes sizes are determined by the computations above
1212                  */
1213                 rc = ecore_cxt_tables_alloc(p_hwfn);
1214                 if (rc)
1215                         goto alloc_err;
1216
1217                 /* SPQ, must follow ILT because initializes SPQ context */
1218                 rc = ecore_spq_alloc(p_hwfn);
1219                 if (rc)
1220                         goto alloc_err;
1221
1222                 /* SP status block allocation */
1223                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1224                                                            RESERVED_PTT_DPC);
1225
1226                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1227                 if (rc)
1228                         goto alloc_err;
1229
1230                 rc = ecore_iov_alloc(p_hwfn);
1231                 if (rc)
1232                         goto alloc_err;
1233
1234                 /* EQ */
1235                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1236                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1237                         /* Calculate the EQ size
1238                          * ---------------------
1239                          * Each ICID may generate up to one event at a time i.e.
1240                          * the event must be handled/cleared before a new one
1241                          * can be generated. We calculate the sum of events per
1242                          * protocol and create an EQ deep enough to handle the
1243                          * worst case:
1244                          * - Core - according to SPQ.
1245                          * - RoCE - per QP there are a couple of ICIDs, one
1246                          *        responder and one requester, each can
1247                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1248                          *        Each CQ can generate an EQE. There are 2 CQs
1249                          *        per QP => n_eqes_cq = 2 * n_qp.
1250                          *        Hence the RoCE total is 4 * n_qp or
1251                          *        2 * num_cons.
1252                          * - ENet - There can be up to two events per VF. One
1253                          *        for VF-PF channel and another for VF FLR
1254                          *        initial cleanup. The number of VFs is
1255                          *        bounded by MAX_NUM_VFS_BB, and is much
1256                          *        smaller than RoCE's so we avoid exact
1257                          *        calculation.
1258                          */
1259                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1260                                 num_cons =
1261                                     ecore_cxt_get_proto_cid_count(
1262                                                 p_hwfn,
1263                                                 PROTOCOLID_ROCE,
1264                                                 OSAL_NULL);
1265                                 num_cons *= 2;
1266                         } else {
1267                                 num_cons = ecore_cxt_get_proto_cid_count(
1268                                                 p_hwfn,
1269                                                 PROTOCOLID_IWARP,
1270                                                 OSAL_NULL);
1271                         }
1272                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1273                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1274                         num_cons =
1275                             ecore_cxt_get_proto_cid_count(p_hwfn,
1276                                                           PROTOCOLID_ISCSI,
1277                                                           OSAL_NULL);
1278                         n_eqes += 2 * num_cons;
1279                 }
1280
1281                 if (n_eqes > 0xFFFF) {
1282                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1283                                        "The maximum of a u16 chain is 0x%x\n",
1284                                n_eqes, 0xFFFF);
1285                         goto alloc_no_mem;
1286                 }
1287
1288                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1289                 if (rc)
1290                         goto alloc_err;
1291
1292                 rc = ecore_consq_alloc(p_hwfn);
1293                 if (rc)
1294                         goto alloc_err;
1295
1296                 rc = ecore_l2_alloc(p_hwfn);
1297                 if (rc != ECORE_SUCCESS)
1298                         goto alloc_err;
1299
1300                 /* DMA info initialization */
1301                 rc = ecore_dmae_info_alloc(p_hwfn);
1302                 if (rc) {
1303                         DP_NOTICE(p_hwfn, true,
1304                                   "Failed to allocate memory for dmae_info"
1305                                   " structure\n");
1306                         goto alloc_err;
1307                 }
1308
1309                 /* DCBX initialization */
1310                 rc = ecore_dcbx_info_alloc(p_hwfn);
1311                 if (rc) {
1312                         DP_NOTICE(p_hwfn, true,
1313                                   "Failed to allocate memory for dcbx structure\n");
1314                         goto alloc_err;
1315                 }
1316         }
1317
1318         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1319                                          sizeof(*p_dev->reset_stats));
1320         if (!p_dev->reset_stats) {
1321                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1322                 goto alloc_no_mem;
1323         }
1324
1325         return ECORE_SUCCESS;
1326
1327 alloc_no_mem:
1328         rc = ECORE_NOMEM;
1329 alloc_err:
1330         ecore_resc_free(p_dev);
1331         return rc;
1332 }
1333
1334 void ecore_resc_setup(struct ecore_dev *p_dev)
1335 {
1336         int i;
1337
1338         if (IS_VF(p_dev)) {
1339                 for_each_hwfn(p_dev, i)
1340                         ecore_l2_setup(&p_dev->hwfns[i]);
1341                 return;
1342         }
1343
1344         for_each_hwfn(p_dev, i) {
1345                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1346
1347                 ecore_cxt_mngr_setup(p_hwfn);
1348                 ecore_spq_setup(p_hwfn);
1349                 ecore_eq_setup(p_hwfn);
1350                 ecore_consq_setup(p_hwfn);
1351
1352                 /* Read shadow of current MFW mailbox */
1353                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1354                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1355                             p_hwfn->mcp_info->mfw_mb_cur,
1356                             p_hwfn->mcp_info->mfw_mb_length);
1357
1358                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1359
1360                 ecore_l2_setup(p_hwfn);
1361                 ecore_iov_setup(p_hwfn);
1362         }
1363 }
1364
1365 #define FINAL_CLEANUP_POLL_CNT  (100)
1366 #define FINAL_CLEANUP_POLL_TIME (10)
1367 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1368                                          struct ecore_ptt *p_ptt,
1369                                          u16 id, bool is_vf)
1370 {
1371         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1372         enum _ecore_status_t rc = ECORE_TIMEOUT;
1373
1374 #ifndef ASIC_ONLY
1375         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1376             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1377                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1378                 return ECORE_SUCCESS;
1379         }
1380 #endif
1381
1382         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1383             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1384
1385         if (is_vf)
1386                 id += 0x10;
1387
1388         command |= X_FINAL_CLEANUP_AGG_INT <<
1389             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1390         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1391         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1392         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1393
1394 /* Make sure notification is not set before initiating final cleanup */
1395
1396         if (REG_RD(p_hwfn, addr)) {
1397                 DP_NOTICE(p_hwfn, false,
1398                           "Unexpected; Found final cleanup notification");
1399                 DP_NOTICE(p_hwfn, false,
1400                           " before initiating final cleanup\n");
1401                 REG_WR(p_hwfn, addr, 0);
1402         }
1403
1404         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1405                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1406                    id, command);
1407
1408         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1409
1410         /* Poll until completion */
1411         while (!REG_RD(p_hwfn, addr) && count--)
1412                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1413
1414         if (REG_RD(p_hwfn, addr))
1415                 rc = ECORE_SUCCESS;
1416         else
1417                 DP_NOTICE(p_hwfn, true,
1418                           "Failed to receive FW final cleanup notification\n");
1419
1420         /* Cleanup afterwards */
1421         REG_WR(p_hwfn, addr, 0);
1422
1423         return rc;
1424 }
1425
1426 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1427 {
1428         int hw_mode = 0;
1429
1430         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1431                 hw_mode |= 1 << MODE_BB;
1432         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1433                 hw_mode |= 1 << MODE_K2;
1434         } else {
1435                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1436                           p_hwfn->p_dev->type);
1437                 return ECORE_INVAL;
1438         }
1439
1440         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1441         switch (p_hwfn->p_dev->num_ports_in_engine) {
1442         case 1:
1443                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1444                 break;
1445         case 2:
1446                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1447                 break;
1448         case 4:
1449                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1450                 break;
1451         default:
1452                 DP_NOTICE(p_hwfn, true,
1453                           "num_ports_in_engine = %d not supported\n",
1454                           p_hwfn->p_dev->num_ports_in_engine);
1455                 return ECORE_INVAL;
1456         }
1457
1458         switch (p_hwfn->p_dev->mf_mode) {
1459         case ECORE_MF_DEFAULT:
1460         case ECORE_MF_NPAR:
1461                 hw_mode |= 1 << MODE_MF_SI;
1462                 break;
1463         case ECORE_MF_OVLAN:
1464                 hw_mode |= 1 << MODE_MF_SD;
1465                 break;
1466         default:
1467                 DP_NOTICE(p_hwfn, true,
1468                           "Unsupported MF mode, init as DEFAULT\n");
1469                 hw_mode |= 1 << MODE_MF_SI;
1470         }
1471
1472 #ifndef ASIC_ONLY
1473         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1474                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1475                         hw_mode |= 1 << MODE_FPGA;
1476                 } else {
1477                         if (p_hwfn->p_dev->b_is_emul_full)
1478                                 hw_mode |= 1 << MODE_EMUL_FULL;
1479                         else
1480                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1481                 }
1482         } else
1483 #endif
1484                 hw_mode |= 1 << MODE_ASIC;
1485
1486         if (ECORE_IS_CMT(p_hwfn->p_dev))
1487                 hw_mode |= 1 << MODE_100G;
1488
1489         p_hwfn->hw_info.hw_mode = hw_mode;
1490
1491         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1492                    "Configuring function for hw_mode: 0x%08x\n",
1493                    p_hwfn->hw_info.hw_mode);
1494
1495         return ECORE_SUCCESS;
1496 }
1497
1498 #ifndef ASIC_ONLY
1499 /* MFW-replacement initializations for non-ASIC */
1500 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1501                                                struct ecore_ptt *p_ptt)
1502 {
1503         struct ecore_dev *p_dev = p_hwfn->p_dev;
1504         u32 pl_hv = 1;
1505         int i;
1506
1507         if (CHIP_REV_IS_EMUL(p_dev)) {
1508                 if (ECORE_IS_AH(p_dev))
1509                         pl_hv |= 0x600;
1510         }
1511
1512         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1513
1514         if (CHIP_REV_IS_EMUL(p_dev) &&
1515             (ECORE_IS_AH(p_dev)))
1516                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1517                          0x3ffffff);
1518
1519         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1520         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1521         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1522                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1523
1524         if (CHIP_REV_IS_EMUL(p_dev)) {
1525                 if (ECORE_IS_AH(p_dev)) {
1526                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1527                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1528                                  (p_dev->num_ports_in_engine >> 1));
1529
1530                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1531                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1532                 }
1533         }
1534
1535         /* Poll on RBC */
1536         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1537         for (i = 0; i < 100; i++) {
1538                 OSAL_UDELAY(50);
1539                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1540                         break;
1541         }
1542         if (i == 100)
1543                 DP_NOTICE(p_hwfn, true,
1544                           "RBC done failed to complete in PSWRQ2\n");
1545
1546         return ECORE_SUCCESS;
1547 }
1548 #endif
1549
1550 /* Init run time data for all PFs and their VFs on an engine.
1551  * TBD - for VFs - Once we have parent PF info for each VF in
1552  * shmem available as CAU requires knowledge of parent PF for each VF.
1553  */
1554 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1555 {
1556         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1557         int i, igu_sb_id;
1558
1559         for_each_hwfn(p_dev, i) {
1560                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1561                 struct ecore_igu_info *p_igu_info;
1562                 struct ecore_igu_block *p_block;
1563                 struct cau_sb_entry sb_entry;
1564
1565                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1566
1567                 for (igu_sb_id = 0;
1568                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1569                      igu_sb_id++) {
1570                         p_block = &p_igu_info->entry[igu_sb_id];
1571
1572                         if (!p_block->is_pf)
1573                                 continue;
1574
1575                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1576                                                 p_block->function_id, 0, 0);
1577                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1578                                          sb_entry);
1579                 }
1580         }
1581 }
1582
1583 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1584                                        struct ecore_ptt *p_ptt)
1585 {
1586         u32 val, wr_mbs, cache_line_size;
1587
1588         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1589         switch (val) {
1590         case 0:
1591                 wr_mbs = 128;
1592                 break;
1593         case 1:
1594                 wr_mbs = 256;
1595                 break;
1596         case 2:
1597                 wr_mbs = 512;
1598                 break;
1599         default:
1600                 DP_INFO(p_hwfn,
1601                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1602                         val);
1603                 return;
1604         }
1605
1606         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1607         switch (cache_line_size) {
1608         case 32:
1609                 val = 0;
1610                 break;
1611         case 64:
1612                 val = 1;
1613                 break;
1614         case 128:
1615                 val = 2;
1616                 break;
1617         case 256:
1618                 val = 3;
1619                 break;
1620         default:
1621                 DP_INFO(p_hwfn,
1622                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1623                         cache_line_size);
1624         }
1625
1626         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1627                 DP_INFO(p_hwfn,
1628                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1629                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1630
1631         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1632         if (val > 0) {
1633                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1634                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1635         }
1636 }
1637
1638 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1639                                                  struct ecore_ptt *p_ptt,
1640                                                  int hw_mode)
1641 {
1642         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1643         struct ecore_dev *p_dev = p_hwfn->p_dev;
1644         u8 vf_id, max_num_vfs;
1645         u16 num_pfs, pf_id;
1646         u32 concrete_fid;
1647         enum _ecore_status_t rc = ECORE_SUCCESS;
1648
1649         ecore_init_cau_rt_data(p_dev);
1650
1651         /* Program GTT windows */
1652         ecore_gtt_init(p_hwfn, p_ptt);
1653
1654 #ifndef ASIC_ONLY
1655         if (CHIP_REV_IS_EMUL(p_dev)) {
1656                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1657                 if (rc != ECORE_SUCCESS)
1658                         return rc;
1659         }
1660 #endif
1661
1662         if (p_hwfn->mcp_info) {
1663                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1664                         qm_info->pf_rl_en = 1;
1665                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1666                         qm_info->pf_wfq_en = 1;
1667         }
1668
1669         ecore_qm_common_rt_init(p_hwfn,
1670                                 p_dev->num_ports_in_engine,
1671                                 qm_info->max_phys_tcs_per_port,
1672                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1673                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1674                                 qm_info->qm_port_params);
1675
1676         ecore_cxt_hw_init_common(p_hwfn);
1677
1678         ecore_init_cache_line_size(p_hwfn, p_ptt);
1679
1680         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1681         if (rc != ECORE_SUCCESS)
1682                 return rc;
1683
1684         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1685          * need to decide with which value, maybe runtime
1686          */
1687         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1688         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1689
1690         if (ECORE_IS_BB(p_dev)) {
1691                 /* Workaround clears ROCE search for all functions to prevent
1692                  * involving non initialized function in processing ROCE packet.
1693                  */
1694                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1695                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1696                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1697                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1698                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1699                 }
1700                 /* pretend to original PF */
1701                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1702         }
1703
1704         /* Workaround for avoiding CCFC execution error when getting packets
1705          * with CRC errors, and allowing instead the invoking of the FW error
1706          * handler.
1707          * This is not done inside the init tool since it currently can't
1708          * perform a pretending to VFs.
1709          */
1710         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1711         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1712                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1713                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1714                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1715                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1716                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1717                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1718         }
1719         /* pretend to original PF */
1720         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1721
1722         return rc;
1723 }
1724
1725 #ifndef ASIC_ONLY
1726 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1727 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1728
1729 #define PMEG_IF_BYTE_COUNT      8
1730
1731 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1732                              struct ecore_ptt *p_ptt,
1733                              u32 addr, u64 data, u8 reg_type, u8 port)
1734 {
1735         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1736                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1737                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1738                    (8 << PMEG_IF_BYTE_COUNT),
1739                    (reg_type << 25) | (addr << 8) | port,
1740                    (u32)((data >> 32) & 0xffffffff),
1741                    (u32)(data & 0xffffffff));
1742
1743         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1744                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1745                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1746         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1747                  (reg_type << 25) | (addr << 8) | port);
1748         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1749         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1750                  (data >> 32) & 0xffffffff);
1751 }
1752
1753 #define XLPORT_MODE_REG (0x20a)
1754 #define XLPORT_MAC_CONTROL (0x210)
1755 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1756 #define XLPORT_ENABLE_REG (0x20b)
1757
1758 #define XLMAC_CTRL (0x600)
1759 #define XLMAC_MODE (0x601)
1760 #define XLMAC_RX_MAX_SIZE (0x608)
1761 #define XLMAC_TX_CTRL (0x604)
1762 #define XLMAC_PAUSE_CTRL (0x60d)
1763 #define XLMAC_PFC_CTRL (0x60e)
1764
1765 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1766                                     struct ecore_ptt *p_ptt)
1767 {
1768         u8 loopback = 0, port = p_hwfn->port_id * 2;
1769
1770         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1771
1772         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1773         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1774                          port);
1775         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1776         /* XLMAC: SOFT RESET */
1777         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1778         /* XLMAC: Port Speed >= 10Gbps */
1779         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1780         /* XLMAC: Max Size */
1781         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1782         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1783                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1784                          0, port);
1785         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1786         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1787                          0x30ffffc000ULL, 0, port);
1788         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1789                          port); /* XLMAC: TX_EN, RX_EN */
1790         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1791         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1792                          0x1003 | (loopback << 2), 0, port);
1793         /* Enabled Parallel PFC interface */
1794         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1795
1796         /* XLPORT port enable */
1797         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1798 }
1799
1800 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1801                                        struct ecore_ptt *p_ptt)
1802 {
1803         u8 port = p_hwfn->port_id;
1804         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1805
1806         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1807
1808         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1809                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1810                  (port <<
1811                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1812                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1813
1814         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1815                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1816
1817         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1818                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1819
1820         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1821                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1822
1823         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1824                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1825
1826         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1827                  (0xA <<
1828                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1829                  (8 <<
1830                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1831
1832         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1833                  0xa853);
1834 }
1835
1836 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1837                                  struct ecore_ptt *p_ptt)
1838 {
1839         if (ECORE_IS_AH(p_hwfn->p_dev))
1840                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1841         else /* BB */
1842                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1843 }
1844
1845 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1846                                struct ecore_ptt *p_ptt,  u8 port)
1847 {
1848         int port_offset = port ? 0x800 : 0;
1849         u32 xmac_rxctrl = 0;
1850
1851         /* Reset of XMAC */
1852         /* FIXME: move to common start */
1853         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1854                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1855         OSAL_MSLEEP(1);
1856         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1857                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1858
1859         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1860
1861         /* Set the number of ports on the Warp Core to 10G */
1862         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1863
1864         /* Soft reset of XMAC */
1865         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1866                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1867         OSAL_MSLEEP(1);
1868         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1869                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1870
1871         /* FIXME: move to common end */
1872         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1873                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1874
1875         /* Set Max packet size: initialize XMAC block register for port 0 */
1876         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1877
1878         /* CRC append for Tx packets: init XMAC block register for port 1 */
1879         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1880
1881         /* Enable TX and RX: initialize XMAC block register for port 1 */
1882         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1883                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1884         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1885                                XMAC_REG_RX_CTRL_BB + port_offset);
1886         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1887         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1888 }
1889 #endif
1890
1891 static enum _ecore_status_t
1892 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1893                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1894 {
1895         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1896         u32 min_dpis;
1897         u32 n_wids;
1898
1899         /* Calculate DPI size
1900          * ------------------
1901          * The PWM region contains Doorbell Pages. The first is reserverd for
1902          * the kernel for, e.g, L2. The others are free to be used by non-
1903          * trusted applications, typically from user space. Each page, called a
1904          * doorbell page is sectioned into windows that allow doorbells to be
1905          * issued in parallel by the kernel/application. The size of such a
1906          * window (a.k.a. WID) is 1kB.
1907          * Summary:
1908          *    1kB WID x N WIDS = DPI page size
1909          *    DPI page size x N DPIs = PWM region size
1910          * Notes:
1911          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1912          * in order to ensure that two applications won't share the same page.
1913          * It also must contain at least one WID per CPU to allow parallelism.
1914          * It also must be a power of 2, since it is stored as a bit shift.
1915          *
1916          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1917          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1918          * containing 4 WIDs.
1919          */
1920         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1921         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1922         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1923                         ~(OSAL_PAGE_SIZE - 1);
1924         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1925         dpi_count = pwm_region_size / dpi_page_size;
1926
1927         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1928         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1929
1930         /* Update hwfn */
1931         p_hwfn->dpi_size = dpi_page_size;
1932         p_hwfn->dpi_count = dpi_count;
1933
1934         /* Update registers */
1935         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1936
1937         if (dpi_count < min_dpis)
1938                 return ECORE_NORESOURCES;
1939
1940         return ECORE_SUCCESS;
1941 }
1942
1943 enum ECORE_ROCE_EDPM_MODE {
1944         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1945         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1946         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1947 };
1948
1949 static enum _ecore_status_t
1950 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1951                               struct ecore_ptt *p_ptt)
1952 {
1953         u32 pwm_regsize, norm_regsize;
1954         u32 non_pwm_conn, min_addr_reg1;
1955         u32 db_bar_size, n_cpus;
1956         u32 roce_edpm_mode;
1957         u32 pf_dems_shift;
1958         enum _ecore_status_t rc = ECORE_SUCCESS;
1959         u8 cond;
1960
1961         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1962         if (ECORE_IS_CMT(p_hwfn->p_dev))
1963                 db_bar_size /= 2;
1964
1965         /* Calculate doorbell regions
1966          * -----------------------------------
1967          * The doorbell BAR is made of two regions. The first is called normal
1968          * region and the second is called PWM region. In the normal region
1969          * each ICID has its own set of addresses so that writing to that
1970          * specific address identifies the ICID. In the Process Window Mode
1971          * region the ICID is given in the data written to the doorbell. The
1972          * above per PF register denotes the offset in the doorbell BAR in which
1973          * the PWM region begins.
1974          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1975          * non-PWM connection. The calculation below computes the total non-PWM
1976          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1977          * in units of 4,096 bytes.
1978          */
1979         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1980             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1981                                           OSAL_NULL) +
1982             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1983         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1984                                OSAL_PAGE_SIZE);
1985         min_addr_reg1 = norm_regsize / 4096;
1986         pwm_regsize = db_bar_size - norm_regsize;
1987
1988         /* Check that the normal and PWM sizes are valid */
1989         if (db_bar_size < norm_regsize) {
1990                 DP_ERR(p_hwfn->p_dev,
1991                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1992                        db_bar_size, norm_regsize);
1993                 return ECORE_NORESOURCES;
1994         }
1995         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1996                 DP_ERR(p_hwfn->p_dev,
1997                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1998                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1999                        norm_regsize);
2000                 return ECORE_NORESOURCES;
2001         }
2002
2003         /* Calculate number of DPIs */
2004         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2005         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2006             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2007                 /* Either EDPM is mandatory, or we are attempting to allocate a
2008                  * WID per CPU.
2009                  */
2010                 n_cpus = OSAL_NUM_ACTIVE_CPU();
2011                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2012         }
2013
2014         cond = ((rc != ECORE_SUCCESS) &&
2015                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2016                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2017         if (cond || p_hwfn->dcbx_no_edpm) {
2018                 /* Either EDPM is disabled from user configuration, or it is
2019                  * disabled via DCBx, or it is not mandatory and we failed to
2020                  * allocated a WID per CPU.
2021                  */
2022                 n_cpus = 1;
2023                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2024
2025                 /* If we entered this flow due to DCBX then the DPM register is
2026                  * already configured.
2027                  */
2028         }
2029
2030         DP_INFO(p_hwfn,
2031                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2032                 norm_regsize, pwm_regsize);
2033         DP_INFO(p_hwfn,
2034                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2035                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2036                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2037                 "disabled" : "enabled");
2038
2039         /* Check return codes from above calls */
2040         if (rc != ECORE_SUCCESS) {
2041                 DP_ERR(p_hwfn,
2042                        "Failed to allocate enough DPIs\n");
2043                 return ECORE_NORESOURCES;
2044         }
2045
2046         /* Update hwfn */
2047         p_hwfn->dpi_start_offset = norm_regsize;
2048
2049         /* Update registers */
2050         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2051         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2052         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2053         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2054
2055         return ECORE_SUCCESS;
2056 }
2057
2058 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2059                                                struct ecore_ptt *p_ptt,
2060                                                int hw_mode)
2061 {
2062         enum _ecore_status_t rc = ECORE_SUCCESS;
2063
2064         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2065                             hw_mode);
2066         if (rc != ECORE_SUCCESS)
2067                 return rc;
2068
2069         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2070
2071 #ifndef ASIC_ONLY
2072         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2073                 return ECORE_SUCCESS;
2074
2075         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2076                 if (ECORE_IS_AH(p_hwfn->p_dev))
2077                         return ECORE_SUCCESS;
2078                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2079                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2080         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2081                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2082                         /* Activate OPTE in CMT */
2083                         u32 val;
2084
2085                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2086                         val |= 0x10;
2087                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2088                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2089                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2090                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2091                         ecore_wr(p_hwfn, p_ptt,
2092                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2093                         ecore_wr(p_hwfn, p_ptt,
2094                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2095                         ecore_wr(p_hwfn, p_ptt,
2096                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2097                                  0x55555555);
2098                 }
2099
2100                 ecore_emul_link_init(p_hwfn, p_ptt);
2101         } else {
2102                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2103         }
2104 #endif
2105
2106         return rc;
2107 }
2108
2109 static enum _ecore_status_t
2110 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2111                  struct ecore_ptt *p_ptt,
2112                  struct ecore_tunnel_info *p_tunn,
2113                  int hw_mode,
2114                  bool b_hw_start,
2115                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2116 {
2117         u8 rel_pf_id = p_hwfn->rel_pf_id;
2118         u32 prs_reg;
2119         enum _ecore_status_t rc = ECORE_SUCCESS;
2120         u16 ctrl;
2121         int pos;
2122
2123         if (p_hwfn->mcp_info) {
2124                 struct ecore_mcp_function_info *p_info;
2125
2126                 p_info = &p_hwfn->mcp_info->func_info;
2127                 if (p_info->bandwidth_min)
2128                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2129
2130                 /* Update rate limit once we'll actually have a link */
2131                 p_hwfn->qm_info.pf_rl = 100000;
2132         }
2133         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2134
2135         ecore_int_igu_init_rt(p_hwfn);
2136
2137         /* Set VLAN in NIG if needed */
2138         if (hw_mode & (1 << MODE_MF_SD)) {
2139                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2140                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2141                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2142                              p_hwfn->hw_info.ovlan);
2143         }
2144
2145         /* Enable classification by MAC if needed */
2146         if (hw_mode & (1 << MODE_MF_SI)) {
2147                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2148                            "Configuring TAGMAC_CLS_TYPE\n");
2149                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2150                              1);
2151         }
2152
2153         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2154         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2155                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2156         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2157                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2158         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2159
2160         /* perform debug configuration when chip is out of reset */
2161         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2162
2163         /* PF Init sequence */
2164         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2165         if (rc)
2166                 return rc;
2167
2168         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2169         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2170         if (rc)
2171                 return rc;
2172
2173         /* Pure runtime initializations - directly to the HW  */
2174         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2175
2176         /* PCI relaxed ordering causes a decrease in the performance on some
2177          * systems. Till a root cause is found, disable this attribute in the
2178          * PCI config space.
2179          */
2180         /* Not in use @DPDK
2181         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2182         * if (!pos) {
2183         *       DP_NOTICE(p_hwfn, true,
2184         *                 "Failed to find the PCIe Cap\n");
2185         *       return ECORE_IO;
2186         * }
2187         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2188         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2189         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2190         */
2191
2192         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2193         if (rc)
2194                 return rc;
2195         if (b_hw_start) {
2196                 /* enable interrupts */
2197                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2198                 if (rc != ECORE_SUCCESS)
2199                         return rc;
2200
2201                 /* send function start command */
2202                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2203                                        p_hwfn->p_dev->mf_mode,
2204                                        allow_npar_tx_switch);
2205                 if (rc) {
2206                         DP_NOTICE(p_hwfn, true,
2207                                   "Function start ramrod failed\n");
2208                 } else {
2209                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2210                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2211                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2212
2213                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2214                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2215                                          (1 << 2));
2216                                 ecore_wr(p_hwfn, p_ptt,
2217                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2218                                     0x100);
2219                         }
2220                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2221                                    "PRS_REG_SEARCH registers after start PFn\n");
2222                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2223                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2224                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2225                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2226                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2227                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2228                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2229                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2230                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2231                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2232                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2233                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2234                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2235                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2236                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2237                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2238                                    prs_reg);
2239                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2240                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2241                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2242                 }
2243         }
2244         return rc;
2245 }
2246
2247 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2248                                                   struct ecore_ptt *p_ptt,
2249                                                   bool b_enable)
2250 {
2251         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2252
2253         /* Configure the PF's internal FID_enable for master transactions */
2254         ecore_wr(p_hwfn, p_ptt,
2255                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2256
2257         /* Wait until value is set - try for 1 second every 50us */
2258         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2259                 val = ecore_rd(p_hwfn, p_ptt,
2260                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2261                 if (val == set_val)
2262                         break;
2263
2264                 OSAL_UDELAY(50);
2265         }
2266
2267         if (val != set_val) {
2268                 DP_NOTICE(p_hwfn, true,
2269                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2270                 return ECORE_UNKNOWN_ERROR;
2271         }
2272
2273         return ECORE_SUCCESS;
2274 }
2275
2276 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2277                                   struct ecore_ptt *p_main_ptt)
2278 {
2279         /* Read shadow of current MFW mailbox */
2280         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2281         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2282                     p_hwfn->mcp_info->mfw_mb_cur,
2283                     p_hwfn->mcp_info->mfw_mb_length);
2284 }
2285
2286 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2287                                     struct ecore_hw_init_params *p_params)
2288 {
2289         if (p_params->p_tunn) {
2290                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2291                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2292         }
2293
2294         p_hwfn->b_int_enabled = 1;
2295
2296         return ECORE_SUCCESS;
2297 }
2298
2299 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2300                                      struct ecore_ptt *p_ptt)
2301 {
2302         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2303                  1 << p_hwfn->abs_pf_id);
2304 }
2305
2306 static void
2307 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2308                            struct ecore_drv_load_params *p_drv_load)
2309 {
2310         /* Make sure that if ecore-client didn't provide inputs, all the
2311          * expected defaults are indeed zero.
2312          */
2313         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2314         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2315         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2316
2317         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2318
2319         if (p_drv_load != OSAL_NULL) {
2320                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2321                                        ECORE_DRV_ROLE_KDUMP :
2322                                        ECORE_DRV_ROLE_OS;
2323                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2324                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2325                 p_load_req->override_force_load =
2326                         p_drv_load->override_force_load;
2327         }
2328 }
2329
2330 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2331                                    struct ecore_hw_init_params *p_params)
2332 {
2333         struct ecore_load_req_params load_req_params;
2334         u32 load_code, resp, param, drv_mb_param;
2335         bool b_default_mtu = true;
2336         struct ecore_hwfn *p_hwfn;
2337         enum _ecore_status_t rc = ECORE_SUCCESS;
2338         int i;
2339
2340         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2341                 DP_NOTICE(p_dev, false,
2342                           "MSI mode is not supported for CMT devices\n");
2343                 return ECORE_INVAL;
2344         }
2345
2346         if (IS_PF(p_dev)) {
2347                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2348                 if (rc != ECORE_SUCCESS)
2349                         return rc;
2350         }
2351
2352         for_each_hwfn(p_dev, i) {
2353                 p_hwfn = &p_dev->hwfns[i];
2354
2355                 /* If management didn't provide a default, set one of our own */
2356                 if (!p_hwfn->hw_info.mtu) {
2357                         p_hwfn->hw_info.mtu = 1500;
2358                         b_default_mtu = false;
2359                 }
2360
2361                 if (IS_VF(p_dev)) {
2362                         ecore_vf_start(p_hwfn, p_params);
2363                         continue;
2364                 }
2365
2366                 rc = ecore_calc_hw_mode(p_hwfn);
2367                 if (rc != ECORE_SUCCESS)
2368                         return rc;
2369
2370                 ecore_fill_load_req_params(&load_req_params,
2371                                            p_params->p_drv_load_params);
2372                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2373                                         &load_req_params);
2374                 if (rc != ECORE_SUCCESS) {
2375                         DP_NOTICE(p_hwfn, true,
2376                                   "Failed sending a LOAD_REQ command\n");
2377                         return rc;
2378                 }
2379
2380                 load_code = load_req_params.load_code;
2381                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2382                            "Load request was sent. Load code: 0x%x\n",
2383                            load_code);
2384
2385                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2386
2387                 /* CQ75580:
2388                  * When coming back from hiberbate state, the registers from
2389                  * which shadow is read initially are not initialized. It turns
2390                  * out that these registers get initialized during the call to
2391                  * ecore_mcp_load_req request. So we need to reread them here
2392                  * to get the proper shadow register value.
2393                  * Note: This is a workaround for the missing MFW
2394                  * initialization. It may be removed once the implementation
2395                  * is done.
2396                  */
2397                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2398
2399                 /* Only relevant for recovery:
2400                  * Clear the indication after the LOAD_REQ command is responded
2401                  * by the MFW.
2402                  */
2403                 p_dev->recov_in_prog = false;
2404
2405                 p_hwfn->first_on_engine = (load_code ==
2406                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2407
2408                 if (!qm_lock_init) {
2409                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2410                         qm_lock_init = true;
2411                 }
2412
2413                 /* Clean up chip from previous driver if such remains exist.
2414                  * This is not needed when the PF is the first one on the
2415                  * engine, since afterwards we are going to init the FW.
2416                  */
2417                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2418                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2419                                                  p_hwfn->rel_pf_id, false);
2420                         if (rc != ECORE_SUCCESS) {
2421                                 ecore_hw_err_notify(p_hwfn,
2422                                                     ECORE_HW_ERR_RAMROD_FAIL);
2423                                 goto load_err;
2424                         }
2425                 }
2426
2427                 /* Log and clean previous pglue_b errors if such exist */
2428                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2429                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2430
2431                 /* Enable the PF's internal FID_enable in the PXP */
2432                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2433                                                   true);
2434                 if (rc != ECORE_SUCCESS)
2435                         goto load_err;
2436
2437                 switch (load_code) {
2438                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2439                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2440                                                   p_hwfn->hw_info.hw_mode);
2441                         if (rc != ECORE_SUCCESS)
2442                                 break;
2443                         /* Fall into */
2444                 case FW_MSG_CODE_DRV_LOAD_PORT:
2445                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2446                                                 p_hwfn->hw_info.hw_mode);
2447                         if (rc != ECORE_SUCCESS)
2448                                 break;
2449                         /* Fall into */
2450                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2451                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2452                                               p_params->p_tunn,
2453                                               p_hwfn->hw_info.hw_mode,
2454                                               p_params->b_hw_start,
2455                                               p_params->int_mode,
2456                                               p_params->allow_npar_tx_switch);
2457                         break;
2458                 default:
2459                         DP_NOTICE(p_hwfn, false,
2460                                   "Unexpected load code [0x%08x]", load_code);
2461                         rc = ECORE_NOTIMPL;
2462                         break;
2463                 }
2464
2465                 if (rc != ECORE_SUCCESS) {
2466                         DP_NOTICE(p_hwfn, true,
2467                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2468                                   load_code, rc);
2469                         goto load_err;
2470                 }
2471
2472                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2473                 if (rc != ECORE_SUCCESS)
2474                         return rc;
2475
2476                 /* send DCBX attention request command */
2477                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2478                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2479                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2480                                    DRV_MSG_CODE_SET_DCBX,
2481                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2482                                    &param);
2483                 if (rc != ECORE_SUCCESS) {
2484                         DP_NOTICE(p_hwfn, true,
2485                                   "Failed to send DCBX attention request\n");
2486                         return rc;
2487                 }
2488
2489                 p_hwfn->hw_init_done = true;
2490         }
2491
2492         if (IS_PF(p_dev)) {
2493                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2494                 drv_mb_param = STORM_FW_VERSION;
2495                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2496                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2497                                    drv_mb_param, &resp, &param);
2498                 if (rc != ECORE_SUCCESS)
2499                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2500
2501                 if (!b_default_mtu)
2502                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2503                                                       p_hwfn->hw_info.mtu);
2504                 if (rc != ECORE_SUCCESS)
2505                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2506
2507                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2508                                                       p_hwfn->p_main_ptt,
2509                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2510                 if (rc != ECORE_SUCCESS)
2511                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2512         }
2513
2514         return rc;
2515
2516 load_err:
2517         /* The MFW load lock should be released regardless of success or failure
2518          * of initialization.
2519          * TODO: replace this with an attempt to send cancel_load.
2520          */
2521         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2522         return rc;
2523 }
2524
2525 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2526 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2527                                  struct ecore_hwfn *p_hwfn,
2528                                  struct ecore_ptt *p_ptt)
2529 {
2530         int i;
2531
2532         /* close timers */
2533         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2534         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2535         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2536                                                                         i++) {
2537                 if ((!ecore_rd(p_hwfn, p_ptt,
2538                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2539                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2540                         break;
2541
2542                 /* Dependent on number of connection/tasks, possibly
2543                  * 1ms sleep is required between polls
2544                  */
2545                 OSAL_MSLEEP(1);
2546         }
2547
2548         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2549                 return;
2550
2551         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2552                   " [Connection %02x Tasks %02x]\n",
2553                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2554                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2555 }
2556
2557 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2558 {
2559         int j;
2560
2561         for_each_hwfn(p_dev, j) {
2562                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2563                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2564
2565                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2566         }
2567 }
2568
2569 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2570                                                  struct ecore_ptt *p_ptt,
2571                                                  u32 addr, u32 expected_val)
2572 {
2573         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2574
2575         if (val != expected_val) {
2576                 DP_NOTICE(p_hwfn, true,
2577                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2578                           addr, val, expected_val);
2579                 return ECORE_UNKNOWN_ERROR;
2580         }
2581
2582         return ECORE_SUCCESS;
2583 }
2584
2585 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2586 {
2587         struct ecore_hwfn *p_hwfn;
2588         struct ecore_ptt *p_ptt;
2589         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2590         int j;
2591
2592         for_each_hwfn(p_dev, j) {
2593                 p_hwfn = &p_dev->hwfns[j];
2594                 p_ptt = p_hwfn->p_main_ptt;
2595
2596                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2597
2598                 if (IS_VF(p_dev)) {
2599                         ecore_vf_pf_int_cleanup(p_hwfn);
2600                         rc = ecore_vf_pf_reset(p_hwfn);
2601                         if (rc != ECORE_SUCCESS) {
2602                                 DP_NOTICE(p_hwfn, true,
2603                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2604                                           rc);
2605                                 rc2 = ECORE_UNKNOWN_ERROR;
2606                         }
2607                         continue;
2608                 }
2609
2610                 /* mark the hw as uninitialized... */
2611                 p_hwfn->hw_init_done = false;
2612
2613                 /* Send unload command to MCP */
2614                 if (!p_dev->recov_in_prog) {
2615                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2616                         if (rc != ECORE_SUCCESS) {
2617                                 DP_NOTICE(p_hwfn, true,
2618                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2619                                           rc);
2620                                 rc2 = ECORE_UNKNOWN_ERROR;
2621                         }
2622                 }
2623
2624                 OSAL_DPC_SYNC(p_hwfn);
2625
2626                 /* After this point no MFW attentions are expected, e.g. prevent
2627                  * race between pf stop and dcbx pf update.
2628                  */
2629
2630                 rc = ecore_sp_pf_stop(p_hwfn);
2631                 if (rc != ECORE_SUCCESS) {
2632                         DP_NOTICE(p_hwfn, true,
2633                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2634                                   rc);
2635                         rc2 = ECORE_UNKNOWN_ERROR;
2636                 }
2637
2638                 /* perform debug action after PF stop was sent */
2639                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2640
2641                 /* close NIG to BRB gate */
2642                 ecore_wr(p_hwfn, p_ptt,
2643                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2644
2645                 /* close parser */
2646                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2647                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2648                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2649                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2650                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2651
2652                 /* @@@TBD - clean transmission queues (5.b) */
2653                 /* @@@TBD - clean BTB (5.c) */
2654
2655                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2656
2657                 /* @@@TBD - verify DMAE requests are done (8) */
2658
2659                 /* Disable Attention Generation */
2660                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2661                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2662                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2663                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2664                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2665                 if (rc != ECORE_SUCCESS) {
2666                         DP_NOTICE(p_hwfn, true,
2667                                   "Failed to return IGU CAM to default\n");
2668                         rc2 = ECORE_UNKNOWN_ERROR;
2669                 }
2670
2671                 /* Need to wait 1ms to guarantee SBs are cleared */
2672                 OSAL_MSLEEP(1);
2673
2674                 if (!p_dev->recov_in_prog) {
2675                         ecore_verify_reg_val(p_hwfn, p_ptt,
2676                                              QM_REG_USG_CNT_PF_TX, 0);
2677                         ecore_verify_reg_val(p_hwfn, p_ptt,
2678                                              QM_REG_USG_CNT_PF_OTHER, 0);
2679                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2680                 }
2681
2682                 /* Disable PF in HW blocks */
2683                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2684                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2685
2686                 if (!p_dev->recov_in_prog) {
2687                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2688                         if (rc != ECORE_SUCCESS) {
2689                                 DP_NOTICE(p_hwfn, true,
2690                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2691                                           rc);
2692                                 rc2 = ECORE_UNKNOWN_ERROR;
2693                         }
2694                 }
2695         } /* hwfn loop */
2696
2697         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2698                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2699                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2700
2701                  /* Clear the PF's internal FID_enable in the PXP.
2702                   * In CMT this should only be done for first hw-function, and
2703                   * only after all transactions have stopped for all active
2704                   * hw-functions.
2705                   */
2706                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2707                                                   false);
2708                 if (rc != ECORE_SUCCESS) {
2709                         DP_NOTICE(p_hwfn, true,
2710                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2711                                   rc);
2712                         rc2 = ECORE_UNKNOWN_ERROR;
2713                 }
2714         }
2715
2716         return rc2;
2717 }
2718
2719 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2720 {
2721         int j;
2722
2723         for_each_hwfn(p_dev, j) {
2724                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2725                 struct ecore_ptt *p_ptt;
2726
2727                 if (IS_VF(p_dev)) {
2728                         ecore_vf_pf_int_cleanup(p_hwfn);
2729                         continue;
2730                 }
2731                 p_ptt = ecore_ptt_acquire(p_hwfn);
2732                 if (!p_ptt)
2733                         return ECORE_AGAIN;
2734
2735                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2736                            "Shutting down the fastpath\n");
2737
2738                 ecore_wr(p_hwfn, p_ptt,
2739                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2740
2741                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2742                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2743                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2744                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2745                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2746
2747                 /* @@@TBD - clean transmission queues (5.b) */
2748                 /* @@@TBD - clean BTB (5.c) */
2749
2750                 /* @@@TBD - verify DMAE requests are done (8) */
2751
2752                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2753                 /* Need to wait 1ms to guarantee SBs are cleared */
2754                 OSAL_MSLEEP(1);
2755                 ecore_ptt_release(p_hwfn, p_ptt);
2756         }
2757
2758         return ECORE_SUCCESS;
2759 }
2760
2761 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2762 {
2763         struct ecore_ptt *p_ptt;
2764
2765         if (IS_VF(p_hwfn->p_dev))
2766                 return ECORE_SUCCESS;
2767
2768         p_ptt = ecore_ptt_acquire(p_hwfn);
2769         if (!p_ptt)
2770                 return ECORE_AGAIN;
2771
2772         /* If roce info is allocated it means roce is initialized and should
2773          * be enabled in searcher.
2774          */
2775         if (p_hwfn->p_rdma_info) {
2776                 if (p_hwfn->b_rdma_enabled_in_prs)
2777                         ecore_wr(p_hwfn, p_ptt,
2778                                  p_hwfn->rdma_prs_search_reg, 0x1);
2779                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2780         }
2781
2782         /* Re-open incoming traffic */
2783         ecore_wr(p_hwfn, p_ptt,
2784                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2785         ecore_ptt_release(p_hwfn, p_ptt);
2786
2787         return ECORE_SUCCESS;
2788 }
2789
2790 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2791 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2792 {
2793         ecore_ptt_pool_free(p_hwfn);
2794         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2795 }
2796
2797 /* Setup bar access */
2798 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2799 {
2800         /* clear indirect access */
2801         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2802                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2803                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2804                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2805                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2806                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2807                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2808                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2809                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2810         } else {
2811                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2812                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2813                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2814                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2815                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2816                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2817                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2818                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2819         }
2820
2821         /* Clean previous pglue_b errors if such exist */
2822         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2823
2824         /* enable internal target-read */
2825         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2826                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2827 }
2828
2829 static void get_function_id(struct ecore_hwfn *p_hwfn)
2830 {
2831         /* ME Register */
2832         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2833                                                   PXP_PF_ME_OPAQUE_ADDR);
2834
2835         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2836
2837         /* Bits 16-19 from the ME registers are the pf_num */
2838         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2839         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2840                                       PXP_CONCRETE_FID_PFID);
2841         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2842                                     PXP_CONCRETE_FID_PORT);
2843
2844         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2845                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2846                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2847 }
2848
2849 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2850 {
2851         u32 *feat_num = p_hwfn->hw_info.feat_num;
2852         struct ecore_sb_cnt_info sb_cnt;
2853         u32 non_l2_sbs = 0;
2854
2855         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2856         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2857
2858         /* L2 Queues require each: 1 status block. 1 L2 queue */
2859         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2860                 /* Start by allocating VF queues, then PF's */
2861                 feat_num[ECORE_VF_L2_QUE] =
2862                         OSAL_MIN_T(u32,
2863                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2864                                    sb_cnt.iov_cnt);
2865                 feat_num[ECORE_PF_L2_QUE] =
2866                         OSAL_MIN_T(u32,
2867                                    sb_cnt.cnt - non_l2_sbs,
2868                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2869                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2870         }
2871
2872         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2873                                              RESC_NUM(p_hwfn,
2874                                                       ECORE_CMDQS_CQS));
2875         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2876                                               RESC_NUM(p_hwfn,
2877                                                        ECORE_CMDQS_CQS));
2878
2879         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2880                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2881                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2882                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2883                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2884                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2885                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2886                    (int)sb_cnt.cnt);
2887 }
2888
2889 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2890 {
2891         switch (res_id) {
2892         case ECORE_L2_QUEUE:
2893                 return "L2_QUEUE";
2894         case ECORE_VPORT:
2895                 return "VPORT";
2896         case ECORE_RSS_ENG:
2897                 return "RSS_ENG";
2898         case ECORE_PQ:
2899                 return "PQ";
2900         case ECORE_RL:
2901                 return "RL";
2902         case ECORE_MAC:
2903                 return "MAC";
2904         case ECORE_VLAN:
2905                 return "VLAN";
2906         case ECORE_RDMA_CNQ_RAM:
2907                 return "RDMA_CNQ_RAM";
2908         case ECORE_ILT:
2909                 return "ILT";
2910         case ECORE_LL2_QUEUE:
2911                 return "LL2_QUEUE";
2912         case ECORE_CMDQS_CQS:
2913                 return "CMDQS_CQS";
2914         case ECORE_RDMA_STATS_QUEUE:
2915                 return "RDMA_STATS_QUEUE";
2916         case ECORE_BDQ:
2917                 return "BDQ";
2918         case ECORE_SB:
2919                 return "SB";
2920         default:
2921                 return "UNKNOWN_RESOURCE";
2922         }
2923 }
2924
2925 static enum _ecore_status_t
2926 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2927                               struct ecore_ptt *p_ptt,
2928                               enum ecore_resources res_id,
2929                               u32 resc_max_val,
2930                               u32 *p_mcp_resp)
2931 {
2932         enum _ecore_status_t rc;
2933
2934         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2935                                         resc_max_val, p_mcp_resp);
2936         if (rc != ECORE_SUCCESS) {
2937                 DP_NOTICE(p_hwfn, true,
2938                           "MFW response failure for a max value setting of resource %d [%s]\n",
2939                           res_id, ecore_hw_get_resc_name(res_id));
2940                 return rc;
2941         }
2942
2943         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2944                 DP_INFO(p_hwfn,
2945                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2946                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2947
2948         return ECORE_SUCCESS;
2949 }
2950
2951 static enum _ecore_status_t
2952 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2953                             struct ecore_ptt *p_ptt)
2954 {
2955         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2956         u32 resc_max_val, mcp_resp;
2957         u8 res_id;
2958         enum _ecore_status_t rc;
2959
2960         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2961                 /* @DPDK */
2962                 switch (res_id) {
2963                 case ECORE_LL2_QUEUE:
2964                 case ECORE_RDMA_CNQ_RAM:
2965                 case ECORE_RDMA_STATS_QUEUE:
2966                 case ECORE_BDQ:
2967                         resc_max_val = 0;
2968                         break;
2969                 default:
2970                         continue;
2971                 }
2972
2973                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2974                                                    resc_max_val, &mcp_resp);
2975                 if (rc != ECORE_SUCCESS)
2976                         return rc;
2977
2978                 /* There's no point to continue to the next resource if the
2979                  * command is not supported by the MFW.
2980                  * We do continue if the command is supported but the resource
2981                  * is unknown to the MFW. Such a resource will be later
2982                  * configured with the default allocation values.
2983                  */
2984                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2985                         return ECORE_NOTIMPL;
2986         }
2987
2988         return ECORE_SUCCESS;
2989 }
2990
2991 static
2992 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2993                                             enum ecore_resources res_id,
2994                                             u32 *p_resc_num, u32 *p_resc_start)
2995 {
2996         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2997         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2998
2999         switch (res_id) {
3000         case ECORE_L2_QUEUE:
3001                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3002                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3003                 break;
3004         case ECORE_VPORT:
3005                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3006                                  MAX_NUM_VPORTS_BB) / num_funcs;
3007                 break;
3008         case ECORE_RSS_ENG:
3009                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3010                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3011                 break;
3012         case ECORE_PQ:
3013                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3014                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3015                 break;
3016         case ECORE_RL:
3017                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3018                 break;
3019         case ECORE_MAC:
3020         case ECORE_VLAN:
3021                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3022                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3023                 break;
3024         case ECORE_ILT:
3025                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3026                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3027                 break;
3028         case ECORE_LL2_QUEUE:
3029                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3030                 break;
3031         case ECORE_RDMA_CNQ_RAM:
3032         case ECORE_CMDQS_CQS:
3033                 /* CNQ/CMDQS are the same resource */
3034                 /* @DPDK */
3035                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3036                 break;
3037         case ECORE_RDMA_STATS_QUEUE:
3038                 /* @DPDK */
3039                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3040                                  MAX_NUM_VPORTS_BB) / num_funcs;
3041                 break;
3042         case ECORE_BDQ:
3043                 /* @DPDK */
3044                 *p_resc_num = 0;
3045                 break;
3046         default:
3047                 break;
3048         }
3049
3050
3051         switch (res_id) {
3052         case ECORE_BDQ:
3053                 if (!*p_resc_num)
3054                         *p_resc_start = 0;
3055                 break;
3056         case ECORE_SB:
3057                 /* Since we want its value to reflect whether MFW supports
3058                  * the new scheme, have a default of 0.
3059                  */
3060                 *p_resc_num = 0;
3061                 break;
3062         default:
3063                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3064                 break;
3065         }
3066
3067         return ECORE_SUCCESS;
3068 }
3069
3070 static enum _ecore_status_t
3071 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3072                          bool drv_resc_alloc)
3073 {
3074         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3075         u32 mcp_resp, *p_resc_num, *p_resc_start;
3076         enum _ecore_status_t rc;
3077
3078         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3079         p_resc_start = &RESC_START(p_hwfn, res_id);
3080
3081         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3082                                     &dflt_resc_start);
3083         if (rc != ECORE_SUCCESS) {
3084                 DP_ERR(p_hwfn,
3085                        "Failed to get default amount for resource %d [%s]\n",
3086                         res_id, ecore_hw_get_resc_name(res_id));
3087                 return rc;
3088         }
3089
3090 #ifndef ASIC_ONLY
3091         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3092                 *p_resc_num = dflt_resc_num;
3093                 *p_resc_start = dflt_resc_start;
3094                 goto out;
3095         }
3096 #endif
3097
3098         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3099                                      &mcp_resp, p_resc_num, p_resc_start);
3100         if (rc != ECORE_SUCCESS) {
3101                 DP_NOTICE(p_hwfn, true,
3102                           "MFW response failure for an allocation request for"
3103                           " resource %d [%s]\n",
3104                           res_id, ecore_hw_get_resc_name(res_id));
3105                 return rc;
3106         }
3107
3108         /* Default driver values are applied in the following cases:
3109          * - The resource allocation MB command is not supported by the MFW
3110          * - There is an internal error in the MFW while processing the request
3111          * - The resource ID is unknown to the MFW
3112          */
3113         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3114                 DP_INFO(p_hwfn,
3115                         "Failed to receive allocation info for resource %d [%s]."
3116                         " mcp_resp = 0x%x. Applying default values"
3117                         " [%d,%d].\n",
3118                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3119                         dflt_resc_num, dflt_resc_start);
3120
3121                 *p_resc_num = dflt_resc_num;
3122                 *p_resc_start = dflt_resc_start;
3123                 goto out;
3124         }
3125
3126         if ((*p_resc_num != dflt_resc_num ||
3127              *p_resc_start != dflt_resc_start) &&
3128             res_id != ECORE_SB) {
3129                 DP_INFO(p_hwfn,
3130                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3131                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3132                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3133                         drv_resc_alloc ? " - Applying default values" : "");
3134                 if (drv_resc_alloc) {
3135                         *p_resc_num = dflt_resc_num;
3136                         *p_resc_start = dflt_resc_start;
3137                 }
3138         }
3139 out:
3140         return ECORE_SUCCESS;
3141 }
3142
3143 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3144                                                    bool drv_resc_alloc)
3145 {
3146         enum _ecore_status_t rc;
3147         u8 res_id;
3148
3149         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3150                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3151                 if (rc != ECORE_SUCCESS)
3152                         return rc;
3153         }
3154
3155         return ECORE_SUCCESS;
3156 }
3157
3158 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3159                                               struct ecore_ptt *p_ptt,
3160                                               bool drv_resc_alloc)
3161 {
3162         struct ecore_resc_unlock_params resc_unlock_params;
3163         struct ecore_resc_lock_params resc_lock_params;
3164         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3165         u8 res_id;
3166         enum _ecore_status_t rc;
3167 #ifndef ASIC_ONLY
3168         u32 *resc_start = p_hwfn->hw_info.resc_start;
3169         u32 *resc_num = p_hwfn->hw_info.resc_num;
3170         /* For AH, an equal share of the ILT lines between the maximal number of
3171          * PFs is not enough for RoCE. This would be solved by the future
3172          * resource allocation scheme, but isn't currently present for
3173          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3174          * to work - the BB number of ILT lines divided by its max PFs number.
3175          */
3176         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3177 #endif
3178
3179         /* Setting the max values of the soft resources and the following
3180          * resources allocation queries should be atomic. Since several PFs can
3181          * run in parallel - a resource lock is needed.
3182          * If either the resource lock or resource set value commands are not
3183          * supported - skip the the max values setting, release the lock if
3184          * needed, and proceed to the queries. Other failures, including a
3185          * failure to acquire the lock, will cause this function to fail.
3186          * Old drivers that don't acquire the lock can run in parallel, and
3187          * their allocation values won't be affected by the updated max values.
3188          */
3189         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3190                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3191
3192         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3193         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3194                 return rc;
3195         } else if (rc == ECORE_NOTIMPL) {
3196                 DP_INFO(p_hwfn,
3197                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3198         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3199                 DP_NOTICE(p_hwfn, false,
3200                           "Failed to acquire the resource lock for the resource allocation commands\n");
3201                 rc = ECORE_BUSY;
3202                 goto unlock_and_exit;
3203         } else {
3204                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3205                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3206                         DP_NOTICE(p_hwfn, false,
3207                                   "Failed to set the max values of the soft resources\n");
3208                         goto unlock_and_exit;
3209                 } else if (rc == ECORE_NOTIMPL) {
3210                         DP_INFO(p_hwfn,
3211                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3212                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3213                                                    &resc_unlock_params);
3214                         if (rc != ECORE_SUCCESS)
3215                                 DP_INFO(p_hwfn,
3216                                         "Failed to release the resource lock for the resource allocation commands\n");
3217                 }
3218         }
3219
3220         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3221         if (rc != ECORE_SUCCESS)
3222                 goto unlock_and_exit;
3223
3224         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3225                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3226                                            &resc_unlock_params);
3227                 if (rc != ECORE_SUCCESS)
3228                         DP_INFO(p_hwfn,
3229                                 "Failed to release the resource lock for the resource allocation commands\n");
3230         }
3231
3232 #ifndef ASIC_ONLY
3233         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3234                 /* Reduced build contains less PQs */
3235                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3236                         resc_num[ECORE_PQ] = 32;
3237                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3238                             p_hwfn->enabled_func_idx;
3239                 }
3240
3241                 /* For AH emulation, since we have a possible maximal number of
3242                  * 16 enabled PFs, in case there are not enough ILT lines -
3243                  * allocate only first PF as RoCE and have all the other ETH
3244                  * only with less ILT lines.
3245                  */
3246                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3247                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3248                                                          resc_num[ECORE_ILT],
3249                                                          roce_min_ilt_lines);
3250         }
3251
3252         /* Correct the common ILT calculation if PF0 has more */
3253         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3254             p_hwfn->p_dev->b_is_emul_full &&
3255             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3256                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3257                     resc_num[ECORE_ILT];
3258 #endif
3259
3260         /* Sanity for ILT */
3261         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3262             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3263                 DP_NOTICE(p_hwfn, true,
3264                           "Can't assign ILT pages [%08x,...,%08x]\n",
3265                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3266                                                                   ECORE_ILT) -
3267                           1);
3268                 return ECORE_INVAL;
3269         }
3270
3271         /* This will also learn the number of SBs from MFW */
3272         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3273                 return ECORE_INVAL;
3274
3275         ecore_hw_set_feat(p_hwfn);
3276
3277         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3278                    "The numbers for each resource are:\n");
3279         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3280                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3281                            ecore_hw_get_resc_name(res_id),
3282                            RESC_NUM(p_hwfn, res_id),
3283                            RESC_START(p_hwfn, res_id));
3284
3285         return ECORE_SUCCESS;
3286
3287 unlock_and_exit:
3288         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3289                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3290                                       &resc_unlock_params);
3291         return rc;
3292 }
3293
3294 static enum _ecore_status_t
3295 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3296                       struct ecore_ptt *p_ptt,
3297                       struct ecore_hw_prepare_params *p_params)
3298 {
3299         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3300         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3301         struct ecore_mcp_link_capabilities *p_caps;
3302         struct ecore_mcp_link_params *link;
3303         enum _ecore_status_t rc;
3304
3305         /* Read global nvm_cfg address */
3306         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3307
3308         /* Verify MCP has initialized it */
3309         if (!nvm_cfg_addr) {
3310                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3311                 if (p_params->b_relaxed_probe)
3312                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3313                 return ECORE_INVAL;
3314         }
3315
3316 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3317
3318         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3319
3320         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3321             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
3322                                                        core_cfg);
3323
3324         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3325
3326         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3327                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3328         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3329                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3330                 break;
3331         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3332                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3333                 break;
3334         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3335                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3336                 break;
3337         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3338                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3339                 break;
3340         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3341                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3342                 break;
3343         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3344                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3345                 break;
3346         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3347                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3348                 break;
3349         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3350                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3351                 break;
3352         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3353                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3354                 break;
3355         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3356                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3357                 break;
3358         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3359                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3360                 break;
3361         default:
3362                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3363                           core_cfg);
3364                 break;
3365         }
3366
3367         /* Read DCBX configuration */
3368         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3369                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3370         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3371                              port_cfg_addr +
3372                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3373         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3374                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3375         switch (dcbx_mode) {
3376         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3377                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3378                 break;
3379         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3380                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3381                 break;
3382         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3383                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3384                 break;
3385         default:
3386                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3387         }
3388
3389         /* Read default link configuration */
3390         link = &p_hwfn->mcp_info->link_input;
3391         p_caps = &p_hwfn->mcp_info->link_capabilities;
3392         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3393             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3394         link_temp = ecore_rd(p_hwfn, p_ptt,
3395                              port_cfg_addr +
3396                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3397         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3398         link->speed.advertised_speeds = link_temp;
3399         p_caps->speed_capabilities = link->speed.advertised_speeds;
3400
3401         link_temp = ecore_rd(p_hwfn, p_ptt,
3402                              port_cfg_addr +
3403                              OFFSETOF(struct nvm_cfg1_port, link_settings));
3404         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3405                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3406         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3407                 link->speed.autoneg = true;
3408                 break;
3409         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3410                 link->speed.forced_speed = 1000;
3411                 break;
3412         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3413                 link->speed.forced_speed = 10000;
3414                 break;
3415         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3416                 link->speed.forced_speed = 25000;
3417                 break;
3418         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3419                 link->speed.forced_speed = 40000;
3420                 break;
3421         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3422                 link->speed.forced_speed = 50000;
3423                 break;
3424         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3425                 link->speed.forced_speed = 100000;
3426                 break;
3427         default:
3428                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3429         }
3430
3431         p_caps->default_speed = link->speed.forced_speed;
3432         p_caps->default_speed_autoneg = link->speed.autoneg;
3433
3434         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3435         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3436         link->pause.autoneg = !!(link_temp &
3437                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3438         link->pause.forced_rx = !!(link_temp &
3439                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3440         link->pause.forced_tx = !!(link_temp &
3441                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3442         link->loopback_mode = 0;
3443
3444         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3445                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3446                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3447                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3448                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3449                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3450                 link->eee.enable = true;
3451                 switch (link_temp) {
3452                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3453                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3454                         link->eee.enable = false;
3455                         break;
3456                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3457                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3458                         break;
3459                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3460                         p_caps->eee_lpi_timer =
3461                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3462                         break;
3463                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3464                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3465                         break;
3466                 }
3467
3468                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3469                 link->eee.tx_lpi_enable = link->eee.enable;
3470                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3471         } else {
3472                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3473         }
3474
3475         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3476                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3477                    link->speed.forced_speed, link->speed.advertised_speeds,
3478                    link->speed.autoneg, link->pause.autoneg,
3479                    p_caps->default_eee, p_caps->eee_lpi_timer);
3480
3481         /* Read Multi-function information from shmem */
3482         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3483             OFFSETOF(struct nvm_cfg1, glob) +
3484             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3485
3486         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3487
3488         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3489             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3490
3491         switch (mf_mode) {
3492         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3493                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3494                 break;
3495         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3496                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3497                 break;
3498         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3499                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3500                 break;
3501         }
3502         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3503                 p_hwfn->p_dev->mf_mode);
3504
3505         /* Read Multi-function information from shmem */
3506         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3507             OFFSETOF(struct nvm_cfg1, glob) +
3508             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3509
3510         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3511         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3512                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3513                              &p_hwfn->hw_info.device_capabilities);
3514         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3515                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3516                              &p_hwfn->hw_info.device_capabilities);
3517         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3518                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3519                              &p_hwfn->hw_info.device_capabilities);
3520         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3521                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3522                              &p_hwfn->hw_info.device_capabilities);
3523         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3524                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3525                              &p_hwfn->hw_info.device_capabilities);
3526
3527         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3528         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3529                 rc = ECORE_SUCCESS;
3530                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3531         }
3532
3533         return rc;
3534 }
3535
3536 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3537                                 struct ecore_ptt *p_ptt)
3538 {
3539         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3540         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3541         struct ecore_dev *p_dev = p_hwfn->p_dev;
3542
3543         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3544
3545         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3546          * in the other bits are selected.
3547          * Bits 1-15 are for functions 1-15, respectively, and their value is
3548          * '0' only for enabled functions (function 0 always exists and
3549          * enabled).
3550          * In case of CMT in BB, only the "even" functions are enabled, and thus
3551          * the number of functions for both hwfns is learnt from the same bits.
3552          */
3553         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3554                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3555                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3556         } else { /* E5 */
3557                 reg_function_hide = 0;
3558         }
3559
3560         if (reg_function_hide & 0x1) {
3561                 if (ECORE_IS_BB(p_dev)) {
3562                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3563                                 num_funcs = 0;
3564                                 eng_mask = 0xaaaa;
3565                         } else {
3566                                 num_funcs = 1;
3567                                 eng_mask = 0x5554;
3568                         }
3569                 } else {
3570                         num_funcs = 1;
3571                         eng_mask = 0xfffe;
3572                 }
3573
3574                 /* Get the number of the enabled functions on the engine */
3575                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3576                 while (tmp) {
3577                         if (tmp & 0x1)
3578                                 num_funcs++;
3579                         tmp >>= 0x1;
3580                 }
3581
3582                 /* Get the PF index within the enabled functions */
3583                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3584                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3585                 while (tmp) {
3586                         if (tmp & 0x1)
3587                                 enabled_func_idx--;
3588                         tmp >>= 0x1;
3589                 }
3590         }
3591
3592         p_hwfn->num_funcs_on_engine = num_funcs;
3593         p_hwfn->enabled_func_idx = enabled_func_idx;
3594
3595 #ifndef ASIC_ONLY
3596         if (CHIP_REV_IS_FPGA(p_dev)) {
3597                 DP_NOTICE(p_hwfn, false,
3598                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3599                 p_hwfn->num_funcs_on_engine = 4;
3600         }
3601 #endif
3602
3603         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3604                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3605                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3606                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3607 }
3608
3609 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3610                                       struct ecore_ptt *p_ptt)
3611 {
3612         struct ecore_dev *p_dev = p_hwfn->p_dev;
3613         u32 port_mode;
3614
3615 #ifndef ASIC_ONLY
3616         /* Read the port mode */
3617         if (CHIP_REV_IS_FPGA(p_dev))
3618                 port_mode = 4;
3619         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3620                 /* In CMT on emulation, assume 1 port */
3621                 port_mode = 1;
3622         else
3623 #endif
3624         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3625
3626         if (port_mode < 3) {
3627                 p_dev->num_ports_in_engine = 1;
3628         } else if (port_mode <= 5) {
3629                 p_dev->num_ports_in_engine = 2;
3630         } else {
3631                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3632                           p_dev->num_ports_in_engine);
3633
3634                 /* Default num_ports_in_engine to something */
3635                 p_dev->num_ports_in_engine = 1;
3636         }
3637 }
3638
3639 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3640                                          struct ecore_ptt *p_ptt)
3641 {
3642         struct ecore_dev *p_dev = p_hwfn->p_dev;
3643         u32 port;
3644         int i;
3645
3646         p_dev->num_ports_in_engine = 0;
3647
3648 #ifndef ASIC_ONLY
3649         if (CHIP_REV_IS_EMUL(p_dev)) {
3650                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3651                 switch ((port & 0xf000) >> 12) {
3652                 case 1:
3653                         p_dev->num_ports_in_engine = 1;
3654                         break;
3655                 case 3:
3656                         p_dev->num_ports_in_engine = 2;
3657                         break;
3658                 case 0xf:
3659                         p_dev->num_ports_in_engine = 4;
3660                         break;
3661                 default:
3662                         DP_NOTICE(p_hwfn, false,
3663                                   "Unknown port mode in ECO_RESERVED %08x\n",
3664                                   port);
3665                 }
3666         } else
3667 #endif
3668                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3669                         port = ecore_rd(p_hwfn, p_ptt,
3670                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3671                                         (i * 4));
3672                         if (port & 1)
3673                                 p_dev->num_ports_in_engine++;
3674                 }
3675
3676         if (!p_dev->num_ports_in_engine) {
3677                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3678
3679                 /* Default num_ports_in_engine to something */
3680                 p_dev->num_ports_in_engine = 1;
3681         }
3682 }
3683
3684 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3685                                    struct ecore_ptt *p_ptt)
3686 {
3687         struct ecore_dev *p_dev = p_hwfn->p_dev;
3688
3689         /* Determine the number of ports per engine */
3690         if (ECORE_IS_BB(p_dev))
3691                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3692         else
3693                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3694
3695         /* Get the total number of ports of the device */
3696         if (ECORE_IS_CMT(p_dev)) {
3697                 /* In CMT there is always only one port */
3698                 p_dev->num_ports = 1;
3699 #ifndef ASIC_ONLY
3700         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3701                 p_dev->num_ports = p_dev->num_ports_in_engine *
3702                                    ecore_device_num_engines(p_dev);
3703 #endif
3704         } else {
3705                 u32 addr, global_offsize, global_addr;
3706
3707                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3708                                             PUBLIC_GLOBAL);
3709                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3710                 global_addr = SECTION_ADDR(global_offsize, 0);
3711                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3712                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3713         }
3714 }
3715
3716 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3717                                    struct ecore_ptt *p_ptt)
3718 {
3719         struct ecore_mcp_link_capabilities *p_caps;
3720         u32 eee_status;
3721
3722         p_caps = &p_hwfn->mcp_info->link_capabilities;
3723         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3724                 return;
3725
3726         p_caps->eee_speed_caps = 0;
3727         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3728                               OFFSETOF(struct public_port, eee_status));
3729         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3730                         EEE_SUPPORTED_SPEED_OFFSET;
3731         if (eee_status & EEE_1G_SUPPORTED)
3732                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3733         if (eee_status & EEE_10G_ADV)
3734                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3735 }
3736
3737 static enum _ecore_status_t
3738 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3739                   enum ecore_pci_personality personality,
3740                   struct ecore_hw_prepare_params *p_params)
3741 {
3742         bool drv_resc_alloc = p_params->drv_resc_alloc;
3743         enum _ecore_status_t rc;
3744
3745         /* Since all information is common, only first hwfns should do this */
3746         if (IS_LEAD_HWFN(p_hwfn)) {
3747                 rc = ecore_iov_hw_info(p_hwfn);
3748                 if (rc != ECORE_SUCCESS) {
3749                         if (p_params->b_relaxed_probe)
3750                                 p_params->p_relaxed_res =
3751                                                 ECORE_HW_PREPARE_BAD_IOV;
3752                         else
3753                                 return rc;
3754                 }
3755         }
3756
3757         if (IS_LEAD_HWFN(p_hwfn))
3758                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3759
3760         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3761
3762 #ifndef ASIC_ONLY
3763         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3764 #endif
3765         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3766         if (rc != ECORE_SUCCESS)
3767                 return rc;
3768 #ifndef ASIC_ONLY
3769         }
3770 #endif
3771
3772         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3773         if (rc != ECORE_SUCCESS) {
3774                 if (p_params->b_relaxed_probe)
3775                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3776                 else
3777                         return rc;
3778         }
3779
3780 #ifndef ASIC_ONLY
3781         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3782 #endif
3783                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3784                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3785 #ifndef ASIC_ONLY
3786         } else {
3787                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3788
3789                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3790                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3791         }
3792 #endif
3793
3794         if (ecore_mcp_is_init(p_hwfn)) {
3795                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3796                         p_hwfn->hw_info.ovlan =
3797                             p_hwfn->mcp_info->func_info.ovlan;
3798
3799                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3800
3801                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3802         }
3803
3804         if (personality != ECORE_PCI_DEFAULT) {
3805                 p_hwfn->hw_info.personality = personality;
3806         } else if (ecore_mcp_is_init(p_hwfn)) {
3807                 enum ecore_pci_personality protocol;
3808
3809                 protocol = p_hwfn->mcp_info->func_info.protocol;
3810                 p_hwfn->hw_info.personality = protocol;
3811         }
3812
3813 #ifndef ASIC_ONLY
3814         /* To overcome ILT lack for emulation, until at least until we'll have
3815          * a definite answer from system about it, allow only PF0 to be RoCE.
3816          */
3817         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3818                 if (!p_hwfn->rel_pf_id)
3819                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3820                 else
3821                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3822         }
3823 #endif
3824
3825         /* although in BB some constellations may support more than 4 tcs,
3826          * that can result in performance penalty in some cases. 4
3827          * represents a good tradeoff between performance and flexibility.
3828          */
3829         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3830
3831         /* start out with a single active tc. This can be increased either
3832          * by dcbx negotiation or by upper layer driver
3833          */
3834         p_hwfn->hw_info.num_active_tc = 1;
3835
3836         ecore_get_num_funcs(p_hwfn, p_ptt);
3837
3838         if (ecore_mcp_is_init(p_hwfn))
3839                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3840
3841         /* In case of forcing the driver's default resource allocation, calling
3842          * ecore_hw_get_resc() should come after initializing the personality
3843          * and after getting the number of functions, since the calculation of
3844          * the resources/features depends on them.
3845          * This order is not harmful if not forcing.
3846          */
3847         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3848         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3849                 rc = ECORE_SUCCESS;
3850                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3851         }
3852
3853         return rc;
3854 }
3855
3856 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3857                                                struct ecore_ptt *p_ptt)
3858 {
3859         struct ecore_dev *p_dev = p_hwfn->p_dev;
3860         u16 device_id_mask;
3861         u32 tmp;
3862
3863         /* Read Vendor Id / Device Id */
3864         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3865                                   &p_dev->vendor_id);
3866         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3867                                   &p_dev->device_id);
3868
3869         /* Determine type */
3870         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3871         switch (device_id_mask) {
3872         case ECORE_DEV_ID_MASK_BB:
3873                 p_dev->type = ECORE_DEV_TYPE_BB;
3874                 break;
3875         case ECORE_DEV_ID_MASK_AH:
3876                 p_dev->type = ECORE_DEV_TYPE_AH;
3877                 break;
3878         default:
3879                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3880                           p_dev->device_id);
3881                 return ECORE_ABORTED;
3882         }
3883
3884         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3885         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3886         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3887         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3888
3889         /* Learn number of HW-functions */
3890         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3891
3892         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3893                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3894                 p_dev->num_hwfns = 2;
3895         } else {
3896                 p_dev->num_hwfns = 1;
3897         }
3898
3899 #ifndef ASIC_ONLY
3900         if (CHIP_REV_IS_EMUL(p_dev)) {
3901                 /* For some reason we have problems with this register
3902                  * in B0 emulation; Simply assume no CMT
3903                  */
3904                 DP_NOTICE(p_dev->hwfns, false,
3905                           "device on emul - assume no CMT\n");
3906                 p_dev->num_hwfns = 1;
3907         }
3908 #endif
3909
3910         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3911         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3912         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3913         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3914
3915         DP_INFO(p_dev->hwfns,
3916                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3917                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3918                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3919                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3920                 p_dev->chip_metal);
3921
3922         if (ECORE_IS_BB_A0(p_dev)) {
3923                 DP_NOTICE(p_dev->hwfns, false,
3924                           "The chip type/rev (BB A0) is not supported!\n");
3925                 return ECORE_ABORTED;
3926         }
3927 #ifndef ASIC_ONLY
3928         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3929                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3930
3931         if (CHIP_REV_IS_EMUL(p_dev)) {
3932                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3933                 if (tmp & (1 << 29)) {
3934                         DP_NOTICE(p_hwfn, false,
3935                                   "Emulation: Running on a FULL build\n");
3936                         p_dev->b_is_emul_full = true;
3937                 } else {
3938                         DP_NOTICE(p_hwfn, false,
3939                                   "Emulation: Running on a REDUCED build\n");
3940                 }
3941         }
3942 #endif
3943
3944         return ECORE_SUCCESS;
3945 }
3946
3947 #ifndef LINUX_REMOVE
3948 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3949 {
3950         int j;
3951
3952         if (IS_VF(p_dev))
3953                 return;
3954
3955         for_each_hwfn(p_dev, j) {
3956                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3957
3958                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3959                            "Mark hw/fw uninitialized\n");
3960
3961                 p_hwfn->hw_init_done = false;
3962                 p_hwfn->first_on_engine = false;
3963
3964                 ecore_ptt_invalidate(p_hwfn);
3965         }
3966 }
3967 #endif
3968
3969 static enum _ecore_status_t
3970 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3971                         void OSAL_IOMEM * p_regview,
3972                         void OSAL_IOMEM * p_doorbells,
3973                         struct ecore_hw_prepare_params *p_params)
3974 {
3975         struct ecore_mdump_retain_data mdump_retain;
3976         struct ecore_dev *p_dev = p_hwfn->p_dev;
3977         struct ecore_mdump_info mdump_info;
3978         enum _ecore_status_t rc = ECORE_SUCCESS;
3979
3980         /* Split PCI bars evenly between hwfns */
3981         p_hwfn->regview = p_regview;
3982         p_hwfn->doorbells = p_doorbells;
3983
3984         if (IS_VF(p_dev))
3985                 return ecore_vf_hw_prepare(p_hwfn);
3986
3987         /* Validate that chip access is feasible */
3988         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3989                 DP_ERR(p_hwfn,
3990                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3991                 if (p_params->b_relaxed_probe)
3992                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3993                 return ECORE_INVAL;
3994         }
3995
3996         get_function_id(p_hwfn);
3997
3998         /* Allocate PTT pool */
3999         rc = ecore_ptt_pool_alloc(p_hwfn);
4000         if (rc) {
4001                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4002                 if (p_params->b_relaxed_probe)
4003                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4004                 goto err0;
4005         }
4006
4007         /* Allocate the main PTT */
4008         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4009
4010         /* First hwfn learns basic information, e.g., number of hwfns */
4011         if (!p_hwfn->my_id) {
4012                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4013                 if (rc != ECORE_SUCCESS) {
4014                         if (p_params->b_relaxed_probe)
4015                                 p_params->p_relaxed_res =
4016                                         ECORE_HW_PREPARE_FAILED_DEV;
4017                         goto err1;
4018                 }
4019         }
4020
4021         ecore_hw_hwfn_prepare(p_hwfn);
4022
4023         /* Initialize MCP structure */
4024         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4025         if (rc) {
4026                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4027                 if (p_params->b_relaxed_probe)
4028                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4029                 goto err1;
4030         }
4031
4032         /* Read the device configuration information from the HW and SHMEM */
4033         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4034                                p_params->personality, p_params);
4035         if (rc) {
4036                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4037                 goto err2;
4038         }
4039
4040         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4041          * called, since among others it sets the ports number in an engine.
4042          */
4043         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4044             !p_dev->recov_in_prog) {
4045                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4046                 if (rc != ECORE_SUCCESS)
4047                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4048         }
4049
4050         /* Check if mdump logs/data are present and update the epoch value */
4051         if (IS_LEAD_HWFN(p_hwfn)) {
4052 #ifndef ASIC_ONLY
4053                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4054 #endif
4055                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4056                                               &mdump_info);
4057                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4058                         DP_NOTICE(p_hwfn, false,
4059                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4060
4061                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4062                                                 &mdump_retain);
4063                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4064                         DP_NOTICE(p_hwfn, false,
4065                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4066                                   mdump_retain.epoch, mdump_retain.pf,
4067                                   mdump_retain.status);
4068
4069                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4070                                            p_params->epoch);
4071 #ifndef ASIC_ONLY
4072                 }
4073 #endif
4074         }
4075
4076         /* Allocate the init RT array and initialize the init-ops engine */
4077         rc = ecore_init_alloc(p_hwfn);
4078         if (rc) {
4079                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4080                 if (p_params->b_relaxed_probe)
4081                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4082                 goto err2;
4083         }
4084 #ifndef ASIC_ONLY
4085         if (CHIP_REV_IS_FPGA(p_dev)) {
4086                 DP_NOTICE(p_hwfn, false,
4087                           "FPGA: workaround; Prevent DMAE parities\n");
4088                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4089                          7);
4090
4091                 DP_NOTICE(p_hwfn, false,
4092                           "FPGA: workaround: Set VF bar0 size\n");
4093                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4094                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4095         }
4096 #endif
4097
4098         return rc;
4099 err2:
4100         if (IS_LEAD_HWFN(p_hwfn))
4101                 ecore_iov_free_hw_info(p_dev);
4102         ecore_mcp_free(p_hwfn);
4103 err1:
4104         ecore_hw_hwfn_free(p_hwfn);
4105 err0:
4106         return rc;
4107 }
4108
4109 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4110                                       struct ecore_hw_prepare_params *p_params)
4111 {
4112         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4113         enum _ecore_status_t rc;
4114
4115         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4116         p_dev->allow_mdump = p_params->allow_mdump;
4117
4118         if (p_params->b_relaxed_probe)
4119                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4120
4121         /* Store the precompiled init data ptrs */
4122         if (IS_PF(p_dev))
4123                 ecore_init_iro_array(p_dev);
4124
4125         /* Initialize the first hwfn - will learn number of hwfns */
4126         rc = ecore_hw_prepare_single(p_hwfn,
4127                                      p_dev->regview,
4128                                      p_dev->doorbells, p_params);
4129         if (rc != ECORE_SUCCESS)
4130                 return rc;
4131
4132         p_params->personality = p_hwfn->hw_info.personality;
4133
4134         /* initilalize 2nd hwfn if necessary */
4135         if (ECORE_IS_CMT(p_dev)) {
4136                 void OSAL_IOMEM *p_regview, *p_doorbell;
4137                 u8 OSAL_IOMEM *addr;
4138
4139                 /* adjust bar offset for second engine */
4140                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4141                                         ecore_hw_bar_size(p_hwfn,
4142                                                           p_hwfn->p_main_ptt,
4143                                                           BAR_ID_0) / 2;
4144                 p_regview = (void OSAL_IOMEM *)addr;
4145
4146                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4147                                         ecore_hw_bar_size(p_hwfn,
4148                                                           p_hwfn->p_main_ptt,
4149                                                           BAR_ID_1) / 2;
4150                 p_doorbell = (void OSAL_IOMEM *)addr;
4151
4152                 /* prepare second hw function */
4153                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4154                                              p_doorbell, p_params);
4155
4156                 /* in case of error, need to free the previously
4157                  * initiliazed hwfn 0.
4158                  */
4159                 if (rc != ECORE_SUCCESS) {
4160                         if (p_params->b_relaxed_probe)
4161                                 p_params->p_relaxed_res =
4162                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4163
4164                         if (IS_PF(p_dev)) {
4165                                 ecore_init_free(p_hwfn);
4166                                 ecore_mcp_free(p_hwfn);
4167                                 ecore_hw_hwfn_free(p_hwfn);
4168                         } else {
4169                                 DP_NOTICE(p_dev, true,
4170                                           "What do we need to free when VF hwfn1 init fails\n");
4171                         }
4172                         return rc;
4173                 }
4174         }
4175
4176         return rc;
4177 }
4178
4179 void ecore_hw_remove(struct ecore_dev *p_dev)
4180 {
4181         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4182         int i;
4183
4184         if (IS_PF(p_dev))
4185                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4186                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4187
4188         for_each_hwfn(p_dev, i) {
4189                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4190
4191                 if (IS_VF(p_dev)) {
4192                         ecore_vf_pf_release(p_hwfn);
4193                         continue;
4194                 }
4195
4196                 ecore_init_free(p_hwfn);
4197                 ecore_hw_hwfn_free(p_hwfn);
4198                 ecore_mcp_free(p_hwfn);
4199
4200 #ifdef CONFIG_ECORE_LOCK_ALLOC
4201                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4202 #endif
4203         }
4204
4205         ecore_iov_free_hw_info(p_dev);
4206 }
4207
4208 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4209                                       struct ecore_chain *p_chain)
4210 {
4211         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4212         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4213         struct ecore_chain_next *p_next;
4214         u32 size, i;
4215
4216         if (!p_virt)
4217                 return;
4218
4219         size = p_chain->elem_size * p_chain->usable_per_page;
4220
4221         for (i = 0; i < p_chain->page_cnt; i++) {
4222                 if (!p_virt)
4223                         break;
4224
4225                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4226                 p_virt_next = p_next->next_virt;
4227                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4228
4229                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4230                                        ECORE_CHAIN_PAGE_SIZE);
4231
4232                 p_virt = p_virt_next;
4233                 p_phys = p_phys_next;
4234         }
4235 }
4236
4237 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4238                                     struct ecore_chain *p_chain)
4239 {
4240         if (!p_chain->p_virt_addr)
4241                 return;
4242
4243         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4244                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4245 }
4246
4247 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4248                                  struct ecore_chain *p_chain)
4249 {
4250         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4251         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4252         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4253
4254         if (!pp_virt_addr_tbl)
4255                 return;
4256
4257         if (!p_pbl_virt)
4258                 goto out;
4259
4260         for (i = 0; i < page_cnt; i++) {
4261                 if (!pp_virt_addr_tbl[i])
4262                         break;
4263
4264                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4265                                        *(dma_addr_t *)p_pbl_virt,
4266                                        ECORE_CHAIN_PAGE_SIZE);
4267
4268                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4269         }
4270
4271         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4272
4273         if (!p_chain->b_external_pbl)
4274                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4275                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4276 out:
4277         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4278 }
4279
4280 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4281 {
4282         switch (p_chain->mode) {
4283         case ECORE_CHAIN_MODE_NEXT_PTR:
4284                 ecore_chain_free_next_ptr(p_dev, p_chain);
4285                 break;
4286         case ECORE_CHAIN_MODE_SINGLE:
4287                 ecore_chain_free_single(p_dev, p_chain);
4288                 break;
4289         case ECORE_CHAIN_MODE_PBL:
4290                 ecore_chain_free_pbl(p_dev, p_chain);
4291                 break;
4292         }
4293 }
4294
4295 static enum _ecore_status_t
4296 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4297                                enum ecore_chain_cnt_type cnt_type,
4298                                osal_size_t elem_size, u32 page_cnt)
4299 {
4300         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4301
4302         /* The actual chain size can be larger than the maximal possible value
4303          * after rounding up the requested elements number to pages, and after
4304          * taking into acount the unusuable elements (next-ptr elements).
4305          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4306          * size/capacity fields are of a u32 type.
4307          */
4308         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4309              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4310             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4311              chain_size > ECORE_U32_MAX)) {
4312                 DP_NOTICE(p_dev, true,
4313                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4314                           (unsigned long)chain_size);
4315                 return ECORE_INVAL;
4316         }
4317
4318         return ECORE_SUCCESS;
4319 }
4320
4321 static enum _ecore_status_t
4322 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4323 {
4324         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4325         dma_addr_t p_phys = 0;
4326         u32 i;
4327
4328         for (i = 0; i < p_chain->page_cnt; i++) {
4329                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4330                                                  ECORE_CHAIN_PAGE_SIZE);
4331                 if (!p_virt) {
4332                         DP_NOTICE(p_dev, true,
4333                                   "Failed to allocate chain memory\n");
4334                         return ECORE_NOMEM;
4335                 }
4336
4337                 if (i == 0) {
4338                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4339                         ecore_chain_reset(p_chain);
4340                 } else {
4341                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4342                                                        p_virt, p_phys);
4343                 }
4344
4345                 p_virt_prev = p_virt;
4346         }
4347         /* Last page's next element should point to the beginning of the
4348          * chain.
4349          */
4350         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4351                                        p_chain->p_virt_addr,
4352                                        p_chain->p_phys_addr);
4353
4354         return ECORE_SUCCESS;
4355 }
4356
4357 static enum _ecore_status_t
4358 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4359 {
4360         dma_addr_t p_phys = 0;
4361         void *p_virt = OSAL_NULL;
4362
4363         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4364         if (!p_virt) {
4365                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4366                 return ECORE_NOMEM;
4367         }
4368
4369         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4370         ecore_chain_reset(p_chain);
4371
4372         return ECORE_SUCCESS;
4373 }
4374
4375 static enum _ecore_status_t
4376 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4377                       struct ecore_chain *p_chain,
4378                       struct ecore_chain_ext_pbl *ext_pbl)
4379 {
4380         void *p_virt = OSAL_NULL;
4381         u8 *p_pbl_virt = OSAL_NULL;
4382         void **pp_virt_addr_tbl = OSAL_NULL;
4383         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4384         u32 page_cnt = p_chain->page_cnt, size, i;
4385
4386         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4387         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4388         if (!pp_virt_addr_tbl) {
4389                 DP_NOTICE(p_dev, true,
4390                           "Failed to allocate memory for the chain virtual addresses table\n");
4391                 return ECORE_NOMEM;
4392         }
4393
4394         /* The allocation of the PBL table is done with its full size, since it
4395          * is expected to be successive.
4396          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4397          * failure, since pp_virt_addr_tbl was previously allocated, and it
4398          * should be saved to allow its freeing during the error flow.
4399          */
4400         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4401
4402         if (ext_pbl == OSAL_NULL) {
4403                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4404         } else {
4405                 p_pbl_virt = ext_pbl->p_pbl_virt;
4406                 p_pbl_phys = ext_pbl->p_pbl_phys;
4407                 p_chain->b_external_pbl = true;
4408         }
4409
4410         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4411                                  pp_virt_addr_tbl);
4412         if (!p_pbl_virt) {
4413                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4414                 return ECORE_NOMEM;
4415         }
4416
4417         for (i = 0; i < page_cnt; i++) {
4418                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4419                                                  ECORE_CHAIN_PAGE_SIZE);
4420                 if (!p_virt) {
4421                         DP_NOTICE(p_dev, true,
4422                                   "Failed to allocate chain memory\n");
4423                         return ECORE_NOMEM;
4424                 }
4425
4426                 if (i == 0) {
4427                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4428                         ecore_chain_reset(p_chain);
4429                 }
4430
4431                 /* Fill the PBL table with the physical address of the page */
4432                 *(dma_addr_t *)p_pbl_virt = p_phys;
4433                 /* Keep the virtual address of the page */
4434                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4435
4436                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4437         }
4438
4439         return ECORE_SUCCESS;
4440 }
4441
4442 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4443                                        enum ecore_chain_use_mode intended_use,
4444                                        enum ecore_chain_mode mode,
4445                                        enum ecore_chain_cnt_type cnt_type,
4446                                        u32 num_elems, osal_size_t elem_size,
4447                                        struct ecore_chain *p_chain,
4448                                        struct ecore_chain_ext_pbl *ext_pbl)
4449 {
4450         u32 page_cnt;
4451         enum _ecore_status_t rc = ECORE_SUCCESS;
4452
4453         if (mode == ECORE_CHAIN_MODE_SINGLE)
4454                 page_cnt = 1;
4455         else
4456                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4457
4458         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4459                                             page_cnt);
4460         if (rc) {
4461                 DP_NOTICE(p_dev, true,
4462                           "Cannot allocate a chain with the given arguments:\n"
4463                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4464                           intended_use, mode, cnt_type, num_elems, elem_size);
4465                 return rc;
4466         }
4467
4468         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4469                                 mode, cnt_type, p_dev->dp_ctx);
4470
4471         switch (mode) {
4472         case ECORE_CHAIN_MODE_NEXT_PTR:
4473                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4474                 break;
4475         case ECORE_CHAIN_MODE_SINGLE:
4476                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4477                 break;
4478         case ECORE_CHAIN_MODE_PBL:
4479                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4480                 break;
4481         }
4482         if (rc)
4483                 goto nomem;
4484
4485         return ECORE_SUCCESS;
4486
4487 nomem:
4488         ecore_chain_free(p_dev, p_chain);
4489         return rc;
4490 }
4491
4492 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4493                                        u16 src_id, u16 *dst_id)
4494 {
4495         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4496                 u16 min, max;
4497
4498                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4499                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4500                 DP_NOTICE(p_hwfn, true,
4501                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4502                           src_id, min, max);
4503
4504                 return ECORE_INVAL;
4505         }
4506
4507         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4508
4509         return ECORE_SUCCESS;
4510 }
4511
4512 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4513                                     u8 src_id, u8 *dst_id)
4514 {
4515         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4516                 u8 min, max;
4517
4518                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4519                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4520                 DP_NOTICE(p_hwfn, true,
4521                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4522                           src_id, min, max);
4523
4524                 return ECORE_INVAL;
4525         }
4526
4527         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4528
4529         return ECORE_SUCCESS;
4530 }
4531
4532 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4533                                       u8 src_id, u8 *dst_id)
4534 {
4535         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4536                 u8 min, max;
4537
4538                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4539                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4540                 DP_NOTICE(p_hwfn, true,
4541                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4542                           src_id, min, max);
4543
4544                 return ECORE_INVAL;
4545         }
4546
4547         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4548
4549         return ECORE_SUCCESS;
4550 }
4551
4552 static enum _ecore_status_t
4553 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4554                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4555                                u32 *p_entry_num)
4556 {
4557         u32 en;
4558         int i;
4559
4560         /* Find a free entry and utilize it */
4561         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4562                 en = ecore_rd(p_hwfn, p_ptt,
4563                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4564                               i * sizeof(u32));
4565                 if (en)
4566                         continue;
4567                 ecore_wr(p_hwfn, p_ptt,
4568                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4569                          2 * i * sizeof(u32), low);
4570                 ecore_wr(p_hwfn, p_ptt,
4571                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4572                          (2 * i + 1) * sizeof(u32), high);
4573                 ecore_wr(p_hwfn, p_ptt,
4574                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4575                          i * sizeof(u32), 0);
4576                 ecore_wr(p_hwfn, p_ptt,
4577                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4578                          i * sizeof(u32), 0);
4579                 ecore_wr(p_hwfn, p_ptt,
4580                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4581                          i * sizeof(u32), 1);
4582                 break;
4583         }
4584
4585         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4586                 return ECORE_NORESOURCES;
4587
4588         *p_entry_num = i;
4589
4590         return ECORE_SUCCESS;
4591 }
4592
4593 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4594                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4595 {
4596         u32 high, low, entry_num;
4597         enum _ecore_status_t rc;
4598
4599         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4600                 return ECORE_SUCCESS;
4601
4602         high = p_filter[1] | (p_filter[0] << 8);
4603         low = p_filter[5] | (p_filter[4] << 8) |
4604               (p_filter[3] << 16) | (p_filter[2] << 24);
4605
4606         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4607                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4608                                                     &entry_num);
4609         if (rc != ECORE_SUCCESS) {
4610                 DP_NOTICE(p_hwfn, false,
4611                           "Failed to find an empty LLH filter to utilize\n");
4612                 return rc;
4613         }
4614
4615         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4616                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4617                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4618                    p_filter[4], p_filter[5], entry_num);
4619
4620         return ECORE_SUCCESS;
4621 }
4622
4623 static enum _ecore_status_t
4624 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4625                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4626                                   u32 *p_entry_num)
4627 {
4628         int i;
4629
4630         /* Find the entry and clean it */
4631         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4632                 if (ecore_rd(p_hwfn, p_ptt,
4633                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4634                              2 * i * sizeof(u32)) != low)
4635                         continue;
4636                 if (ecore_rd(p_hwfn, p_ptt,
4637                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4638                              (2 * i + 1) * sizeof(u32)) != high)
4639                         continue;
4640
4641                 ecore_wr(p_hwfn, p_ptt,
4642                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4643                 ecore_wr(p_hwfn, p_ptt,
4644                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4645                          2 * i * sizeof(u32), 0);
4646                 ecore_wr(p_hwfn, p_ptt,
4647                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4648                          (2 * i + 1) * sizeof(u32), 0);
4649                 break;
4650         }
4651
4652         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4653                 return ECORE_INVAL;
4654
4655         *p_entry_num = i;
4656
4657         return ECORE_SUCCESS;
4658 }
4659
4660 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4661                              struct ecore_ptt *p_ptt, u8 *p_filter)
4662 {
4663         u32 high, low, entry_num;
4664         enum _ecore_status_t rc;
4665
4666         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4667                 return;
4668
4669         high = p_filter[1] | (p_filter[0] << 8);
4670         low = p_filter[5] | (p_filter[4] << 8) |
4671               (p_filter[3] << 16) | (p_filter[2] << 24);
4672
4673         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4674                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4675                                                        low, &entry_num);
4676         if (rc != ECORE_SUCCESS) {
4677                 DP_NOTICE(p_hwfn, false,
4678                           "Tried to remove a non-configured filter\n");
4679                 return;
4680         }
4681
4682
4683         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4684                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4685                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4686                    p_filter[4], p_filter[5], entry_num);
4687 }
4688
4689 static enum _ecore_status_t
4690 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4691                                     struct ecore_ptt *p_ptt,
4692                                     enum ecore_llh_port_filter_type_t type,
4693                                     u32 high, u32 low, u32 *p_entry_num)
4694 {
4695         u32 en;
4696         int i;
4697
4698         /* Find a free entry and utilize it */
4699         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4700                 en = ecore_rd(p_hwfn, p_ptt,
4701                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4702                               i * sizeof(u32));
4703                 if (en)
4704                         continue;
4705                 ecore_wr(p_hwfn, p_ptt,
4706                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4707                          2 * i * sizeof(u32), low);
4708                 ecore_wr(p_hwfn, p_ptt,
4709                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4710                          (2 * i + 1) * sizeof(u32), high);
4711                 ecore_wr(p_hwfn, p_ptt,
4712                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4713                          i * sizeof(u32), 1);
4714                 ecore_wr(p_hwfn, p_ptt,
4715                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4716                          i * sizeof(u32), 1 << type);
4717                 ecore_wr(p_hwfn, p_ptt,
4718                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4719                 break;
4720         }
4721
4722         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4723                 return ECORE_NORESOURCES;
4724
4725         *p_entry_num = i;
4726
4727         return ECORE_SUCCESS;
4728 }
4729
4730 enum _ecore_status_t
4731 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4732                               struct ecore_ptt *p_ptt,
4733                               u16 source_port_or_eth_type,
4734                               u16 dest_port,
4735                               enum ecore_llh_port_filter_type_t type)
4736 {
4737         u32 high, low, entry_num;
4738         enum _ecore_status_t rc;
4739
4740         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4741                 return ECORE_SUCCESS;
4742
4743         high = 0;
4744         low = 0;
4745
4746         switch (type) {
4747         case ECORE_LLH_FILTER_ETHERTYPE:
4748                 high = source_port_or_eth_type;
4749                 break;
4750         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4751         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4752                 low = source_port_or_eth_type << 16;
4753                 break;
4754         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4755         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4756                 low = dest_port;
4757                 break;
4758         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4759         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4760                 low = (source_port_or_eth_type << 16) | dest_port;
4761                 break;
4762         default:
4763                 DP_NOTICE(p_hwfn, true,
4764                           "Non valid LLH protocol filter type %d\n", type);
4765                 return ECORE_INVAL;
4766         }
4767
4768         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4769                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4770                                                          high, low, &entry_num);
4771         if (rc != ECORE_SUCCESS) {
4772                 DP_NOTICE(p_hwfn, false,
4773                           "Failed to find an empty LLH filter to utilize\n");
4774                 return rc;
4775         }
4776         switch (type) {
4777         case ECORE_LLH_FILTER_ETHERTYPE:
4778                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4779                            "ETH type %x is added at %d\n",
4780                            source_port_or_eth_type, entry_num);
4781                 break;
4782         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4783                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4784                            "TCP src port %x is added at %d\n",
4785                            source_port_or_eth_type, entry_num);
4786                 break;
4787         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4788                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4789                            "UDP src port %x is added at %d\n",
4790                            source_port_or_eth_type, entry_num);
4791                 break;
4792         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4793                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4794                            "TCP dst port %x is added at %d\n", dest_port,
4795                            entry_num);
4796                 break;
4797         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4798                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4799                            "UDP dst port %x is added at %d\n", dest_port,
4800                            entry_num);
4801                 break;
4802         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4803                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4804                            "TCP src/dst ports %x/%x are added at %d\n",
4805                            source_port_or_eth_type, dest_port, entry_num);
4806                 break;
4807         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4808                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4809                            "UDP src/dst ports %x/%x are added at %d\n",
4810                            source_port_or_eth_type, dest_port, entry_num);
4811                 break;
4812         }
4813
4814         return ECORE_SUCCESS;
4815 }
4816
4817 static enum _ecore_status_t
4818 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4819                                        struct ecore_ptt *p_ptt,
4820                                        enum ecore_llh_port_filter_type_t type,
4821                                        u32 high, u32 low, u32 *p_entry_num)
4822 {
4823         int i;
4824
4825         /* Find the entry and clean it */
4826         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4827                 if (!ecore_rd(p_hwfn, p_ptt,
4828                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4829                               i * sizeof(u32)))
4830                         continue;
4831                 if (!ecore_rd(p_hwfn, p_ptt,
4832                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4833                               i * sizeof(u32)))
4834                         continue;
4835                 if (!(ecore_rd(p_hwfn, p_ptt,
4836                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4837                                i * sizeof(u32)) & (1 << type)))
4838                         continue;
4839                 if (ecore_rd(p_hwfn, p_ptt,
4840                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4841                              2 * i * sizeof(u32)) != low)
4842                         continue;
4843                 if (ecore_rd(p_hwfn, p_ptt,
4844                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4845                              (2 * i + 1) * sizeof(u32)) != high)
4846                         continue;
4847
4848                 ecore_wr(p_hwfn, p_ptt,
4849                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4850                 ecore_wr(p_hwfn, p_ptt,
4851                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4852                          i * sizeof(u32), 0);
4853                 ecore_wr(p_hwfn, p_ptt,
4854                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4855                          i * sizeof(u32), 0);
4856                 ecore_wr(p_hwfn, p_ptt,
4857                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4858                          2 * i * sizeof(u32), 0);
4859                 ecore_wr(p_hwfn, p_ptt,
4860                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4861                          (2 * i + 1) * sizeof(u32), 0);
4862                 break;
4863         }
4864
4865         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4866                 return ECORE_INVAL;
4867
4868         *p_entry_num = i;
4869
4870         return ECORE_SUCCESS;
4871 }
4872
4873 void
4874 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4875                                  struct ecore_ptt *p_ptt,
4876                                  u16 source_port_or_eth_type,
4877                                  u16 dest_port,
4878                                  enum ecore_llh_port_filter_type_t type)
4879 {
4880         u32 high, low, entry_num;
4881         enum _ecore_status_t rc;
4882
4883         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4884                 return;
4885
4886         high = 0;
4887         low = 0;
4888
4889         switch (type) {
4890         case ECORE_LLH_FILTER_ETHERTYPE:
4891                 high = source_port_or_eth_type;
4892                 break;
4893         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4894         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4895                 low = source_port_or_eth_type << 16;
4896                 break;
4897         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4898         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4899                 low = dest_port;
4900                 break;
4901         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4902         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4903                 low = (source_port_or_eth_type << 16) | dest_port;
4904                 break;
4905         default:
4906                 DP_NOTICE(p_hwfn, true,
4907                           "Non valid LLH protocol filter type %d\n", type);
4908                 return;
4909         }
4910
4911         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4912                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4913                                                             high, low,
4914                                                             &entry_num);
4915         if (rc != ECORE_SUCCESS) {
4916                 DP_NOTICE(p_hwfn, false,
4917                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4918                           type, source_port_or_eth_type, dest_port);
4919                 return;
4920         }
4921
4922         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4923                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4924                    type, source_port_or_eth_type, dest_port, entry_num);
4925 }
4926
4927 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4928                                               struct ecore_ptt *p_ptt)
4929 {
4930         int i;
4931
4932         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4933                 return;
4934
4935         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4936                 ecore_wr(p_hwfn, p_ptt,
4937                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4938                          i * sizeof(u32), 0);
4939                 ecore_wr(p_hwfn, p_ptt,
4940                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4941                          2 * i * sizeof(u32), 0);
4942                 ecore_wr(p_hwfn, p_ptt,
4943                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4944                          (2 * i + 1) * sizeof(u32), 0);
4945         }
4946 }
4947
4948 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4949                              struct ecore_ptt *p_ptt)
4950 {
4951         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4952                 return;
4953
4954         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4955                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4956 }
4957
4958 enum _ecore_status_t
4959 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4960                                   struct ecore_ptt *p_ptt)
4961 {
4962         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4963                 ecore_wr(p_hwfn, p_ptt,
4964                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4965                          1 << p_hwfn->abs_pf_id / 2);
4966                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4967                 return ECORE_SUCCESS;
4968         }
4969
4970         DP_NOTICE(p_hwfn, false,
4971                   "This function can't be set as default\n");
4972         return ECORE_INVAL;
4973 }
4974
4975 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4976                                                struct ecore_ptt *p_ptt,
4977                                                u32 hw_addr, void *p_eth_qzone,
4978                                                osal_size_t eth_qzone_size,
4979                                                u8 timeset)
4980 {
4981         struct coalescing_timeset *p_coal_timeset;
4982
4983         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4984                 DP_NOTICE(p_hwfn, true,
4985                           "Coalescing configuration not enabled\n");
4986                 return ECORE_INVAL;
4987         }
4988
4989         p_coal_timeset = p_eth_qzone;
4990         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4991         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4992         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4993         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4994
4995         return ECORE_SUCCESS;
4996 }
4997
4998 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4999                                               u16 rx_coal, u16 tx_coal,
5000                                               void *p_handle)
5001 {
5002         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5003         enum _ecore_status_t rc = ECORE_SUCCESS;
5004         struct ecore_ptt *p_ptt;
5005
5006         /* TODO - Configuring a single queue's coalescing but
5007          * claiming all queues are abiding same configuration
5008          * for PF and VF both.
5009          */
5010
5011         if (IS_VF(p_hwfn->p_dev))
5012                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5013                                                 tx_coal, p_cid);
5014
5015         p_ptt = ecore_ptt_acquire(p_hwfn);
5016         if (!p_ptt)
5017                 return ECORE_AGAIN;
5018
5019         if (rx_coal) {
5020                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5021                 if (rc)
5022                         goto out;
5023                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5024         }
5025
5026         if (tx_coal) {
5027                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5028                 if (rc)
5029                         goto out;
5030                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5031         }
5032 out:
5033         ecore_ptt_release(p_hwfn, p_ptt);
5034
5035         return rc;
5036 }
5037
5038 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5039                                             struct ecore_ptt *p_ptt,
5040                                             u16 coalesce,
5041                                             struct ecore_queue_cid *p_cid)
5042 {
5043         struct ustorm_eth_queue_zone eth_qzone;
5044         u8 timeset, timer_res;
5045         u32 address;
5046         enum _ecore_status_t rc;
5047
5048         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5049         if (coalesce <= 0x7F) {
5050                 timer_res = 0;
5051         } else if (coalesce <= 0xFF) {
5052                 timer_res = 1;
5053         } else if (coalesce <= 0x1FF) {
5054                 timer_res = 2;
5055         } else {
5056                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5057                 return ECORE_INVAL;
5058         }
5059         timeset = (u8)(coalesce >> timer_res);
5060
5061         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5062                                      p_cid->sb_igu_id, false);
5063         if (rc != ECORE_SUCCESS)
5064                 goto out;
5065
5066         address = BAR0_MAP_REG_USDM_RAM +
5067                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5068
5069         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5070                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5071         if (rc != ECORE_SUCCESS)
5072                 goto out;
5073
5074 out:
5075         return rc;
5076 }
5077
5078 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5079                                             struct ecore_ptt *p_ptt,
5080                                             u16 coalesce,
5081                                             struct ecore_queue_cid *p_cid)
5082 {
5083         struct xstorm_eth_queue_zone eth_qzone;
5084         u8 timeset, timer_res;
5085         u32 address;
5086         enum _ecore_status_t rc;
5087
5088         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5089         if (coalesce <= 0x7F) {
5090                 timer_res = 0;
5091         } else if (coalesce <= 0xFF) {
5092                 timer_res = 1;
5093         } else if (coalesce <= 0x1FF) {
5094                 timer_res = 2;
5095         } else {
5096                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5097                 return ECORE_INVAL;
5098         }
5099
5100         timeset = (u8)(coalesce >> timer_res);
5101
5102         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5103                                      p_cid->sb_igu_id, true);
5104         if (rc != ECORE_SUCCESS)
5105                 goto out;
5106
5107         address = BAR0_MAP_REG_XSDM_RAM +
5108                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5109
5110         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5111                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5112 out:
5113         return rc;
5114 }
5115
5116 /* Calculate final WFQ values for all vports and configure it.
5117  * After this configuration each vport must have
5118  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5119  */
5120 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5121                                                struct ecore_ptt *p_ptt,
5122                                                u32 min_pf_rate)
5123 {
5124         struct init_qm_vport_params *vport_params;
5125         int i;
5126
5127         vport_params = p_hwfn->qm_info.qm_vport_params;
5128
5129         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5130                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5131
5132                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5133                     min_pf_rate;
5134                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5135                                      vport_params[i].first_tx_pq_id,
5136                                      vport_params[i].vport_wfq);
5137         }
5138 }
5139
5140 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5141 {
5142         int i;
5143
5144         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5145                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5146 }
5147
5148 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5149                                              struct ecore_ptt *p_ptt)
5150 {
5151         struct init_qm_vport_params *vport_params;
5152         int i;
5153
5154         vport_params = p_hwfn->qm_info.qm_vport_params;
5155
5156         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5157                 ecore_init_wfq_default_param(p_hwfn);
5158                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5159                                      vport_params[i].first_tx_pq_id,
5160                                      vport_params[i].vport_wfq);
5161         }
5162 }
5163
5164 /* This function performs several validations for WFQ
5165  * configuration and required min rate for a given vport
5166  * 1. req_rate must be greater than one percent of min_pf_rate.
5167  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5168  *    rates to get less than one percent of min_pf_rate.
5169  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5170  */
5171 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5172                                                  u16 vport_id, u32 req_rate,
5173                                                  u32 min_pf_rate)
5174 {
5175         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5176         int non_requested_count = 0, req_count = 0, i, num_vports;
5177
5178         num_vports = p_hwfn->qm_info.num_vports;
5179
5180 /* Accounting for the vports which are configured for WFQ explicitly */
5181
5182         for (i = 0; i < num_vports; i++) {
5183                 u32 tmp_speed;
5184
5185                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5186                         req_count++;
5187                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5188                         total_req_min_rate += tmp_speed;
5189                 }
5190         }
5191
5192         /* Include current vport data as well */
5193         req_count++;
5194         total_req_min_rate += req_rate;
5195         non_requested_count = num_vports - req_count;
5196
5197         /* validate possible error cases */
5198         if (req_rate > min_pf_rate) {
5199                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5200                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5201                            vport_id, req_rate, min_pf_rate);
5202                 return ECORE_INVAL;
5203         }
5204
5205         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5206                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5207                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5208                            vport_id, req_rate, min_pf_rate);
5209                 return ECORE_INVAL;
5210         }
5211
5212         /* TBD - for number of vports greater than 100 */
5213         if (num_vports > ECORE_WFQ_UNIT) {
5214                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5215                            "Number of vports is greater than %d\n",
5216                            ECORE_WFQ_UNIT);
5217                 return ECORE_INVAL;
5218         }
5219
5220         if (total_req_min_rate > min_pf_rate) {
5221                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5222                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5223                            total_req_min_rate, min_pf_rate);
5224                 return ECORE_INVAL;
5225         }
5226
5227         /* Data left for non requested vports */
5228         total_left_rate = min_pf_rate - total_req_min_rate;
5229         left_rate_per_vp = total_left_rate / non_requested_count;
5230
5231         /* validate if non requested get < 1% of min bw */
5232         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5233                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5234                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5235                            left_rate_per_vp, min_pf_rate);
5236                 return ECORE_INVAL;
5237         }
5238
5239         /* now req_rate for given vport passes all scenarios.
5240          * assign final wfq rates to all vports.
5241          */
5242         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5243         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5244
5245         for (i = 0; i < num_vports; i++) {
5246                 if (p_hwfn->qm_info.wfq_data[i].configured)
5247                         continue;
5248
5249                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5250         }
5251
5252         return ECORE_SUCCESS;
5253 }
5254
5255 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5256                                        struct ecore_ptt *p_ptt,
5257                                        u16 vp_id, u32 rate)
5258 {
5259         struct ecore_mcp_link_state *p_link;
5260         int rc = ECORE_SUCCESS;
5261
5262         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5263
5264         if (!p_link->min_pf_rate) {
5265                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5266                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5267                 return rc;
5268         }
5269
5270         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5271
5272         if (rc == ECORE_SUCCESS)
5273                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5274                                                    p_link->min_pf_rate);
5275         else
5276                 DP_NOTICE(p_hwfn, false,
5277                           "Validation failed while configuring min rate\n");
5278
5279         return rc;
5280 }
5281
5282 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5283                                                    struct ecore_ptt *p_ptt,
5284                                                    u32 min_pf_rate)
5285 {
5286         bool use_wfq = false;
5287         int rc = ECORE_SUCCESS;
5288         u16 i;
5289
5290         /* Validate all pre configured vports for wfq */
5291         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5292                 u32 rate;
5293
5294                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5295                         continue;
5296
5297                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5298                 use_wfq = true;
5299
5300                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5301                 if (rc != ECORE_SUCCESS) {
5302                         DP_NOTICE(p_hwfn, false,
5303                                   "WFQ validation failed while configuring min rate\n");
5304                         break;
5305                 }
5306         }
5307
5308         if (rc == ECORE_SUCCESS && use_wfq)
5309                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5310         else
5311                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5312
5313         return rc;
5314 }
5315
5316 /* Main API for ecore clients to configure vport min rate.
5317  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5318  * rate - Speed in Mbps needs to be assigned to a given vport.
5319  */
5320 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5321 {
5322         int i, rc = ECORE_INVAL;
5323
5324         /* TBD - for multiple hardware functions - that is 100 gig */
5325         if (ECORE_IS_CMT(p_dev)) {
5326                 DP_NOTICE(p_dev, false,
5327                           "WFQ configuration is not supported for this device\n");
5328                 return rc;
5329         }
5330
5331         for_each_hwfn(p_dev, i) {
5332                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5333                 struct ecore_ptt *p_ptt;
5334
5335                 p_ptt = ecore_ptt_acquire(p_hwfn);
5336                 if (!p_ptt)
5337                         return ECORE_TIMEOUT;
5338
5339                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5340
5341                 if (rc != ECORE_SUCCESS) {
5342                         ecore_ptt_release(p_hwfn, p_ptt);
5343                         return rc;
5344                 }
5345
5346                 ecore_ptt_release(p_hwfn, p_ptt);
5347         }
5348
5349         return rc;
5350 }
5351
5352 /* API to configure WFQ from mcp link change */
5353 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5354                                            struct ecore_ptt *p_ptt,
5355                                            u32 min_pf_rate)
5356 {
5357         int i;
5358
5359         /* TBD - for multiple hardware functions - that is 100 gig */
5360         if (ECORE_IS_CMT(p_dev)) {
5361                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5362                            "WFQ configuration is not supported for this device\n");
5363                 return;
5364         }
5365
5366         for_each_hwfn(p_dev, i) {
5367                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5368
5369                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5370                                                         min_pf_rate);
5371         }
5372 }
5373
5374 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5375                                        struct ecore_ptt *p_ptt,
5376                                        struct ecore_mcp_link_state *p_link,
5377                                        u8 max_bw)
5378 {
5379         int rc = ECORE_SUCCESS;
5380
5381         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5382
5383         if (!p_link->line_speed && (max_bw != 100))
5384                 return rc;
5385
5386         p_link->speed = (p_link->line_speed * max_bw) / 100;
5387         p_hwfn->qm_info.pf_rl = p_link->speed;
5388
5389         /* Since the limiter also affects Tx-switched traffic, we don't want it
5390          * to limit such traffic in case there's no actual limit.
5391          * In that case, set limit to imaginary high boundary.
5392          */
5393         if (max_bw == 100)
5394                 p_hwfn->qm_info.pf_rl = 100000;
5395
5396         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5397                               p_hwfn->qm_info.pf_rl);
5398
5399         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5400                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5401                    p_link->speed);
5402
5403         return rc;
5404 }
5405
5406 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5407 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5408 {
5409         int i, rc = ECORE_INVAL;
5410
5411         if (max_bw < 1 || max_bw > 100) {
5412                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5413                 return rc;
5414         }
5415
5416         for_each_hwfn(p_dev, i) {
5417                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5418                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5419                 struct ecore_mcp_link_state *p_link;
5420                 struct ecore_ptt *p_ptt;
5421
5422                 p_link = &p_lead->mcp_info->link_output;
5423
5424                 p_ptt = ecore_ptt_acquire(p_hwfn);
5425                 if (!p_ptt)
5426                         return ECORE_TIMEOUT;
5427
5428                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5429                                                         p_link, max_bw);
5430
5431                 ecore_ptt_release(p_hwfn, p_ptt);
5432
5433                 if (rc != ECORE_SUCCESS)
5434                         break;
5435         }
5436
5437         return rc;
5438 }
5439
5440 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5441                                        struct ecore_ptt *p_ptt,
5442                                        struct ecore_mcp_link_state *p_link,
5443                                        u8 min_bw)
5444 {
5445         int rc = ECORE_SUCCESS;
5446
5447         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5448         p_hwfn->qm_info.pf_wfq = min_bw;
5449
5450         if (!p_link->line_speed)
5451                 return rc;
5452
5453         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5454
5455         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5456
5457         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5458                    "Configured MIN bandwidth to be %d Mb/sec\n",
5459                    p_link->min_pf_rate);
5460
5461         return rc;
5462 }
5463
5464 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5465 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5466 {
5467         int i, rc = ECORE_INVAL;
5468
5469         if (min_bw < 1 || min_bw > 100) {
5470                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5471                 return rc;
5472         }
5473
5474         for_each_hwfn(p_dev, i) {
5475                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5476                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5477                 struct ecore_mcp_link_state *p_link;
5478                 struct ecore_ptt *p_ptt;
5479
5480                 p_link = &p_lead->mcp_info->link_output;
5481
5482                 p_ptt = ecore_ptt_acquire(p_hwfn);
5483                 if (!p_ptt)
5484                         return ECORE_TIMEOUT;
5485
5486                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5487                                                         p_link, min_bw);
5488                 if (rc != ECORE_SUCCESS) {
5489                         ecore_ptt_release(p_hwfn, p_ptt);
5490                         return rc;
5491                 }
5492
5493                 if (p_link->min_pf_rate) {
5494                         u32 min_rate = p_link->min_pf_rate;
5495
5496                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5497                                                                      p_ptt,
5498                                                                      min_rate);
5499                 }
5500
5501                 ecore_ptt_release(p_hwfn, p_ptt);
5502         }
5503
5504         return rc;
5505 }
5506
5507 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5508 {
5509         struct ecore_mcp_link_state *p_link;
5510
5511         p_link = &p_hwfn->mcp_info->link_output;
5512
5513         if (p_link->min_pf_rate)
5514                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5515
5516         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5517                     sizeof(*p_hwfn->qm_info.wfq_data) *
5518                     p_hwfn->qm_info.num_vports);
5519 }
5520
5521 int ecore_device_num_engines(struct ecore_dev *p_dev)
5522 {
5523         return ECORE_IS_BB(p_dev) ? 2 : 1;
5524 }
5525
5526 int ecore_device_num_ports(struct ecore_dev *p_dev)
5527 {
5528         return p_dev->num_ports;
5529 }
5530
5531 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5532                           __le16 *fw_mid,
5533                           __le16 *fw_lsb,
5534                           u8 *mac)
5535 {
5536         ((u8 *)fw_msb)[0] = mac[1];
5537         ((u8 *)fw_msb)[1] = mac[0];
5538         ((u8 *)fw_mid)[0] = mac[3];
5539         ((u8 *)fw_mid)[1] = mac[2];
5540         ((u8 *)fw_lsb)[0] = mac[5];
5541         ((u8 *)fw_lsb)[1] = mac[4];
5542 }