drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /******************** Doorbell Recovery *******************/
  46 /* The doorbell recovery mechanism consists of a list of entries which represent
  47  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  48  * entity needs to register with the mechanism and provide the parameters
  49  * describing it's doorbell, including a location where last used doorbell data
  50  * can be found. The doorbell execute function will traverse the list and
  51  * doorbell all of the registered entries.
  52  */
  53 struct ecore_db_recovery_entry {
  54         osal_list_entry_t       list_entry;
  55         void OSAL_IOMEM         *db_addr;
  56         void                    *db_data;
  57         enum ecore_db_rec_width db_width;
  58         enum ecore_db_rec_space db_space;
  59         u8                      hwfn_idx;
  60 };
  61
  62 /* display a single doorbell recovery entry */
  63 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  64                                 struct ecore_db_recovery_entry *db_entry,
  65                                 const char *action)
  66 {
  67         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  68                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  69                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  70                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  71                    db_entry->hwfn_idx);
  72 }
  73
  74 /* doorbell address sanity (address within doorbell bar range) */
  75 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  76                          void *db_data)
  77 {
  78         /* make sure doorbell address  is within the doorbell bar */
  79         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  80                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  81                 OSAL_WARN(true,
  82                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  83                           db_addr, p_dev->doorbells,
  84                           (u8 *)p_dev->doorbells + p_dev->db_size);
  85                 return false;
  86         }
  87
  88         /* make sure doorbell data pointer is not null */
  89         if (!db_data) {
  90                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  91                 return false;
  92         }
  93
  94         return true;
  95 }
  96
  97 /* find hwfn according to the doorbell address */
  98 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  99                                           void OSAL_IOMEM *db_addr)
 100 {
 101         struct ecore_hwfn *p_hwfn;
 102
 103         /* In CMT doorbell bar is split down the middle between engine 0 and
 104          * enigne 1
 105          */
 106         if (ECORE_IS_CMT(p_dev))
 107                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 108                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 109         else
 110                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 111
 112         return p_hwfn;
 113 }
 114
 115 /* add a new entry to the doorbell recovery mechanism */
 116 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 117                                            void OSAL_IOMEM *db_addr,
 118                                            void *db_data,
 119                                            enum ecore_db_rec_width db_width,
 120                                            enum ecore_db_rec_space db_space)
 121 {
 122         struct ecore_db_recovery_entry *db_entry;
 123         struct ecore_hwfn *p_hwfn;
 124
 125         /* shortcircuit VFs, for now */
 126         if (IS_VF(p_dev)) {
 127                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 128                 return ECORE_SUCCESS;
 129         }
 130
 131         /* sanitize doorbell address */
 132         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 133                 return ECORE_INVAL;
 134
 135         /* obtain hwfn from doorbell address */
 136         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 137
 138         /* create entry */
 139         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 140         if (!db_entry) {
 141                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 142                 return ECORE_NOMEM;
 143         }
 144
 145         /* populate entry */
 146         db_entry->db_addr = db_addr;
 147         db_entry->db_data = db_data;
 148         db_entry->db_width = db_width;
 149         db_entry->db_space = db_space;
 150         db_entry->hwfn_idx = p_hwfn->my_id;
 151
 152         /* display */
 153         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 154
 155         /* protect the list */
 156         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 157         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 158                             &p_hwfn->db_recovery_info.list);
 159         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 160
 161         return ECORE_SUCCESS;
 162 }
 163
 164 /* remove an entry from the doorbell recovery mechanism */
 165 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 166                                            void OSAL_IOMEM *db_addr,
 167                                            void *db_data)
 168 {
 169         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 170         enum _ecore_status_t rc = ECORE_INVAL;
 171         struct ecore_hwfn *p_hwfn;
 172
 173         /* shortcircuit VFs, for now */
 174         if (IS_VF(p_dev)) {
 175                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 176                 return ECORE_SUCCESS;
 177         }
 178
 179         /* sanitize doorbell address */
 180         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 181                 return ECORE_INVAL;
 182
 183         /* obtain hwfn from doorbell address */
 184         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 185
 186         /* protect the list */
 187         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 188         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 189                                  &p_hwfn->db_recovery_info.list,
 190                                  list_entry,
 191                                  struct ecore_db_recovery_entry) {
 192                 /* search according to db_data addr since db_addr is not unique
 193                  * (roce)
 194                  */
 195                 if (db_entry->db_data == db_data) {
 196                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 197                                                    "Deleting");
 198                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 199                                                &p_hwfn->db_recovery_info.list);
 200                         rc = ECORE_SUCCESS;
 201                         break;
 202                 }
 203         }
 204
 205         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 206
 207         if (rc == ECORE_INVAL)
 208                 /*OSAL_WARN(true,*/
 209                 DP_NOTICE(p_hwfn, false,
 210                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 211                           db_data, db_addr);
 212         else
 213                 OSAL_FREE(p_dev, db_entry);
 214
 215         return rc;
 216 }
 217
 218 /* initialize the doorbell recovery mechanism */
 219 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 220 {
 221         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 222
 223         /* make sure db_size was set in p_dev */
 224         if (!p_hwfn->p_dev->db_size) {
 225                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 226                 return ECORE_INVAL;
 227         }
 228
 229         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 230 #ifdef CONFIG_ECORE_LOCK_ALLOC
 231         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 232 #endif
 233         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 234         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 235
 236         return ECORE_SUCCESS;
 237 }
 238
 239 /* destroy the doorbell recovery mechanism */
 240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 241 {
 242         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 243
 244         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 245         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 247                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 248                         db_entry = OSAL_LIST_FIRST_ENTRY(
 249                                                 &p_hwfn->db_recovery_info.list,
 250                                                 struct ecore_db_recovery_entry,
 251                                                 list_entry);
 252                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 253                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 254                                                &p_hwfn->db_recovery_info.list);
 255                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 256                 }
 257         }
 258 #ifdef CONFIG_ECORE_LOCK_ALLOC
 259         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 260 #endif
 261         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 262 }
 263
 264 /* print the content of the doorbell recovery mechanism */
 265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 266 {
 267         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 268
 269         DP_NOTICE(p_hwfn, false,
 270                   "Dispalying doorbell recovery database. Counter was %d\n",
 271                   p_hwfn->db_recovery_info.db_recovery_counter);
 272
 273         /* protect the list */
 274         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 275         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 276                                  &p_hwfn->db_recovery_info.list,
 277                                  list_entry,
 278                                  struct ecore_db_recovery_entry) {
 279                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 280         }
 281
 282         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 283 }
 284
 285 /* ring the doorbell of a single doorbell recovery entry */
 286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 287                             struct ecore_db_recovery_entry *db_entry,
 288                             enum ecore_db_rec_exec db_exec)
 289 {
 290         /* Print according to width */
 291         if (db_entry->db_width == DB_REC_WIDTH_32B)
 292                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 293                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 294                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 295         else
 296                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 297                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 298                            db_entry->db_addr,
 299                            *(unsigned long *)(db_entry->db_data));
 300
 301         /* Sanity */
 302         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 303                                  db_entry->db_data))
 304                 return;
 305
 306         /* Flush the write combined buffer. Since there are multiple doorbelling
 307          * entities using the same address, if we don't flush, a transaction
 308          * could be lost.
 309          */
 310         OSAL_WMB(p_hwfn->p_dev);
 311
 312         /* Ring the doorbell */
 313         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 314                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 315                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 316                                       *(u32 *)(db_entry->db_data));
 317                 else
 318                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 319                                         *(u64 *)(db_entry->db_data));
 320         }
 321
 322         /* Flush the write combined buffer. Next doorbell may come from a
 323          * different entity to the same address...
 324          */
 325         OSAL_WMB(p_hwfn->p_dev);
 326 }
 327
 328 /* traverse the doorbell recovery entry list and ring all the doorbells */
 329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 330                                enum ecore_db_rec_exec db_exec)
 331 {
 332         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 333
 334         if (db_exec != DB_REC_ONCE) {
 335                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 336                           p_hwfn->db_recovery_info.db_recovery_counter);
 337
 338                 /* track amount of times recovery was executed */
 339                 p_hwfn->db_recovery_info.db_recovery_counter++;
 340         }
 341
 342         /* protect the list */
 343         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 344         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 345                                  &p_hwfn->db_recovery_info.list,
 346                                  list_entry,
 347                                  struct ecore_db_recovery_entry) {
 348                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 349                 if (db_exec == DB_REC_ONCE)
 350                         break;
 351         }
 352
 353         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 354 }
 355 /******************** Doorbell Recovery end ****************/
 356
 357 /* Configurable */
 358 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 359                                          * load the driver. The number was
 360                                          * arbitrarily set.
 361                                          */
 362
 363 /* Derived */
 364 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 365
 366 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 367                              struct ecore_ptt *p_ptt,
 368                              enum BAR_ID bar_id)
 369 {
 370         u32 bar_reg = (bar_id == BAR_ID_0 ?
 371                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 372         u32 val;
 373
 374         if (IS_VF(p_hwfn->p_dev))
 375                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
 376
 377         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 378         if (val)
 379                 return 1 << (val + 15);
 380
 381         /* The above registers were updated in the past only in CMT mode. Since
 382          * they were found to be useful MFW started updating them from 8.7.7.0.
 383          * In older MFW versions they are set to 0 which means disabled.
 384          */
 385         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 386                 DP_INFO(p_hwfn,
 387                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 388                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 389         } else {
 390                 DP_INFO(p_hwfn,
 391                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 392                 val = 512 * 1024;
 393         }
 394
 395         return val;
 396 }
 397
 398 void ecore_init_dp(struct ecore_dev *p_dev,
 399                    u32 dp_module, u8 dp_level, void *dp_ctx)
 400 {
 401         u32 i;
 402
 403         p_dev->dp_level = dp_level;
 404         p_dev->dp_module = dp_module;
 405         p_dev->dp_ctx = dp_ctx;
 406         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 407                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 408
 409                 p_hwfn->dp_level = dp_level;
 410                 p_hwfn->dp_module = dp_module;
 411                 p_hwfn->dp_ctx = dp_ctx;
 412         }
 413 }
 414
 415 void ecore_init_struct(struct ecore_dev *p_dev)
 416 {
 417         u8 i;
 418
 419         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 420                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 421
 422                 p_hwfn->p_dev = p_dev;
 423                 p_hwfn->my_id = i;
 424                 p_hwfn->b_active = false;
 425
 426 #ifdef CONFIG_ECORE_LOCK_ALLOC
 427                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 428 #endif
 429                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 430         }
 431
 432         /* hwfn 0 is always active */
 433         p_dev->hwfns[0].b_active = true;
 434
 435         /* set the default cache alignment to 128 (may be overridden later) */
 436         p_dev->cache_shift = 7;
 437 }
 438
 439 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 440 {
 441         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 442
 443         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 444         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 445         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 446         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 447 }
 448
 449 void ecore_resc_free(struct ecore_dev *p_dev)
 450 {
 451         int i;
 452
 453         if (IS_VF(p_dev)) {
 454                 for_each_hwfn(p_dev, i)
 455                         ecore_l2_free(&p_dev->hwfns[i]);
 456                 return;
 457         }
 458
 459         OSAL_FREE(p_dev, p_dev->fw_data);
 460
 461         OSAL_FREE(p_dev, p_dev->reset_stats);
 462
 463         for_each_hwfn(p_dev, i) {
 464                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 465
 466                 ecore_cxt_mngr_free(p_hwfn);
 467                 ecore_qm_info_free(p_hwfn);
 468                 ecore_spq_free(p_hwfn);
 469                 ecore_eq_free(p_hwfn);
 470                 ecore_consq_free(p_hwfn);
 471                 ecore_int_free(p_hwfn);
 472                 ecore_iov_free(p_hwfn);
 473                 ecore_l2_free(p_hwfn);
 474                 ecore_dmae_info_free(p_hwfn);
 475                 ecore_dcbx_info_free(p_hwfn);
 476                 /* @@@TBD Flush work-queue ? */
 477
 478                 /* destroy doorbell recovery mechanism */
 479                 ecore_db_recovery_teardown(p_hwfn);
 480         }
 481 }
 482
 483 /******************** QM initialization *******************/
 484
 485 /* bitmaps for indicating active traffic classes.
 486  * Special case for Arrowhead 4 port
 487  */
 488 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 489 #define ACTIVE_TCS_BMAP 0x9f
 490 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 491 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 492
 493 /* determines the physical queue flags for a given PF. */
 494 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 495 {
 496         u32 flags;
 497
 498         /* common flags */
 499         flags = PQ_FLAGS_LB;
 500
 501         /* feature flags */
 502         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 503                 flags |= PQ_FLAGS_VFS;
 504
 505         /* protocol flags */
 506         switch (p_hwfn->hw_info.personality) {
 507         case ECORE_PCI_ETH:
 508                 flags |= PQ_FLAGS_MCOS;
 509                 break;
 510         case ECORE_PCI_FCOE:
 511                 flags |= PQ_FLAGS_OFLD;
 512                 break;
 513         case ECORE_PCI_ISCSI:
 514                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 515                 break;
 516         case ECORE_PCI_ETH_ROCE:
 517                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 518                 break;
 519         case ECORE_PCI_ETH_IWARP:
 520                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 521                          PQ_FLAGS_OFLD;
 522                 break;
 523         default:
 524                 DP_ERR(p_hwfn, "unknown personality %d\n",
 525                        p_hwfn->hw_info.personality);
 526                 return 0;
 527         }
 528         return flags;
 529 }
 530
 531 /* Getters for resource amounts necessary for qm initialization */
 532 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 533 {
 534         return p_hwfn->hw_info.num_hw_tc;
 535 }
 536
 537 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 538 {
 539         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 540                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 541 }
 542
 543 #define NUM_DEFAULT_RLS 1
 544
 545 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 546 {
 547         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 548
 549         /* @DPDK */
 550         /* num RLs can't exceed resource amount of rls or vports or the
 551          * dcqcn qps
 552          */
 553         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 554                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 555
 556         /* make sure after we reserve the default and VF rls we'll have
 557          * something left
 558          */
 559         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 560                 DP_NOTICE(p_hwfn, false,
 561                           "no rate limiters left for PF rate limiting"
 562                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 563                 return 0;
 564         }
 565
 566         /* subtract rls necessary for VFs and one default one for the PF */
 567         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 568
 569         return num_pf_rls;
 570 }
 571
 572 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 573 {
 574         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 575
 576         /* all pqs share the same vport (hence the 1 below), except for vfs
 577          * and pf_rl pqs
 578          */
 579         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 580                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 581                (!!(PQ_FLAGS_VFS & pq_flags)) *
 582                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 583 }
 584
 585 /* calc amount of PQs according to the requested flags */
 586 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 587 {
 588         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 589
 590         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 591                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 592                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 593                 ecore_init_qm_get_num_tcs(p_hwfn) +
 594                (!!(PQ_FLAGS_LB & pq_flags)) +
 595                (!!(PQ_FLAGS_OOO & pq_flags)) +
 596                (!!(PQ_FLAGS_ACK & pq_flags)) +
 597                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 598                (!!(PQ_FLAGS_VFS & pq_flags)) *
 599                 ecore_init_qm_get_num_vfs(p_hwfn);
 600 }
 601
 602 /* initialize the top level QM params */
 603 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 604 {
 605         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 606         bool four_port;
 607
 608         /* pq and vport bases for this PF */
 609         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 610         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 611
 612         /* rate limiting and weighted fair queueing are always enabled */
 613         qm_info->vport_rl_en = 1;
 614         qm_info->vport_wfq_en = 1;
 615
 616         /* TC config is different for AH 4 port */
 617         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 618
 619         /* in AH 4 port we have fewer TCs per port */
 620         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 621                                                      NUM_OF_PHYS_TCS;
 622
 623         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 624          * 4 otherwise
 625          */
 626         if (!qm_info->ooo_tc)
 627                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 628                                               DCBX_TCP_OOO_TC;
 629 }
 630
 631 /* initialize qm vport params */
 632 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 633 {
 634         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 635         u8 i;
 636
 637         /* all vports participate in weighted fair queueing */
 638         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 639                 qm_info->qm_vport_params[i].vport_wfq = 1;
 640 }
 641
 642 /* initialize qm port params */
 643 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 644 {
 645         /* Initialize qm port parameters */
 646         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 647
 648         /* indicate how ooo and high pri traffic is dealt with */
 649         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 650                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 651
 652         for (i = 0; i < num_ports; i++) {
 653                 struct init_qm_port_params *p_qm_port =
 654                         &p_hwfn->qm_info.qm_port_params[i];
 655
 656                 p_qm_port->active = 1;
 657                 p_qm_port->active_phys_tcs = active_phys_tcs;
 658                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 659                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 660         }
 661 }
 662
 663 /* Reset the params which must be reset for qm init. QM init may be called as
 664  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 665  * params may be affected by the init but would simply recalculate to the same
 666  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 667  * affected as these amounts stay the same.
 668  */
 669 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 670 {
 671         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 672
 673         qm_info->num_pqs = 0;
 674         qm_info->num_vports = 0;
 675         qm_info->num_pf_rls = 0;
 676         qm_info->num_vf_pqs = 0;
 677         qm_info->first_vf_pq = 0;
 678         qm_info->first_mcos_pq = 0;
 679         qm_info->first_rl_pq = 0;
 680 }
 681
 682 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 683 {
 684         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 685
 686         qm_info->num_vports++;
 687
 688         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 689                 DP_ERR(p_hwfn,
 690                        "vport overflow! qm_info->num_vports %d,"
 691                        " qm_init_get_num_vports() %d\n",
 692                        qm_info->num_vports,
 693                        ecore_init_qm_get_num_vports(p_hwfn));
 694 }
 695
 696 /* initialize a single pq and manage qm_info resources accounting.
 697  * The pq_init_flags param determines whether the PQ is rate limited
 698  * (for VF or PF)
 699  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 700  * shared)
 701  */
 702
 703 /* flags for pq init */
 704 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 705 #define PQ_INIT_PF_RL           (1 << 1)
 706 #define PQ_INIT_VF_RL           (1 << 2)
 707
 708 /* defines for pq init */
 709 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 710 #define PQ_INIT_DEFAULT_TC              0
 711 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 712
 713 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 714                              struct ecore_qm_info *qm_info,
 715                              u8 tc, u32 pq_init_flags)
 716 {
 717         u16 pq_idx = qm_info->num_pqs, max_pq =
 718                                         ecore_init_qm_get_num_pqs(p_hwfn);
 719
 720         if (pq_idx > max_pq)
 721                 DP_ERR(p_hwfn,
 722                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 723
 724         /* init pq params */
 725         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 726                                                  qm_info->num_vports;
 727         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 728         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 729         qm_info->qm_pq_params[pq_idx].rl_valid =
 730                 (pq_init_flags & PQ_INIT_PF_RL ||
 731                  pq_init_flags & PQ_INIT_VF_RL);
 732
 733         /* qm params accounting */
 734         qm_info->num_pqs++;
 735         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 736                 qm_info->num_vports++;
 737
 738         if (pq_init_flags & PQ_INIT_PF_RL)
 739                 qm_info->num_pf_rls++;
 740
 741         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 742                 DP_ERR(p_hwfn,
 743                        "vport overflow! qm_info->num_vports %d,"
 744                        " qm_init_get_num_vports() %d\n",
 745                        qm_info->num_vports,
 746                        ecore_init_qm_get_num_vports(p_hwfn));
 747
 748         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 749                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 750                        " qm_init_get_num_pf_rls() %d\n",
 751                        qm_info->num_pf_rls,
 752                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 753 }
 754
 755 /* get pq index according to PQ_FLAGS */
 756 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 757                                              u32 pq_flags)
 758 {
 759         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 760
 761         /* Can't have multiple flags set here */
 762         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 763                                 sizeof(pq_flags)) > 1)
 764                 goto err;
 765
 766         switch (pq_flags) {
 767         case PQ_FLAGS_RLS:
 768                 return &qm_info->first_rl_pq;
 769         case PQ_FLAGS_MCOS:
 770                 return &qm_info->first_mcos_pq;
 771         case PQ_FLAGS_LB:
 772                 return &qm_info->pure_lb_pq;
 773         case PQ_FLAGS_OOO:
 774                 return &qm_info->ooo_pq;
 775         case PQ_FLAGS_ACK:
 776                 return &qm_info->pure_ack_pq;
 777         case PQ_FLAGS_OFLD:
 778                 return &qm_info->offload_pq;
 779         case PQ_FLAGS_VFS:
 780                 return &qm_info->first_vf_pq;
 781         default:
 782                 goto err;
 783         }
 784
 785 err:
 786         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 787         return OSAL_NULL;
 788 }
 789
 790 /* save pq index in qm info */
 791 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 792                                   u32 pq_flags, u16 pq_val)
 793 {
 794         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 795
 796         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 797 }
 798
 799 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 800 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 801 {
 802         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 803
 804         return *base_pq_idx + CM_TX_PQ_BASE;
 805 }
 806
 807 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 808 {
 809         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 810
 811         if (tc > max_tc)
 812                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 813
 814         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 815 }
 816
 817 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 818 {
 819         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 820
 821         if (vf > max_vf)
 822                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 823
 824         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 825 }
 826
 827 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 828 {
 829         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 830
 831         if (rl > max_rl)
 832                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 833
 834         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 835 }
 836
 837 /* Functions for creating specific types of pqs */
 838 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 839 {
 840         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 841
 842         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 843                 return;
 844
 845         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 846         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 847 }
 848
 849 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 850 {
 851         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 852
 853         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 854                 return;
 855
 856         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 857         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 858 }
 859
 860 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 861 {
 862         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 863
 864         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 865                 return;
 866
 867         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 868         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 869 }
 870
 871 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 872 {
 873         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 874
 875         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 876                 return;
 877
 878         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 879         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 880 }
 881
 882 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 883 {
 884         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 885         u8 tc_idx;
 886
 887         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 888                 return;
 889
 890         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 891         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 892                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 893 }
 894
 895 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 896 {
 897         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 898         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 899
 900         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 901                 return;
 902
 903         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 904
 905         qm_info->num_vf_pqs = num_vfs;
 906         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 907                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 908                                  PQ_INIT_VF_RL);
 909 }
 910
 911 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 912 {
 913         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 914         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 915
 916         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 917                 return;
 918
 919         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 920         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 921                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 922                                  PQ_INIT_PF_RL);
 923 }
 924
 925 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 926 {
 927         /* rate limited pqs, must come first (FW assumption) */
 928         ecore_init_qm_rl_pqs(p_hwfn);
 929
 930         /* pqs for multi cos */
 931         ecore_init_qm_mcos_pqs(p_hwfn);
 932
 933         /* pure loopback pq */
 934         ecore_init_qm_lb_pq(p_hwfn);
 935
 936         /* out of order pq */
 937         ecore_init_qm_ooo_pq(p_hwfn);
 938
 939         /* pure ack pq */
 940         ecore_init_qm_pure_ack_pq(p_hwfn);
 941
 942         /* pq for offloaded protocol */
 943         ecore_init_qm_offload_pq(p_hwfn);
 944
 945         /* done sharing vports */
 946         ecore_init_qm_advance_vport(p_hwfn);
 947
 948         /* pqs for vfs */
 949         ecore_init_qm_vf_pqs(p_hwfn);
 950 }
 951
 952 /* compare values of getters against resources amounts */
 953 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 954 {
 955         if (ecore_init_qm_get_num_vports(p_hwfn) >
 956             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 957                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 958                 return ECORE_INVAL;
 959         }
 960
 961         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 962                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 963                 return ECORE_INVAL;
 964         }
 965
 966         return ECORE_SUCCESS;
 967 }
 968
 969 /*
 970  * Function for verbose printing of the qm initialization results
 971  */
 972 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 973 {
 974         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 975         struct init_qm_vport_params *vport;
 976         struct init_qm_port_params *port;
 977         struct init_qm_pq_params *pq;
 978         int i, tc;
 979
 980         /* top level params */
 981         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 982                    "qm init top level params: start_pq %d, start_vport %d,"
 983                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 984                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 985                    qm_info->offload_pq, qm_info->pure_ack_pq);
 986         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 987                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 988                    " num_vports %d, max_phys_tcs_per_port %d\n",
 989                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 990                    qm_info->num_vf_pqs, qm_info->num_vports,
 991                    qm_info->max_phys_tcs_per_port);
 992         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 993                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 994                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 995                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 996                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 997                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 998
 999         /* port table */
1000         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1001                 port = &qm_info->qm_port_params[i];
1002                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003                            "port idx %d, active %d, active_phys_tcs %d,"
1004                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1005                            " reserved %d\n",
1006                            i, port->active, port->active_phys_tcs,
1007                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1008                            port->reserved);
1009         }
1010
1011         /* vport table */
1012         for (i = 0; i < qm_info->num_vports; i++) {
1013                 vport = &qm_info->qm_vport_params[i];
1014                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1015                            "vport idx %d, vport_rl %d, wfq %d,"
1016                            " first_tx_pq_id [ ",
1017                            qm_info->start_vport + i, vport->vport_rl,
1018                            vport->vport_wfq);
1019                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1020                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1021                                    vport->first_tx_pq_id[tc]);
1022                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1023         }
1024
1025         /* pq table */
1026         for (i = 0; i < qm_info->num_pqs; i++) {
1027                 pq = &qm_info->qm_pq_params[i];
1028                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1029                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1030                            " rl_valid %d\n",
1031                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1032                            pq->wrr_group, pq->rl_valid);
1033         }
1034 }
1035
1036 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1037 {
1038         /* reset params required for init run */
1039         ecore_init_qm_reset_params(p_hwfn);
1040
1041         /* init QM top level params */
1042         ecore_init_qm_params(p_hwfn);
1043
1044         /* init QM port params */
1045         ecore_init_qm_port_params(p_hwfn);
1046
1047         /* init QM vport params */
1048         ecore_init_qm_vport_params(p_hwfn);
1049
1050         /* init QM physical queue params */
1051         ecore_init_qm_pq_params(p_hwfn);
1052
1053         /* display all that init */
1054         ecore_dp_init_qm_params(p_hwfn);
1055 }
1056
1057 /* This function reconfigures the QM pf on the fly.
1058  * For this purpose we:
1059  * 1. reconfigure the QM database
1060  * 2. set new values to runtime array
1061  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1062  * 4. activate init tool in QM_PF stage
1063  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1064  */
1065 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1066                                      struct ecore_ptt *p_ptt)
1067 {
1068         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1069         bool b_rc;
1070         enum _ecore_status_t rc;
1071
1072         /* initialize ecore's qm data structure */
1073         ecore_init_qm_info(p_hwfn);
1074
1075         /* stop PF's qm queues */
1076         OSAL_SPIN_LOCK(&qm_lock);
1077         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1078                                       qm_info->start_pq, qm_info->num_pqs);
1079         OSAL_SPIN_UNLOCK(&qm_lock);
1080         if (!b_rc)
1081                 return ECORE_INVAL;
1082
1083         /* clear the QM_PF runtime phase leftovers from previous init */
1084         ecore_init_clear_rt_data(p_hwfn);
1085
1086         /* prepare QM portion of runtime array */
1087         ecore_qm_init_pf(p_hwfn, p_ptt);
1088
1089         /* activate init tool on runtime array */
1090         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1091                             p_hwfn->hw_info.hw_mode);
1092         if (rc != ECORE_SUCCESS)
1093                 return rc;
1094
1095         /* start PF's qm queues */
1096         OSAL_SPIN_LOCK(&qm_lock);
1097         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1098                                       qm_info->start_pq, qm_info->num_pqs);
1099         OSAL_SPIN_UNLOCK(&qm_lock);
1100         if (!b_rc)
1101                 return ECORE_INVAL;
1102
1103         return ECORE_SUCCESS;
1104 }
1105
1106 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1107 {
1108         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1109         enum _ecore_status_t rc;
1110
1111         rc = ecore_init_qm_sanity(p_hwfn);
1112         if (rc != ECORE_SUCCESS)
1113                 goto alloc_err;
1114
1115         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1116                                             sizeof(struct init_qm_pq_params) *
1117                                             ecore_init_qm_get_num_pqs(p_hwfn));
1118         if (!qm_info->qm_pq_params)
1119                 goto alloc_err;
1120
1121         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1122                                        sizeof(struct init_qm_vport_params) *
1123                                        ecore_init_qm_get_num_vports(p_hwfn));
1124         if (!qm_info->qm_vport_params)
1125                 goto alloc_err;
1126
1127         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1128                                       sizeof(struct init_qm_port_params) *
1129                                       p_hwfn->p_dev->num_ports_in_engine);
1130         if (!qm_info->qm_port_params)
1131                 goto alloc_err;
1132
1133         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1134                                         sizeof(struct ecore_wfq_data) *
1135                                         ecore_init_qm_get_num_vports(p_hwfn));
1136         if (!qm_info->wfq_data)
1137                 goto alloc_err;
1138
1139         return ECORE_SUCCESS;
1140
1141 alloc_err:
1142         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1143         ecore_qm_info_free(p_hwfn);
1144         return ECORE_NOMEM;
1145 }
1146 /******************** End QM initialization ***************/
1147
1148 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1149 {
1150         enum _ecore_status_t rc = ECORE_SUCCESS;
1151         int i;
1152
1153         if (IS_VF(p_dev)) {
1154                 for_each_hwfn(p_dev, i) {
1155                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1156                         if (rc != ECORE_SUCCESS)
1157                                 return rc;
1158                 }
1159                 return rc;
1160         }
1161
1162         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1163                                      sizeof(*p_dev->fw_data));
1164         if (!p_dev->fw_data)
1165                 return ECORE_NOMEM;
1166
1167         for_each_hwfn(p_dev, i) {
1168                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1169                 u32 n_eqes, num_cons;
1170
1171                 /* initialize the doorbell recovery mechanism */
1172                 rc = ecore_db_recovery_setup(p_hwfn);
1173                 if (rc)
1174                         goto alloc_err;
1175
1176                 /* First allocate the context manager structure */
1177                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1178                 if (rc)
1179                         goto alloc_err;
1180
1181                 /* Set the HW cid/tid numbers (in the context manager)
1182                  * Must be done prior to any further computations.
1183                  */
1184                 rc = ecore_cxt_set_pf_params(p_hwfn);
1185                 if (rc)
1186                         goto alloc_err;
1187
1188                 rc = ecore_alloc_qm_data(p_hwfn);
1189                 if (rc)
1190                         goto alloc_err;
1191
1192                 /* init qm info */
1193                 ecore_init_qm_info(p_hwfn);
1194
1195                 /* Compute the ILT client partition */
1196                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1197                 if (rc)
1198                         goto alloc_err;
1199
1200                 /* CID map / ILT shadow table / T2
1201                  * The talbes sizes are determined by the computations above
1202                  */
1203                 rc = ecore_cxt_tables_alloc(p_hwfn);
1204                 if (rc)
1205                         goto alloc_err;
1206
1207                 /* SPQ, must follow ILT because initializes SPQ context */
1208                 rc = ecore_spq_alloc(p_hwfn);
1209                 if (rc)
1210                         goto alloc_err;
1211
1212                 /* SP status block allocation */
1213                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1214                                                            RESERVED_PTT_DPC);
1215
1216                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1217                 if (rc)
1218                         goto alloc_err;
1219
1220                 rc = ecore_iov_alloc(p_hwfn);
1221                 if (rc)
1222                         goto alloc_err;
1223
1224                 /* EQ */
1225                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1226                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1227                         /* Calculate the EQ size
1228                          * ---------------------
1229                          * Each ICID may generate up to one event at a time i.e.
1230                          * the event must be handled/cleared before a new one
1231                          * can be generated. We calculate the sum of events per
1232                          * protocol and create an EQ deep enough to handle the
1233                          * worst case:
1234                          * - Core - according to SPQ.
1235                          * - RoCE - per QP there are a couple of ICIDs, one
1236                          *        responder and one requester, each can
1237                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1238                          *        Each CQ can generate an EQE. There are 2 CQs
1239                          *        per QP => n_eqes_cq = 2 * n_qp.
1240                          *        Hence the RoCE total is 4 * n_qp or
1241                          *        2 * num_cons.
1242                          * - ENet - There can be up to two events per VF. One
1243                          *        for VF-PF channel and another for VF FLR
1244                          *        initial cleanup. The number of VFs is
1245                          *        bounded by MAX_NUM_VFS_BB, and is much
1246                          *        smaller than RoCE's so we avoid exact
1247                          *        calculation.
1248                          */
1249                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1250                                 num_cons =
1251                                     ecore_cxt_get_proto_cid_count(
1252                                                 p_hwfn,
1253                                                 PROTOCOLID_ROCE,
1254                                                 OSAL_NULL);
1255                                 num_cons *= 2;
1256                         } else {
1257                                 num_cons = ecore_cxt_get_proto_cid_count(
1258                                                 p_hwfn,
1259                                                 PROTOCOLID_IWARP,
1260                                                 OSAL_NULL);
1261                         }
1262                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1263                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1264                         num_cons =
1265                             ecore_cxt_get_proto_cid_count(p_hwfn,
1266                                                           PROTOCOLID_ISCSI,
1267                                                           OSAL_NULL);
1268                         n_eqes += 2 * num_cons;
1269                 }
1270
1271                 if (n_eqes > 0xFFFF) {
1272                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1273                                        "The maximum of a u16 chain is 0x%x\n",
1274                                n_eqes, 0xFFFF);
1275                         goto alloc_no_mem;
1276                 }
1277
1278                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1279                 if (rc)
1280                         goto alloc_err;
1281
1282                 rc = ecore_consq_alloc(p_hwfn);
1283                 if (rc)
1284                         goto alloc_err;
1285
1286                 rc = ecore_l2_alloc(p_hwfn);
1287                 if (rc != ECORE_SUCCESS)
1288                         goto alloc_err;
1289
1290                 /* DMA info initialization */
1291                 rc = ecore_dmae_info_alloc(p_hwfn);
1292                 if (rc) {
1293                         DP_NOTICE(p_hwfn, true,
1294                                   "Failed to allocate memory for dmae_info"
1295                                   " structure\n");
1296                         goto alloc_err;
1297                 }
1298
1299                 /* DCBX initialization */
1300                 rc = ecore_dcbx_info_alloc(p_hwfn);
1301                 if (rc) {
1302                         DP_NOTICE(p_hwfn, true,
1303                                   "Failed to allocate memory for dcbx structure\n");
1304                         goto alloc_err;
1305                 }
1306         }
1307
1308         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1309                                          sizeof(*p_dev->reset_stats));
1310         if (!p_dev->reset_stats) {
1311                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1312                 goto alloc_no_mem;
1313         }
1314
1315         return ECORE_SUCCESS;
1316
1317 alloc_no_mem:
1318         rc = ECORE_NOMEM;
1319 alloc_err:
1320         ecore_resc_free(p_dev);
1321         return rc;
1322 }
1323
1324 void ecore_resc_setup(struct ecore_dev *p_dev)
1325 {
1326         int i;
1327
1328         if (IS_VF(p_dev)) {
1329                 for_each_hwfn(p_dev, i)
1330                         ecore_l2_setup(&p_dev->hwfns[i]);
1331                 return;
1332         }
1333
1334         for_each_hwfn(p_dev, i) {
1335                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1336
1337                 ecore_cxt_mngr_setup(p_hwfn);
1338                 ecore_spq_setup(p_hwfn);
1339                 ecore_eq_setup(p_hwfn);
1340                 ecore_consq_setup(p_hwfn);
1341
1342                 /* Read shadow of current MFW mailbox */
1343                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1344                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1345                             p_hwfn->mcp_info->mfw_mb_cur,
1346                             p_hwfn->mcp_info->mfw_mb_length);
1347
1348                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1349
1350                 ecore_l2_setup(p_hwfn);
1351                 ecore_iov_setup(p_hwfn);
1352         }
1353 }
1354
1355 #define FINAL_CLEANUP_POLL_CNT  (100)
1356 #define FINAL_CLEANUP_POLL_TIME (10)
1357 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1358                                          struct ecore_ptt *p_ptt,
1359                                          u16 id, bool is_vf)
1360 {
1361         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1362         enum _ecore_status_t rc = ECORE_TIMEOUT;
1363
1364 #ifndef ASIC_ONLY
1365         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1366             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1367                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1368                 return ECORE_SUCCESS;
1369         }
1370 #endif
1371
1372         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1373             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1374
1375         if (is_vf)
1376                 id += 0x10;
1377
1378         command |= X_FINAL_CLEANUP_AGG_INT <<
1379             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1380         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1381         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1382         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1383
1384 /* Make sure notification is not set before initiating final cleanup */
1385
1386         if (REG_RD(p_hwfn, addr)) {
1387                 DP_NOTICE(p_hwfn, false,
1388                           "Unexpected; Found final cleanup notification");
1389                 DP_NOTICE(p_hwfn, false,
1390                           " before initiating final cleanup\n");
1391                 REG_WR(p_hwfn, addr, 0);
1392         }
1393
1394         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1395                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1396                    id, command);
1397
1398         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1399
1400         /* Poll until completion */
1401         while (!REG_RD(p_hwfn, addr) && count--)
1402                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1403
1404         if (REG_RD(p_hwfn, addr))
1405                 rc = ECORE_SUCCESS;
1406         else
1407                 DP_NOTICE(p_hwfn, true,
1408                           "Failed to receive FW final cleanup notification\n");
1409
1410         /* Cleanup afterwards */
1411         REG_WR(p_hwfn, addr, 0);
1412
1413         return rc;
1414 }
1415
1416 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1417 {
1418         int hw_mode = 0;
1419
1420         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1421                 hw_mode |= 1 << MODE_BB;
1422         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1423                 hw_mode |= 1 << MODE_K2;
1424         } else {
1425                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1426                           p_hwfn->p_dev->type);
1427                 return ECORE_INVAL;
1428         }
1429
1430         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1431         switch (p_hwfn->p_dev->num_ports_in_engine) {
1432         case 1:
1433                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1434                 break;
1435         case 2:
1436                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1437                 break;
1438         case 4:
1439                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1440                 break;
1441         default:
1442                 DP_NOTICE(p_hwfn, true,
1443                           "num_ports_in_engine = %d not supported\n",
1444                           p_hwfn->p_dev->num_ports_in_engine);
1445                 return ECORE_INVAL;
1446         }
1447
1448         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1449                           &p_hwfn->p_dev->mf_bits))
1450                 hw_mode |= 1 << MODE_MF_SD;
1451         else
1452                 hw_mode |= 1 << MODE_MF_SI;
1453
1454 #ifndef ASIC_ONLY
1455         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1456                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1457                         hw_mode |= 1 << MODE_FPGA;
1458                 } else {
1459                         if (p_hwfn->p_dev->b_is_emul_full)
1460                                 hw_mode |= 1 << MODE_EMUL_FULL;
1461                         else
1462                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1463                 }
1464         } else
1465 #endif
1466                 hw_mode |= 1 << MODE_ASIC;
1467
1468         if (ECORE_IS_CMT(p_hwfn->p_dev))
1469                 hw_mode |= 1 << MODE_100G;
1470
1471         p_hwfn->hw_info.hw_mode = hw_mode;
1472
1473         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1474                    "Configuring function for hw_mode: 0x%08x\n",
1475                    p_hwfn->hw_info.hw_mode);
1476
1477         return ECORE_SUCCESS;
1478 }
1479
1480 #ifndef ASIC_ONLY
1481 /* MFW-replacement initializations for non-ASIC */
1482 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1483                                                struct ecore_ptt *p_ptt)
1484 {
1485         struct ecore_dev *p_dev = p_hwfn->p_dev;
1486         u32 pl_hv = 1;
1487         int i;
1488
1489         if (CHIP_REV_IS_EMUL(p_dev)) {
1490                 if (ECORE_IS_AH(p_dev))
1491                         pl_hv |= 0x600;
1492         }
1493
1494         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1495
1496         if (CHIP_REV_IS_EMUL(p_dev) &&
1497             (ECORE_IS_AH(p_dev)))
1498                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1499                          0x3ffffff);
1500
1501         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1502         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1503         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1504                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1505
1506         if (CHIP_REV_IS_EMUL(p_dev)) {
1507                 if (ECORE_IS_AH(p_dev)) {
1508                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1509                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1510                                  (p_dev->num_ports_in_engine >> 1));
1511
1512                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1513                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1514                 }
1515         }
1516
1517         /* Poll on RBC */
1518         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1519         for (i = 0; i < 100; i++) {
1520                 OSAL_UDELAY(50);
1521                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1522                         break;
1523         }
1524         if (i == 100)
1525                 DP_NOTICE(p_hwfn, true,
1526                           "RBC done failed to complete in PSWRQ2\n");
1527
1528         return ECORE_SUCCESS;
1529 }
1530 #endif
1531
1532 /* Init run time data for all PFs and their VFs on an engine.
1533  * TBD - for VFs - Once we have parent PF info for each VF in
1534  * shmem available as CAU requires knowledge of parent PF for each VF.
1535  */
1536 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1537 {
1538         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1539         int i, igu_sb_id;
1540
1541         for_each_hwfn(p_dev, i) {
1542                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1543                 struct ecore_igu_info *p_igu_info;
1544                 struct ecore_igu_block *p_block;
1545                 struct cau_sb_entry sb_entry;
1546
1547                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1548
1549                 for (igu_sb_id = 0;
1550                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1551                      igu_sb_id++) {
1552                         p_block = &p_igu_info->entry[igu_sb_id];
1553
1554                         if (!p_block->is_pf)
1555                                 continue;
1556
1557                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1558                                                 p_block->function_id, 0, 0);
1559                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1560                                          sb_entry);
1561                 }
1562         }
1563 }
1564
1565 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1566                                        struct ecore_ptt *p_ptt)
1567 {
1568         u32 val, wr_mbs, cache_line_size;
1569
1570         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1571         switch (val) {
1572         case 0:
1573                 wr_mbs = 128;
1574                 break;
1575         case 1:
1576                 wr_mbs = 256;
1577                 break;
1578         case 2:
1579                 wr_mbs = 512;
1580                 break;
1581         default:
1582                 DP_INFO(p_hwfn,
1583                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1584                         val);
1585                 return;
1586         }
1587
1588         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1589         switch (cache_line_size) {
1590         case 32:
1591                 val = 0;
1592                 break;
1593         case 64:
1594                 val = 1;
1595                 break;
1596         case 128:
1597                 val = 2;
1598                 break;
1599         case 256:
1600                 val = 3;
1601                 break;
1602         default:
1603                 DP_INFO(p_hwfn,
1604                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1605                         cache_line_size);
1606         }
1607
1608         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1609                 DP_INFO(p_hwfn,
1610                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1611                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1612
1613         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1614         if (val > 0) {
1615                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1616                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1617         }
1618 }
1619
1620 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1621                                                  struct ecore_ptt *p_ptt,
1622                                                  int hw_mode)
1623 {
1624         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1625         struct ecore_dev *p_dev = p_hwfn->p_dev;
1626         u8 vf_id, max_num_vfs;
1627         u16 num_pfs, pf_id;
1628         u32 concrete_fid;
1629         enum _ecore_status_t rc = ECORE_SUCCESS;
1630
1631         ecore_init_cau_rt_data(p_dev);
1632
1633         /* Program GTT windows */
1634         ecore_gtt_init(p_hwfn, p_ptt);
1635
1636 #ifndef ASIC_ONLY
1637         if (CHIP_REV_IS_EMUL(p_dev)) {
1638                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1639                 if (rc != ECORE_SUCCESS)
1640                         return rc;
1641         }
1642 #endif
1643
1644         if (p_hwfn->mcp_info) {
1645                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1646                         qm_info->pf_rl_en = 1;
1647                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1648                         qm_info->pf_wfq_en = 1;
1649         }
1650
1651         ecore_qm_common_rt_init(p_hwfn,
1652                                 p_dev->num_ports_in_engine,
1653                                 qm_info->max_phys_tcs_per_port,
1654                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1655                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1656                                 qm_info->qm_port_params);
1657
1658         ecore_cxt_hw_init_common(p_hwfn);
1659
1660         ecore_init_cache_line_size(p_hwfn, p_ptt);
1661
1662         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1663         if (rc != ECORE_SUCCESS)
1664                 return rc;
1665
1666         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1667          * need to decide with which value, maybe runtime
1668          */
1669         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1670         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1671
1672         if (ECORE_IS_BB(p_dev)) {
1673                 /* Workaround clears ROCE search for all functions to prevent
1674                  * involving non initialized function in processing ROCE packet.
1675                  */
1676                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1677                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1678                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1679                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1680                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1681                 }
1682                 /* pretend to original PF */
1683                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1684         }
1685
1686         /* Workaround for avoiding CCFC execution error when getting packets
1687          * with CRC errors, and allowing instead the invoking of the FW error
1688          * handler.
1689          * This is not done inside the init tool since it currently can't
1690          * perform a pretending to VFs.
1691          */
1692         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1693         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1694                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1695                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1696                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1697                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1698                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1699                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1700         }
1701         /* pretend to original PF */
1702         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1703
1704         return rc;
1705 }
1706
1707 #ifndef ASIC_ONLY
1708 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1709 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1710
1711 #define PMEG_IF_BYTE_COUNT      8
1712
1713 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1714                              struct ecore_ptt *p_ptt,
1715                              u32 addr, u64 data, u8 reg_type, u8 port)
1716 {
1717         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1718                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1719                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1720                    (8 << PMEG_IF_BYTE_COUNT),
1721                    (reg_type << 25) | (addr << 8) | port,
1722                    (u32)((data >> 32) & 0xffffffff),
1723                    (u32)(data & 0xffffffff));
1724
1725         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1726                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1727                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1728         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1729                  (reg_type << 25) | (addr << 8) | port);
1730         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1731         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1732                  (data >> 32) & 0xffffffff);
1733 }
1734
1735 #define XLPORT_MODE_REG (0x20a)
1736 #define XLPORT_MAC_CONTROL (0x210)
1737 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1738 #define XLPORT_ENABLE_REG (0x20b)
1739
1740 #define XLMAC_CTRL (0x600)
1741 #define XLMAC_MODE (0x601)
1742 #define XLMAC_RX_MAX_SIZE (0x608)
1743 #define XLMAC_TX_CTRL (0x604)
1744 #define XLMAC_PAUSE_CTRL (0x60d)
1745 #define XLMAC_PFC_CTRL (0x60e)
1746
1747 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1748                                     struct ecore_ptt *p_ptt)
1749 {
1750         u8 loopback = 0, port = p_hwfn->port_id * 2;
1751
1752         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1753
1754         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1755         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1756                          port);
1757         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1758         /* XLMAC: SOFT RESET */
1759         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1760         /* XLMAC: Port Speed >= 10Gbps */
1761         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1762         /* XLMAC: Max Size */
1763         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1764         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1765                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1766                          0, port);
1767         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1768         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1769                          0x30ffffc000ULL, 0, port);
1770         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1771                          port); /* XLMAC: TX_EN, RX_EN */
1772         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1773         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1774                          0x1003 | (loopback << 2), 0, port);
1775         /* Enabled Parallel PFC interface */
1776         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1777
1778         /* XLPORT port enable */
1779         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1780 }
1781
1782 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1783                                        struct ecore_ptt *p_ptt)
1784 {
1785         u8 port = p_hwfn->port_id;
1786         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1787
1788         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1789
1790         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1791                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1792                  (port <<
1793                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1794                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1795
1796         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1797                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1798
1799         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1800                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1801
1802         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1803                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1804
1805         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1806                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1807
1808         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1809                  (0xA <<
1810                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1811                  (8 <<
1812                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1813
1814         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1815                  0xa853);
1816 }
1817
1818 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1819                                  struct ecore_ptt *p_ptt)
1820 {
1821         if (ECORE_IS_AH(p_hwfn->p_dev))
1822                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1823         else /* BB */
1824                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1825 }
1826
1827 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1828                                struct ecore_ptt *p_ptt,  u8 port)
1829 {
1830         int port_offset = port ? 0x800 : 0;
1831         u32 xmac_rxctrl = 0;
1832
1833         /* Reset of XMAC */
1834         /* FIXME: move to common start */
1835         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1836                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1837         OSAL_MSLEEP(1);
1838         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1839                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1840
1841         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1842
1843         /* Set the number of ports on the Warp Core to 10G */
1844         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1845
1846         /* Soft reset of XMAC */
1847         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1848                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1849         OSAL_MSLEEP(1);
1850         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1851                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1852
1853         /* FIXME: move to common end */
1854         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1855                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1856
1857         /* Set Max packet size: initialize XMAC block register for port 0 */
1858         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1859
1860         /* CRC append for Tx packets: init XMAC block register for port 1 */
1861         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1862
1863         /* Enable TX and RX: initialize XMAC block register for port 1 */
1864         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1865                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1866         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1867                                XMAC_REG_RX_CTRL_BB + port_offset);
1868         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1869         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1870 }
1871 #endif
1872
1873 static enum _ecore_status_t
1874 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1875                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1876 {
1877         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1878         u32 min_dpis;
1879         u32 n_wids;
1880
1881         /* Calculate DPI size
1882          * ------------------
1883          * The PWM region contains Doorbell Pages. The first is reserverd for
1884          * the kernel for, e.g, L2. The others are free to be used by non-
1885          * trusted applications, typically from user space. Each page, called a
1886          * doorbell page is sectioned into windows that allow doorbells to be
1887          * issued in parallel by the kernel/application. The size of such a
1888          * window (a.k.a. WID) is 1kB.
1889          * Summary:
1890          *    1kB WID x N WIDS = DPI page size
1891          *    DPI page size x N DPIs = PWM region size
1892          * Notes:
1893          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1894          * in order to ensure that two applications won't share the same page.
1895          * It also must contain at least one WID per CPU to allow parallelism.
1896          * It also must be a power of 2, since it is stored as a bit shift.
1897          *
1898          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1899          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1900          * containing 4 WIDs.
1901          */
1902         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1903         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1904         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1905                         ~(OSAL_PAGE_SIZE - 1);
1906         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1907         dpi_count = pwm_region_size / dpi_page_size;
1908
1909         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1910         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1911
1912         /* Update hwfn */
1913         p_hwfn->dpi_size = dpi_page_size;
1914         p_hwfn->dpi_count = dpi_count;
1915
1916         /* Update registers */
1917         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1918
1919         if (dpi_count < min_dpis)
1920                 return ECORE_NORESOURCES;
1921
1922         return ECORE_SUCCESS;
1923 }
1924
1925 enum ECORE_ROCE_EDPM_MODE {
1926         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1927         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1928         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1929 };
1930
1931 static enum _ecore_status_t
1932 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1933                               struct ecore_ptt *p_ptt)
1934 {
1935         u32 pwm_regsize, norm_regsize;
1936         u32 non_pwm_conn, min_addr_reg1;
1937         u32 db_bar_size, n_cpus;
1938         u32 roce_edpm_mode;
1939         u32 pf_dems_shift;
1940         enum _ecore_status_t rc = ECORE_SUCCESS;
1941         u8 cond;
1942
1943         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1944         if (ECORE_IS_CMT(p_hwfn->p_dev))
1945                 db_bar_size /= 2;
1946
1947         /* Calculate doorbell regions
1948          * -----------------------------------
1949          * The doorbell BAR is made of two regions. The first is called normal
1950          * region and the second is called PWM region. In the normal region
1951          * each ICID has its own set of addresses so that writing to that
1952          * specific address identifies the ICID. In the Process Window Mode
1953          * region the ICID is given in the data written to the doorbell. The
1954          * above per PF register denotes the offset in the doorbell BAR in which
1955          * the PWM region begins.
1956          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1957          * non-PWM connection. The calculation below computes the total non-PWM
1958          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1959          * in units of 4,096 bytes.
1960          */
1961         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1962             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1963                                           OSAL_NULL) +
1964             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1965         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1966                                OSAL_PAGE_SIZE);
1967         min_addr_reg1 = norm_regsize / 4096;
1968         pwm_regsize = db_bar_size - norm_regsize;
1969
1970         /* Check that the normal and PWM sizes are valid */
1971         if (db_bar_size < norm_regsize) {
1972                 DP_ERR(p_hwfn->p_dev,
1973                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1974                        db_bar_size, norm_regsize);
1975                 return ECORE_NORESOURCES;
1976         }
1977         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1978                 DP_ERR(p_hwfn->p_dev,
1979                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1980                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1981                        norm_regsize);
1982                 return ECORE_NORESOURCES;
1983         }
1984
1985         /* Calculate number of DPIs */
1986         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1987         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1988             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1989                 /* Either EDPM is mandatory, or we are attempting to allocate a
1990                  * WID per CPU.
1991                  */
1992                 n_cpus = OSAL_NUM_CPUS();
1993                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1994         }
1995
1996         cond = ((rc != ECORE_SUCCESS) &&
1997                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1998                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1999         if (cond || p_hwfn->dcbx_no_edpm) {
2000                 /* Either EDPM is disabled from user configuration, or it is
2001                  * disabled via DCBx, or it is not mandatory and we failed to
2002                  * allocated a WID per CPU.
2003                  */
2004                 n_cpus = 1;
2005                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2006
2007                 /* If we entered this flow due to DCBX then the DPM register is
2008                  * already configured.
2009                  */
2010         }
2011
2012         DP_INFO(p_hwfn,
2013                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2014                 norm_regsize, pwm_regsize);
2015         DP_INFO(p_hwfn,
2016                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2017                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2018                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2019                 "disabled" : "enabled");
2020
2021         /* Check return codes from above calls */
2022         if (rc != ECORE_SUCCESS) {
2023                 DP_ERR(p_hwfn,
2024                        "Failed to allocate enough DPIs\n");
2025                 return ECORE_NORESOURCES;
2026         }
2027
2028         /* Update hwfn */
2029         p_hwfn->dpi_start_offset = norm_regsize;
2030
2031         /* Update registers */
2032         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2033         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2034         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2035         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2036
2037         return ECORE_SUCCESS;
2038 }
2039
2040 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2041                                                struct ecore_ptt *p_ptt,
2042                                                int hw_mode)
2043 {
2044         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2045         u32 val;
2046         enum _ecore_status_t rc = ECORE_SUCCESS;
2047         u8 i;
2048
2049         /* In CMT for non-RoCE packets - use connection based classification */
2050         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2051         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2052                 ppf_to_eng_sel[i] = val;
2053         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2054                          ppf_to_eng_sel);
2055
2056         /* In CMT the gate should be cleared by the 2nd hwfn */
2057         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2058                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2059
2060         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2061                             hw_mode);
2062         if (rc != ECORE_SUCCESS)
2063                 return rc;
2064
2065         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2066
2067 #ifndef ASIC_ONLY
2068         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2069                 return ECORE_SUCCESS;
2070
2071         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2072                 if (ECORE_IS_AH(p_hwfn->p_dev))
2073                         return ECORE_SUCCESS;
2074                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2075                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2076         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2077                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2078                         /* Activate OPTE in CMT */
2079                         u32 val;
2080
2081                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2082                         val |= 0x10;
2083                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2084                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2085                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2086                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2087                         ecore_wr(p_hwfn, p_ptt,
2088                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2089                         ecore_wr(p_hwfn, p_ptt,
2090                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2091                         ecore_wr(p_hwfn, p_ptt,
2092                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2093                                  0x55555555);
2094                 }
2095
2096                 ecore_emul_link_init(p_hwfn, p_ptt);
2097         } else {
2098                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2099         }
2100 #endif
2101
2102         return rc;
2103 }
2104
2105 static enum _ecore_status_t
2106 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2107                  struct ecore_ptt *p_ptt,
2108                  struct ecore_tunnel_info *p_tunn,
2109                  int hw_mode,
2110                  bool b_hw_start,
2111                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2112 {
2113         u8 rel_pf_id = p_hwfn->rel_pf_id;
2114         u32 prs_reg;
2115         enum _ecore_status_t rc = ECORE_SUCCESS;
2116         u16 ctrl;
2117         int pos;
2118
2119         if (p_hwfn->mcp_info) {
2120                 struct ecore_mcp_function_info *p_info;
2121
2122                 p_info = &p_hwfn->mcp_info->func_info;
2123                 if (p_info->bandwidth_min)
2124                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2125
2126                 /* Update rate limit once we'll actually have a link */
2127                 p_hwfn->qm_info.pf_rl = 100000;
2128         }
2129         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2130
2131         ecore_int_igu_init_rt(p_hwfn);
2132
2133         /* Set VLAN in NIG if needed */
2134         if (hw_mode & (1 << MODE_MF_SD)) {
2135                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2136                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2137                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2138                              p_hwfn->hw_info.ovlan);
2139
2140                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2141                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2142                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2143                              1);
2144         }
2145
2146         /* Enable classification by MAC if needed */
2147         if (hw_mode & (1 << MODE_MF_SI)) {
2148                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2149                            "Configuring TAGMAC_CLS_TYPE\n");
2150                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2151                              1);
2152         }
2153
2154         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2155         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2156                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2157         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2158                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2159         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2160
2161         /* perform debug configuration when chip is out of reset */
2162         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2163
2164         /* PF Init sequence */
2165         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2166         if (rc)
2167                 return rc;
2168
2169         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2170         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2171         if (rc)
2172                 return rc;
2173
2174         /* Pure runtime initializations - directly to the HW  */
2175         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2176
2177         /* PCI relaxed ordering causes a decrease in the performance on some
2178          * systems. Till a root cause is found, disable this attribute in the
2179          * PCI config space.
2180          */
2181         /* Not in use @DPDK
2182         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2183         * if (!pos) {
2184         *       DP_NOTICE(p_hwfn, true,
2185         *                 "Failed to find the PCIe Cap\n");
2186         *       return ECORE_IO;
2187         * }
2188         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2189         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2190         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2191         */
2192
2193         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2194         if (rc)
2195                 return rc;
2196         if (b_hw_start) {
2197                 /* enable interrupts */
2198                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2199                 if (rc != ECORE_SUCCESS)
2200                         return rc;
2201
2202                 /* send function start command */
2203                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2204                                        allow_npar_tx_switch);
2205                 if (rc) {
2206                         DP_NOTICE(p_hwfn, true,
2207                                   "Function start ramrod failed\n");
2208                 } else {
2209                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2210                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2211                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2212
2213                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2214                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2215                                          (1 << 2));
2216                                 ecore_wr(p_hwfn, p_ptt,
2217                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2218                                     0x100);
2219                         }
2220                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2221                                    "PRS_REG_SEARCH registers after start PFn\n");
2222                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2223                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2224                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2225                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2226                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2227                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2228                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2229                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2230                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2231                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2232                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2233                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2234                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2235                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2236                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2237                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2238                                    prs_reg);
2239                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2240                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2241                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2242                 }
2243         }
2244         return rc;
2245 }
2246
2247 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2248                                                   struct ecore_ptt *p_ptt,
2249                                                   bool b_enable)
2250 {
2251         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2252
2253         /* Configure the PF's internal FID_enable for master transactions */
2254         ecore_wr(p_hwfn, p_ptt,
2255                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2256
2257         /* Wait until value is set - try for 1 second every 50us */
2258         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2259                 val = ecore_rd(p_hwfn, p_ptt,
2260                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2261                 if (val == set_val)
2262                         break;
2263
2264                 OSAL_UDELAY(50);
2265         }
2266
2267         if (val != set_val) {
2268                 DP_NOTICE(p_hwfn, true,
2269                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2270                 return ECORE_UNKNOWN_ERROR;
2271         }
2272
2273         return ECORE_SUCCESS;
2274 }
2275
2276 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2277                                   struct ecore_ptt *p_main_ptt)
2278 {
2279         /* Read shadow of current MFW mailbox */
2280         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2281         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2282                     p_hwfn->mcp_info->mfw_mb_cur,
2283                     p_hwfn->mcp_info->mfw_mb_length);
2284 }
2285
2286 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2287                                      struct ecore_ptt *p_ptt)
2288 {
2289         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2290                  1 << p_hwfn->abs_pf_id);
2291 }
2292
2293 static void
2294 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2295                            struct ecore_drv_load_params *p_drv_load)
2296 {
2297         /* Make sure that if ecore-client didn't provide inputs, all the
2298          * expected defaults are indeed zero.
2299          */
2300         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2301         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2302         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2303
2304         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2305
2306         if (p_drv_load != OSAL_NULL) {
2307                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2308                                        ECORE_DRV_ROLE_KDUMP :
2309                                        ECORE_DRV_ROLE_OS;
2310                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2311                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2312                 p_load_req->override_force_load =
2313                         p_drv_load->override_force_load;
2314         }
2315 }
2316
2317 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2318                                     struct ecore_hw_init_params *p_params)
2319 {
2320         if (p_params->p_tunn) {
2321                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2322                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2323         }
2324
2325         p_hwfn->b_int_enabled = 1;
2326
2327         return ECORE_SUCCESS;
2328 }
2329
2330 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2331                                    struct ecore_hw_init_params *p_params)
2332 {
2333         struct ecore_load_req_params load_req_params;
2334         u32 load_code, resp, param, drv_mb_param;
2335         bool b_default_mtu = true;
2336         struct ecore_hwfn *p_hwfn;
2337         enum _ecore_status_t rc = ECORE_SUCCESS;
2338         int i;
2339
2340         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2341                 DP_NOTICE(p_dev, false,
2342                           "MSI mode is not supported for CMT devices\n");
2343                 return ECORE_INVAL;
2344         }
2345
2346         if (IS_PF(p_dev)) {
2347                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2348                 if (rc != ECORE_SUCCESS)
2349                         return rc;
2350         }
2351
2352         for_each_hwfn(p_dev, i) {
2353                 p_hwfn = &p_dev->hwfns[i];
2354
2355                 /* If management didn't provide a default, set one of our own */
2356                 if (!p_hwfn->hw_info.mtu) {
2357                         p_hwfn->hw_info.mtu = 1500;
2358                         b_default_mtu = false;
2359                 }
2360
2361                 if (IS_VF(p_dev)) {
2362                         ecore_vf_start(p_hwfn, p_params);
2363                         continue;
2364                 }
2365
2366                 rc = ecore_calc_hw_mode(p_hwfn);
2367                 if (rc != ECORE_SUCCESS)
2368                         return rc;
2369
2370                 ecore_fill_load_req_params(&load_req_params,
2371                                            p_params->p_drv_load_params);
2372                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2373                                         &load_req_params);
2374                 if (rc != ECORE_SUCCESS) {
2375                         DP_NOTICE(p_hwfn, true,
2376                                   "Failed sending a LOAD_REQ command\n");
2377                         return rc;
2378                 }
2379
2380                 load_code = load_req_params.load_code;
2381                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2382                            "Load request was sent. Load code: 0x%x\n",
2383                            load_code);
2384
2385                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2386
2387                 /* CQ75580:
2388                  * When coming back from hiberbate state, the registers from
2389                  * which shadow is read initially are not initialized. It turns
2390                  * out that these registers get initialized during the call to
2391                  * ecore_mcp_load_req request. So we need to reread them here
2392                  * to get the proper shadow register value.
2393                  * Note: This is a workaround for the missing MFW
2394                  * initialization. It may be removed once the implementation
2395                  * is done.
2396                  */
2397                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2398
2399                 /* Only relevant for recovery:
2400                  * Clear the indication after the LOAD_REQ command is responded
2401                  * by the MFW.
2402                  */
2403                 p_dev->recov_in_prog = false;
2404
2405                 p_hwfn->first_on_engine = (load_code ==
2406                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2407
2408                 if (!qm_lock_init) {
2409                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2410                         qm_lock_init = true;
2411                 }
2412
2413                 /* Clean up chip from previous driver if such remains exist.
2414                  * This is not needed when the PF is the first one on the
2415                  * engine, since afterwards we are going to init the FW.
2416                  */
2417                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2418                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2419                                                  p_hwfn->rel_pf_id, false);
2420                         if (rc != ECORE_SUCCESS) {
2421                                 ecore_hw_err_notify(p_hwfn,
2422                                                     ECORE_HW_ERR_RAMROD_FAIL);
2423                                 goto load_err;
2424                         }
2425                 }
2426
2427                 /* Log and clean previous pglue_b errors if such exist */
2428                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2429                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2430
2431                 /* Enable the PF's internal FID_enable in the PXP */
2432                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2433                                                   true);
2434                 if (rc != ECORE_SUCCESS)
2435                         goto load_err;
2436
2437                 switch (load_code) {
2438                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2439                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2440                                                   p_hwfn->hw_info.hw_mode);
2441                         if (rc != ECORE_SUCCESS)
2442                                 break;
2443                         /* Fall into */
2444                 case FW_MSG_CODE_DRV_LOAD_PORT:
2445                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2446                                                 p_hwfn->hw_info.hw_mode);
2447                         if (rc != ECORE_SUCCESS)
2448                                 break;
2449                         /* Fall into */
2450                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2451                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2452                                               p_params->p_tunn,
2453                                               p_hwfn->hw_info.hw_mode,
2454                                               p_params->b_hw_start,
2455                                               p_params->int_mode,
2456                                               p_params->allow_npar_tx_switch);
2457                         break;
2458                 default:
2459                         DP_NOTICE(p_hwfn, false,
2460                                   "Unexpected load code [0x%08x]", load_code);
2461                         rc = ECORE_NOTIMPL;
2462                         break;
2463                 }
2464
2465                 if (rc != ECORE_SUCCESS) {
2466                         DP_NOTICE(p_hwfn, true,
2467                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2468                                   load_code, rc);
2469                         goto load_err;
2470                 }
2471
2472                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2473                 if (rc != ECORE_SUCCESS)
2474                         return rc;
2475
2476                 /* send DCBX attention request command */
2477                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2478                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2479                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2480                                    DRV_MSG_CODE_SET_DCBX,
2481                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2482                                    &param);
2483                 if (rc != ECORE_SUCCESS) {
2484                         DP_NOTICE(p_hwfn, true,
2485                                   "Failed to send DCBX attention request\n");
2486                         return rc;
2487                 }
2488
2489                 p_hwfn->hw_init_done = true;
2490         }
2491
2492         if (IS_PF(p_dev)) {
2493                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2494                 drv_mb_param = STORM_FW_VERSION;
2495                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2496                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2497                                    drv_mb_param, &resp, &param);
2498                 if (rc != ECORE_SUCCESS)
2499                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2500
2501                 if (!b_default_mtu)
2502                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2503                                                       p_hwfn->hw_info.mtu);
2504                 if (rc != ECORE_SUCCESS)
2505                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2506
2507                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2508                                                       p_hwfn->p_main_ptt,
2509                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2510                 if (rc != ECORE_SUCCESS)
2511                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2512         }
2513
2514         return rc;
2515
2516 load_err:
2517         /* The MFW load lock should be released regardless of success or failure
2518          * of initialization.
2519          * TODO: replace this with an attempt to send cancel_load.
2520          */
2521         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2522         return rc;
2523 }
2524
2525 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2526 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2527                                  struct ecore_hwfn *p_hwfn,
2528                                  struct ecore_ptt *p_ptt)
2529 {
2530         int i;
2531
2532         /* close timers */
2533         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2534         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2535         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2536                                                                         i++) {
2537                 if ((!ecore_rd(p_hwfn, p_ptt,
2538                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2539                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2540                         break;
2541
2542                 /* Dependent on number of connection/tasks, possibly
2543                  * 1ms sleep is required between polls
2544                  */
2545                 OSAL_MSLEEP(1);
2546         }
2547
2548         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2549                 return;
2550
2551         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2552                   " [Connection %02x Tasks %02x]\n",
2553                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2554                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2555 }
2556
2557 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2558 {
2559         int j;
2560
2561         for_each_hwfn(p_dev, j) {
2562                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2563                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2564
2565                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2566         }
2567 }
2568
2569 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2570                                                  struct ecore_ptt *p_ptt,
2571                                                  u32 addr, u32 expected_val)
2572 {
2573         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2574
2575         if (val != expected_val) {
2576                 DP_NOTICE(p_hwfn, true,
2577                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2578                           addr, val, expected_val);
2579                 return ECORE_UNKNOWN_ERROR;
2580         }
2581
2582         return ECORE_SUCCESS;
2583 }
2584
2585 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2586 {
2587         struct ecore_hwfn *p_hwfn;
2588         struct ecore_ptt *p_ptt;
2589         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2590         int j;
2591
2592         for_each_hwfn(p_dev, j) {
2593                 p_hwfn = &p_dev->hwfns[j];
2594                 p_ptt = p_hwfn->p_main_ptt;
2595
2596                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2597
2598                 if (IS_VF(p_dev)) {
2599                         ecore_vf_pf_int_cleanup(p_hwfn);
2600                         rc = ecore_vf_pf_reset(p_hwfn);
2601                         if (rc != ECORE_SUCCESS) {
2602                                 DP_NOTICE(p_hwfn, true,
2603                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2604                                           rc);
2605                                 rc2 = ECORE_UNKNOWN_ERROR;
2606                         }
2607                         continue;
2608                 }
2609
2610                 /* mark the hw as uninitialized... */
2611                 p_hwfn->hw_init_done = false;
2612
2613                 /* Send unload command to MCP */
2614                 if (!p_dev->recov_in_prog) {
2615                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2616                         if (rc != ECORE_SUCCESS) {
2617                                 DP_NOTICE(p_hwfn, true,
2618                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2619                                           rc);
2620                                 rc2 = ECORE_UNKNOWN_ERROR;
2621                         }
2622                 }
2623
2624                 OSAL_DPC_SYNC(p_hwfn);
2625
2626                 /* After this point no MFW attentions are expected, e.g. prevent
2627                  * race between pf stop and dcbx pf update.
2628                  */
2629
2630                 rc = ecore_sp_pf_stop(p_hwfn);
2631                 if (rc != ECORE_SUCCESS) {
2632                         DP_NOTICE(p_hwfn, true,
2633                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2634                                   rc);
2635                         rc2 = ECORE_UNKNOWN_ERROR;
2636                 }
2637
2638                 /* perform debug action after PF stop was sent */
2639                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2640
2641                 /* close NIG to BRB gate */
2642                 ecore_wr(p_hwfn, p_ptt,
2643                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2644
2645                 /* close parser */
2646                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2647                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2648                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2649                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2650                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2651
2652                 /* @@@TBD - clean transmission queues (5.b) */
2653                 /* @@@TBD - clean BTB (5.c) */
2654
2655                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2656
2657                 /* @@@TBD - verify DMAE requests are done (8) */
2658
2659                 /* Disable Attention Generation */
2660                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2661                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2662                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2663                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2664                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2665                 if (rc != ECORE_SUCCESS) {
2666                         DP_NOTICE(p_hwfn, true,
2667                                   "Failed to return IGU CAM to default\n");
2668                         rc2 = ECORE_UNKNOWN_ERROR;
2669                 }
2670
2671                 /* Need to wait 1ms to guarantee SBs are cleared */
2672                 OSAL_MSLEEP(1);
2673
2674                 if (!p_dev->recov_in_prog) {
2675                         ecore_verify_reg_val(p_hwfn, p_ptt,
2676                                              QM_REG_USG_CNT_PF_TX, 0);
2677                         ecore_verify_reg_val(p_hwfn, p_ptt,
2678                                              QM_REG_USG_CNT_PF_OTHER, 0);
2679                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2680                 }
2681
2682                 /* Disable PF in HW blocks */
2683                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2684                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2685
2686                 if (!p_dev->recov_in_prog) {
2687                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2688                         if (rc != ECORE_SUCCESS) {
2689                                 DP_NOTICE(p_hwfn, true,
2690                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2691                                           rc);
2692                                 rc2 = ECORE_UNKNOWN_ERROR;
2693                         }
2694                 }
2695         } /* hwfn loop */
2696
2697         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2698                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2699                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2700
2701                  /* Clear the PF's internal FID_enable in the PXP.
2702                   * In CMT this should only be done for first hw-function, and
2703                   * only after all transactions have stopped for all active
2704                   * hw-functions.
2705                   */
2706                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2707                                                   false);
2708                 if (rc != ECORE_SUCCESS) {
2709                         DP_NOTICE(p_hwfn, true,
2710                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2711                                   rc);
2712                         rc2 = ECORE_UNKNOWN_ERROR;
2713                 }
2714         }
2715
2716         return rc2;
2717 }
2718
2719 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2720 {
2721         int j;
2722
2723         for_each_hwfn(p_dev, j) {
2724                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2725                 struct ecore_ptt *p_ptt;
2726
2727                 if (IS_VF(p_dev)) {
2728                         ecore_vf_pf_int_cleanup(p_hwfn);
2729                         continue;
2730                 }
2731                 p_ptt = ecore_ptt_acquire(p_hwfn);
2732                 if (!p_ptt)
2733                         return ECORE_AGAIN;
2734
2735                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2736                            "Shutting down the fastpath\n");
2737
2738                 ecore_wr(p_hwfn, p_ptt,
2739                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2740
2741                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2742                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2743                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2744                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2745                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2746
2747                 /* @@@TBD - clean transmission queues (5.b) */
2748                 /* @@@TBD - clean BTB (5.c) */
2749
2750                 /* @@@TBD - verify DMAE requests are done (8) */
2751
2752                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2753                 /* Need to wait 1ms to guarantee SBs are cleared */
2754                 OSAL_MSLEEP(1);
2755                 ecore_ptt_release(p_hwfn, p_ptt);
2756         }
2757
2758         return ECORE_SUCCESS;
2759 }
2760
2761 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2762 {
2763         struct ecore_ptt *p_ptt;
2764
2765         if (IS_VF(p_hwfn->p_dev))
2766                 return ECORE_SUCCESS;
2767
2768         p_ptt = ecore_ptt_acquire(p_hwfn);
2769         if (!p_ptt)
2770                 return ECORE_AGAIN;
2771
2772         /* If roce info is allocated it means roce is initialized and should
2773          * be enabled in searcher.
2774          */
2775         if (p_hwfn->p_rdma_info) {
2776                 if (p_hwfn->b_rdma_enabled_in_prs)
2777                         ecore_wr(p_hwfn, p_ptt,
2778                                  p_hwfn->rdma_prs_search_reg, 0x1);
2779                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2780         }
2781
2782         /* Re-open incoming traffic */
2783         ecore_wr(p_hwfn, p_ptt,
2784                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2785         ecore_ptt_release(p_hwfn, p_ptt);
2786
2787         return ECORE_SUCCESS;
2788 }
2789
2790 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2791 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2792 {
2793         ecore_ptt_pool_free(p_hwfn);
2794         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2795 }
2796
2797 /* Setup bar access */
2798 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2799 {
2800         /* clear indirect access */
2801         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2802                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2803                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2804                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2805                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2806                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2807                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2808                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2809                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2810         } else {
2811                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2812                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2813                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2814                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2815                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2816                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2817                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2818                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2819         }
2820
2821         /* Clean previous pglue_b errors if such exist */
2822         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2823
2824         /* enable internal target-read */
2825         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2826                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2827 }
2828
2829 static void get_function_id(struct ecore_hwfn *p_hwfn)
2830 {
2831         /* ME Register */
2832         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2833                                                   PXP_PF_ME_OPAQUE_ADDR);
2834
2835         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2836
2837         /* Bits 16-19 from the ME registers are the pf_num */
2838         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2839         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2840                                       PXP_CONCRETE_FID_PFID);
2841         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2842                                     PXP_CONCRETE_FID_PORT);
2843
2844         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2845                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2846                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2847 }
2848
2849 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2850 {
2851         u32 *feat_num = p_hwfn->hw_info.feat_num;
2852         struct ecore_sb_cnt_info sb_cnt;
2853         u32 non_l2_sbs = 0;
2854
2855         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2856         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2857
2858         /* L2 Queues require each: 1 status block. 1 L2 queue */
2859         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2860                 /* Start by allocating VF queues, then PF's */
2861                 feat_num[ECORE_VF_L2_QUE] =
2862                         OSAL_MIN_T(u32,
2863                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2864                                    sb_cnt.iov_cnt);
2865                 feat_num[ECORE_PF_L2_QUE] =
2866                         OSAL_MIN_T(u32,
2867                                    sb_cnt.cnt - non_l2_sbs,
2868                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2869                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2870         }
2871
2872         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2873                 feat_num[ECORE_FCOE_CQ] =
2874                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2875                                                              ECORE_CMDQS_CQS));
2876
2877         if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2878                 feat_num[ECORE_ISCSI_CQ] =
2879                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2880                                                              ECORE_CMDQS_CQS));
2881
2882         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2883                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2884                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2885                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2886                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2887                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2888                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2889                    (int)sb_cnt.cnt);
2890 }
2891
2892 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2893 {
2894         switch (res_id) {
2895         case ECORE_L2_QUEUE:
2896                 return "L2_QUEUE";
2897         case ECORE_VPORT:
2898                 return "VPORT";
2899         case ECORE_RSS_ENG:
2900                 return "RSS_ENG";
2901         case ECORE_PQ:
2902                 return "PQ";
2903         case ECORE_RL:
2904                 return "RL";
2905         case ECORE_MAC:
2906                 return "MAC";
2907         case ECORE_VLAN:
2908                 return "VLAN";
2909         case ECORE_RDMA_CNQ_RAM:
2910                 return "RDMA_CNQ_RAM";
2911         case ECORE_ILT:
2912                 return "ILT";
2913         case ECORE_LL2_QUEUE:
2914                 return "LL2_QUEUE";
2915         case ECORE_CMDQS_CQS:
2916                 return "CMDQS_CQS";
2917         case ECORE_RDMA_STATS_QUEUE:
2918                 return "RDMA_STATS_QUEUE";
2919         case ECORE_BDQ:
2920                 return "BDQ";
2921         case ECORE_SB:
2922                 return "SB";
2923         default:
2924                 return "UNKNOWN_RESOURCE";
2925         }
2926 }
2927
2928 static enum _ecore_status_t
2929 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2930                               struct ecore_ptt *p_ptt,
2931                               enum ecore_resources res_id,
2932                               u32 resc_max_val,
2933                               u32 *p_mcp_resp)
2934 {
2935         enum _ecore_status_t rc;
2936
2937         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2938                                         resc_max_val, p_mcp_resp);
2939         if (rc != ECORE_SUCCESS) {
2940                 DP_NOTICE(p_hwfn, true,
2941                           "MFW response failure for a max value setting of resource %d [%s]\n",
2942                           res_id, ecore_hw_get_resc_name(res_id));
2943                 return rc;
2944         }
2945
2946         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2947                 DP_INFO(p_hwfn,
2948                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2949                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2950
2951         return ECORE_SUCCESS;
2952 }
2953
2954 static enum _ecore_status_t
2955 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2956                             struct ecore_ptt *p_ptt)
2957 {
2958         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2959         u32 resc_max_val, mcp_resp;
2960         u8 res_id;
2961         enum _ecore_status_t rc;
2962
2963         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2964                 /* @DPDK */
2965                 switch (res_id) {
2966                 case ECORE_LL2_QUEUE:
2967                 case ECORE_RDMA_CNQ_RAM:
2968                 case ECORE_RDMA_STATS_QUEUE:
2969                 case ECORE_BDQ:
2970                         resc_max_val = 0;
2971                         break;
2972                 default:
2973                         continue;
2974                 }
2975
2976                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2977                                                    resc_max_val, &mcp_resp);
2978                 if (rc != ECORE_SUCCESS)
2979                         return rc;
2980
2981                 /* There's no point to continue to the next resource if the
2982                  * command is not supported by the MFW.
2983                  * We do continue if the command is supported but the resource
2984                  * is unknown to the MFW. Such a resource will be later
2985                  * configured with the default allocation values.
2986                  */
2987                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2988                         return ECORE_NOTIMPL;
2989         }
2990
2991         return ECORE_SUCCESS;
2992 }
2993
2994 static
2995 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2996                                             enum ecore_resources res_id,
2997                                             u32 *p_resc_num, u32 *p_resc_start)
2998 {
2999         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3000         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3001
3002         switch (res_id) {
3003         case ECORE_L2_QUEUE:
3004                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3005                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3006                 break;
3007         case ECORE_VPORT:
3008                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3009                                  MAX_NUM_VPORTS_BB) / num_funcs;
3010                 break;
3011         case ECORE_RSS_ENG:
3012                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3013                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3014                 break;
3015         case ECORE_PQ:
3016                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3017                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3018                 break;
3019         case ECORE_RL:
3020                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3021                 break;
3022         case ECORE_MAC:
3023         case ECORE_VLAN:
3024                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3025                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3026                 break;
3027         case ECORE_ILT:
3028                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3029                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3030                 break;
3031         case ECORE_LL2_QUEUE:
3032                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3033                 break;
3034         case ECORE_RDMA_CNQ_RAM:
3035         case ECORE_CMDQS_CQS:
3036                 /* CNQ/CMDQS are the same resource */
3037                 /* @DPDK */
3038                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3039                 break;
3040         case ECORE_RDMA_STATS_QUEUE:
3041                 /* @DPDK */
3042                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3043                                  MAX_NUM_VPORTS_BB) / num_funcs;
3044                 break;
3045         case ECORE_BDQ:
3046                 /* @DPDK */
3047                 *p_resc_num = 0;
3048                 break;
3049         default:
3050                 break;
3051         }
3052
3053
3054         switch (res_id) {
3055         case ECORE_BDQ:
3056                 if (!*p_resc_num)
3057                         *p_resc_start = 0;
3058                 break;
3059         case ECORE_SB:
3060                 /* Since we want its value to reflect whether MFW supports
3061                  * the new scheme, have a default of 0.
3062                  */
3063                 *p_resc_num = 0;
3064                 break;
3065         default:
3066                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3067                 break;
3068         }
3069
3070         return ECORE_SUCCESS;
3071 }
3072
3073 static enum _ecore_status_t
3074 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3075                          bool drv_resc_alloc)
3076 {
3077         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3078         u32 mcp_resp, *p_resc_num, *p_resc_start;
3079         enum _ecore_status_t rc;
3080
3081         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3082         p_resc_start = &RESC_START(p_hwfn, res_id);
3083
3084         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3085                                     &dflt_resc_start);
3086         if (rc != ECORE_SUCCESS) {
3087                 DP_ERR(p_hwfn,
3088                        "Failed to get default amount for resource %d [%s]\n",
3089                         res_id, ecore_hw_get_resc_name(res_id));
3090                 return rc;
3091         }
3092
3093 #ifndef ASIC_ONLY
3094         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3095                 *p_resc_num = dflt_resc_num;
3096                 *p_resc_start = dflt_resc_start;
3097                 goto out;
3098         }
3099 #endif
3100
3101         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3102                                      &mcp_resp, p_resc_num, p_resc_start);
3103         if (rc != ECORE_SUCCESS) {
3104                 DP_NOTICE(p_hwfn, true,
3105                           "MFW response failure for an allocation request for"
3106                           " resource %d [%s]\n",
3107                           res_id, ecore_hw_get_resc_name(res_id));
3108                 return rc;
3109         }
3110
3111         /* Default driver values are applied in the following cases:
3112          * - The resource allocation MB command is not supported by the MFW
3113          * - There is an internal error in the MFW while processing the request
3114          * - The resource ID is unknown to the MFW
3115          */
3116         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3117                 DP_INFO(p_hwfn,
3118                         "Failed to receive allocation info for resource %d [%s]."
3119                         " mcp_resp = 0x%x. Applying default values"
3120                         " [%d,%d].\n",
3121                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3122                         dflt_resc_num, dflt_resc_start);
3123
3124                 *p_resc_num = dflt_resc_num;
3125                 *p_resc_start = dflt_resc_start;
3126                 goto out;
3127         }
3128
3129         if ((*p_resc_num != dflt_resc_num ||
3130              *p_resc_start != dflt_resc_start) &&
3131             res_id != ECORE_SB) {
3132                 DP_INFO(p_hwfn,
3133                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3134                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3135                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3136                         drv_resc_alloc ? " - Applying default values" : "");
3137                 if (drv_resc_alloc) {
3138                         *p_resc_num = dflt_resc_num;
3139                         *p_resc_start = dflt_resc_start;
3140                 }
3141         }
3142 out:
3143         return ECORE_SUCCESS;
3144 }
3145
3146 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3147                                                    bool drv_resc_alloc)
3148 {
3149         enum _ecore_status_t rc;
3150         u8 res_id;
3151
3152         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3153                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3154                 if (rc != ECORE_SUCCESS)
3155                         return rc;
3156         }
3157
3158         return ECORE_SUCCESS;
3159 }
3160
3161 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3162                                               struct ecore_ptt *p_ptt,
3163                                               bool drv_resc_alloc)
3164 {
3165         struct ecore_resc_unlock_params resc_unlock_params;
3166         struct ecore_resc_lock_params resc_lock_params;
3167         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3168         u8 res_id;
3169         enum _ecore_status_t rc;
3170 #ifndef ASIC_ONLY
3171         u32 *resc_start = p_hwfn->hw_info.resc_start;
3172         u32 *resc_num = p_hwfn->hw_info.resc_num;
3173         /* For AH, an equal share of the ILT lines between the maximal number of
3174          * PFs is not enough for RoCE. This would be solved by the future
3175          * resource allocation scheme, but isn't currently present for
3176          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3177          * to work - the BB number of ILT lines divided by its max PFs number.
3178          */
3179         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3180 #endif
3181
3182         /* Setting the max values of the soft resources and the following
3183          * resources allocation queries should be atomic. Since several PFs can
3184          * run in parallel - a resource lock is needed.
3185          * If either the resource lock or resource set value commands are not
3186          * supported - skip the the max values setting, release the lock if
3187          * needed, and proceed to the queries. Other failures, including a
3188          * failure to acquire the lock, will cause this function to fail.
3189          * Old drivers that don't acquire the lock can run in parallel, and
3190          * their allocation values won't be affected by the updated max values.
3191          */
3192         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3193                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3194
3195         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3196         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3197                 return rc;
3198         } else if (rc == ECORE_NOTIMPL) {
3199                 DP_INFO(p_hwfn,
3200                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3201         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3202                 DP_NOTICE(p_hwfn, false,
3203                           "Failed to acquire the resource lock for the resource allocation commands\n");
3204                 rc = ECORE_BUSY;
3205                 goto unlock_and_exit;
3206         } else {
3207                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3208                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3209                         DP_NOTICE(p_hwfn, false,
3210                                   "Failed to set the max values of the soft resources\n");
3211                         goto unlock_and_exit;
3212                 } else if (rc == ECORE_NOTIMPL) {
3213                         DP_INFO(p_hwfn,
3214                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3215                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3216                                                    &resc_unlock_params);
3217                         if (rc != ECORE_SUCCESS)
3218                                 DP_INFO(p_hwfn,
3219                                         "Failed to release the resource lock for the resource allocation commands\n");
3220                 }
3221         }
3222
3223         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3224         if (rc != ECORE_SUCCESS)
3225                 goto unlock_and_exit;
3226
3227         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3228                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3229                                            &resc_unlock_params);
3230                 if (rc != ECORE_SUCCESS)
3231                         DP_INFO(p_hwfn,
3232                                 "Failed to release the resource lock for the resource allocation commands\n");
3233         }
3234
3235 #ifndef ASIC_ONLY
3236         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3237                 /* Reduced build contains less PQs */
3238                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3239                         resc_num[ECORE_PQ] = 32;
3240                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3241                             p_hwfn->enabled_func_idx;
3242                 }
3243
3244                 /* For AH emulation, since we have a possible maximal number of
3245                  * 16 enabled PFs, in case there are not enough ILT lines -
3246                  * allocate only first PF as RoCE and have all the other ETH
3247                  * only with less ILT lines.
3248                  */
3249                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3250                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3251                                                          resc_num[ECORE_ILT],
3252                                                          roce_min_ilt_lines);
3253         }
3254
3255         /* Correct the common ILT calculation if PF0 has more */
3256         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3257             p_hwfn->p_dev->b_is_emul_full &&
3258             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3259                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3260                     resc_num[ECORE_ILT];
3261 #endif
3262
3263         /* Sanity for ILT */
3264         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3265             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3266                 DP_NOTICE(p_hwfn, true,
3267                           "Can't assign ILT pages [%08x,...,%08x]\n",
3268                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3269                                                                   ECORE_ILT) -
3270                           1);
3271                 return ECORE_INVAL;
3272         }
3273
3274         /* This will also learn the number of SBs from MFW */
3275         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3276                 return ECORE_INVAL;
3277
3278         ecore_hw_set_feat(p_hwfn);
3279
3280         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3281                    "The numbers for each resource are:\n");
3282         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3283                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3284                            ecore_hw_get_resc_name(res_id),
3285                            RESC_NUM(p_hwfn, res_id),
3286                            RESC_START(p_hwfn, res_id));
3287
3288         return ECORE_SUCCESS;
3289
3290 unlock_and_exit:
3291         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3292                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3293                                       &resc_unlock_params);
3294         return rc;
3295 }
3296
3297 static enum _ecore_status_t
3298 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3299                       struct ecore_ptt *p_ptt,
3300                       struct ecore_hw_prepare_params *p_params)
3301 {
3302         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3303         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3304         struct ecore_mcp_link_capabilities *p_caps;
3305         struct ecore_mcp_link_params *link;
3306         enum _ecore_status_t rc;
3307
3308         /* Read global nvm_cfg address */
3309         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3310
3311         /* Verify MCP has initialized it */
3312         if (!nvm_cfg_addr) {
3313                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3314                 if (p_params->b_relaxed_probe)
3315                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3316                 return ECORE_INVAL;
3317         }
3318
3319 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3320
3321         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3322
3323         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3324                    OFFSETOF(struct nvm_cfg1, glob) +
3325                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3326
3327         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3328
3329         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3330                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3331         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3332                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3333                 break;
3334         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3335                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3336                 break;
3337         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3338                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3339                 break;
3340         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3341                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3342                 break;
3343         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3344                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3345                 break;
3346         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3347                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3348                 break;
3349         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3350                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3351                 break;
3352         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3353                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3354                 break;
3355         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3356                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3357                 break;
3358         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3359                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3360                 break;
3361         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3362                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3363                 break;
3364         default:
3365                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3366                           core_cfg);
3367                 break;
3368         }
3369
3370         /* Read DCBX configuration */
3371         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3372                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3373         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3374                              port_cfg_addr +
3375                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3376         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3377                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3378         switch (dcbx_mode) {
3379         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3380                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3381                 break;
3382         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3383                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3384                 break;
3385         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3386                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3387                 break;
3388         default:
3389                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3390         }
3391
3392         /* Read default link configuration */
3393         link = &p_hwfn->mcp_info->link_input;
3394         p_caps = &p_hwfn->mcp_info->link_capabilities;
3395         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3396             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3397         link_temp = ecore_rd(p_hwfn, p_ptt,
3398                              port_cfg_addr +
3399                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3400         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3401         link->speed.advertised_speeds = link_temp;
3402         p_caps->speed_capabilities = link->speed.advertised_speeds;
3403
3404         link_temp = ecore_rd(p_hwfn, p_ptt,
3405                                  port_cfg_addr +
3406                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
3407         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3408                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3409         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3410                 link->speed.autoneg = true;
3411                 break;
3412         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3413                 link->speed.forced_speed = 1000;
3414                 break;
3415         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3416                 link->speed.forced_speed = 10000;
3417                 break;
3418         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3419                 link->speed.forced_speed = 25000;
3420                 break;
3421         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3422                 link->speed.forced_speed = 40000;
3423                 break;
3424         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3425                 link->speed.forced_speed = 50000;
3426                 break;
3427         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3428                 link->speed.forced_speed = 100000;
3429                 break;
3430         default:
3431                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3432         }
3433
3434         p_caps->default_speed = link->speed.forced_speed;
3435         p_caps->default_speed_autoneg = link->speed.autoneg;
3436
3437         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3438         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3439         link->pause.autoneg = !!(link_temp &
3440                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3441         link->pause.forced_rx = !!(link_temp &
3442                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3443         link->pause.forced_tx = !!(link_temp &
3444                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3445         link->loopback_mode = 0;
3446
3447         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3448                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3449                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3450                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3451                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3452                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3453                 link->eee.enable = true;
3454                 switch (link_temp) {
3455                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3456                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3457                         link->eee.enable = false;
3458                         break;
3459                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3460                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3461                         break;
3462                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3463                         p_caps->eee_lpi_timer =
3464                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3465                         break;
3466                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3467                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3468                         break;
3469                 }
3470
3471                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3472                 link->eee.tx_lpi_enable = link->eee.enable;
3473                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3474         } else {
3475                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3476         }
3477
3478         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3479                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3480                    link->speed.forced_speed, link->speed.advertised_speeds,
3481                    link->speed.autoneg, link->pause.autoneg,
3482                    p_caps->default_eee, p_caps->eee_lpi_timer);
3483
3484         /* Read Multi-function information from shmem */
3485         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3486                    OFFSETOF(struct nvm_cfg1, glob) +
3487                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3488
3489         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3490
3491         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3492             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3493
3494         switch (mf_mode) {
3495         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3496                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3497                 break;
3498         case NVM_CFG1_GLOB_MF_MODE_UFP:
3499                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3500                                          1 << ECORE_MF_UFP_SPECIFIC;
3501                 break;
3502
3503         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3504                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3505                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3506                                          1 << ECORE_MF_LL2_NON_UNICAST |
3507                                          1 << ECORE_MF_INTER_PF_SWITCH |
3508                                          1 << ECORE_MF_DISABLE_ARFS;
3509                 break;
3510         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3511                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3512                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3513                                          1 << ECORE_MF_LL2_NON_UNICAST;
3514                 if (ECORE_IS_BB(p_hwfn->p_dev))
3515                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3516                 break;
3517         }
3518         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3519                 p_hwfn->p_dev->mf_bits);
3520
3521         if (ECORE_IS_CMT(p_hwfn->p_dev))
3522                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3523
3524         /* It's funny since we have another switch, but it's easier
3525          * to throw this away in linux this way. Long term, it might be
3526          * better to have have getters for needed ECORE_MF_* fields,
3527          * convert client code and eliminate this.
3528          */
3529         switch (mf_mode) {
3530         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3531                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3532                 break;
3533         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3534                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3535                 break;
3536         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3537                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3538                 break;
3539         case NVM_CFG1_GLOB_MF_MODE_UFP:
3540                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3541                 break;
3542         }
3543
3544         /* Read Multi-function information from shmem */
3545         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3546                    OFFSETOF(struct nvm_cfg1, glob) +
3547                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3548
3549         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3550         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3551                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3552                                 &p_hwfn->hw_info.device_capabilities);
3553         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3554                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3555                                 &p_hwfn->hw_info.device_capabilities);
3556         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3557                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3558                                 &p_hwfn->hw_info.device_capabilities);
3559         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3560                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3561                                 &p_hwfn->hw_info.device_capabilities);
3562         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3563                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3564                                 &p_hwfn->hw_info.device_capabilities);
3565
3566         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3567         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3568                 rc = ECORE_SUCCESS;
3569                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3570         }
3571
3572         return rc;
3573 }
3574
3575 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3576                                 struct ecore_ptt *p_ptt)
3577 {
3578         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3579         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3580         struct ecore_dev *p_dev = p_hwfn->p_dev;
3581
3582         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3583
3584         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3585          * in the other bits are selected.
3586          * Bits 1-15 are for functions 1-15, respectively, and their value is
3587          * '0' only for enabled functions (function 0 always exists and
3588          * enabled).
3589          * In case of CMT in BB, only the "even" functions are enabled, and thus
3590          * the number of functions for both hwfns is learnt from the same bits.
3591          */
3592         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3593                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3594                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3595         } else { /* E5 */
3596                 reg_function_hide = 0;
3597         }
3598
3599         if (reg_function_hide & 0x1) {
3600                 if (ECORE_IS_BB(p_dev)) {
3601                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3602                                 num_funcs = 0;
3603                                 eng_mask = 0xaaaa;
3604                         } else {
3605                                 num_funcs = 1;
3606                                 eng_mask = 0x5554;
3607                         }
3608                 } else {
3609                         num_funcs = 1;
3610                         eng_mask = 0xfffe;
3611                 }
3612
3613                 /* Get the number of the enabled functions on the engine */
3614                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3615                 while (tmp) {
3616                         if (tmp & 0x1)
3617                                 num_funcs++;
3618                         tmp >>= 0x1;
3619                 }
3620
3621                 /* Get the PF index within the enabled functions */
3622                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3623                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3624                 while (tmp) {
3625                         if (tmp & 0x1)
3626                                 enabled_func_idx--;
3627                         tmp >>= 0x1;
3628                 }
3629         }
3630
3631         p_hwfn->num_funcs_on_engine = num_funcs;
3632         p_hwfn->enabled_func_idx = enabled_func_idx;
3633
3634 #ifndef ASIC_ONLY
3635         if (CHIP_REV_IS_FPGA(p_dev)) {
3636                 DP_NOTICE(p_hwfn, false,
3637                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3638                 p_hwfn->num_funcs_on_engine = 4;
3639         }
3640 #endif
3641
3642         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3643                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3644                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3645                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3646 }
3647
3648 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3649                                       struct ecore_ptt *p_ptt)
3650 {
3651         struct ecore_dev *p_dev = p_hwfn->p_dev;
3652         u32 port_mode;
3653
3654 #ifndef ASIC_ONLY
3655         /* Read the port mode */
3656         if (CHIP_REV_IS_FPGA(p_dev))
3657                 port_mode = 4;
3658         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3659                 /* In CMT on emulation, assume 1 port */
3660                 port_mode = 1;
3661         else
3662 #endif
3663         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3664
3665         if (port_mode < 3) {
3666                 p_dev->num_ports_in_engine = 1;
3667         } else if (port_mode <= 5) {
3668                 p_dev->num_ports_in_engine = 2;
3669         } else {
3670                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3671                           p_dev->num_ports_in_engine);
3672
3673                 /* Default num_ports_in_engine to something */
3674                 p_dev->num_ports_in_engine = 1;
3675         }
3676 }
3677
3678 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3679                                          struct ecore_ptt *p_ptt)
3680 {
3681         struct ecore_dev *p_dev = p_hwfn->p_dev;
3682         u32 port;
3683         int i;
3684
3685         p_dev->num_ports_in_engine = 0;
3686
3687 #ifndef ASIC_ONLY
3688         if (CHIP_REV_IS_EMUL(p_dev)) {
3689                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3690                 switch ((port & 0xf000) >> 12) {
3691                 case 1:
3692                         p_dev->num_ports_in_engine = 1;
3693                         break;
3694                 case 3:
3695                         p_dev->num_ports_in_engine = 2;
3696                         break;
3697                 case 0xf:
3698                         p_dev->num_ports_in_engine = 4;
3699                         break;
3700                 default:
3701                         DP_NOTICE(p_hwfn, false,
3702                                   "Unknown port mode in ECO_RESERVED %08x\n",
3703                                   port);
3704                 }
3705         } else
3706 #endif
3707                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3708                         port = ecore_rd(p_hwfn, p_ptt,
3709                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3710                                         (i * 4));
3711                         if (port & 1)
3712                                 p_dev->num_ports_in_engine++;
3713                 }
3714
3715         if (!p_dev->num_ports_in_engine) {
3716                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3717
3718                 /* Default num_ports_in_engine to something */
3719                 p_dev->num_ports_in_engine = 1;
3720         }
3721 }
3722
3723 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3724                                    struct ecore_ptt *p_ptt)
3725 {
3726         struct ecore_dev *p_dev = p_hwfn->p_dev;
3727
3728         /* Determine the number of ports per engine */
3729         if (ECORE_IS_BB(p_dev))
3730                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3731         else
3732                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3733
3734         /* Get the total number of ports of the device */
3735         if (ECORE_IS_CMT(p_dev)) {
3736                 /* In CMT there is always only one port */
3737                 p_dev->num_ports = 1;
3738 #ifndef ASIC_ONLY
3739         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3740                 p_dev->num_ports = p_dev->num_ports_in_engine *
3741                                    ecore_device_num_engines(p_dev);
3742 #endif
3743         } else {
3744                 u32 addr, global_offsize, global_addr;
3745
3746                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3747                                             PUBLIC_GLOBAL);
3748                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3749                 global_addr = SECTION_ADDR(global_offsize, 0);
3750                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3751                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3752         }
3753 }
3754
3755 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3756                                    struct ecore_ptt *p_ptt)
3757 {
3758         struct ecore_mcp_link_capabilities *p_caps;
3759         u32 eee_status;
3760
3761         p_caps = &p_hwfn->mcp_info->link_capabilities;
3762         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3763                 return;
3764
3765         p_caps->eee_speed_caps = 0;
3766         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3767                               OFFSETOF(struct public_port, eee_status));
3768         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3769                         EEE_SUPPORTED_SPEED_OFFSET;
3770         if (eee_status & EEE_1G_SUPPORTED)
3771                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3772         if (eee_status & EEE_10G_ADV)
3773                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3774 }
3775
3776 static enum _ecore_status_t
3777 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3778                   enum ecore_pci_personality personality,
3779                   struct ecore_hw_prepare_params *p_params)
3780 {
3781         bool drv_resc_alloc = p_params->drv_resc_alloc;
3782         enum _ecore_status_t rc;
3783
3784         /* Since all information is common, only first hwfns should do this */
3785         if (IS_LEAD_HWFN(p_hwfn)) {
3786                 rc = ecore_iov_hw_info(p_hwfn);
3787                 if (rc != ECORE_SUCCESS) {
3788                         if (p_params->b_relaxed_probe)
3789                                 p_params->p_relaxed_res =
3790                                                 ECORE_HW_PREPARE_BAD_IOV;
3791                         else
3792                                 return rc;
3793                 }
3794         }
3795
3796         if (IS_LEAD_HWFN(p_hwfn))
3797                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3798
3799         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3800
3801 #ifndef ASIC_ONLY
3802         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3803 #endif
3804         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3805         if (rc != ECORE_SUCCESS)
3806                 return rc;
3807 #ifndef ASIC_ONLY
3808         }
3809 #endif
3810
3811         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3812         if (rc != ECORE_SUCCESS) {
3813                 if (p_params->b_relaxed_probe)
3814                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3815                 else
3816                         return rc;
3817         }
3818
3819 #ifndef ASIC_ONLY
3820         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3821 #endif
3822                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3823                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3824 #ifndef ASIC_ONLY
3825         } else {
3826                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3827
3828                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3829                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3830         }
3831 #endif
3832
3833         if (ecore_mcp_is_init(p_hwfn)) {
3834                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3835                         p_hwfn->hw_info.ovlan =
3836                             p_hwfn->mcp_info->func_info.ovlan;
3837
3838                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3839
3840                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3841
3842                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3843         }
3844
3845         if (personality != ECORE_PCI_DEFAULT) {
3846                 p_hwfn->hw_info.personality = personality;
3847         } else if (ecore_mcp_is_init(p_hwfn)) {
3848                 enum ecore_pci_personality protocol;
3849
3850                 protocol = p_hwfn->mcp_info->func_info.protocol;
3851                 p_hwfn->hw_info.personality = protocol;
3852         }
3853
3854 #ifndef ASIC_ONLY
3855         /* To overcome ILT lack for emulation, until at least until we'll have
3856          * a definite answer from system about it, allow only PF0 to be RoCE.
3857          */
3858         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3859                 if (!p_hwfn->rel_pf_id)
3860                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3861                 else
3862                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3863         }
3864 #endif
3865
3866         /* although in BB some constellations may support more than 4 tcs,
3867          * that can result in performance penalty in some cases. 4
3868          * represents a good tradeoff between performance and flexibility.
3869          */
3870         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3871
3872         /* start out with a single active tc. This can be increased either
3873          * by dcbx negotiation or by upper layer driver
3874          */
3875         p_hwfn->hw_info.num_active_tc = 1;
3876
3877         ecore_get_num_funcs(p_hwfn, p_ptt);
3878
3879         if (ecore_mcp_is_init(p_hwfn))
3880                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3881
3882         /* In case of forcing the driver's default resource allocation, calling
3883          * ecore_hw_get_resc() should come after initializing the personality
3884          * and after getting the number of functions, since the calculation of
3885          * the resources/features depends on them.
3886          * This order is not harmful if not forcing.
3887          */
3888         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3889         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3890                 rc = ECORE_SUCCESS;
3891                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3892         }
3893
3894         return rc;
3895 }
3896
3897 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3898                                                struct ecore_ptt *p_ptt)
3899 {
3900         struct ecore_dev *p_dev = p_hwfn->p_dev;
3901         u16 device_id_mask;
3902         u32 tmp;
3903
3904         /* Read Vendor Id / Device Id */
3905         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3906                                   &p_dev->vendor_id);
3907         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3908                                   &p_dev->device_id);
3909
3910         /* Determine type */
3911         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3912         switch (device_id_mask) {
3913         case ECORE_DEV_ID_MASK_BB:
3914                 p_dev->type = ECORE_DEV_TYPE_BB;
3915                 break;
3916         case ECORE_DEV_ID_MASK_AH:
3917                 p_dev->type = ECORE_DEV_TYPE_AH;
3918                 break;
3919         default:
3920                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3921                           p_dev->device_id);
3922                 return ECORE_ABORTED;
3923         }
3924
3925         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3926         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3927         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3928         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3929
3930         /* Learn number of HW-functions */
3931         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3932
3933         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3934                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3935                 p_dev->num_hwfns = 2;
3936         } else {
3937                 p_dev->num_hwfns = 1;
3938         }
3939
3940 #ifndef ASIC_ONLY
3941         if (CHIP_REV_IS_EMUL(p_dev)) {
3942                 /* For some reason we have problems with this register
3943                  * in B0 emulation; Simply assume no CMT
3944                  */
3945                 DP_NOTICE(p_dev->hwfns, false,
3946                           "device on emul - assume no CMT\n");
3947                 p_dev->num_hwfns = 1;
3948         }
3949 #endif
3950
3951         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3952         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3953         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3954         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3955
3956         DP_INFO(p_dev->hwfns,
3957                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3958                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3959                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3960                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3961                 p_dev->chip_metal);
3962
3963         if (ECORE_IS_BB_A0(p_dev)) {
3964                 DP_NOTICE(p_dev->hwfns, false,
3965                           "The chip type/rev (BB A0) is not supported!\n");
3966                 return ECORE_ABORTED;
3967         }
3968 #ifndef ASIC_ONLY
3969         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3970                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3971
3972         if (CHIP_REV_IS_EMUL(p_dev)) {
3973                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3974                 if (tmp & (1 << 29)) {
3975                         DP_NOTICE(p_hwfn, false,
3976                                   "Emulation: Running on a FULL build\n");
3977                         p_dev->b_is_emul_full = true;
3978                 } else {
3979                         DP_NOTICE(p_hwfn, false,
3980                                   "Emulation: Running on a REDUCED build\n");
3981                 }
3982         }
3983 #endif
3984
3985         return ECORE_SUCCESS;
3986 }
3987
3988 #ifndef LINUX_REMOVE
3989 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3990 {
3991         int j;
3992
3993         if (IS_VF(p_dev))
3994                 return;
3995
3996         for_each_hwfn(p_dev, j) {
3997                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3998
3999                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4000                            "Mark hw/fw uninitialized\n");
4001
4002                 p_hwfn->hw_init_done = false;
4003
4004                 ecore_ptt_invalidate(p_hwfn);
4005         }
4006 }
4007 #endif
4008
4009 static enum _ecore_status_t
4010 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4011                         void OSAL_IOMEM * p_regview,
4012                         void OSAL_IOMEM * p_doorbells,
4013                         struct ecore_hw_prepare_params *p_params)
4014 {
4015         struct ecore_mdump_retain_data mdump_retain;
4016         struct ecore_dev *p_dev = p_hwfn->p_dev;
4017         struct ecore_mdump_info mdump_info;
4018         enum _ecore_status_t rc = ECORE_SUCCESS;
4019
4020         /* Split PCI bars evenly between hwfns */
4021         p_hwfn->regview = p_regview;
4022         p_hwfn->doorbells = p_doorbells;
4023
4024         if (IS_VF(p_dev))
4025                 return ecore_vf_hw_prepare(p_hwfn);
4026
4027         /* Validate that chip access is feasible */
4028         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4029                 DP_ERR(p_hwfn,
4030                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4031                 if (p_params->b_relaxed_probe)
4032                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4033                 return ECORE_INVAL;
4034         }
4035
4036         get_function_id(p_hwfn);
4037
4038         /* Allocate PTT pool */
4039         rc = ecore_ptt_pool_alloc(p_hwfn);
4040         if (rc) {
4041                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4042                 if (p_params->b_relaxed_probe)
4043                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4044                 goto err0;
4045         }
4046
4047         /* Allocate the main PTT */
4048         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4049
4050         /* First hwfn learns basic information, e.g., number of hwfns */
4051         if (!p_hwfn->my_id) {
4052                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4053                 if (rc != ECORE_SUCCESS) {
4054                         if (p_params->b_relaxed_probe)
4055                                 p_params->p_relaxed_res =
4056                                         ECORE_HW_PREPARE_FAILED_DEV;
4057                         goto err1;
4058                 }
4059         }
4060
4061         ecore_hw_hwfn_prepare(p_hwfn);
4062
4063         /* Initialize MCP structure */
4064         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4065         if (rc) {
4066                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4067                 if (p_params->b_relaxed_probe)
4068                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4069                 goto err1;
4070         }
4071
4072         /* Read the device configuration information from the HW and SHMEM */
4073         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4074                                p_params->personality, p_params);
4075         if (rc) {
4076                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4077                 goto err2;
4078         }
4079
4080         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4081          * called, since among others it sets the ports number in an engine.
4082          */
4083         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4084             !p_dev->recov_in_prog) {
4085                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4086                 if (rc != ECORE_SUCCESS)
4087                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4088         }
4089
4090         /* Check if mdump logs/data are present and update the epoch value */
4091         if (IS_LEAD_HWFN(p_hwfn)) {
4092 #ifndef ASIC_ONLY
4093                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4094 #endif
4095                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4096                                               &mdump_info);
4097                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4098                         DP_NOTICE(p_hwfn, false,
4099                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4100
4101                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4102                                                 &mdump_retain);
4103                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4104                         DP_NOTICE(p_hwfn, false,
4105                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4106                                   mdump_retain.epoch, mdump_retain.pf,
4107                                   mdump_retain.status);
4108
4109                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4110                                            p_params->epoch);
4111 #ifndef ASIC_ONLY
4112                 }
4113 #endif
4114         }
4115
4116         /* Allocate the init RT array and initialize the init-ops engine */
4117         rc = ecore_init_alloc(p_hwfn);
4118         if (rc) {
4119                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4120                 if (p_params->b_relaxed_probe)
4121                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4122                 goto err2;
4123         }
4124 #ifndef ASIC_ONLY
4125         if (CHIP_REV_IS_FPGA(p_dev)) {
4126                 DP_NOTICE(p_hwfn, false,
4127                           "FPGA: workaround; Prevent DMAE parities\n");
4128                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4129                          7);
4130
4131                 DP_NOTICE(p_hwfn, false,
4132                           "FPGA: workaround: Set VF bar0 size\n");
4133                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4134                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4135         }
4136 #endif
4137
4138         return rc;
4139 err2:
4140         if (IS_LEAD_HWFN(p_hwfn))
4141                 ecore_iov_free_hw_info(p_dev);
4142         ecore_mcp_free(p_hwfn);
4143 err1:
4144         ecore_hw_hwfn_free(p_hwfn);
4145 err0:
4146         return rc;
4147 }
4148
4149 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4150                                       struct ecore_hw_prepare_params *p_params)
4151 {
4152         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4153         enum _ecore_status_t rc;
4154
4155         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4156         p_dev->allow_mdump = p_params->allow_mdump;
4157
4158         if (p_params->b_relaxed_probe)
4159                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4160
4161         /* Store the precompiled init data ptrs */
4162         if (IS_PF(p_dev))
4163                 ecore_init_iro_array(p_dev);
4164
4165         /* Initialize the first hwfn - will learn number of hwfns */
4166         rc = ecore_hw_prepare_single(p_hwfn,
4167                                      p_dev->regview,
4168                                      p_dev->doorbells, p_params);
4169         if (rc != ECORE_SUCCESS)
4170                 return rc;
4171
4172         p_params->personality = p_hwfn->hw_info.personality;
4173
4174         /* initilalize 2nd hwfn if necessary */
4175         if (ECORE_IS_CMT(p_dev)) {
4176                 void OSAL_IOMEM *p_regview, *p_doorbell;
4177                 u8 OSAL_IOMEM *addr;
4178
4179                 /* adjust bar offset for second engine */
4180                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4181                                         ecore_hw_bar_size(p_hwfn,
4182                                                           p_hwfn->p_main_ptt,
4183                                                           BAR_ID_0) / 2;
4184                 p_regview = (void OSAL_IOMEM *)addr;
4185
4186                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4187                                         ecore_hw_bar_size(p_hwfn,
4188                                                           p_hwfn->p_main_ptt,
4189                                                           BAR_ID_1) / 2;
4190                 p_doorbell = (void OSAL_IOMEM *)addr;
4191
4192                 /* prepare second hw function */
4193                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4194                                              p_doorbell, p_params);
4195
4196                 /* in case of error, need to free the previously
4197                  * initiliazed hwfn 0.
4198                  */
4199                 if (rc != ECORE_SUCCESS) {
4200                         if (p_params->b_relaxed_probe)
4201                                 p_params->p_relaxed_res =
4202                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4203
4204                         if (IS_PF(p_dev)) {
4205                                 ecore_init_free(p_hwfn);
4206                                 ecore_mcp_free(p_hwfn);
4207                                 ecore_hw_hwfn_free(p_hwfn);
4208                         } else {
4209                                 DP_NOTICE(p_dev, true,
4210                                           "What do we need to free when VF hwfn1 init fails\n");
4211                         }
4212                         return rc;
4213                 }
4214         }
4215
4216         return rc;
4217 }
4218
4219 void ecore_hw_remove(struct ecore_dev *p_dev)
4220 {
4221         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4222         int i;
4223
4224         if (IS_PF(p_dev))
4225                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4226                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4227
4228         for_each_hwfn(p_dev, i) {
4229                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4230
4231                 if (IS_VF(p_dev)) {
4232                         ecore_vf_pf_release(p_hwfn);
4233                         continue;
4234                 }
4235
4236                 ecore_init_free(p_hwfn);
4237                 ecore_hw_hwfn_free(p_hwfn);
4238                 ecore_mcp_free(p_hwfn);
4239
4240 #ifdef CONFIG_ECORE_LOCK_ALLOC
4241                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4242 #endif
4243         }
4244
4245         ecore_iov_free_hw_info(p_dev);
4246 }
4247
4248 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4249                                       struct ecore_chain *p_chain)
4250 {
4251         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4252         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4253         struct ecore_chain_next *p_next;
4254         u32 size, i;
4255
4256         if (!p_virt)
4257                 return;
4258
4259         size = p_chain->elem_size * p_chain->usable_per_page;
4260
4261         for (i = 0; i < p_chain->page_cnt; i++) {
4262                 if (!p_virt)
4263                         break;
4264
4265                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4266                 p_virt_next = p_next->next_virt;
4267                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4268
4269                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4270                                        ECORE_CHAIN_PAGE_SIZE);
4271
4272                 p_virt = p_virt_next;
4273                 p_phys = p_phys_next;
4274         }
4275 }
4276
4277 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4278                                     struct ecore_chain *p_chain)
4279 {
4280         if (!p_chain->p_virt_addr)
4281                 return;
4282
4283         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4284                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4285 }
4286
4287 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4288                                  struct ecore_chain *p_chain)
4289 {
4290         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4291         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4292         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4293
4294         if (!pp_virt_addr_tbl)
4295                 return;
4296
4297         if (!p_pbl_virt)
4298                 goto out;
4299
4300         for (i = 0; i < page_cnt; i++) {
4301                 if (!pp_virt_addr_tbl[i])
4302                         break;
4303
4304                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4305                                        *(dma_addr_t *)p_pbl_virt,
4306                                        ECORE_CHAIN_PAGE_SIZE);
4307
4308                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4309         }
4310
4311         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4312
4313         if (!p_chain->b_external_pbl)
4314                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4315                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4316 out:
4317         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4318 }
4319
4320 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4321 {
4322         switch (p_chain->mode) {
4323         case ECORE_CHAIN_MODE_NEXT_PTR:
4324                 ecore_chain_free_next_ptr(p_dev, p_chain);
4325                 break;
4326         case ECORE_CHAIN_MODE_SINGLE:
4327                 ecore_chain_free_single(p_dev, p_chain);
4328                 break;
4329         case ECORE_CHAIN_MODE_PBL:
4330                 ecore_chain_free_pbl(p_dev, p_chain);
4331                 break;
4332         }
4333 }
4334
4335 static enum _ecore_status_t
4336 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4337                                enum ecore_chain_cnt_type cnt_type,
4338                                osal_size_t elem_size, u32 page_cnt)
4339 {
4340         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4341
4342         /* The actual chain size can be larger than the maximal possible value
4343          * after rounding up the requested elements number to pages, and after
4344          * taking into acount the unusuable elements (next-ptr elements).
4345          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4346          * size/capacity fields are of a u32 type.
4347          */
4348         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4349              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4350             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4351              chain_size > ECORE_U32_MAX)) {
4352                 DP_NOTICE(p_dev, true,
4353                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4354                           (unsigned long)chain_size);
4355                 return ECORE_INVAL;
4356         }
4357
4358         return ECORE_SUCCESS;
4359 }
4360
4361 static enum _ecore_status_t
4362 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4363 {
4364         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4365         dma_addr_t p_phys = 0;
4366         u32 i;
4367
4368         for (i = 0; i < p_chain->page_cnt; i++) {
4369                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4370                                                  ECORE_CHAIN_PAGE_SIZE);
4371                 if (!p_virt) {
4372                         DP_NOTICE(p_dev, true,
4373                                   "Failed to allocate chain memory\n");
4374                         return ECORE_NOMEM;
4375                 }
4376
4377                 if (i == 0) {
4378                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4379                         ecore_chain_reset(p_chain);
4380                 } else {
4381                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4382                                                        p_virt, p_phys);
4383                 }
4384
4385                 p_virt_prev = p_virt;
4386         }
4387         /* Last page's next element should point to the beginning of the
4388          * chain.
4389          */
4390         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4391                                        p_chain->p_virt_addr,
4392                                        p_chain->p_phys_addr);
4393
4394         return ECORE_SUCCESS;
4395 }
4396
4397 static enum _ecore_status_t
4398 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4399 {
4400         dma_addr_t p_phys = 0;
4401         void *p_virt = OSAL_NULL;
4402
4403         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4404         if (!p_virt) {
4405                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4406                 return ECORE_NOMEM;
4407         }
4408
4409         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4410         ecore_chain_reset(p_chain);
4411
4412         return ECORE_SUCCESS;
4413 }
4414
4415 static enum _ecore_status_t
4416 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4417                       struct ecore_chain *p_chain,
4418                       struct ecore_chain_ext_pbl *ext_pbl)
4419 {
4420         u32 page_cnt = p_chain->page_cnt, size, i;
4421         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4422         void **pp_virt_addr_tbl = OSAL_NULL;
4423         u8 *p_pbl_virt = OSAL_NULL;
4424         void *p_virt = OSAL_NULL;
4425
4426         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4427         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4428         if (!pp_virt_addr_tbl) {
4429                 DP_NOTICE(p_dev, true,
4430                           "Failed to allocate memory for the chain virtual addresses table\n");
4431                 return ECORE_NOMEM;
4432         }
4433
4434         /* The allocation of the PBL table is done with its full size, since it
4435          * is expected to be successive.
4436          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4437          * failure, since pp_virt_addr_tbl was previously allocated, and it
4438          * should be saved to allow its freeing during the error flow.
4439          */
4440         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4441
4442         if (ext_pbl == OSAL_NULL) {
4443                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4444         } else {
4445                 p_pbl_virt = ext_pbl->p_pbl_virt;
4446                 p_pbl_phys = ext_pbl->p_pbl_phys;
4447                 p_chain->b_external_pbl = true;
4448         }
4449
4450         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4451                                  pp_virt_addr_tbl);
4452         if (!p_pbl_virt) {
4453                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4454                 return ECORE_NOMEM;
4455         }
4456
4457         for (i = 0; i < page_cnt; i++) {
4458                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4459                                                  ECORE_CHAIN_PAGE_SIZE);
4460                 if (!p_virt) {
4461                         DP_NOTICE(p_dev, true,
4462                                   "Failed to allocate chain memory\n");
4463                         return ECORE_NOMEM;
4464                 }
4465
4466                 if (i == 0) {
4467                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4468                         ecore_chain_reset(p_chain);
4469                 }
4470
4471                 /* Fill the PBL table with the physical address of the page */
4472                 *(dma_addr_t *)p_pbl_virt = p_phys;
4473                 /* Keep the virtual address of the page */
4474                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4475
4476                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4477         }
4478
4479         return ECORE_SUCCESS;
4480 }
4481
4482 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4483                                        enum ecore_chain_use_mode intended_use,
4484                                        enum ecore_chain_mode mode,
4485                                        enum ecore_chain_cnt_type cnt_type,
4486                                        u32 num_elems, osal_size_t elem_size,
4487                                        struct ecore_chain *p_chain,
4488                                        struct ecore_chain_ext_pbl *ext_pbl)
4489 {
4490         u32 page_cnt;
4491         enum _ecore_status_t rc = ECORE_SUCCESS;
4492
4493         if (mode == ECORE_CHAIN_MODE_SINGLE)
4494                 page_cnt = 1;
4495         else
4496                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4497
4498         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4499                                             page_cnt);
4500         if (rc) {
4501                 DP_NOTICE(p_dev, true,
4502                           "Cannot allocate a chain with the given arguments:\n"
4503                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4504                           intended_use, mode, cnt_type, num_elems, elem_size);
4505                 return rc;
4506         }
4507
4508         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4509                                 mode, cnt_type, p_dev->dp_ctx);
4510
4511         switch (mode) {
4512         case ECORE_CHAIN_MODE_NEXT_PTR:
4513                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4514                 break;
4515         case ECORE_CHAIN_MODE_SINGLE:
4516                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4517                 break;
4518         case ECORE_CHAIN_MODE_PBL:
4519                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4520                 break;
4521         }
4522         if (rc)
4523                 goto nomem;
4524
4525         return ECORE_SUCCESS;
4526
4527 nomem:
4528         ecore_chain_free(p_dev, p_chain);
4529         return rc;
4530 }
4531
4532 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4533                                        u16 src_id, u16 *dst_id)
4534 {
4535         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4536                 u16 min, max;
4537
4538                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4539                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4540                 DP_NOTICE(p_hwfn, true,
4541                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4542                           src_id, min, max);
4543
4544                 return ECORE_INVAL;
4545         }
4546
4547         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4548
4549         return ECORE_SUCCESS;
4550 }
4551
4552 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4553                                     u8 src_id, u8 *dst_id)
4554 {
4555         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4556                 u8 min, max;
4557
4558                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4559                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4560                 DP_NOTICE(p_hwfn, true,
4561                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4562                           src_id, min, max);
4563
4564                 return ECORE_INVAL;
4565         }
4566
4567         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4568
4569         return ECORE_SUCCESS;
4570 }
4571
4572 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4573                                       u8 src_id, u8 *dst_id)
4574 {
4575         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4576                 u8 min, max;
4577
4578                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4579                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4580                 DP_NOTICE(p_hwfn, true,
4581                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4582                           src_id, min, max);
4583
4584                 return ECORE_INVAL;
4585         }
4586
4587         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4588
4589         return ECORE_SUCCESS;
4590 }
4591
4592 static enum _ecore_status_t
4593 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4594                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4595                                u32 *p_entry_num)
4596 {
4597         u32 en;
4598         int i;
4599
4600         /* Find a free entry and utilize it */
4601         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4602                 en = ecore_rd(p_hwfn, p_ptt,
4603                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4604                               i * sizeof(u32));
4605                 if (en)
4606                         continue;
4607                 ecore_wr(p_hwfn, p_ptt,
4608                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4609                          2 * i * sizeof(u32), low);
4610                 ecore_wr(p_hwfn, p_ptt,
4611                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4612                          (2 * i + 1) * sizeof(u32), high);
4613                 ecore_wr(p_hwfn, p_ptt,
4614                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4615                          i * sizeof(u32), 0);
4616                 ecore_wr(p_hwfn, p_ptt,
4617                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4618                          i * sizeof(u32), 0);
4619                 ecore_wr(p_hwfn, p_ptt,
4620                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4621                          i * sizeof(u32), 1);
4622                 break;
4623         }
4624
4625         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4626                 return ECORE_NORESOURCES;
4627
4628         *p_entry_num = i;
4629
4630         return ECORE_SUCCESS;
4631 }
4632
4633 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4634                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4635 {
4636         u32 high, low, entry_num;
4637         enum _ecore_status_t rc;
4638
4639         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4640                            &p_hwfn->p_dev->mf_bits))
4641                 return ECORE_SUCCESS;
4642
4643         high = p_filter[1] | (p_filter[0] << 8);
4644         low = p_filter[5] | (p_filter[4] << 8) |
4645               (p_filter[3] << 16) | (p_filter[2] << 24);
4646
4647         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4648                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4649                                                     &entry_num);
4650         if (rc != ECORE_SUCCESS) {
4651                 DP_NOTICE(p_hwfn, false,
4652                           "Failed to find an empty LLH filter to utilize\n");
4653                 return rc;
4654         }
4655
4656         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4657                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4658                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4659                    p_filter[4], p_filter[5], entry_num);
4660
4661         return ECORE_SUCCESS;
4662 }
4663
4664 static enum _ecore_status_t
4665 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4666                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4667                                   u32 *p_entry_num)
4668 {
4669         int i;
4670
4671         /* Find the entry and clean it */
4672         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4673                 if (ecore_rd(p_hwfn, p_ptt,
4674                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4675                              2 * i * sizeof(u32)) != low)
4676                         continue;
4677                 if (ecore_rd(p_hwfn, p_ptt,
4678                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4679                              (2 * i + 1) * sizeof(u32)) != high)
4680                         continue;
4681
4682                 ecore_wr(p_hwfn, p_ptt,
4683                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4684                 ecore_wr(p_hwfn, p_ptt,
4685                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4686                          2 * i * sizeof(u32), 0);
4687                 ecore_wr(p_hwfn, p_ptt,
4688                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4689                          (2 * i + 1) * sizeof(u32), 0);
4690                 break;
4691         }
4692
4693         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4694                 return ECORE_INVAL;
4695
4696         *p_entry_num = i;
4697
4698         return ECORE_SUCCESS;
4699 }
4700
4701 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4702                              struct ecore_ptt *p_ptt, u8 *p_filter)
4703 {
4704         u32 high, low, entry_num;
4705         enum _ecore_status_t rc;
4706
4707         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4708                            &p_hwfn->p_dev->mf_bits))
4709                 return;
4710
4711         high = p_filter[1] | (p_filter[0] << 8);
4712         low = p_filter[5] | (p_filter[4] << 8) |
4713               (p_filter[3] << 16) | (p_filter[2] << 24);
4714
4715         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4716                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4717                                                        low, &entry_num);
4718         if (rc != ECORE_SUCCESS) {
4719                 DP_NOTICE(p_hwfn, false,
4720                           "Tried to remove a non-configured filter\n");
4721                 return;
4722         }
4723
4724
4725         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4726                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4727                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4728                    p_filter[4], p_filter[5], entry_num);
4729 }
4730
4731 static enum _ecore_status_t
4732 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4733                                     struct ecore_ptt *p_ptt,
4734                                     enum ecore_llh_port_filter_type_t type,
4735                                     u32 high, u32 low, u32 *p_entry_num)
4736 {
4737         u32 en;
4738         int i;
4739
4740         /* Find a free entry and utilize it */
4741         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4742                 en = ecore_rd(p_hwfn, p_ptt,
4743                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4744                               i * sizeof(u32));
4745                 if (en)
4746                         continue;
4747                 ecore_wr(p_hwfn, p_ptt,
4748                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4749                          2 * i * sizeof(u32), low);
4750                 ecore_wr(p_hwfn, p_ptt,
4751                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4752                          (2 * i + 1) * sizeof(u32), high);
4753                 ecore_wr(p_hwfn, p_ptt,
4754                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4755                          i * sizeof(u32), 1);
4756                 ecore_wr(p_hwfn, p_ptt,
4757                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4758                          i * sizeof(u32), 1 << type);
4759                 ecore_wr(p_hwfn, p_ptt,
4760                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4761                 break;
4762         }
4763
4764         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4765                 return ECORE_NORESOURCES;
4766
4767         *p_entry_num = i;
4768
4769         return ECORE_SUCCESS;
4770 }
4771
4772 enum _ecore_status_t
4773 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4774                               struct ecore_ptt *p_ptt,
4775                               u16 source_port_or_eth_type,
4776                               u16 dest_port,
4777                               enum ecore_llh_port_filter_type_t type)
4778 {
4779         u32 high, low, entry_num;
4780         enum _ecore_status_t rc;
4781
4782         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4783                            &p_hwfn->p_dev->mf_bits))
4784                 return ECORE_SUCCESS;
4785
4786         high = 0;
4787         low = 0;
4788
4789         switch (type) {
4790         case ECORE_LLH_FILTER_ETHERTYPE:
4791                 high = source_port_or_eth_type;
4792                 break;
4793         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4794         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4795                 low = source_port_or_eth_type << 16;
4796                 break;
4797         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4798         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4799                 low = dest_port;
4800                 break;
4801         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4802         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4803                 low = (source_port_or_eth_type << 16) | dest_port;
4804                 break;
4805         default:
4806                 DP_NOTICE(p_hwfn, true,
4807                           "Non valid LLH protocol filter type %d\n", type);
4808                 return ECORE_INVAL;
4809         }
4810
4811         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4812                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4813                                                          high, low, &entry_num);
4814         if (rc != ECORE_SUCCESS) {
4815                 DP_NOTICE(p_hwfn, false,
4816                           "Failed to find an empty LLH filter to utilize\n");
4817                 return rc;
4818         }
4819         switch (type) {
4820         case ECORE_LLH_FILTER_ETHERTYPE:
4821                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4822                            "ETH type %x is added at %d\n",
4823                            source_port_or_eth_type, entry_num);
4824                 break;
4825         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4826                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4827                            "TCP src port %x is added at %d\n",
4828                            source_port_or_eth_type, entry_num);
4829                 break;
4830         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4831                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4832                            "UDP src port %x is added at %d\n",
4833                            source_port_or_eth_type, entry_num);
4834                 break;
4835         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4836                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4837                            "TCP dst port %x is added at %d\n", dest_port,
4838                            entry_num);
4839                 break;
4840         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4841                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4842                            "UDP dst port %x is added at %d\n", dest_port,
4843                            entry_num);
4844                 break;
4845         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4846                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4847                            "TCP src/dst ports %x/%x are added at %d\n",
4848                            source_port_or_eth_type, dest_port, entry_num);
4849                 break;
4850         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4851                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4852                            "UDP src/dst ports %x/%x are added at %d\n",
4853                            source_port_or_eth_type, dest_port, entry_num);
4854                 break;
4855         }
4856
4857         return ECORE_SUCCESS;
4858 }
4859
4860 static enum _ecore_status_t
4861 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4862                                        struct ecore_ptt *p_ptt,
4863                                        enum ecore_llh_port_filter_type_t type,
4864                                        u32 high, u32 low, u32 *p_entry_num)
4865 {
4866         int i;
4867
4868         /* Find the entry and clean it */
4869         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4870                 if (!ecore_rd(p_hwfn, p_ptt,
4871                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4872                               i * sizeof(u32)))
4873                         continue;
4874                 if (!ecore_rd(p_hwfn, p_ptt,
4875                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4876                               i * sizeof(u32)))
4877                         continue;
4878                 if (!(ecore_rd(p_hwfn, p_ptt,
4879                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4880                                i * sizeof(u32)) & (1 << type)))
4881                         continue;
4882                 if (ecore_rd(p_hwfn, p_ptt,
4883                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4884                              2 * i * sizeof(u32)) != low)
4885                         continue;
4886                 if (ecore_rd(p_hwfn, p_ptt,
4887                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4888                              (2 * i + 1) * sizeof(u32)) != high)
4889                         continue;
4890
4891                 ecore_wr(p_hwfn, p_ptt,
4892                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4893                 ecore_wr(p_hwfn, p_ptt,
4894                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4895                          i * sizeof(u32), 0);
4896                 ecore_wr(p_hwfn, p_ptt,
4897                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4898                          i * sizeof(u32), 0);
4899                 ecore_wr(p_hwfn, p_ptt,
4900                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4901                          2 * i * sizeof(u32), 0);
4902                 ecore_wr(p_hwfn, p_ptt,
4903                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4904                          (2 * i + 1) * sizeof(u32), 0);
4905                 break;
4906         }
4907
4908         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4909                 return ECORE_INVAL;
4910
4911         *p_entry_num = i;
4912
4913         return ECORE_SUCCESS;
4914 }
4915
4916 void
4917 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4918                                  struct ecore_ptt *p_ptt,
4919                                  u16 source_port_or_eth_type,
4920                                  u16 dest_port,
4921                                  enum ecore_llh_port_filter_type_t type)
4922 {
4923         u32 high, low, entry_num;
4924         enum _ecore_status_t rc;
4925
4926         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4927                            &p_hwfn->p_dev->mf_bits))
4928                 return;
4929
4930         high = 0;
4931         low = 0;
4932
4933         switch (type) {
4934         case ECORE_LLH_FILTER_ETHERTYPE:
4935                 high = source_port_or_eth_type;
4936                 break;
4937         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4938         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4939                 low = source_port_or_eth_type << 16;
4940                 break;
4941         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4942         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4943                 low = dest_port;
4944                 break;
4945         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4946         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4947                 low = (source_port_or_eth_type << 16) | dest_port;
4948                 break;
4949         default:
4950                 DP_NOTICE(p_hwfn, true,
4951                           "Non valid LLH protocol filter type %d\n", type);
4952                 return;
4953         }
4954
4955         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4956                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4957                                                             high, low,
4958                                                             &entry_num);
4959         if (rc != ECORE_SUCCESS) {
4960                 DP_NOTICE(p_hwfn, false,
4961                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4962                           type, source_port_or_eth_type, dest_port);
4963                 return;
4964         }
4965
4966         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4967                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4968                    type, source_port_or_eth_type, dest_port, entry_num);
4969 }
4970
4971 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4972                                               struct ecore_ptt *p_ptt)
4973 {
4974         int i;
4975
4976         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4977                 return;
4978
4979         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4980                 ecore_wr(p_hwfn, p_ptt,
4981                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4982                          i * sizeof(u32), 0);
4983                 ecore_wr(p_hwfn, p_ptt,
4984                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4985                          2 * i * sizeof(u32), 0);
4986                 ecore_wr(p_hwfn, p_ptt,
4987                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4988                          (2 * i + 1) * sizeof(u32), 0);
4989         }
4990 }
4991
4992 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4993                              struct ecore_ptt *p_ptt)
4994 {
4995         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4996                            &p_hwfn->p_dev->mf_bits) &&
4997             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4998                            &p_hwfn->p_dev->mf_bits))
4999                 return;
5000
5001         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5002                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5003 }
5004
5005 enum _ecore_status_t
5006 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5007                                   struct ecore_ptt *p_ptt)
5008 {
5009         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5010                 ecore_wr(p_hwfn, p_ptt,
5011                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5012                          1 << p_hwfn->abs_pf_id / 2);
5013                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5014                 return ECORE_SUCCESS;
5015         }
5016
5017         DP_NOTICE(p_hwfn, false,
5018                   "This function can't be set as default\n");
5019         return ECORE_INVAL;
5020 }
5021
5022 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5023                                                struct ecore_ptt *p_ptt,
5024                                                u32 hw_addr, void *p_eth_qzone,
5025                                                osal_size_t eth_qzone_size,
5026                                                u8 timeset)
5027 {
5028         struct coalescing_timeset *p_coal_timeset;
5029
5030         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5031                 DP_NOTICE(p_hwfn, true,
5032                           "Coalescing configuration not enabled\n");
5033                 return ECORE_INVAL;
5034         }
5035
5036         p_coal_timeset = p_eth_qzone;
5037         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5038         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5039         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5040         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5041
5042         return ECORE_SUCCESS;
5043 }
5044
5045 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5046                                               u16 rx_coal, u16 tx_coal,
5047                                               void *p_handle)
5048 {
5049         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5050         enum _ecore_status_t rc = ECORE_SUCCESS;
5051         struct ecore_ptt *p_ptt;
5052
5053         /* TODO - Configuring a single queue's coalescing but
5054          * claiming all queues are abiding same configuration
5055          * for PF and VF both.
5056          */
5057
5058         if (IS_VF(p_hwfn->p_dev))
5059                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5060                                                 tx_coal, p_cid);
5061
5062         p_ptt = ecore_ptt_acquire(p_hwfn);
5063         if (!p_ptt)
5064                 return ECORE_AGAIN;
5065
5066         if (rx_coal) {
5067                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5068                 if (rc)
5069                         goto out;
5070                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5071         }
5072
5073         if (tx_coal) {
5074                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5075                 if (rc)
5076                         goto out;
5077                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5078         }
5079 out:
5080         ecore_ptt_release(p_hwfn, p_ptt);
5081
5082         return rc;
5083 }
5084
5085 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5086                                             struct ecore_ptt *p_ptt,
5087                                             u16 coalesce,
5088                                             struct ecore_queue_cid *p_cid)
5089 {
5090         struct ustorm_eth_queue_zone eth_qzone;
5091         u8 timeset, timer_res;
5092         u32 address;
5093         enum _ecore_status_t rc;
5094
5095         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5096         if (coalesce <= 0x7F) {
5097                 timer_res = 0;
5098         } else if (coalesce <= 0xFF) {
5099                 timer_res = 1;
5100         } else if (coalesce <= 0x1FF) {
5101                 timer_res = 2;
5102         } else {
5103                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5104                 return ECORE_INVAL;
5105         }
5106         timeset = (u8)(coalesce >> timer_res);
5107
5108         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5109                                      p_cid->sb_igu_id, false);
5110         if (rc != ECORE_SUCCESS)
5111                 goto out;
5112
5113         address = BAR0_MAP_REG_USDM_RAM +
5114                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5115
5116         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5117                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5118         if (rc != ECORE_SUCCESS)
5119                 goto out;
5120
5121 out:
5122         return rc;
5123 }
5124
5125 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5126                                             struct ecore_ptt *p_ptt,
5127                                             u16 coalesce,
5128                                             struct ecore_queue_cid *p_cid)
5129 {
5130         struct xstorm_eth_queue_zone eth_qzone;
5131         u8 timeset, timer_res;
5132         u32 address;
5133         enum _ecore_status_t rc;
5134
5135         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5136         if (coalesce <= 0x7F) {
5137                 timer_res = 0;
5138         } else if (coalesce <= 0xFF) {
5139                 timer_res = 1;
5140         } else if (coalesce <= 0x1FF) {
5141                 timer_res = 2;
5142         } else {
5143                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5144                 return ECORE_INVAL;
5145         }
5146
5147         timeset = (u8)(coalesce >> timer_res);
5148
5149         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5150                                      p_cid->sb_igu_id, true);
5151         if (rc != ECORE_SUCCESS)
5152                 goto out;
5153
5154         address = BAR0_MAP_REG_XSDM_RAM +
5155                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5156
5157         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5158                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5159 out:
5160         return rc;
5161 }
5162
5163 /* Calculate final WFQ values for all vports and configure it.
5164  * After this configuration each vport must have
5165  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5166  */
5167 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5168                                                struct ecore_ptt *p_ptt,
5169                                                u32 min_pf_rate)
5170 {
5171         struct init_qm_vport_params *vport_params;
5172         int i;
5173
5174         vport_params = p_hwfn->qm_info.qm_vport_params;
5175
5176         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5177                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5178
5179                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5180                     min_pf_rate;
5181                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5182                                      vport_params[i].first_tx_pq_id,
5183                                      vport_params[i].vport_wfq);
5184         }
5185 }
5186
5187 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5188 {
5189         int i;
5190
5191         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5192                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5193 }
5194
5195 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5196                                              struct ecore_ptt *p_ptt)
5197 {
5198         struct init_qm_vport_params *vport_params;
5199         int i;
5200
5201         vport_params = p_hwfn->qm_info.qm_vport_params;
5202
5203         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5204                 ecore_init_wfq_default_param(p_hwfn);
5205                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5206                                      vport_params[i].first_tx_pq_id,
5207                                      vport_params[i].vport_wfq);
5208         }
5209 }
5210
5211 /* This function performs several validations for WFQ
5212  * configuration and required min rate for a given vport
5213  * 1. req_rate must be greater than one percent of min_pf_rate.
5214  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5215  *    rates to get less than one percent of min_pf_rate.
5216  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5217  */
5218 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5219                                                  u16 vport_id, u32 req_rate,
5220                                                  u32 min_pf_rate)
5221 {
5222         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5223         int non_requested_count = 0, req_count = 0, i, num_vports;
5224
5225         num_vports = p_hwfn->qm_info.num_vports;
5226
5227 /* Accounting for the vports which are configured for WFQ explicitly */
5228
5229         for (i = 0; i < num_vports; i++) {
5230                 u32 tmp_speed;
5231
5232                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5233                         req_count++;
5234                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5235                         total_req_min_rate += tmp_speed;
5236                 }
5237         }
5238
5239         /* Include current vport data as well */
5240         req_count++;
5241         total_req_min_rate += req_rate;
5242         non_requested_count = num_vports - req_count;
5243
5244         /* validate possible error cases */
5245         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5246                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5247                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5248                            vport_id, req_rate, min_pf_rate);
5249                 return ECORE_INVAL;
5250         }
5251
5252         /* TBD - for number of vports greater than 100 */
5253         if (num_vports > ECORE_WFQ_UNIT) {
5254                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5255                            "Number of vports is greater than %d\n",
5256                            ECORE_WFQ_UNIT);
5257                 return ECORE_INVAL;
5258         }
5259
5260         if (total_req_min_rate > min_pf_rate) {
5261                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5262                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5263                            total_req_min_rate, min_pf_rate);
5264                 return ECORE_INVAL;
5265         }
5266
5267         /* Data left for non requested vports */
5268         total_left_rate = min_pf_rate - total_req_min_rate;
5269         left_rate_per_vp = total_left_rate / non_requested_count;
5270
5271         /* validate if non requested get < 1% of min bw */
5272         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5273                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5274                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5275                            left_rate_per_vp, min_pf_rate);
5276                 return ECORE_INVAL;
5277         }
5278
5279         /* now req_rate for given vport passes all scenarios.
5280          * assign final wfq rates to all vports.
5281          */
5282         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5283         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5284
5285         for (i = 0; i < num_vports; i++) {
5286                 if (p_hwfn->qm_info.wfq_data[i].configured)
5287                         continue;
5288
5289                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5290         }
5291
5292         return ECORE_SUCCESS;
5293 }
5294
5295 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5296                                        struct ecore_ptt *p_ptt,
5297                                        u16 vp_id, u32 rate)
5298 {
5299         struct ecore_mcp_link_state *p_link;
5300         int rc = ECORE_SUCCESS;
5301
5302         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5303
5304         if (!p_link->min_pf_rate) {
5305                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5306                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5307                 return rc;
5308         }
5309
5310         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5311
5312         if (rc == ECORE_SUCCESS)
5313                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5314                                                    p_link->min_pf_rate);
5315         else
5316                 DP_NOTICE(p_hwfn, false,
5317                           "Validation failed while configuring min rate\n");
5318
5319         return rc;
5320 }
5321
5322 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5323                                                    struct ecore_ptt *p_ptt,
5324                                                    u32 min_pf_rate)
5325 {
5326         bool use_wfq = false;
5327         int rc = ECORE_SUCCESS;
5328         u16 i;
5329
5330         /* Validate all pre configured vports for wfq */
5331         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5332                 u32 rate;
5333
5334                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5335                         continue;
5336
5337                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5338                 use_wfq = true;
5339
5340                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5341                 if (rc != ECORE_SUCCESS) {
5342                         DP_NOTICE(p_hwfn, false,
5343                                   "WFQ validation failed while configuring min rate\n");
5344                         break;
5345                 }
5346         }
5347
5348         if (rc == ECORE_SUCCESS && use_wfq)
5349                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5350         else
5351                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5352
5353         return rc;
5354 }
5355
5356 /* Main API for ecore clients to configure vport min rate.
5357  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5358  * rate - Speed in Mbps needs to be assigned to a given vport.
5359  */
5360 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5361 {
5362         int i, rc = ECORE_INVAL;
5363
5364         /* TBD - for multiple hardware functions - that is 100 gig */
5365         if (ECORE_IS_CMT(p_dev)) {
5366                 DP_NOTICE(p_dev, false,
5367                           "WFQ configuration is not supported for this device\n");
5368                 return rc;
5369         }
5370
5371         for_each_hwfn(p_dev, i) {
5372                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5373                 struct ecore_ptt *p_ptt;
5374
5375                 p_ptt = ecore_ptt_acquire(p_hwfn);
5376                 if (!p_ptt)
5377                         return ECORE_TIMEOUT;
5378
5379                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5380
5381                 if (rc != ECORE_SUCCESS) {
5382                         ecore_ptt_release(p_hwfn, p_ptt);
5383                         return rc;
5384                 }
5385
5386                 ecore_ptt_release(p_hwfn, p_ptt);
5387         }
5388
5389         return rc;
5390 }
5391
5392 /* API to configure WFQ from mcp link change */
5393 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5394                                            struct ecore_ptt *p_ptt,
5395                                            u32 min_pf_rate)
5396 {
5397         int i;
5398
5399         /* TBD - for multiple hardware functions - that is 100 gig */
5400         if (ECORE_IS_CMT(p_dev)) {
5401                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5402                            "WFQ configuration is not supported for this device\n");
5403                 return;
5404         }
5405
5406         for_each_hwfn(p_dev, i) {
5407                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5408
5409                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5410                                                         min_pf_rate);
5411         }
5412 }
5413
5414 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5415                                        struct ecore_ptt *p_ptt,
5416                                        struct ecore_mcp_link_state *p_link,
5417                                        u8 max_bw)
5418 {
5419         int rc = ECORE_SUCCESS;
5420
5421         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5422
5423         if (!p_link->line_speed && (max_bw != 100))
5424                 return rc;
5425
5426         p_link->speed = (p_link->line_speed * max_bw) / 100;
5427         p_hwfn->qm_info.pf_rl = p_link->speed;
5428
5429         /* Since the limiter also affects Tx-switched traffic, we don't want it
5430          * to limit such traffic in case there's no actual limit.
5431          * In that case, set limit to imaginary high boundary.
5432          */
5433         if (max_bw == 100)
5434                 p_hwfn->qm_info.pf_rl = 100000;
5435
5436         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5437                               p_hwfn->qm_info.pf_rl);
5438
5439         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5440                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5441                    p_link->speed);
5442
5443         return rc;
5444 }
5445
5446 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5447 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5448 {
5449         int i, rc = ECORE_INVAL;
5450
5451         if (max_bw < 1 || max_bw > 100) {
5452                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5453                 return rc;
5454         }
5455
5456         for_each_hwfn(p_dev, i) {
5457                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5458                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5459                 struct ecore_mcp_link_state *p_link;
5460                 struct ecore_ptt *p_ptt;
5461
5462                 p_link = &p_lead->mcp_info->link_output;
5463
5464                 p_ptt = ecore_ptt_acquire(p_hwfn);
5465                 if (!p_ptt)
5466                         return ECORE_TIMEOUT;
5467
5468                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5469                                                         p_link, max_bw);
5470
5471                 ecore_ptt_release(p_hwfn, p_ptt);
5472
5473                 if (rc != ECORE_SUCCESS)
5474                         break;
5475         }
5476
5477         return rc;
5478 }
5479
5480 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5481                                        struct ecore_ptt *p_ptt,
5482                                        struct ecore_mcp_link_state *p_link,
5483                                        u8 min_bw)
5484 {
5485         int rc = ECORE_SUCCESS;
5486
5487         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5488         p_hwfn->qm_info.pf_wfq = min_bw;
5489
5490         if (!p_link->line_speed)
5491                 return rc;
5492
5493         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5494
5495         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5496
5497         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5498                    "Configured MIN bandwidth to be %d Mb/sec\n",
5499                    p_link->min_pf_rate);
5500
5501         return rc;
5502 }
5503
5504 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5505 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5506 {
5507         int i, rc = ECORE_INVAL;
5508
5509         if (min_bw < 1 || min_bw > 100) {
5510                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5511                 return rc;
5512         }
5513
5514         for_each_hwfn(p_dev, i) {
5515                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5516                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5517                 struct ecore_mcp_link_state *p_link;
5518                 struct ecore_ptt *p_ptt;
5519
5520                 p_link = &p_lead->mcp_info->link_output;
5521
5522                 p_ptt = ecore_ptt_acquire(p_hwfn);
5523                 if (!p_ptt)
5524                         return ECORE_TIMEOUT;
5525
5526                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5527                                                         p_link, min_bw);
5528                 if (rc != ECORE_SUCCESS) {
5529                         ecore_ptt_release(p_hwfn, p_ptt);
5530                         return rc;
5531                 }
5532
5533                 if (p_link->min_pf_rate) {
5534                         u32 min_rate = p_link->min_pf_rate;
5535
5536                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5537                                                                      p_ptt,
5538                                                                      min_rate);
5539                 }
5540
5541                 ecore_ptt_release(p_hwfn, p_ptt);
5542         }
5543
5544         return rc;
5545 }
5546
5547 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5548 {
5549         struct ecore_mcp_link_state *p_link;
5550
5551         p_link = &p_hwfn->mcp_info->link_output;
5552
5553         if (p_link->min_pf_rate)
5554                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5555
5556         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5557                     sizeof(*p_hwfn->qm_info.wfq_data) *
5558                     p_hwfn->qm_info.num_vports);
5559 }
5560
5561 int ecore_device_num_engines(struct ecore_dev *p_dev)
5562 {
5563         return ECORE_IS_BB(p_dev) ? 2 : 1;
5564 }
5565
5566 int ecore_device_num_ports(struct ecore_dev *p_dev)
5567 {
5568         return p_dev->num_ports;
5569 }
5570
5571 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5572                           __le16 *fw_mid,
5573                           __le16 *fw_lsb,
5574                           u8 *mac)
5575 {
5576         ((u8 *)fw_msb)[0] = mac[1];
5577         ((u8 *)fw_msb)[1] = mac[0];
5578         ((u8 *)fw_mid)[0] = mac[3];
5579         ((u8 *)fw_mid)[1] = mac[2];
5580         ((u8 *)fw_lsb)[0] = mac[5];
5581         ((u8 *)fw_lsb)[1] = mac[4];
5582 }