drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_mcp.h"
  25 #include "ecore_hw_defs.h"
  26 #include "mcp_public.h"
  27 #include "ecore_iro.h"
  28 #include "nvm_cfg.h"
  29 #include "ecore_dev_api.h"
  30
  31 /* Configurable */
  32 #define ECORE_MIN_DPIS          (4)     /* The minimal number of DPIs required
  33                                          * load the driver. The number was
  34                                          * arbitrarily set.
  35                                          */
  36
  37 /* Derived */
  38 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  39
  40 enum BAR_ID {
  41         BAR_ID_0,               /* used for GRC */
  42         BAR_ID_1                /* Used for doorbells */
  43 };
  44
  45 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  46 {
  47         u32 bar_reg = (bar_id == BAR_ID_0 ?
  48                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  49         u32 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  50
  51         /* The above registers were updated in the past only in CMT mode. Since
  52          * they were found to be useful MFW started updating them from 8.7.7.0.
  53          * In older MFW versions they are set to 0 which means disabled.
  54          */
  55         if (!val) {
  56                 if (p_hwfn->p_dev->num_hwfns > 1) {
  57                         DP_NOTICE(p_hwfn, false,
  58                                   "BAR size not configured. Assuming BAR"
  59                                   " size of 256kB for GRC and 512kB for DB\n");
  60                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  61                 }
  62
  63                 DP_NOTICE(p_hwfn, false,
  64                           "BAR size not configured. Assuming BAR"
  65                           " size of 512kB for GRC and 512kB for DB\n");
  66                 return 512 * 1024;
  67         }
  68
  69         return 1 << (val + 15);
  70 }
  71
  72 void ecore_init_dp(struct ecore_dev *p_dev,
  73                    u32 dp_module, u8 dp_level, void *dp_ctx)
  74 {
  75         u32 i;
  76
  77         p_dev->dp_level = dp_level;
  78         p_dev->dp_module = dp_module;
  79         p_dev->dp_ctx = dp_ctx;
  80         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  81                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
  82
  83                 p_hwfn->dp_level = dp_level;
  84                 p_hwfn->dp_module = dp_module;
  85                 p_hwfn->dp_ctx = dp_ctx;
  86         }
  87 }
  88
  89 void ecore_init_struct(struct ecore_dev *p_dev)
  90 {
  91         u8 i;
  92
  93         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  94                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
  95
  96                 p_hwfn->p_dev = p_dev;
  97                 p_hwfn->my_id = i;
  98                 p_hwfn->b_active = false;
  99
 100                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 101                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 102         }
 103
 104         /* hwfn 0 is always active */
 105         p_dev->hwfns[0].b_active = true;
 106
 107         /* set the default cache alignment to 128 (may be overridden later) */
 108         p_dev->cache_shift = 7;
 109 }
 110
 111 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 112 {
 113         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 114
 115         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 116         qm_info->qm_pq_params = OSAL_NULL;
 117         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 118         qm_info->qm_vport_params = OSAL_NULL;
 119         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 120         qm_info->qm_port_params = OSAL_NULL;
 121         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 122         qm_info->wfq_data = OSAL_NULL;
 123 }
 124
 125 void ecore_resc_free(struct ecore_dev *p_dev)
 126 {
 127         int i;
 128
 129         OSAL_FREE(p_dev, p_dev->fw_data);
 130         p_dev->fw_data = OSAL_NULL;
 131
 132         OSAL_FREE(p_dev, p_dev->reset_stats);
 133
 134         for_each_hwfn(p_dev, i) {
 135                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 136
 137                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 138                 p_hwfn->p_tx_cids = OSAL_NULL;
 139                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 140                 p_hwfn->p_rx_cids = OSAL_NULL;
 141         }
 142
 143         for_each_hwfn(p_dev, i) {
 144                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 145
 146                 ecore_cxt_mngr_free(p_hwfn);
 147                 ecore_qm_info_free(p_hwfn);
 148                 ecore_spq_free(p_hwfn);
 149                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 150                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 151                 ecore_int_free(p_hwfn);
 152                 ecore_dmae_info_free(p_hwfn);
 153                 /* @@@TBD Flush work-queue ? */
 154         }
 155 }
 156
 157 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 158                                                bool b_sleepable)
 159 {
 160         u8 num_vports, vf_offset = 0, i, vport_id, num_ports;
 161         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 162         struct init_qm_port_params *p_qm_port;
 163         u16 num_pqs, multi_cos_tcs = 1;
 164         u16 num_vfs = 0;
 165
 166         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 167
 168 #ifndef ASIC_ONLY
 169         /* @TMP - Don't allocate QM queues for VFs on emulation */
 170         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 171                 DP_NOTICE(p_hwfn, false,
 172                           "Emulation - skip configuring QM queues for VFs\n");
 173                 num_vfs = 0;
 174         }
 175 #endif
 176
 177         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 178         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 179
 180         /* Sanity checking that setup requires legal number of resources */
 181         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 182                 DP_ERR(p_hwfn,
 183                        "Need too many Physical queues - 0x%04x when"
 184                         " only %04x are available\n",
 185                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 186                 return ECORE_INVAL;
 187         }
 188
 189         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 190          * then special queues, then per-VF PQ.
 191          */
 192         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 193                                             b_sleepable ? GFP_KERNEL :
 194                                             GFP_ATOMIC,
 195                                             sizeof(struct init_qm_pq_params) *
 196                                             num_pqs);
 197         if (!qm_info->qm_pq_params)
 198                 goto alloc_err;
 199
 200         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 201                                                b_sleepable ? GFP_KERNEL :
 202                                                GFP_ATOMIC,
 203                                                sizeof(struct
 204                                                       init_qm_vport_params) *
 205                                                num_vports);
 206         if (!qm_info->qm_vport_params)
 207                 goto alloc_err;
 208
 209         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 210                                               b_sleepable ? GFP_KERNEL :
 211                                               GFP_ATOMIC,
 212                                               sizeof(struct init_qm_port_params)
 213                                               * MAX_NUM_PORTS);
 214         if (!qm_info->qm_port_params)
 215                 goto alloc_err;
 216
 217         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 218                                         b_sleepable ? GFP_KERNEL :
 219                                         GFP_ATOMIC,
 220                                         sizeof(struct ecore_wfq_data) *
 221                                         num_vports);
 222
 223         if (!qm_info->wfq_data)
 224                 goto alloc_err;
 225
 226         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 227
 228         /* First init per-TC PQs */
 229         for (i = 0; i < multi_cos_tcs; i++) {
 230                 struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];
 231
 232                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 233                         params->vport_id = vport_id;
 234                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 235                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 236                 } else {
 237                         params->vport_id = vport_id;
 238                         params->tc_id = p_hwfn->hw_info.offload_tc;
 239                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 240                 }
 241         }
 242
 243         /* Then init pure-LB PQ */
 244         qm_info->pure_lb_pq = i;
 245         qm_info->qm_pq_params[i].vport_id =
 246             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 247         qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;
 248         qm_info->qm_pq_params[i].wrr_group = 1;
 249         i++;
 250
 251         /* Then init per-VF PQs */
 252         vf_offset = i;
 253         for (i = 0; i < num_vfs; i++) {
 254                 /* First vport is used by the PF */
 255                 qm_info->qm_pq_params[vf_offset + i].vport_id = vport_id +
 256                     i + 1;
 257                 qm_info->qm_pq_params[vf_offset + i].tc_id =
 258                     p_hwfn->hw_info.non_offload_tc;
 259                 qm_info->qm_pq_params[vf_offset + i].wrr_group = 1;
 260         };
 261
 262         qm_info->vf_queues_offset = vf_offset;
 263         qm_info->num_pqs = num_pqs;
 264         qm_info->num_vports = num_vports;
 265
 266         /* Initialize qm port parameters */
 267         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 268         for (i = 0; i < num_ports; i++) {
 269                 p_qm_port = &qm_info->qm_port_params[i];
 270                 p_qm_port->active = 1;
 271                 if (num_ports == 4)
 272                         p_qm_port->num_active_phys_tcs = 2;
 273                 else
 274                         p_qm_port->num_active_phys_tcs = 5;
 275                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 276                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 277         }
 278
 279         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 280                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 281         else
 282                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 283
 284         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 285
 286         qm_info->num_vf_pqs = num_vfs;
 287         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 288
 289         for (i = 0; i < qm_info->num_vports; i++)
 290                 qm_info->qm_vport_params[i].vport_wfq = 1;
 291
 292         qm_info->pf_wfq = 0;
 293         qm_info->pf_rl = 0;
 294         qm_info->vport_rl_en = 1;
 295         qm_info->vport_wfq_en = 1;
 296
 297         return ECORE_SUCCESS;
 298
 299 alloc_err:
 300         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 301         ecore_qm_info_free(p_hwfn);
 302         return ECORE_NOMEM;
 303 }
 304
 305 /* This function reconfigures the QM pf on the fly.
 306  * For this purpose we:
 307  * 1. reconfigure the QM database
 308  * 2. set new values to runtime arrat
 309  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 310  * 4. activate init tool in QM_PF stage
 311  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 312  */
 313 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 314                                      struct ecore_ptt *p_ptt)
 315 {
 316         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 317         enum _ecore_status_t rc;
 318         bool b_rc;
 319
 320         /* qm_info is allocated in ecore_init_qm_info() which is already called
 321          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 322          * The allocated size may change each init, so we free it before next
 323          * allocation.
 324          */
 325         ecore_qm_info_free(p_hwfn);
 326
 327         /* initialize ecore's qm data structure */
 328         rc = ecore_init_qm_info(p_hwfn, false);
 329         if (rc != ECORE_SUCCESS)
 330                 return rc;
 331
 332         /* stop PF's qm queues */
 333         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 334                                       qm_info->start_pq, qm_info->num_pqs);
 335         if (!b_rc)
 336                 return ECORE_INVAL;
 337
 338         /* clear the QM_PF runtime phase leftovers from previous init */
 339         ecore_init_clear_rt_data(p_hwfn);
 340
 341         /* prepare QM portion of runtime array */
 342         ecore_qm_init_pf(p_hwfn);
 343
 344         /* activate init tool on runtime array */
 345         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 346                             p_hwfn->hw_info.hw_mode);
 347         if (rc != ECORE_SUCCESS)
 348                 return rc;
 349
 350         /* start PF's qm queues */
 351         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 352                                       qm_info->start_pq, qm_info->num_pqs);
 353         if (!rc)
 354                 return ECORE_INVAL;
 355
 356         return ECORE_SUCCESS;
 357 }
 358
 359 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 360 {
 361         enum _ecore_status_t rc = ECORE_SUCCESS;
 362         struct ecore_consq *p_consq;
 363         struct ecore_eq *p_eq;
 364         int i;
 365
 366         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 367                                      sizeof(struct ecore_fw_data));
 368         if (!p_dev->fw_data)
 369                 return ECORE_NOMEM;
 370
 371         /* Allocate Memory for the Queue->CID mapping */
 372         for_each_hwfn(p_dev, i) {
 373                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 374
 375                 /* @@@TMP - resc management, change to actual required size */
 376                 int tx_size = sizeof(struct ecore_hw_cid_data) *
 377                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 378                 int rx_size = sizeof(struct ecore_hw_cid_data) *
 379                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 380
 381                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 382                                                 tx_size);
 383                 if (!p_hwfn->p_tx_cids) {
 384                         DP_NOTICE(p_hwfn, true,
 385                                   "Failed to allocate memory for Tx Cids\n");
 386                         goto alloc_no_mem;
 387                 }
 388
 389                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 390                                                 rx_size);
 391                 if (!p_hwfn->p_rx_cids) {
 392                         DP_NOTICE(p_hwfn, true,
 393                                   "Failed to allocate memory for Rx Cids\n");
 394                         goto alloc_no_mem;
 395                 }
 396         }
 397
 398         for_each_hwfn(p_dev, i) {
 399                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 400
 401                 /* First allocate the context manager structure */
 402                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 403                 if (rc)
 404                         goto alloc_err;
 405
 406                 /* Set the HW cid/tid numbers (in the contest manager)
 407                  * Must be done prior to any further computations.
 408                  */
 409                 rc = ecore_cxt_set_pf_params(p_hwfn);
 410                 if (rc)
 411                         goto alloc_err;
 412
 413                 /* Prepare and process QM requirements */
 414                 rc = ecore_init_qm_info(p_hwfn, true);
 415                 if (rc)
 416                         goto alloc_err;
 417
 418                 /* Compute the ILT client partition */
 419                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 420                 if (rc)
 421                         goto alloc_err;
 422
 423                 /* CID map / ILT shadow table / T2
 424                  * The talbes sizes are determined by the computations above
 425                  */
 426                 rc = ecore_cxt_tables_alloc(p_hwfn);
 427                 if (rc)
 428                         goto alloc_err;
 429
 430                 /* SPQ, must follow ILT because initializes SPQ context */
 431                 rc = ecore_spq_alloc(p_hwfn);
 432                 if (rc)
 433                         goto alloc_err;
 434
 435                 /* SP status block allocation */
 436                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 437                                                            RESERVED_PTT_DPC);
 438
 439                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 440                 if (rc)
 441                         goto alloc_err;
 442
 443                 /* EQ */
 444                 p_eq = ecore_eq_alloc(p_hwfn, 256);
 445                 if (!p_eq)
 446                         goto alloc_no_mem;
 447                 p_hwfn->p_eq = p_eq;
 448
 449                 p_consq = ecore_consq_alloc(p_hwfn);
 450                 if (!p_consq)
 451                         goto alloc_no_mem;
 452                 p_hwfn->p_consq = p_consq;
 453
 454                 /* DMA info initialization */
 455                 rc = ecore_dmae_info_alloc(p_hwfn);
 456                 if (rc) {
 457                         DP_NOTICE(p_hwfn, true,
 458                                   "Failed to allocate memory for"
 459                                   " dmae_info structure\n");
 460                         goto alloc_err;
 461                 }
 462         }
 463
 464         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 465                                          sizeof(struct ecore_eth_stats));
 466         if (!p_dev->reset_stats) {
 467                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 468                 goto alloc_no_mem;
 469         }
 470
 471         return ECORE_SUCCESS;
 472
 473 alloc_no_mem:
 474         rc = ECORE_NOMEM;
 475 alloc_err:
 476         ecore_resc_free(p_dev);
 477         return rc;
 478 }
 479
 480 void ecore_resc_setup(struct ecore_dev *p_dev)
 481 {
 482         int i;
 483
 484         for_each_hwfn(p_dev, i) {
 485                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 486
 487                 ecore_cxt_mngr_setup(p_hwfn);
 488                 ecore_spq_setup(p_hwfn);
 489                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 490                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 491
 492                 /* Read shadow of current MFW mailbox */
 493                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 494                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 495                             p_hwfn->mcp_info->mfw_mb_cur,
 496                             p_hwfn->mcp_info->mfw_mb_length);
 497
 498                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 499         }
 500 }
 501
 502 #define FINAL_CLEANUP_POLL_CNT  (100)
 503 #define FINAL_CLEANUP_POLL_TIME (10)
 504 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 505                                          struct ecore_ptt *p_ptt,
 506                                          u16 id, bool is_vf)
 507 {
 508         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 509         enum _ecore_status_t rc = ECORE_TIMEOUT;
 510
 511 #ifndef ASIC_ONLY
 512         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 513             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 514                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 515                 return ECORE_SUCCESS;
 516         }
 517 #endif
 518
 519         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 520             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 521
 522         if (is_vf)
 523                 id += 0x10;
 524
 525         command |= X_FINAL_CLEANUP_AGG_INT <<
 526             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 527         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 528         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 529         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 530
 531         /* Make sure notification is not set before initiating final cleanup */
 532         if (REG_RD(p_hwfn, addr)) {
 533                 DP_NOTICE(p_hwfn, false,
 534                           "Unexpected; Found final cleanup notification "
 535                           "before initiating final cleanup\n");
 536                 REG_WR(p_hwfn, addr, 0);
 537         }
 538
 539         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 540                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 541                    id, OSAL_CPU_TO_LE32(command));
 542
 543         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
 544                  OSAL_CPU_TO_LE32(command));
 545
 546         /* Poll until completion */
 547         while (!REG_RD(p_hwfn, addr) && count--)
 548                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 549
 550         if (REG_RD(p_hwfn, addr))
 551                 rc = ECORE_SUCCESS;
 552         else
 553                 DP_NOTICE(p_hwfn, true,
 554                           "Failed to receive FW final cleanup notification\n");
 555
 556         /* Cleanup afterwards */
 557         REG_WR(p_hwfn, addr, 0);
 558
 559         return rc;
 560 }
 561
 562 static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 563 {
 564         int hw_mode = 0;
 565
 566         switch (ECORE_GET_TYPE(p_hwfn->p_dev)) {
 567         case CHIP_BB_A0:
 568                 hw_mode |= 1 << MODE_BB_A0;
 569                 break;
 570         case CHIP_BB_B0:
 571                 hw_mode |= 1 << MODE_BB_B0;
 572                 break;
 573         case CHIP_K2:
 574                 hw_mode |= 1 << MODE_K2;
 575                 break;
 576         default:
 577                 DP_NOTICE(p_hwfn, true, "Can't initialize chip ID %d\n",
 578                           ECORE_GET_TYPE(p_hwfn->p_dev));
 579                 return;
 580         }
 581
 582         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 583         switch (p_hwfn->p_dev->num_ports_in_engines) {
 584         case 1:
 585                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 586                 break;
 587         case 2:
 588                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 589                 break;
 590         case 4:
 591                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 592                 break;
 593         default:
 594                 DP_NOTICE(p_hwfn, true,
 595                           "num_ports_in_engine = %d not supported\n",
 596                           p_hwfn->p_dev->num_ports_in_engines);
 597                 return;
 598         }
 599
 600         switch (p_hwfn->p_dev->mf_mode) {
 601         case ECORE_MF_DEFAULT:
 602         case ECORE_MF_NPAR:
 603                 hw_mode |= 1 << MODE_MF_SI;
 604                 break;
 605         case ECORE_MF_OVLAN:
 606                 hw_mode |= 1 << MODE_MF_SD;
 607                 break;
 608         default:
 609                 DP_NOTICE(p_hwfn, true,
 610                           "Unsupported MF mode, init as DEFAULT\n");
 611                 hw_mode |= 1 << MODE_MF_SI;
 612         }
 613
 614 #ifndef ASIC_ONLY
 615         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 616                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 617                         hw_mode |= 1 << MODE_FPGA;
 618                 } else {
 619                         if (p_hwfn->p_dev->b_is_emul_full)
 620                                 hw_mode |= 1 << MODE_EMUL_FULL;
 621                         else
 622                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 623                 }
 624         } else
 625 #endif
 626                 hw_mode |= 1 << MODE_ASIC;
 627
 628         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
 629                 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
 630
 631         if (p_hwfn->p_dev->num_hwfns > 1)
 632                 hw_mode |= 1 << MODE_100G;
 633
 634         p_hwfn->hw_info.hw_mode = hw_mode;
 635
 636         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 637                    "Configuring function for hw_mode: 0x%08x\n",
 638                    p_hwfn->hw_info.hw_mode);
 639 }
 640
 641 #ifndef ASIC_ONLY
 642 /* MFW-replacement initializations for non-ASIC */
 643 static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 644                                struct ecore_ptt *p_ptt)
 645 {
 646         u32 pl_hv = 1;
 647         int i;
 648
 649         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 650                 pl_hv |= 0x600;
 651
 652         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 653
 654         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 655                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 656
 657         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 658         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 659         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 660                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 661
 662         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 663                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 664                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 665                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 666
 667                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 668                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 669         }
 670
 671         /* Poll on RBC */
 672         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 673         for (i = 0; i < 100; i++) {
 674                 OSAL_UDELAY(50);
 675                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 676                         break;
 677         }
 678         if (i == 100)
 679                 DP_NOTICE(p_hwfn, true,
 680                           "RBC done failed to complete in PSWRQ2\n");
 681 }
 682 #endif
 683
 684 /* Init run time data for all PFs and their VFs on an engine.
 685  * TBD - for VFs - Once we have parent PF info for each VF in
 686  * shmem available as CAU requires knowledge of parent PF for each VF.
 687  */
 688 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 689 {
 690         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 691         int i, sb_id;
 692
 693         for_each_hwfn(p_dev, i) {
 694                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 695                 struct ecore_igu_info *p_igu_info;
 696                 struct ecore_igu_block *p_block;
 697                 struct cau_sb_entry sb_entry;
 698
 699                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 700
 701                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 702                      sb_id++) {
 703                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 704
 705                         if (!p_block->is_pf)
 706                                 continue;
 707
 708                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 709                                                 p_block->function_id, 0, 0);
 710                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 711                 }
 712         }
 713 }
 714
 715 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 716                                                  struct ecore_ptt *p_ptt,
 717                                                  int hw_mode)
 718 {
 719         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 720         enum _ecore_status_t rc = ECORE_SUCCESS;
 721         struct ecore_dev *p_dev = p_hwfn->p_dev;
 722         u8 vf_id, max_num_vfs;
 723         u16 num_pfs, pf_id;
 724         u32 concrete_fid;
 725
 726         ecore_init_cau_rt_data(p_dev);
 727
 728         /* Program GTT windows */
 729         ecore_gtt_init(p_hwfn);
 730
 731 #ifndef ASIC_ONLY
 732         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 733                 ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 734 #endif
 735
 736         if (p_hwfn->mcp_info) {
 737                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 738                         qm_info->pf_rl_en = 1;
 739                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 740                         qm_info->pf_wfq_en = 1;
 741         }
 742
 743         ecore_qm_common_rt_init(p_hwfn,
 744                                 p_hwfn->p_dev->num_ports_in_engines,
 745                                 qm_info->max_phys_tcs_per_port,
 746                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 747                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 748                                 qm_info->qm_port_params);
 749
 750         ecore_cxt_hw_init_common(p_hwfn);
 751
 752         /* Close gate from NIG to BRB/Storm; By default they are open, but
 753          * we close them to prevent NIG from passing data to reset blocks.
 754          * Should have been done in the ENGINE phase, but init-tool lacks
 755          * proper port-pretend capabilities.
 756          */
 757         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 758         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 759         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 760         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 761         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 762         ecore_port_unpretend(p_hwfn, p_ptt);
 763
 764         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 765         if (rc != ECORE_SUCCESS)
 766                 return rc;
 767
 768         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
 769          * need to decide with which value, maybe runtime
 770          */
 771         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 772         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 773
 774         if (ECORE_IS_BB(p_hwfn->p_dev)) {
 775                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
 776                 if (num_pfs == 1)
 777                         return rc;
 778                 /* pretend to original PF */
 779                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 780         }
 781
 782         /* Workaround for avoiding CCFC execution error when getting packets
 783          * with CRC errors, and allowing instead the invoking of the FW error
 784          * handler.
 785          * This is not done inside the init tool since it currently can't
 786          * perform a pretending to VFs.
 787          */
 788         max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
 789             : MAX_NUM_VFS_BB;
 790         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
 791                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
 792                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
 793                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 794         }
 795         /* pretend to original PF */
 796         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 797
 798         return rc;
 799 }
 800
 801 #ifndef ASIC_ONLY
 802 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
 803 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
 804
 805 #define PMEG_IF_BYTE_COUNT      8
 806
 807 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
 808                              struct ecore_ptt *p_ptt,
 809                              u32 addr, u64 data, u8 reg_type, u8 port)
 810 {
 811         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 812                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
 813                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
 814                    (8 << PMEG_IF_BYTE_COUNT),
 815                    (reg_type << 25) | (addr << 8) | port,
 816                    (u32)((data >> 32) & 0xffffffff),
 817                    (u32)(data & 0xffffffff));
 818
 819         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
 820                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
 821                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
 822         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
 823                  (reg_type << 25) | (addr << 8) | port);
 824         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
 825                  data & 0xffffffff);
 826         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
 827                  (data >> 32) & 0xffffffff);
 828 }
 829
 830 #define XLPORT_MODE_REG (0x20a)
 831 #define XLPORT_MAC_CONTROL (0x210)
 832 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
 833 #define XLPORT_ENABLE_REG (0x20b)
 834
 835 #define XLMAC_CTRL (0x600)
 836 #define XLMAC_MODE (0x601)
 837 #define XLMAC_RX_MAX_SIZE (0x608)
 838 #define XLMAC_TX_CTRL (0x604)
 839 #define XLMAC_PAUSE_CTRL (0x60d)
 840 #define XLMAC_PFC_CTRL (0x60e)
 841
 842 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
 843                                     struct ecore_ptt *p_ptt)
 844 {
 845         u8 port = p_hwfn->port_id;
 846         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
 847
 848         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
 849                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
 850                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
 851                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
 852
 853         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
 854                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
 855
 856         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
 857                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
 858
 859         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
 860                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
 861
 862         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
 863                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
 864
 865         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
 866                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
 867                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
 868
 869         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
 870 }
 871
 872 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
 873                                  struct ecore_ptt *p_ptt)
 874 {
 875         u8 loopback = 0, port = p_hwfn->port_id * 2;
 876
 877         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
 878
 879         if (ECORE_IS_AH(p_hwfn->p_dev)) {
 880                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
 881                 return;
 882         }
 883
 884         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
 885                                 port);
 886         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
 887         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
 888         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
 889         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
 890         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
 891                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
 892                          0, port);
 893         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
 894         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
 895                          0x30ffffc000ULL, 0, port);
 896         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
 897                         port);
 898         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x1003 | (loopback << 2),
 899                         0, port);
 900         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
 901         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
 902 }
 903
 904 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
 905                             struct ecore_ptt *p_ptt, u8 port)
 906 {
 907         int port_offset = port ? 0x800 : 0;
 908         u32 xmac_rxctrl = 0;
 909
 910         /* Reset of XMAC */
 911         /* FIXME: move to common start */
 912         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
 913                 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
 914         OSAL_MSLEEP(1);
 915         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
 916                 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
 917
 918         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
 919
 920         /* Set the number of ports on the Warp Core to 10G */
 921         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
 922
 923         /* Soft reset of XMAC */
 924         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
 925                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
 926         OSAL_MSLEEP(1);
 927         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
 928                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
 929
 930         /* FIXME: move to common end */
 931         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 932                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
 933
 934         /* Set Max packet size: initialize XMAC block register for port 0 */
 935         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
 936
 937         /* CRC append for Tx packets: init XMAC block register for port 1 */
 938         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
 939
 940         /* Enable TX and RX: initialize XMAC block register for port 1 */
 941         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
 942                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
 943         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
 944         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
 945         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
 946 }
 947 #endif
 948
 949 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
 950                                                struct ecore_ptt *p_ptt,
 951                                                int hw_mode)
 952 {
 953         enum _ecore_status_t rc = ECORE_SUCCESS;
 954
 955         /* Init sequence */
 956         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
 957                             hw_mode);
 958         if (rc != ECORE_SUCCESS)
 959                 return rc;
 960
 961 #ifndef ASIC_ONLY
 962         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
 963                 return ECORE_SUCCESS;
 964
 965         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 966                 if (ECORE_IS_AH(p_hwfn->p_dev))
 967                         return ECORE_SUCCESS;
 968                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
 969         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 970                 if (p_hwfn->p_dev->num_hwfns > 1) {
 971                         /* Activate OPTE in CMT */
 972                         u32 val;
 973
 974                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
 975                         val |= 0x10;
 976                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
 977                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
 978                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
 979                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
 980                         ecore_wr(p_hwfn, p_ptt,
 981                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
 982                         ecore_wr(p_hwfn, p_ptt,
 983                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
 984                         ecore_wr(p_hwfn, p_ptt,
 985                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
 986                                  0x55555555);
 987                 }
 988
 989                 ecore_emul_link_init(p_hwfn, p_ptt);
 990         } else {
 991                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
 992         }
 993 #endif
 994
 995         return rc;
 996 }
 997
 998 static enum _ecore_status_t
 999 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1000                               struct ecore_ptt *p_ptt)
1001 {
1002         u32 pwm_regsize, norm_regsize;
1003         u32 non_pwm_conn, min_addr_reg1;
1004         u32 db_bar_size, n_cpus;
1005         u32 pf_dems_shift;
1006         int rc = ECORE_SUCCESS;
1007
1008         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1009         if (p_hwfn->p_dev->num_hwfns > 1)
1010                 db_bar_size /= 2;
1011
1012         /* Calculate doorbell regions
1013          * -----------------------------------
1014          * The doorbell BAR is made of two regions. The first is called normal
1015          * region and the second is called PWM region. In the normal region
1016          * each ICID has its own set of addresses so that writing to that
1017          * specific address identifies the ICID. In the Process Window Mode
1018          * region the ICID is given in the data written to the doorbell. The
1019          * above per PF register denotes the offset in the doorbell BAR in which
1020          * the PWM region begins.
1021          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1022          * non-PWM connection. The calculation below computes the total non-PWM
1023          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1024          * in units of 4,096 bytes.
1025          */
1026         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1027             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1028                                           OSAL_NULL) +
1029             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1030         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1031         min_addr_reg1 = norm_regsize / 4096;
1032         pwm_regsize = db_bar_size - norm_regsize;
1033
1034         /* Check that the normal and PWM sizes are valid */
1035         if (db_bar_size < norm_regsize) {
1036                 DP_ERR(p_hwfn->p_dev,
1037                        "Doorbell BAR size 0x%x is too"
1038                        " small (normal region is 0x%0x )\n",
1039                        db_bar_size, norm_regsize);
1040                 return ECORE_NORESOURCES;
1041         }
1042         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1043                 DP_ERR(p_hwfn->p_dev,
1044                        "PWM region size 0x%0x is too small."
1045                        " Should be at least 0x%0x (Doorbell BAR size"
1046                        " is 0x%x and normal region size is 0x%0x)\n",
1047                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1048                        norm_regsize);
1049                 return ECORE_NORESOURCES;
1050         }
1051
1052         /* Update hwfn */
1053         p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
1054                                                   * calculate the doorbell
1055                                                   * address
1056                                                   */
1057
1058         /* Update registers */
1059         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1060         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1061         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1062         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1063
1064         DP_INFO(p_hwfn,
1065                 "Doorbell size 0x%x, Normal region 0x%x, PWM region 0x%x\n",
1066                 db_bar_size, norm_regsize, pwm_regsize);
1067         DP_INFO(p_hwfn, "DPI size 0x%x, DPI count 0x%x\n", p_hwfn->dpi_size,
1068                 p_hwfn->dpi_count);
1069
1070         return ECORE_SUCCESS;
1071 }
1072
1073 static enum _ecore_status_t
1074 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1075                  struct ecore_ptt *p_ptt,
1076                  struct ecore_tunn_start_params *p_tunn,
1077                  int hw_mode,
1078                  bool b_hw_start,
1079                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1080 {
1081         enum _ecore_status_t rc = ECORE_SUCCESS;
1082         u8 rel_pf_id = p_hwfn->rel_pf_id;
1083         u32 prs_reg;
1084         u16 ctrl;
1085         int pos;
1086
1087         /* ILT/DQ/CM/QM */
1088         if (p_hwfn->mcp_info) {
1089                 struct ecore_mcp_function_info *p_info;
1090
1091                 p_info = &p_hwfn->mcp_info->func_info;
1092                 if (p_info->bandwidth_min)
1093                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1094
1095                 /* Update rate limit once we'll actually have a link */
1096                 p_hwfn->qm_info.pf_rl = 100;
1097         }
1098         ecore_cxt_hw_init_pf(p_hwfn);
1099
1100         ecore_int_igu_init_rt(p_hwfn);  /* @@@TBD TODO MichalS multi hwfn ?? */
1101
1102         /* Set VLAN in NIG if needed */
1103         if (hw_mode & (1 << MODE_MF_SD)) {
1104                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1105                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1106                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1107                              p_hwfn->hw_info.ovlan);
1108         }
1109
1110         /* Enable classification by MAC if needed */
1111         if (hw_mode & (1 << MODE_MF_SI)) {
1112                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1113                            "Configuring TAGMAC_CLS_TYPE\n");
1114                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1115                              1);
1116         }
1117
1118         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1119         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
1120
1121         /* perform debug configuration when chip is out of reset */
1122         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1123
1124         /* Cleanup chip from previous driver if such remains exist */
1125         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1126         if (rc != ECORE_SUCCESS) {
1127                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1128                 return rc;
1129         }
1130
1131         /* PF Init sequence */
1132         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1133         if (rc)
1134                 return rc;
1135
1136         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1137         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1138         if (rc)
1139                 return rc;
1140
1141         /* Pure runtime initializations - directly to the HW  */
1142         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1143
1144         /* PCI relaxed ordering causes a decrease in the performance on some
1145          * systems. Till a root cause is found, disable this attribute in the
1146          * PCI config space.
1147          */
1148         /* Not in use @DPDK
1149          * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1150          * if (!pos) {
1151          *      DP_NOTICE(p_hwfn, true,
1152          *                "Failed to find the PCI Express"
1153          *                " Capability structure in the PCI config space\n");
1154          *      return ECORE_IO;
1155          * }
1156          * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1157          *                           &ctrl);
1158          * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1159          * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1160          *                           &ctrl);
1161          */
1162
1163         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1164         if (rc)
1165                 return rc;
1166
1167         if (b_hw_start) {
1168                 /* enable interrupts */
1169                 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1170
1171                 /* send function start command */
1172                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1173                                        allow_npar_tx_switch);
1174                 if (rc) {
1175                         DP_NOTICE(p_hwfn, true,
1176                                   "Function start ramrod failed\n");
1177                 } else {
1178                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1179                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1180                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1181
1182                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1183                                    "PRS_REG_SEARCH register after start PFn\n");
1184                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1185                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1186                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1187                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1188                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1189                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1190                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1191                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1192                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1193                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1194                                    prs_reg);
1195                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1196                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1197                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1198                 }
1199         }
1200         return rc;
1201 }
1202
1203 static enum _ecore_status_t
1204 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1205                       struct ecore_ptt *p_ptt, u8 enable)
1206 {
1207         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1208
1209         /* Change PF in PXP */
1210         ecore_wr(p_hwfn, p_ptt,
1211                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1212
1213         /* wait until value is set - try for 1 second every 50us */
1214         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1215                 val = ecore_rd(p_hwfn, p_ptt,
1216                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1217                 if (val == set_val)
1218                         break;
1219
1220                 OSAL_UDELAY(50);
1221         }
1222
1223         if (val != set_val) {
1224                 DP_NOTICE(p_hwfn, true,
1225                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1226                 return ECORE_UNKNOWN_ERROR;
1227         }
1228
1229         return ECORE_SUCCESS;
1230 }
1231
1232 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1233                                   struct ecore_ptt *p_main_ptt)
1234 {
1235         /* Read shadow of current MFW mailbox */
1236         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1237         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1238                     p_hwfn->mcp_info->mfw_mb_cur,
1239                     p_hwfn->mcp_info->mfw_mb_length);
1240 }
1241
1242 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1243                                    struct ecore_tunn_start_params *p_tunn,
1244                                    bool b_hw_start,
1245                                    enum ecore_int_mode int_mode,
1246                                    bool allow_npar_tx_switch,
1247                                    const u8 *bin_fw_data)
1248 {
1249         enum _ecore_status_t rc, mfw_rc;
1250         u32 load_code, param;
1251         int i, j;
1252
1253         rc = ecore_init_fw_data(p_dev, bin_fw_data);
1254         if (rc != ECORE_SUCCESS)
1255                 return rc;
1256
1257         for_each_hwfn(p_dev, i) {
1258                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1259
1260                 /* Enable DMAE in PXP */
1261                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1262
1263                 ecore_calc_hw_mode(p_hwfn);
1264                 /* @@@TBD need to add here:
1265                  * Check for fan failure
1266                  * Prev_unload
1267                  */
1268                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1269                 if (rc) {
1270                         DP_NOTICE(p_hwfn, true,
1271                                   "Failed sending LOAD_REQ command\n");
1272                         return rc;
1273                 }
1274
1275                 /* CQ75580:
1276                  * When coming back from hiberbate state, the registers from
1277                  * which shadow is read initially are not initialized. It turns
1278                  * out that these registers get initialized during the call to
1279                  * ecore_mcp_load_req request. So we need to reread them here
1280                  * to get the proper shadow register value.
1281                  * Note: This is a workaround for the missinginig MFW
1282                  * initialization. It may be removed once the implementation
1283                  * is done.
1284                  */
1285                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1286
1287                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1288                            "Load request was sent.Resp:0x%x, Load code: 0x%x\n",
1289                            rc, load_code);
1290
1291                 /* Only relevant for recovery:
1292                  * Clear the indication after the LOAD_REQ command is responded
1293                  * by the MFW.
1294                  */
1295                 p_dev->recov_in_prog = false;
1296
1297                 p_hwfn->first_on_engine = (load_code ==
1298                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1299
1300                 switch (load_code) {
1301                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1302                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1303                                                   p_hwfn->hw_info.hw_mode);
1304                         if (rc)
1305                                 break;
1306                         /* Fall into */
1307                 case FW_MSG_CODE_DRV_LOAD_PORT:
1308                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1309                                                 p_hwfn->hw_info.hw_mode);
1310                         if (rc)
1311                                 break;
1312
1313                         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1314                                 struct init_nig_pri_tc_map_req tc_map;
1315
1316                                 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1317
1318                                 /* remove this once flow control is
1319                                  * implemented
1320                                  */
1321                                 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1322                                         tc_map.pri[j].tc_id = 0;
1323                                         tc_map.pri[j].valid = 1;
1324                                 }
1325                                 ecore_init_nig_pri_tc_map(p_hwfn,
1326                                                           p_hwfn->p_main_ptt,
1327                                                           &tc_map);
1328                         }
1329                         /* fallthrough */
1330                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1331                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1332                                               p_tunn, p_hwfn->hw_info.hw_mode,
1333                                               b_hw_start, int_mode,
1334                                               allow_npar_tx_switch);
1335                         break;
1336                 default:
1337                         rc = ECORE_NOTIMPL;
1338                         break;
1339                 }
1340
1341                 if (rc != ECORE_SUCCESS)
1342                         DP_NOTICE(p_hwfn, true,
1343                                   "init phase failed loadcode 0x%x (rc %d)\n",
1344                                   load_code, rc);
1345
1346                 /* ACK mfw regardless of success or failure of initialization */
1347                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1348                                        DRV_MSG_CODE_LOAD_DONE,
1349                                        0, &load_code, &param);
1350                 if (rc != ECORE_SUCCESS)
1351                         return rc;
1352                 if (mfw_rc != ECORE_SUCCESS) {
1353                         DP_NOTICE(p_hwfn, true,
1354                                   "Failed sending LOAD_DONE command\n");
1355                         return mfw_rc;
1356                 }
1357
1358                 p_hwfn->hw_init_done = true;
1359         }
1360
1361         return ECORE_SUCCESS;
1362 }
1363
1364 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1365 static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1366                                              struct ecore_hwfn *p_hwfn,
1367                                              struct ecore_ptt *p_ptt)
1368 {
1369         int i;
1370
1371         /* close timers */
1372         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1373         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1374         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT &&
1375                                         !p_dev->recov_in_prog; i++) {
1376                 if ((!ecore_rd(p_hwfn, p_ptt,
1377                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1378                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1379                         break;
1380
1381                 /* Dependent on number of connection/tasks, possibly
1382                  * 1ms sleep is required between polls
1383                  */
1384                 OSAL_MSLEEP(1);
1385         }
1386         if (i == ECORE_HW_STOP_RETRY_LIMIT)
1387                 DP_NOTICE(p_hwfn, true,
1388                           "Timers linear scans are not over"
1389                           " [Connection %02x Tasks %02x]\n",
1390                           (u8)ecore_rd(p_hwfn, p_ptt,
1391                                        TM_REG_PF_SCAN_ACTIVE_CONN),
1392                           (u8)ecore_rd(p_hwfn, p_ptt,
1393                                        TM_REG_PF_SCAN_ACTIVE_TASK));
1394 }
1395
1396 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1397 {
1398         int j;
1399
1400         for_each_hwfn(p_dev, j) {
1401                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1402                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1403
1404                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1405         }
1406 }
1407
1408 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1409 {
1410         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1411         int j;
1412
1413         for_each_hwfn(p_dev, j) {
1414                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1415                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1416
1417                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1418
1419                 /* mark the hw as uninitialized... */
1420                 p_hwfn->hw_init_done = false;
1421
1422                 rc = ecore_sp_pf_stop(p_hwfn);
1423                 if (rc)
1424                         DP_NOTICE(p_hwfn, true,
1425                                   "Failed to close PF against FW. Continue to"
1426                                   " stop HW to prevent illegal host access"
1427                                   " by the device\n");
1428
1429                 /* perform debug action after PF stop was sent */
1430                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1431
1432                 /* close NIG to BRB gate */
1433                 ecore_wr(p_hwfn, p_ptt,
1434                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1435
1436                 /* close parser */
1437                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1438                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1439                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1440
1441                 /* @@@TBD - clean transmission queues (5.b) */
1442                 /* @@@TBD - clean BTB (5.c) */
1443
1444                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1445
1446                 /* @@@TBD - verify DMAE requests are done (8) */
1447
1448                 /* Disable Attention Generation */
1449                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1450                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1451                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1452                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1453                 /* Need to wait 1ms to guarantee SBs are cleared */
1454                 OSAL_MSLEEP(1);
1455         }
1456
1457         /* Disable DMAE in PXP - in CMT, this should only be done for
1458          * first hw-function, and only after all transactions have
1459          * stopped for all active hw-functions.
1460          */
1461         t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1462                                      p_dev->hwfns[0].p_main_ptt, false);
1463         if (t_rc != ECORE_SUCCESS)
1464                 rc = t_rc;
1465
1466         return rc;
1467 }
1468
1469 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1470 {
1471         int j;
1472
1473         for_each_hwfn(p_dev, j) {
1474                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1475                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1476
1477                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1478                            "Shutting down the fastpath\n");
1479
1480                 ecore_wr(p_hwfn, p_ptt,
1481                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1482
1483                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1484                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1485                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1486
1487                 /* @@@TBD - clean transmission queues (5.b) */
1488                 /* @@@TBD - clean BTB (5.c) */
1489
1490                 /* @@@TBD - verify DMAE requests are done (8) */
1491
1492                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1493                 /* Need to wait 1ms to guarantee SBs are cleared */
1494                 OSAL_MSLEEP(1);
1495         }
1496 }
1497
1498 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1499 {
1500         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1501
1502         /* Re-open incoming traffic */
1503         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1504                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1505 }
1506
1507 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1508                                              struct ecore_ptt *p_ptt, u32 reg,
1509                                              bool expected)
1510 {
1511         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1512
1513         if (assert_val != expected) {
1514                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1515                           reg, expected);
1516                 return ECORE_UNKNOWN_ERROR;
1517         }
1518
1519         return 0;
1520 }
1521
1522 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1523 {
1524         enum _ecore_status_t rc = ECORE_SUCCESS;
1525         u32 unload_resp, unload_param;
1526         int i;
1527
1528         for_each_hwfn(p_dev, i) {
1529                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1530
1531                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1532
1533                 /* Check for incorrect states */
1534                 if (!p_dev->recov_in_prog) {
1535                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1536                                          QM_REG_USG_CNT_PF_TX, 0);
1537                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1538                                          QM_REG_USG_CNT_PF_OTHER, 0);
1539                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1540                 }
1541
1542                 /* Disable PF in HW blocks */
1543                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1544                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1545                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1546                          TCFC_REG_STRONG_ENABLE_PF, 0);
1547                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1548                          CCFC_REG_STRONG_ENABLE_PF, 0);
1549
1550                 if (p_dev->recov_in_prog) {
1551                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1552                                    "Recovery is in progress -> skip "
1553                                    "sending unload_req/done\n");
1554                         break;
1555                 }
1556
1557                 /* Send unload command to MCP */
1558                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1559                                    DRV_MSG_CODE_UNLOAD_REQ,
1560                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
1561                                    &unload_resp, &unload_param);
1562                 if (rc != ECORE_SUCCESS) {
1563                         DP_NOTICE(p_hwfn, true,
1564                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
1565                         /* @@TBD - what to do? for now, assume ENG. */
1566                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1567                 }
1568
1569                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1570                                    DRV_MSG_CODE_UNLOAD_DONE,
1571                                    0, &unload_resp, &unload_param);
1572                 if (rc != ECORE_SUCCESS) {
1573                         DP_NOTICE(p_hwfn,
1574                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1575                         /* @@@TBD - Should it really ASSERT here ? */
1576                         return rc;
1577                 }
1578         }
1579
1580         return rc;
1581 }
1582
1583 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1584 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1585 {
1586         ecore_ptt_pool_free(p_hwfn);
1587         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
1588 }
1589
1590 /* Setup bar access */
1591 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
1592 {
1593         /* clear indirect access */
1594         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1595         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1596         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1597         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1598
1599         /* Clean Previous errors if such exist */
1600         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1601                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1602
1603         /* enable internal target-read */
1604         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1605                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1606 }
1607
1608 static void get_function_id(struct ecore_hwfn *p_hwfn)
1609 {
1610         /* ME Register */
1611         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
1612                                                  PXP_PF_ME_OPAQUE_ADDR);
1613
1614         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1615
1616         /* Bits 16-19 from the ME registers are the pf_num */
1617         /* @@ @TBD - check, may be wrong after B0 implementation for CMT */
1618         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1619         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1620                                       PXP_CONCRETE_FID_PFID);
1621         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1622                                     PXP_CONCRETE_FID_PORT);
1623
1624         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1625                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1626                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1627 }
1628
1629 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
1630 {
1631         u32 *feat_num = p_hwfn->hw_info.feat_num;
1632         int num_features = 1;
1633
1634         /* L2 Queues require each: 1 status block. 1 L2 queue */
1635         feat_num[ECORE_PF_L2_QUE] =
1636             OSAL_MIN_T(u32,
1637                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
1638                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
1639
1640         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1641                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1642                    feat_num[ECORE_PF_L2_QUE],
1643                    RESC_NUM(p_hwfn, ECORE_SB), num_features);
1644 }
1645
1646 /* @@@TBD MK RESC: This info is currently hard code and set as if we were MF
1647  * need to read it from shmem...
1648  */
1649 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)
1650 {
1651         u32 *resc_start = p_hwfn->hw_info.resc_start;
1652         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1653         u32 *resc_num = p_hwfn->hw_info.resc_num;
1654         int i, max_vf_vlan_filters;
1655         struct ecore_sb_cnt_info sb_cnt_info;
1656         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
1657
1658         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
1659
1660         max_vf_vlan_filters = 0;
1661
1662         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1663         resc_num[ECORE_SB] = OSAL_MIN_T(u32,
1664                                         (MAX_SB_PER_PATH_BB / num_funcs),
1665                                         sb_cnt_info.sb_cnt);
1666
1667         resc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
1668                                     MAX_NUM_L2_QUEUES_BB) / num_funcs;
1669         resc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 :
1670                                  MAX_NUM_VPORTS_BB) / num_funcs;
1671         resc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
1672                                    ETH_RSS_ENGINE_NUM_BB) / num_funcs;
1673         resc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 :
1674                               MAX_QM_TX_QUEUES_BB) / num_funcs;
1675         resc_num[ECORE_RL] = 8;
1676         resc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1677         resc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS -
1678                                 max_vf_vlan_filters +
1679                                 1 /*For vlan0 */) / num_funcs;
1680
1681         /* TODO - there will be a problem in AH - there are only 11k lines */
1682         resc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
1683                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
1684
1685 #ifndef ASIC_ONLY
1686         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1687                 /* Reduced build contains less PQs */
1688                 if (!(p_hwfn->p_dev->b_is_emul_full))
1689                         resc_num[ECORE_PQ] = 32;
1690
1691                 /* For AH emulation, since we have a possible maximal number of
1692                  * 16 enabled PFs, in case there are not enough ILT lines -
1693                  * allocate only first PF as RoCE and have all the other ETH
1694                  * only with less ILT lines.
1695                  */
1696                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
1697                         resc_num[ECORE_ILT] = resc_num[ECORE_ILT];
1698         }
1699 #endif
1700
1701         for (i = 0; i < ECORE_MAX_RESC; i++)
1702                 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1703
1704 #ifndef ASIC_ONLY
1705         /* Correct the common ILT calculation if PF0 has more */
1706         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
1707             p_hwfn->p_dev->b_is_emul_full &&
1708             p_hwfn->rel_pf_id && resc_num[ECORE_ILT])
1709                 resc_start[ECORE_ILT] += resc_num[ECORE_ILT];
1710 #endif
1711
1712         /* Sanity for ILT */
1713         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1714             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
1715                 DP_NOTICE(p_hwfn, true,
1716                           "Can't assign ILT pages [%08x,...,%08x]\n",
1717                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
1718                                                                   ECORE_ILT) -
1719                           1);
1720                 return ECORE_INVAL;
1721         }
1722
1723         ecore_hw_set_feat(p_hwfn);
1724
1725         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1726                    "The numbers for each resource are:\n"
1727                    "SB = %d start = %d\n"
1728                    "L2_QUEUE = %d start = %d\n"
1729                    "VPORT = %d start = %d\n"
1730                    "PQ = %d start = %d\n"
1731                    "RL = %d start = %d\n"
1732                    "MAC = %d start = %d\n"
1733                    "VLAN = %d start = %d\n"
1734                    "ILT = %d start = %d\n"
1735                    "CMDQS_CQS = %d start = %d\n",
1736                    RESC_NUM(p_hwfn, ECORE_SB), RESC_START(p_hwfn, ECORE_SB),
1737                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
1738                    RESC_START(p_hwfn, ECORE_L2_QUEUE),
1739                    RESC_NUM(p_hwfn, ECORE_VPORT),
1740                    RESC_START(p_hwfn, ECORE_VPORT),
1741                    RESC_NUM(p_hwfn, ECORE_PQ), RESC_START(p_hwfn, ECORE_PQ),
1742                    RESC_NUM(p_hwfn, ECORE_RL), RESC_START(p_hwfn, ECORE_RL),
1743                    RESC_NUM(p_hwfn, ECORE_MAC), RESC_START(p_hwfn, ECORE_MAC),
1744                    RESC_NUM(p_hwfn, ECORE_VLAN),
1745                    RESC_START(p_hwfn, ECORE_VLAN),
1746                    RESC_NUM(p_hwfn, ECORE_ILT), RESC_START(p_hwfn, ECORE_ILT),
1747                    RESC_NUM(p_hwfn, ECORE_CMDQS_CQS),
1748                    RESC_START(p_hwfn, ECORE_CMDQS_CQS));
1749
1750         return ECORE_SUCCESS;
1751 }
1752
1753 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
1754                                                   struct ecore_ptt *p_ptt)
1755 {
1756         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1757         u32 port_cfg_addr, link_temp, device_capabilities;
1758         struct ecore_mcp_link_params *link;
1759
1760         /* Read global nvm_cfg address */
1761         u32 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1762
1763         /* Verify MCP has initialized it */
1764         if (nvm_cfg_addr == 0) {
1765                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
1766                 return ECORE_INVAL;
1767         }
1768
1769         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1770         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1771
1772         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1773             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
1774                                                        core_cfg);
1775
1776         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
1777
1778         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1779                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1780         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1781                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
1782                 break;
1783         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1784                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
1785                 break;
1786         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1787                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
1788                 break;
1789         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1790                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
1791                 break;
1792         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1793                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
1794                 break;
1795         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1796                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
1797                 break;
1798         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1799                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
1800                 break;
1801         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1802                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
1803                 break;
1804         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1805                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
1806                 break;
1807         default:
1808                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
1809                           core_cfg);
1810                 break;
1811         }
1812
1813         /* Read default link configuration */
1814         link = &p_hwfn->mcp_info->link_input;
1815         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1816             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1817         link_temp = ecore_rd(p_hwfn, p_ptt,
1818                              port_cfg_addr +
1819                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
1820         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1821         link->speed.advertised_speeds = link_temp;
1822
1823         link_temp = link->speed.advertised_speeds;
1824         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1825
1826         link_temp = ecore_rd(p_hwfn, p_ptt,
1827                              port_cfg_addr +
1828                              OFFSETOF(struct nvm_cfg1_port, link_settings));
1829         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1830                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1831         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1832                 link->speed.autoneg = true;
1833                 break;
1834         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1835                 link->speed.forced_speed = 1000;
1836                 break;
1837         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1838                 link->speed.forced_speed = 10000;
1839                 break;
1840         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1841                 link->speed.forced_speed = 25000;
1842                 break;
1843         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1844                 link->speed.forced_speed = 40000;
1845                 break;
1846         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1847                 link->speed.forced_speed = 50000;
1848                 break;
1849         case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1850                 link->speed.forced_speed = 100000;
1851                 break;
1852         default:
1853                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
1854         }
1855
1856         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1857         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1858         link->pause.autoneg = !!(link_temp &
1859                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1860         link->pause.forced_rx = !!(link_temp &
1861                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1862         link->pause.forced_tx = !!(link_temp &
1863                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1864         link->loopback_mode = 0;
1865
1866         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1867                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x,"
1868                    " AN: 0x%02x, PAUSE AN: 0x%02x\n",
1869                    link->speed.forced_speed, link->speed.advertised_speeds,
1870                    link->speed.autoneg, link->pause.autoneg);
1871
1872         /* Read Multi-function information from shmem */
1873         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1874             OFFSETOF(struct nvm_cfg1, glob) +
1875             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
1876
1877         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
1878
1879         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1880             NVM_CFG1_GLOB_MF_MODE_OFFSET;
1881
1882         switch (mf_mode) {
1883         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1884                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
1885                 break;
1886         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1887                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
1888                 break;
1889         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1890                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
1891                 break;
1892         }
1893         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1894                 p_hwfn->p_dev->mf_mode);
1895
1896         /* Read Multi-function information from shmem */
1897         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1898             OFFSETOF(struct nvm_cfg1, glob) +
1899             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
1900
1901         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
1902         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1903                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
1904                              &p_hwfn->hw_info.device_capabilities);
1905
1906         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1907 }
1908
1909 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
1910                                 struct ecore_ptt *p_ptt)
1911 {
1912         u8 num_funcs;
1913         u32 tmp, mask;
1914
1915         num_funcs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_PFS_K2
1916             : MAX_NUM_PFS_BB;
1917
1918         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1919          * in the other bits are selected.
1920          * Bits 1-15 are for functions 1-15, respectively, and their value is
1921          * '0' only for enabled functions (function 0 always exists and
1922          * enabled).
1923          * In case of CMT, only the "even" functions are enabled, and thus the
1924          * number of functions for both hwfns is learnt from the same bits.
1925          */
1926
1927         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1928         if (tmp & 0x1) {
1929                 if (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) {
1930                         num_funcs = 0;
1931                         mask = 0xaaaa;
1932                 } else {
1933                         num_funcs = 1;
1934                         mask = 0x5554;
1935                 }
1936
1937                 tmp = (tmp ^ 0xffffffff) & mask;
1938                 while (tmp) {
1939                         if (tmp & 0x1)
1940                                 num_funcs++;
1941                         tmp >>= 0x1;
1942                 }
1943         }
1944
1945         p_hwfn->num_funcs_on_engine = num_funcs;
1946
1947 #ifndef ASIC_ONLY
1948         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1949                 DP_NOTICE(p_hwfn, false,
1950                           "FPGA: Limit number of PFs to 4 [would affect"
1951                           " resource allocation, needed for IOV]\n");
1952                 p_hwfn->num_funcs_on_engine = 4;
1953         }
1954 #endif
1955
1956         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "num_funcs_on_engine = %d\n",
1957                    p_hwfn->num_funcs_on_engine);
1958 }
1959
1960 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
1961                                       struct ecore_ptt *p_ptt)
1962 {
1963         u32 port_mode;
1964
1965 #ifndef ASIC_ONLY
1966         /* Read the port mode */
1967         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1968                 port_mode = 4;
1969         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
1970                  (p_hwfn->p_dev->num_hwfns > 1))
1971                 /* In CMT on emulation, assume 1 port */
1972                 port_mode = 1;
1973         else
1974 #endif
1975                 port_mode = ecore_rd(p_hwfn, p_ptt,
1976                                      CNIG_REG_NW_PORT_MODE_BB_B0);
1977
1978         if (port_mode < 3) {
1979                 p_hwfn->p_dev->num_ports_in_engines = 1;
1980         } else if (port_mode <= 5) {
1981                 p_hwfn->p_dev->num_ports_in_engines = 2;
1982         } else {
1983                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
1984                           p_hwfn->p_dev->num_ports_in_engines);
1985
1986                 /* Default num_ports_in_engines to something */
1987                 p_hwfn->p_dev->num_ports_in_engines = 1;
1988         }
1989 }
1990
1991 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
1992                                       struct ecore_ptt *p_ptt)
1993 {
1994         u32 port;
1995         int i;
1996
1997         p_hwfn->p_dev->num_ports_in_engines = 0;
1998
1999         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2000                 port = ecore_rd(p_hwfn, p_ptt,
2001                                 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2002                 if (port & 1)
2003                         p_hwfn->p_dev->num_ports_in_engines++;
2004         }
2005 }
2006
2007 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2008                                    struct ecore_ptt *p_ptt)
2009 {
2010         if (ECORE_IS_BB(p_hwfn->p_dev))
2011                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2012         else
2013                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2014 }
2015
2016 static enum _ecore_status_t
2017 ecore_get_hw_info(struct ecore_hwfn *p_hwfn,
2018                   struct ecore_ptt *p_ptt,
2019                   enum ecore_pci_personality personality)
2020 {
2021         enum _ecore_status_t rc;
2022
2023         /* TODO In get_hw_info, amoungst others:
2024          * Get MCP FW revision and determine according to it the supported
2025          * featrues (e.g. DCB)
2026          * Get boot mode
2027          * ecore_get_pcie_width_speed, WOL capability.
2028          * Number of global CQ-s (for storage
2029          */
2030         ecore_hw_info_port_num(p_hwfn, p_ptt);
2031
2032 #ifndef ASIC_ONLY
2033         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2034 #endif
2035                 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2036
2037         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2038         if (rc)
2039                 return rc;
2040
2041 #ifndef ASIC_ONLY
2042         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2043 #endif
2044                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2045                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2046 #ifndef ASIC_ONLY
2047         } else {
2048                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2049
2050                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2051                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2052         }
2053 #endif
2054
2055         if (ecore_mcp_is_init(p_hwfn)) {
2056                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2057                         p_hwfn->hw_info.ovlan =
2058                             p_hwfn->mcp_info->func_info.ovlan;
2059
2060                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2061         }
2062
2063         if (personality != ECORE_PCI_DEFAULT)
2064                 p_hwfn->hw_info.personality = personality;
2065         else if (ecore_mcp_is_init(p_hwfn))
2066                 p_hwfn->hw_info.personality =
2067                     p_hwfn->mcp_info->func_info.protocol;
2068
2069 #ifndef ASIC_ONLY
2070         /* To overcome ILT lack for emulation, until at least until we'll have
2071          * a definite answer from system about it, allow only PF0 to be RoCE.
2072          */
2073         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
2074                 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2075 #endif
2076
2077         ecore_get_num_funcs(p_hwfn, p_ptt);
2078
2079         /* Feat num is dependent on personality and on the number of functions
2080          * on the engine. Therefore it should be come after personality
2081          * initialization and after getting the number of functions.
2082          */
2083         return ecore_hw_get_resc(p_hwfn);
2084 }
2085
2086 /* @TMP - this should move to a proper .h */
2087 #define CHIP_NUM_AH                     0x8070
2088
2089 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2090 {
2091         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2092         u32 tmp;
2093
2094         /* Read Vendor Id / Device Id */
2095         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2096                                   &p_dev->vendor_id);
2097         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2098                                   &p_dev->device_id);
2099
2100         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2101                                          MISCS_REG_CHIP_NUM);
2102         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2103                                         MISCS_REG_CHIP_REV);
2104
2105         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2106
2107         /* Determine type */
2108         if (p_dev->device_id == CHIP_NUM_AH)
2109                 p_dev->type = ECORE_DEV_TYPE_AH;
2110         else
2111                 p_dev->type = ECORE_DEV_TYPE_BB;
2112
2113         /* Learn number of HW-functions */
2114         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2115                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2116
2117         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2118                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2119                 p_dev->num_hwfns = 2;
2120         } else {
2121                 p_dev->num_hwfns = 1;
2122         }
2123
2124 #ifndef ASIC_ONLY
2125         if (CHIP_REV_IS_EMUL(p_dev)) {
2126                 /* For some reason we have problems with this register
2127                  * in B0 emulation; Simply assume no CMT
2128                  */
2129                 DP_NOTICE(p_dev->hwfns, false,
2130                           "device on emul - assume no CMT\n");
2131                 p_dev->num_hwfns = 1;
2132         }
2133 #endif
2134
2135         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2136                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2137         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2138         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2139                                           MISCS_REG_CHIP_METAL);
2140         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2141         DP_INFO(p_dev->hwfns,
2142                 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x"
2143                 " Metal: %04x\n",
2144                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2145                 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2146                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2147                 p_dev->chip_metal);
2148
2149         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2150                 DP_NOTICE(p_dev->hwfns, false,
2151                           "The chip type/rev (BB A0) is not supported!\n");
2152                 return ECORE_ABORTED;
2153         }
2154 #ifndef ASIC_ONLY
2155         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2156                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2157                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2158
2159         if (CHIP_REV_IS_EMUL(p_dev)) {
2160                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2161                                MISCS_REG_ECO_RESERVED);
2162                 if (tmp & (1 << 29)) {
2163                         DP_NOTICE(p_hwfn, false,
2164                                   "Emulation: Running on a FULL build\n");
2165                         p_dev->b_is_emul_full = true;
2166                 } else {
2167                         DP_NOTICE(p_hwfn, false,
2168                                   "Emulation: Running on a REDUCED build\n");
2169                 }
2170         }
2171 #endif
2172
2173         return ECORE_SUCCESS;
2174 }
2175
2176 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2177 {
2178         int j;
2179
2180         for_each_hwfn(p_dev, j) {
2181                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2182
2183                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2184                            "Mark hw/fw uninitialized\n");
2185
2186                 p_hwfn->hw_init_done = false;
2187                 p_hwfn->first_on_engine = false;
2188         }
2189 }
2190
2191 static enum _ecore_status_t
2192 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2193                         void OSAL_IOMEM *p_regview,
2194                         void OSAL_IOMEM *p_doorbells,
2195                         enum ecore_pci_personality personality)
2196 {
2197         enum _ecore_status_t rc = ECORE_SUCCESS;
2198
2199         /* Split PCI bars evenly between hwfns */
2200         p_hwfn->regview = p_regview;
2201         p_hwfn->doorbells = p_doorbells;
2202
2203         /* Validate that chip access is feasible */
2204         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2205                 DP_ERR(p_hwfn,
2206                        "Reading the ME register returns all Fs;"
2207                        " Preventing further chip access\n");
2208                 return ECORE_INVAL;
2209         }
2210
2211         get_function_id(p_hwfn);
2212
2213         /* Allocate PTT pool */
2214         rc = ecore_ptt_pool_alloc(p_hwfn);
2215         if (rc) {
2216                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2217                 goto err0;
2218         }
2219
2220         /* Allocate the main PTT */
2221         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2222
2223         /* First hwfn learns basic information, e.g., number of hwfns */
2224         if (!p_hwfn->my_id) {
2225                 rc = ecore_get_dev_info(p_hwfn->p_dev);
2226                 if (rc != ECORE_SUCCESS)
2227                         goto err1;
2228         }
2229
2230         ecore_hw_hwfn_prepare(p_hwfn);
2231
2232         /* Initialize MCP structure */
2233         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2234         if (rc) {
2235                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2236                 goto err1;
2237         }
2238
2239         /* Read the device configuration information from the HW and SHMEM */
2240         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2241         if (rc) {
2242                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
2243                 goto err2;
2244         }
2245
2246         /* Allocate the init RT array and initialize the init-ops engine */
2247         rc = ecore_init_alloc(p_hwfn);
2248         if (rc) {
2249                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
2250                 goto err2;
2251         }
2252 #ifndef ASIC_ONLY
2253         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2254                 DP_NOTICE(p_hwfn, false,
2255                           "FPGA: workaround; Prevent DMAE parities\n");
2256                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
2257
2258                 DP_NOTICE(p_hwfn, false,
2259                           "FPGA: workaround: Set VF bar0 size\n");
2260                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2261                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
2262         }
2263 #endif
2264
2265         return rc;
2266 err2:
2267         ecore_mcp_free(p_hwfn);
2268 err1:
2269         ecore_hw_hwfn_free(p_hwfn);
2270 err0:
2271         return rc;
2272 }
2273
2274 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality)
2275 {
2276         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2277         enum _ecore_status_t rc;
2278
2279         /* Store the precompiled init data ptrs */
2280         ecore_init_iro_array(p_dev);
2281
2282         /* Initialize the first hwfn - will learn number of hwfns */
2283         rc = ecore_hw_prepare_single(p_hwfn,
2284                                      p_dev->regview,
2285                                      p_dev->doorbells, personality);
2286         if (rc != ECORE_SUCCESS)
2287                 return rc;
2288
2289         personality = p_hwfn->hw_info.personality;
2290
2291         /* initialalize 2nd hwfn if necessary */
2292         if (p_dev->num_hwfns > 1) {
2293                 void OSAL_IOMEM *p_regview, *p_doorbell;
2294                 u8 OSAL_IOMEM *addr;
2295
2296                 /* adjust bar offset for second engine */
2297                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
2298                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
2299                 p_regview = (void OSAL_IOMEM *)addr;
2300
2301                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
2302                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
2303                 p_doorbell = (void OSAL_IOMEM *)addr;
2304
2305                 /* prepare second hw function */
2306                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
2307                                              p_doorbell, personality);
2308
2309                 /* in case of error, need to free the previously
2310                  * initialiazed hwfn 0
2311                  */
2312                 if (rc != ECORE_SUCCESS) {
2313                         ecore_init_free(p_hwfn);
2314                         ecore_mcp_free(p_hwfn);
2315                         ecore_hw_hwfn_free(p_hwfn);
2316                         return rc;
2317                 }
2318         }
2319
2320         return ECORE_SUCCESS;
2321 }
2322
2323 void ecore_hw_remove(struct ecore_dev *p_dev)
2324 {
2325         int i;
2326
2327         for_each_hwfn(p_dev, i) {
2328                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2329
2330                 ecore_init_free(p_hwfn);
2331                 ecore_hw_hwfn_free(p_hwfn);
2332                 ecore_mcp_free(p_hwfn);
2333
2334                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
2335         }
2336 }
2337
2338 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
2339                                       struct ecore_chain *p_chain)
2340 {
2341         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
2342         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2343         struct ecore_chain_next *p_next;
2344         u32 size, i;
2345
2346         if (!p_virt)
2347                 return;
2348
2349         size = p_chain->elem_size * p_chain->usable_per_page;
2350
2351         for (i = 0; i < p_chain->page_cnt; i++) {
2352                 if (!p_virt)
2353                         break;
2354
2355                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
2356                 p_virt_next = p_next->next_virt;
2357                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2358
2359                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
2360                                        ECORE_CHAIN_PAGE_SIZE);
2361
2362                 p_virt = p_virt_next;
2363                 p_phys = p_phys_next;
2364         }
2365 }
2366
2367 static void ecore_chain_free_single(struct ecore_dev *p_dev,
2368                                     struct ecore_chain *p_chain)
2369 {
2370         if (!p_chain->p_virt_addr)
2371                 return;
2372
2373         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
2374                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
2375 }
2376
2377 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
2378                                  struct ecore_chain *p_chain)
2379 {
2380         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2381         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
2382         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2383
2384         if (!pp_virt_addr_tbl)
2385                 return;
2386
2387         if (!p_chain->pbl.p_virt_table)
2388                 goto out;
2389
2390         for (i = 0; i < page_cnt; i++) {
2391                 if (!pp_virt_addr_tbl[i])
2392                         break;
2393
2394                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
2395                                        *(dma_addr_t *)p_pbl_virt,
2396                                        ECORE_CHAIN_PAGE_SIZE);
2397
2398                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2399         }
2400
2401         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2402         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
2403                                p_chain->pbl.p_phys_table, pbl_size);
2404 out:
2405         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
2406 }
2407
2408 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2409 {
2410         switch (p_chain->mode) {
2411         case ECORE_CHAIN_MODE_NEXT_PTR:
2412                 ecore_chain_free_next_ptr(p_dev, p_chain);
2413                 break;
2414         case ECORE_CHAIN_MODE_SINGLE:
2415                 ecore_chain_free_single(p_dev, p_chain);
2416                 break;
2417         case ECORE_CHAIN_MODE_PBL:
2418                 ecore_chain_free_pbl(p_dev, p_chain);
2419                 break;
2420         }
2421 }
2422
2423 static enum _ecore_status_t
2424 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
2425                                enum ecore_chain_cnt_type cnt_type,
2426                                osal_size_t elem_size, u32 page_cnt)
2427 {
2428         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2429
2430         /* The actual chain size can be larger than the maximal possible value
2431          * after rounding up the requested elements number to pages, and after
2432          * taking into acount the unusuable elements (next-ptr elements).
2433          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2434          * size/capacity fields are of a u32 type.
2435          */
2436         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
2437              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
2438             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
2439              chain_size > ECORE_U32_MAX)) {
2440                 DP_NOTICE(p_dev, true,
2441                           "The actual chain size (0x%lx) is larger than"
2442                           " the maximal possible value\n",
2443                           (unsigned long)chain_size);
2444                 return ECORE_INVAL;
2445         }
2446
2447         return ECORE_SUCCESS;
2448 }
2449
2450 static enum _ecore_status_t
2451 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2452 {
2453         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
2454         dma_addr_t p_phys = 0;
2455         u32 i;
2456
2457         for (i = 0; i < p_chain->page_cnt; i++) {
2458                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2459                                                  ECORE_CHAIN_PAGE_SIZE);
2460                 if (!p_virt) {
2461                         DP_NOTICE(p_dev, true,
2462                                   "Failed to allocate chain memory\n");
2463                         return ECORE_NOMEM;
2464                 }
2465
2466                 if (i == 0) {
2467                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2468                         ecore_chain_reset(p_chain);
2469                 } else {
2470                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2471                                                        p_virt, p_phys);
2472                 }
2473
2474                 p_virt_prev = p_virt;
2475         }
2476         /* Last page's next element should point to the beginning of the
2477          * chain.
2478          */
2479         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2480                                        p_chain->p_virt_addr,
2481                                        p_chain->p_phys_addr);
2482
2483         return ECORE_SUCCESS;
2484 }
2485
2486 static enum _ecore_status_t
2487 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2488 {
2489         void *p_virt = OSAL_NULL;
2490         dma_addr_t p_phys = 0;
2491
2492         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
2493         if (!p_virt) {
2494                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
2495                 return ECORE_NOMEM;
2496         }
2497
2498         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2499         ecore_chain_reset(p_chain);
2500
2501         return ECORE_SUCCESS;
2502 }
2503
2504 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
2505                                                   struct ecore_chain *p_chain)
2506 {
2507         void *p_virt = OSAL_NULL;
2508         u8 *p_pbl_virt = OSAL_NULL;
2509         void **pp_virt_addr_tbl = OSAL_NULL;
2510         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2511         u32 page_cnt = p_chain->page_cnt, size, i;
2512
2513         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2514         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
2515         if (!pp_virt_addr_tbl) {
2516                 DP_NOTICE(p_dev, true,
2517                           "Failed to allocate memory for the chain"
2518                           " virtual addresses table\n");
2519                 return ECORE_NOMEM;
2520         }
2521         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
2522
2523         /* The allocation of the PBL table is done with its full size, since it
2524          * is expected to be successive.
2525          */
2526         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2527         p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
2528         if (!p_pbl_virt) {
2529                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
2530                 return ECORE_NOMEM;
2531         }
2532
2533         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2534                                  pp_virt_addr_tbl);
2535
2536         for (i = 0; i < page_cnt; i++) {
2537                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2538                                                  ECORE_CHAIN_PAGE_SIZE);
2539                 if (!p_virt) {
2540                         DP_NOTICE(p_dev, true,
2541                                   "Failed to allocate chain memory\n");
2542                         return ECORE_NOMEM;
2543                 }
2544
2545                 if (i == 0) {
2546                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2547                         ecore_chain_reset(p_chain);
2548                 }
2549
2550                 /* Fill the PBL table with the physical address of the page */
2551                 *(dma_addr_t *)p_pbl_virt = p_phys;
2552                 /* Keep the virtual address of the page */
2553                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2554
2555                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2556         }
2557
2558         return ECORE_SUCCESS;
2559 }
2560
2561 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
2562                                        enum ecore_chain_use_mode intended_use,
2563                                        enum ecore_chain_mode mode,
2564                                        enum ecore_chain_cnt_type cnt_type,
2565                                        u32 num_elems, osal_size_t elem_size,
2566                                        struct ecore_chain *p_chain)
2567 {
2568         u32 page_cnt;
2569         enum _ecore_status_t rc = ECORE_SUCCESS;
2570
2571         if (mode == ECORE_CHAIN_MODE_SINGLE)
2572                 page_cnt = 1;
2573         else
2574                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2575
2576         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
2577                                             page_cnt);
2578         if (rc) {
2579                 DP_NOTICE(p_dev, true,
2580                           "Cannot allocate a chain with the given arguments:\n"
2581                           " [use_mode %d, mode %d, cnt_type %d, num_elems %d,"
2582                           " elem_size %zu]\n",
2583                           intended_use, mode, cnt_type, num_elems, elem_size);
2584                 return rc;
2585         }
2586
2587         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
2588                                 mode, cnt_type);
2589
2590         switch (mode) {
2591         case ECORE_CHAIN_MODE_NEXT_PTR:
2592                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
2593                 break;
2594         case ECORE_CHAIN_MODE_SINGLE:
2595                 rc = ecore_chain_alloc_single(p_dev, p_chain);
2596                 break;
2597         case ECORE_CHAIN_MODE_PBL:
2598                 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
2599                 break;
2600         }
2601         if (rc)
2602                 goto nomem;
2603
2604         return ECORE_SUCCESS;
2605
2606 nomem:
2607         ecore_chain_free(p_dev, p_chain);
2608         return rc;
2609 }
2610
2611 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
2612                                        u16 src_id, u16 *dst_id)
2613 {
2614         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
2615                 u16 min, max;
2616
2617                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
2618                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
2619                 DP_NOTICE(p_hwfn, true,
2620                           "l2_queue id [%d] is not valid, available"
2621                           " indices [%d - %d]\n",
2622                           src_id, min, max);
2623
2624                 return ECORE_INVAL;
2625         }
2626
2627         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
2628
2629         return ECORE_SUCCESS;
2630 }
2631
2632 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
2633                                     u8 src_id, u8 *dst_id)
2634 {
2635         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
2636                 u8 min, max;
2637
2638                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
2639                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
2640                 DP_NOTICE(p_hwfn, true,
2641                           "vport id [%d] is not valid, available"
2642                           " indices [%d - %d]\n",
2643                           src_id, min, max);
2644
2645                 return ECORE_INVAL;
2646         }
2647
2648         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
2649
2650         return ECORE_SUCCESS;
2651 }
2652
2653 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
2654                                       u8 src_id, u8 *dst_id)
2655 {
2656         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
2657                 u8 min, max;
2658
2659                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
2660                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
2661                 DP_NOTICE(p_hwfn, true,
2662                           "rss_eng id [%d] is not valid,avail idx [%d - %d]\n",
2663                           src_id, min, max);
2664
2665                 return ECORE_INVAL;
2666         }
2667
2668         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
2669
2670         return ECORE_SUCCESS;
2671 }
2672
2673 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
2674                                               struct ecore_ptt *p_ptt,
2675                                               u8 *p_filter)
2676 {
2677         u32 high, low, en;
2678         int i;
2679
2680         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2681                 return ECORE_SUCCESS;
2682
2683         high = p_filter[1] | (p_filter[0] << 8);
2684         low = p_filter[5] | (p_filter[4] << 8) |
2685             (p_filter[3] << 16) | (p_filter[2] << 24);
2686
2687         /* Find a free entry and utilize it */
2688         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2689                 en = ecore_rd(p_hwfn, p_ptt,
2690                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2691                 if (en)
2692                         continue;
2693                 ecore_wr(p_hwfn, p_ptt,
2694                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2695                          2 * i * sizeof(u32), low);
2696                 ecore_wr(p_hwfn, p_ptt,
2697                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2698                          (2 * i + 1) * sizeof(u32), high);
2699                 ecore_wr(p_hwfn, p_ptt,
2700                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2701                 ecore_wr(p_hwfn, p_ptt,
2702                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2703                          i * sizeof(u32), 0);
2704                 ecore_wr(p_hwfn, p_ptt,
2705                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2706                 break;
2707         }
2708         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2709                 DP_NOTICE(p_hwfn, false,
2710                           "Failed to find an empty LLH filter to utilize\n");
2711                 return ECORE_INVAL;
2712         }
2713
2714         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2715                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
2716                    p_filter[0], p_filter[1], p_filter[2],
2717                    p_filter[3], p_filter[4], p_filter[5], i);
2718
2719         return ECORE_SUCCESS;
2720 }
2721
2722 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
2723                                  struct ecore_ptt *p_ptt, u8 *p_filter)
2724 {
2725         u32 high, low;
2726         int i;
2727
2728         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2729                 return;
2730
2731         high = p_filter[1] | (p_filter[0] << 8);
2732         low = p_filter[5] | (p_filter[4] << 8) |
2733             (p_filter[3] << 16) | (p_filter[2] << 24);
2734
2735         /* Find the entry and clean it */
2736         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2737                 if (ecore_rd(p_hwfn, p_ptt,
2738                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2739                              2 * i * sizeof(u32)) != low)
2740                         continue;
2741                 if (ecore_rd(p_hwfn, p_ptt,
2742                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2743                              (2 * i + 1) * sizeof(u32)) != high)
2744                         continue;
2745
2746                 ecore_wr(p_hwfn, p_ptt,
2747                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2748                 ecore_wr(p_hwfn, p_ptt,
2749                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2750                          2 * i * sizeof(u32), 0);
2751                 ecore_wr(p_hwfn, p_ptt,
2752                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2753                          (2 * i + 1) * sizeof(u32), 0);
2754                 break;
2755         }
2756         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2757                 DP_NOTICE(p_hwfn, false,
2758                           "Tried to remove a non-configured filter\n");
2759 }
2760
2761 enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,
2762                                                     struct ecore_ptt *p_ptt,
2763                                                     u16 filter)
2764 {
2765         u32 high, low, en;
2766         int i;
2767
2768         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2769                 return ECORE_SUCCESS;
2770
2771         high = filter;
2772         low = 0;
2773
2774         /* Find a free entry and utilize it */
2775         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2776                 en = ecore_rd(p_hwfn, p_ptt,
2777                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2778                 if (en)
2779                         continue;
2780                 ecore_wr(p_hwfn, p_ptt,
2781                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2782                          2 * i * sizeof(u32), low);
2783                 ecore_wr(p_hwfn, p_ptt,
2784                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2785                          (2 * i + 1) * sizeof(u32), high);
2786                 ecore_wr(p_hwfn, p_ptt,
2787                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2788                 ecore_wr(p_hwfn, p_ptt,
2789                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2790                          i * sizeof(u32), 1);
2791                 ecore_wr(p_hwfn, p_ptt,
2792                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2793                 break;
2794         }
2795         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2796                 DP_NOTICE(p_hwfn, false,
2797                           "Failed to find an empty LLH filter to utilize\n");
2798                 return ECORE_INVAL;
2799         }
2800
2801         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2802                    "ETH type: %x is added at %d\n", filter, i);
2803
2804         return ECORE_SUCCESS;
2805 }
2806
2807 void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,
2808                                        struct ecore_ptt *p_ptt, u16 filter)
2809 {
2810         u32 high, low;
2811         int i;
2812
2813         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2814                 return;
2815
2816         high = filter;
2817         low = 0;
2818
2819         /* Find the entry and clean it */
2820         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2821                 if (ecore_rd(p_hwfn, p_ptt,
2822                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2823                              2 * i * sizeof(u32)) != low)
2824                         continue;
2825                 if (ecore_rd(p_hwfn, p_ptt,
2826                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2827                              (2 * i + 1) * sizeof(u32)) != high)
2828                         continue;
2829
2830                 ecore_wr(p_hwfn, p_ptt,
2831                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2832                 ecore_wr(p_hwfn, p_ptt,
2833                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2834                          2 * i * sizeof(u32), 0);
2835                 ecore_wr(p_hwfn, p_ptt,
2836                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2837                          (2 * i + 1) * sizeof(u32), 0);
2838                 break;
2839         }
2840         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2841                 DP_NOTICE(p_hwfn, false,
2842                           "Tried to remove a non-configured filter\n");
2843 }
2844
2845 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
2846                                  struct ecore_ptt *p_ptt)
2847 {
2848         int i;
2849
2850         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2851                 return;
2852
2853         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2854                 ecore_wr(p_hwfn, p_ptt,
2855                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2856                 ecore_wr(p_hwfn, p_ptt,
2857                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2858                          2 * i * sizeof(u32), 0);
2859                 ecore_wr(p_hwfn, p_ptt,
2860                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2861                          (2 * i + 1) * sizeof(u32), 0);
2862         }
2863 }
2864
2865 enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,
2866                                           struct ecore_ptt *p_ptt)
2867 {
2868         u32 reg_tbl[] = {
2869                 BRB_REG_HEADER_SIZE,
2870                 BTB_REG_HEADER_SIZE,
2871                 CAU_REG_LONG_TIMEOUT_THRESHOLD,
2872                 CCFC_REG_ACTIVITY_COUNTER,
2873                 CDU_REG_CID_ADDR_PARAMS,
2874                 DBG_REG_CLIENT_ENABLE,
2875                 DMAE_REG_INIT,
2876                 DORQ_REG_IFEN,
2877                 GRC_REG_TIMEOUT_EN,
2878                 IGU_REG_BLOCK_CONFIGURATION,
2879                 MCM_REG_INIT,
2880                 MCP2_REG_DBG_DWORD_ENABLE,
2881                 MISC_REG_PORT_MODE,
2882                 MISCS_REG_CLK_100G_MODE,
2883                 MSDM_REG_ENABLE_IN1,
2884                 MSEM_REG_ENABLE_IN,
2885                 NIG_REG_CM_HDR,
2886                 NCSI_REG_CONFIG,
2887                 PBF_REG_INIT,
2888                 PTU_REG_ATC_INIT_ARRAY,
2889                 PCM_REG_INIT,
2890                 PGLUE_B_REG_ADMIN_PER_PF_REGION,
2891                 PRM_REG_DISABLE_PRM,
2892                 PRS_REG_SOFT_RST,
2893                 PSDM_REG_ENABLE_IN1,
2894                 PSEM_REG_ENABLE_IN,
2895                 PSWRQ_REG_DBG_SELECT,
2896                 PSWRQ2_REG_CDUT_P_SIZE,
2897                 PSWHST_REG_DISCARD_INTERNAL_WRITES,
2898                 PSWHST2_REG_DBGSYN_ALMOST_FULL_THR,
2899                 PSWRD_REG_DBG_SELECT,
2900                 PSWRD2_REG_CONF11,
2901                 PSWWR_REG_USDM_FULL_TH,
2902                 PSWWR2_REG_CDU_FULL_TH2,
2903                 QM_REG_MAXPQSIZE_0,
2904                 RSS_REG_RSS_INIT_EN,
2905                 RDIF_REG_STOP_ON_ERROR,
2906                 SRC_REG_SOFT_RST,
2907                 TCFC_REG_ACTIVITY_COUNTER,
2908                 TCM_REG_INIT,
2909                 TM_REG_PXP_READ_DATA_FIFO_INIT,
2910                 TSDM_REG_ENABLE_IN1,
2911                 TSEM_REG_ENABLE_IN,
2912                 TDIF_REG_STOP_ON_ERROR,
2913                 UCM_REG_INIT,
2914                 UMAC_REG_IPG_HD_BKP_CNTL_BB_B0,
2915                 USDM_REG_ENABLE_IN1,
2916                 USEM_REG_ENABLE_IN,
2917                 XCM_REG_INIT,
2918                 XSDM_REG_ENABLE_IN1,
2919                 XSEM_REG_ENABLE_IN,
2920                 YCM_REG_INIT,
2921                 YSDM_REG_ENABLE_IN1,
2922                 YSEM_REG_ENABLE_IN,
2923                 XYLD_REG_SCBD_STRICT_PRIO,
2924                 TMLD_REG_SCBD_STRICT_PRIO,
2925                 MULD_REG_SCBD_STRICT_PRIO,
2926                 YULD_REG_SCBD_STRICT_PRIO,
2927         };
2928         u32 test_val[] = { 0x0, 0x1 };
2929         u32 val, save_val, i, j;
2930
2931         for (i = 0; i < OSAL_ARRAY_SIZE(test_val); i++) {
2932                 for (j = 0; j < OSAL_ARRAY_SIZE(reg_tbl); j++) {
2933                         save_val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
2934                         ecore_wr(p_hwfn, p_ptt, reg_tbl[j], test_val[i]);
2935                         val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
2936                         /* Restore the original register's value */
2937                         ecore_wr(p_hwfn, p_ptt, reg_tbl[j], save_val);
2938                         if (val != test_val[i]) {
2939                                 DP_INFO(p_hwfn->p_dev,
2940                                         "offset 0x%x: val 0x%x != 0x%x\n",
2941                                         reg_tbl[j], val, test_val[i]);
2942                                 return ECORE_AGAIN;
2943                         }
2944                 }
2945         }
2946         return ECORE_SUCCESS;
2947 }
2948
2949 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
2950                                                struct ecore_ptt *p_ptt,
2951                                                u32 hw_addr, void *p_qzone,
2952                                                osal_size_t qzone_size,
2953                                                u8 timeset)
2954 {
2955         struct coalescing_timeset *p_coalesce_timeset;
2956
2957         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
2958                 DP_NOTICE(p_hwfn, true,
2959                           "Coalescing configuration not enabled\n");
2960                 return ECORE_INVAL;
2961         }
2962
2963         OSAL_MEMSET(p_qzone, 0, qzone_size);
2964         p_coalesce_timeset = p_qzone;
2965         p_coalesce_timeset->timeset = timeset;
2966         p_coalesce_timeset->valid = 1;
2967         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_qzone, qzone_size);
2968
2969         return ECORE_SUCCESS;
2970 }
2971
2972 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
2973                                             struct ecore_ptt *p_ptt,
2974                                             u8 coalesce, u8 qid)
2975 {
2976         struct ustorm_eth_queue_zone qzone;
2977         u16 fw_qid = 0;
2978         u32 address;
2979         u8 timeset;
2980         enum _ecore_status_t rc;
2981
2982         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2983         if (rc != ECORE_SUCCESS)
2984                 return rc;
2985
2986         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2987         /* Translate the coalescing time into a timeset, according to:
2988          * Timeout[Rx] = TimeSet[Rx] << (TimerRes[Rx] + 1)
2989          */
2990         timeset = coalesce >> (ECORE_CAU_DEF_RX_TIMER_RES + 1);
2991
2992         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
2993                                 sizeof(struct ustorm_eth_queue_zone), timeset);
2994         if (rc != ECORE_SUCCESS)
2995                 goto out;
2996
2997         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
2998 out:
2999         return rc;
3000 }
3001
3002 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3003                                             struct ecore_ptt *p_ptt,
3004                                             u8 coalesce, u8 qid)
3005 {
3006         struct ystorm_eth_queue_zone qzone;
3007         u16 fw_qid = 0;
3008         u32 address;
3009         u8 timeset;
3010         enum _ecore_status_t rc;
3011
3012         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3013         if (rc != ECORE_SUCCESS)
3014                 return rc;
3015
3016         address = BAR0_MAP_REG_YSDM_RAM + YSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3017         /* Translate the coalescing time into a timeset, according to:
3018          * Timeout[Tx] = TimeSet[Tx] << (TimerRes[Tx] + 1)
3019          */
3020         timeset = coalesce >> (ECORE_CAU_DEF_TX_TIMER_RES + 1);
3021
3022         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3023                                 sizeof(struct ystorm_eth_queue_zone), timeset);
3024         if (rc != ECORE_SUCCESS)
3025                 goto out;
3026
3027         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3028 out:
3029         return rc;
3030 }
3031
3032 /* Calculate final WFQ values for all vports and configure it.
3033  * After this configuration each vport must have
3034  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3035  */
3036 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3037                                                struct ecore_ptt *p_ptt,
3038                                                u32 min_pf_rate)
3039 {
3040         struct init_qm_vport_params *vport_params;
3041         int i, num_vports;
3042
3043         vport_params = p_hwfn->qm_info.qm_vport_params;
3044         num_vports = p_hwfn->qm_info.num_vports;
3045
3046         for (i = 0; i < num_vports; i++) {
3047                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3048
3049                 vport_params[i].vport_wfq =
3050                     (wfq_speed * ECORE_WFQ_UNIT) / min_pf_rate;
3051                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3052                                      vport_params[i].first_tx_pq_id,
3053                                      vport_params[i].vport_wfq);
3054         }
3055 }
3056
3057 static void
3058 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3059 {
3060         int i, num_vports;
3061         u32 min_speed;
3062
3063         num_vports = p_hwfn->qm_info.num_vports;
3064         min_speed = min_pf_rate / num_vports;
3065
3066         for (i = 0; i < num_vports; i++) {
3067                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3068                 p_hwfn->qm_info.wfq_data[i].default_min_speed = min_speed;
3069         }
3070 }
3071
3072 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3073                                              struct ecore_ptt *p_ptt,
3074                                              u32 min_pf_rate)
3075 {
3076         struct init_qm_vport_params *vport_params;
3077         int i, num_vports;
3078
3079         vport_params = p_hwfn->qm_info.qm_vport_params;
3080         num_vports = p_hwfn->qm_info.num_vports;
3081
3082         for (i = 0; i < num_vports; i++) {
3083                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3084                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3085                                      vport_params[i].first_tx_pq_id,
3086                                      vport_params[i].vport_wfq);
3087         }
3088 }
3089
3090 /* validate wfq for a given vport and required min rate */
3091 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3092                                                  u16 vport_id, u32 req_rate,
3093                                                  u32 min_pf_rate)
3094 {
3095         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3096         int non_requested_count = 0, req_count = 0, i, num_vports;
3097
3098         num_vports = p_hwfn->qm_info.num_vports;
3099
3100         /* Check pre-set data for some of the vports */
3101         for (i = 0; i < num_vports; i++) {
3102                 u32 tmp_speed;
3103
3104                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3105                         req_count++;
3106                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3107                         total_req_min_rate += tmp_speed;
3108                 }
3109         }
3110
3111         /* Include current vport data as well */
3112         req_count++;
3113         total_req_min_rate += req_rate;
3114         non_requested_count = p_hwfn->qm_info.num_vports - req_count;
3115
3116         /* validate possible error cases */
3117         if (req_rate > min_pf_rate) {
3118                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3119                            "Vport [%d] - Requested rate[%d Mbps] is greater"
3120                            " than configured PF min rate[%d Mbps]\n",
3121                            vport_id, req_rate, min_pf_rate);
3122                 return ECORE_INVAL;
3123         }
3124
3125         if (req_rate * ECORE_WFQ_UNIT / min_pf_rate < 1) {
3126                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3127                            "Vport [%d] - Requested rate[%d Mbps] is less than"
3128                            " one percent of configured PF min rate[%d Mbps]\n",
3129                            vport_id, req_rate, min_pf_rate);
3130                 return ECORE_INVAL;
3131         }
3132
3133         /* TBD - for number of vports greater than 100 */
3134         if (ECORE_WFQ_UNIT / p_hwfn->qm_info.num_vports < 1) {
3135                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3136                            "Number of vports are greater than 100\n");
3137                 return ECORE_INVAL;
3138         }
3139
3140         if (total_req_min_rate > min_pf_rate) {
3141                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3142                            "Total requested min rate for all vports[%d Mbps]"
3143                            "is greater than configured PF min rate[%d Mbps]\n",
3144                            total_req_min_rate, min_pf_rate);
3145                 return ECORE_INVAL;
3146         }
3147
3148         /* Data left for non requested vports */
3149         total_left_rate = min_pf_rate - total_req_min_rate;
3150         left_rate_per_vp = total_left_rate / non_requested_count;
3151
3152         /* validate if non requested get < 1% of min bw */
3153         if (left_rate_per_vp * ECORE_WFQ_UNIT / min_pf_rate < 1)
3154                 return ECORE_INVAL;
3155
3156         /* now req_rate for given vport passes all scenarios.
3157          * assign final wfq rates to all vports.
3158          */
3159         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3160         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3161
3162         for (i = 0; i < num_vports; i++) {
3163                 if (p_hwfn->qm_info.wfq_data[i].configured)
3164                         continue;
3165
3166                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3167         }
3168
3169         return ECORE_SUCCESS;
3170 }
3171
3172 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
3173                                        struct ecore_ptt *p_ptt,
3174                                        u16 vp_id, u32 rate)
3175 {
3176         struct ecore_mcp_link_state *p_link;
3177         int rc = ECORE_SUCCESS;
3178
3179         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
3180
3181         if (!p_link->min_pf_rate) {
3182                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3183                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3184                 return rc;
3185         }
3186
3187         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3188
3189         if (rc == ECORE_SUCCESS)
3190                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3191                                                    p_link->min_pf_rate);
3192         else
3193                 DP_NOTICE(p_hwfn, false,
3194                           "Validation failed while configuring min rate\n");
3195
3196         return rc;
3197 }
3198
3199 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
3200                                                    struct ecore_ptt *p_ptt,
3201                                                    u32 min_pf_rate)
3202 {
3203         int rc = ECORE_SUCCESS;
3204         bool use_wfq = false;
3205         u16 i, num_vports;
3206
3207         num_vports = p_hwfn->qm_info.num_vports;
3208
3209         /* Validate all pre configured vports for wfq */
3210         for (i = 0; i < num_vports; i++) {
3211                 if (p_hwfn->qm_info.wfq_data[i].configured) {
3212                         u32 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3213
3214                         use_wfq = true;
3215                         rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3216                         if (rc == ECORE_INVAL) {
3217                                 DP_NOTICE(p_hwfn, false,
3218                                           "Validation failed while"
3219                                           " configuring min rate\n");
3220                                 break;
3221                         }
3222                 }
3223         }
3224
3225         if (rc == ECORE_SUCCESS && use_wfq)
3226                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3227         else
3228                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3229
3230         return rc;
3231 }
3232
3233 /* Main API for ecore clients to configure vport min rate.
3234  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3235  * rate - Speed in Mbps needs to be assigned to a given vport.
3236  */
3237 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
3238 {
3239         int i, rc = ECORE_INVAL;
3240
3241         /* TBD - for multiple hardware functions - that is 100 gig */
3242         if (p_dev->num_hwfns > 1) {
3243                 DP_NOTICE(p_dev, false,
3244                           "WFQ configuration is not supported for this dev\n");
3245                 return rc;
3246         }
3247
3248         for_each_hwfn(p_dev, i) {
3249                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3250                 struct ecore_ptt *p_ptt;
3251
3252                 p_ptt = ecore_ptt_acquire(p_hwfn);
3253                 if (!p_ptt)
3254                         return ECORE_TIMEOUT;
3255
3256                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3257
3258                 if (rc != ECORE_SUCCESS) {
3259                         ecore_ptt_release(p_hwfn, p_ptt);
3260                         return rc;
3261                 }
3262
3263                 ecore_ptt_release(p_hwfn, p_ptt);
3264         }
3265
3266         return rc;
3267 }
3268
3269 /* API to configure WFQ from mcp link change */
3270 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
3271                                            u32 min_pf_rate)
3272 {
3273         int i;
3274
3275         /* TBD - for multiple hardware functions - that is 100 gig */
3276         if (p_dev->num_hwfns > 1) {
3277                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
3278                            "WFQ configuration is not supported for this dev\n");
3279                 return;
3280         }
3281
3282         for_each_hwfn(p_dev, i) {
3283                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3284
3285                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3286                                                         p_hwfn->p_dpc_ptt,
3287                                                         min_pf_rate);
3288         }
3289 }
3290
3291 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
3292                                        struct ecore_ptt *p_ptt,
3293                                        struct ecore_mcp_link_state *p_link,
3294                                        u8 max_bw)
3295 {
3296         int rc = ECORE_SUCCESS;
3297
3298         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3299
3300         if (!p_link->line_speed)
3301                 return rc;
3302
3303         p_link->speed = (p_link->line_speed * max_bw) / 100;
3304
3305         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, p_link->speed);
3306
3307         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3308                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3309                    p_link->speed);
3310
3311         return rc;
3312 }
3313
3314 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3315 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
3316 {
3317         int i, rc = ECORE_INVAL;
3318
3319         if (max_bw < 1 || max_bw > 100) {
3320                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
3321                 return rc;
3322         }
3323
3324         for_each_hwfn(p_dev, i) {
3325                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3326                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3327                 struct ecore_mcp_link_state *p_link;
3328                 struct ecore_ptt *p_ptt;
3329
3330                 p_link = &p_lead->mcp_info->link_output;
3331
3332                 p_ptt = ecore_ptt_acquire(p_hwfn);
3333                 if (!p_ptt)
3334                         return ECORE_TIMEOUT;
3335
3336                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3337                                                         p_link, max_bw);
3338                 if (rc != ECORE_SUCCESS) {
3339                         ecore_ptt_release(p_hwfn, p_ptt);
3340                         return rc;
3341                 }
3342
3343                 ecore_ptt_release(p_hwfn, p_ptt);
3344         }
3345
3346         return rc;
3347 }
3348
3349 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
3350                                        struct ecore_ptt *p_ptt,
3351                                        struct ecore_mcp_link_state *p_link,
3352                                        u8 min_bw)
3353 {
3354         int rc = ECORE_SUCCESS;
3355
3356         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3357
3358         if (!p_link->line_speed)
3359                 return rc;
3360
3361         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3362
3363         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3364
3365         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3366                    "Configured MIN bandwidth to be %d Mb/sec\n",
3367                    p_link->min_pf_rate);
3368
3369         return rc;
3370 }
3371
3372 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3373 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
3374 {
3375         int i, rc = ECORE_INVAL;
3376
3377         if (min_bw < 1 || min_bw > 100) {
3378                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
3379                 return rc;
3380         }
3381
3382         for_each_hwfn(p_dev, i) {
3383                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3384                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3385                 struct ecore_mcp_link_state *p_link;
3386                 struct ecore_ptt *p_ptt;
3387
3388                 p_link = &p_lead->mcp_info->link_output;
3389
3390                 p_ptt = ecore_ptt_acquire(p_hwfn);
3391                 if (!p_ptt)
3392                         return ECORE_TIMEOUT;
3393
3394                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3395                                                         p_link, min_bw);
3396                 if (rc != ECORE_SUCCESS) {
3397                         ecore_ptt_release(p_hwfn, p_ptt);
3398                         return rc;
3399                 }
3400
3401                 if (p_link->min_pf_rate) {
3402                         u32 min_rate = p_link->min_pf_rate;
3403
3404                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3405                                                                      p_ptt,
3406                                                                      min_rate);
3407                 }
3408
3409                 ecore_ptt_release(p_hwfn, p_ptt);
3410         }
3411
3412         return rc;
3413 }
3414
3415 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
3416 {
3417         struct ecore_mcp_link_state *p_link;
3418
3419         p_link = &p_hwfn->mcp_info->link_output;
3420
3421         if (p_link->min_pf_rate)
3422                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3423                                                  p_link->min_pf_rate);
3424
3425         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
3426                     sizeof(*p_hwfn->qm_info.wfq_data) *
3427                     p_hwfn->qm_info.num_vports);
3428 }
3429
3430 int ecore_device_num_engines(struct ecore_dev *p_dev)
3431 {
3432         return ECORE_IS_BB(p_dev) ? 2 : 1;
3433 }
3434
3435 int ecore_device_num_ports(struct ecore_dev *p_dev)
3436 {
3437         /* in CMT always only one port */
3438         if (p_dev->num_hwfns > 1)
3439                 return 1;
3440
3441         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
3442 }