drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /******************** Doorbell Recovery *******************/
  46 /* The doorbell recovery mechanism consists of a list of entries which represent
  47  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  48  * entity needs to register with the mechanism and provide the parameters
  49  * describing it's doorbell, including a location where last used doorbell data
  50  * can be found. The doorbell execute function will traverse the list and
  51  * doorbell all of the registered entries.
  52  */
  53 struct ecore_db_recovery_entry {
  54         osal_list_entry_t       list_entry;
  55         void OSAL_IOMEM         *db_addr;
  56         void                    *db_data;
  57         enum ecore_db_rec_width db_width;
  58         enum ecore_db_rec_space db_space;
  59         u8                      hwfn_idx;
  60 };
  61
  62 /* display a single doorbell recovery entry */
  63 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  64                                 struct ecore_db_recovery_entry *db_entry,
  65                                 const char *action)
  66 {
  67         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  68                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  69                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  70                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  71                    db_entry->hwfn_idx);
  72 }
  73
  74 /* doorbell address sanity (address within doorbell bar range) */
  75 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  76                          void *db_data)
  77 {
  78         /* make sure doorbell address  is within the doorbell bar */
  79         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  80                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  81                 OSAL_WARN(true,
  82                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  83                           db_addr, p_dev->doorbells,
  84                           (u8 *)p_dev->doorbells + p_dev->db_size);
  85                 return false;
  86         }
  87
  88         /* make sure doorbell data pointer is not null */
  89         if (!db_data) {
  90                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  91                 return false;
  92         }
  93
  94         return true;
  95 }
  96
  97 /* find hwfn according to the doorbell address */
  98 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  99                                           void OSAL_IOMEM *db_addr)
 100 {
 101         struct ecore_hwfn *p_hwfn;
 102
 103         /* In CMT doorbell bar is split down the middle between engine 0 and
 104          * enigne 1
 105          */
 106         if (ECORE_IS_CMT(p_dev))
 107                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 108                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 109         else
 110                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 111
 112         return p_hwfn;
 113 }
 114
 115 /* add a new entry to the doorbell recovery mechanism */
 116 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 117                                            void OSAL_IOMEM *db_addr,
 118                                            void *db_data,
 119                                            enum ecore_db_rec_width db_width,
 120                                            enum ecore_db_rec_space db_space)
 121 {
 122         struct ecore_db_recovery_entry *db_entry;
 123         struct ecore_hwfn *p_hwfn;
 124
 125         /* shortcircuit VFs, for now */
 126         if (IS_VF(p_dev)) {
 127                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 128                 return ECORE_SUCCESS;
 129         }
 130
 131         /* sanitize doorbell address */
 132         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 133                 return ECORE_INVAL;
 134
 135         /* obtain hwfn from doorbell address */
 136         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 137
 138         /* create entry */
 139         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 140         if (!db_entry) {
 141                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 142                 return ECORE_NOMEM;
 143         }
 144
 145         /* populate entry */
 146         db_entry->db_addr = db_addr;
 147         db_entry->db_data = db_data;
 148         db_entry->db_width = db_width;
 149         db_entry->db_space = db_space;
 150         db_entry->hwfn_idx = p_hwfn->my_id;
 151
 152         /* display */
 153         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 154
 155         /* protect the list */
 156         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 157         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 158                             &p_hwfn->db_recovery_info.list);
 159         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 160
 161         return ECORE_SUCCESS;
 162 }
 163
 164 /* remove an entry from the doorbell recovery mechanism */
 165 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 166                                            void OSAL_IOMEM *db_addr,
 167                                            void *db_data)
 168 {
 169         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 170         enum _ecore_status_t rc = ECORE_INVAL;
 171         struct ecore_hwfn *p_hwfn;
 172
 173         /* shortcircuit VFs, for now */
 174         if (IS_VF(p_dev)) {
 175                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 176                 return ECORE_SUCCESS;
 177         }
 178
 179         /* sanitize doorbell address */
 180         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 181                 return ECORE_INVAL;
 182
 183         /* obtain hwfn from doorbell address */
 184         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 185
 186         /* protect the list */
 187         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 188         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 189                                  &p_hwfn->db_recovery_info.list,
 190                                  list_entry,
 191                                  struct ecore_db_recovery_entry) {
 192                 /* search according to db_data addr since db_addr is not unique
 193                  * (roce)
 194                  */
 195                 if (db_entry->db_data == db_data) {
 196                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 197                                                    "Deleting");
 198                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 199                                                &p_hwfn->db_recovery_info.list);
 200                         rc = ECORE_SUCCESS;
 201                         break;
 202                 }
 203         }
 204
 205         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 206
 207         if (rc == ECORE_INVAL)
 208                 /*OSAL_WARN(true,*/
 209                 DP_NOTICE(p_hwfn, false,
 210                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 211                           db_data, db_addr);
 212         else
 213                 OSAL_FREE(p_dev, db_entry);
 214
 215         return rc;
 216 }
 217
 218 /* initialize the doorbell recovery mechanism */
 219 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 220 {
 221         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 222
 223         /* make sure db_size was set in p_dev */
 224         if (!p_hwfn->p_dev->db_size) {
 225                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 226                 return ECORE_INVAL;
 227         }
 228
 229         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 230 #ifdef CONFIG_ECORE_LOCK_ALLOC
 231         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 232 #endif
 233         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 234         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 235
 236         return ECORE_SUCCESS;
 237 }
 238
 239 /* destroy the doorbell recovery mechanism */
 240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 241 {
 242         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 243
 244         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 245         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 247                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 248                         db_entry = OSAL_LIST_FIRST_ENTRY(
 249                                                 &p_hwfn->db_recovery_info.list,
 250                                                 struct ecore_db_recovery_entry,
 251                                                 list_entry);
 252                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 253                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 254                                                &p_hwfn->db_recovery_info.list);
 255                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 256                 }
 257         }
 258 #ifdef CONFIG_ECORE_LOCK_ALLOC
 259         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 260 #endif
 261         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 262 }
 263
 264 /* print the content of the doorbell recovery mechanism */
 265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 266 {
 267         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 268
 269         DP_NOTICE(p_hwfn, false,
 270                   "Dispalying doorbell recovery database. Counter was %d\n",
 271                   p_hwfn->db_recovery_info.db_recovery_counter);
 272
 273         /* protect the list */
 274         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 275         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 276                                  &p_hwfn->db_recovery_info.list,
 277                                  list_entry,
 278                                  struct ecore_db_recovery_entry) {
 279                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 280         }
 281
 282         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 283 }
 284
 285 /* ring the doorbell of a single doorbell recovery entry */
 286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 287                             struct ecore_db_recovery_entry *db_entry,
 288                             enum ecore_db_rec_exec db_exec)
 289 {
 290         /* Print according to width */
 291         if (db_entry->db_width == DB_REC_WIDTH_32B)
 292                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 293                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 294                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 295         else
 296                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 297                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 298                            db_entry->db_addr,
 299                            *(unsigned long *)(db_entry->db_data));
 300
 301         /* Sanity */
 302         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 303                                  db_entry->db_data))
 304                 return;
 305
 306         /* Flush the write combined buffer. Since there are multiple doorbelling
 307          * entities using the same address, if we don't flush, a transaction
 308          * could be lost.
 309          */
 310         OSAL_WMB(p_hwfn->p_dev);
 311
 312         /* Ring the doorbell */
 313         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 314                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 315                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 316                                       *(u32 *)(db_entry->db_data));
 317                 else
 318                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 319                                         *(u64 *)(db_entry->db_data));
 320         }
 321
 322         /* Flush the write combined buffer. Next doorbell may come from a
 323          * different entity to the same address...
 324          */
 325         OSAL_WMB(p_hwfn->p_dev);
 326 }
 327
 328 /* traverse the doorbell recovery entry list and ring all the doorbells */
 329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 330                                enum ecore_db_rec_exec db_exec)
 331 {
 332         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 333
 334         if (db_exec != DB_REC_ONCE) {
 335                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 336                           p_hwfn->db_recovery_info.db_recovery_counter);
 337
 338                 /* track amount of times recovery was executed */
 339                 p_hwfn->db_recovery_info.db_recovery_counter++;
 340         }
 341
 342         /* protect the list */
 343         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 344         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 345                                  &p_hwfn->db_recovery_info.list,
 346                                  list_entry,
 347                                  struct ecore_db_recovery_entry) {
 348                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 349                 if (db_exec == DB_REC_ONCE)
 350                         break;
 351         }
 352
 353         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 354 }
 355 /******************** Doorbell Recovery end ****************/
 356
 357 /* Configurable */
 358 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 359                                          * load the driver. The number was
 360                                          * arbitrarily set.
 361                                          */
 362
 363 /* Derived */
 364 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 365
 366 enum BAR_ID {
 367         BAR_ID_0,               /* used for GRC */
 368         BAR_ID_1                /* Used for doorbells */
 369 };
 370
 371 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 372                              struct ecore_ptt *p_ptt,
 373                              enum BAR_ID bar_id)
 374 {
 375         u32 bar_reg = (bar_id == BAR_ID_0 ?
 376                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 377         u32 val;
 378
 379         if (IS_VF(p_hwfn->p_dev)) {
 380                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
 381                  * read from actual register, but we're currently not using
 382                  * it for actual doorbelling.
 383                  */
 384                 return 1 << 17;
 385         }
 386
 387         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 388         if (val)
 389                 return 1 << (val + 15);
 390
 391         /* The above registers were updated in the past only in CMT mode. Since
 392          * they were found to be useful MFW started updating them from 8.7.7.0.
 393          * In older MFW versions they are set to 0 which means disabled.
 394          */
 395         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 396                 DP_INFO(p_hwfn,
 397                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 398                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 399         } else {
 400                 DP_INFO(p_hwfn,
 401                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 402                 val = 512 * 1024;
 403         }
 404
 405         return val;
 406 }
 407
 408 void ecore_init_dp(struct ecore_dev *p_dev,
 409                    u32 dp_module, u8 dp_level, void *dp_ctx)
 410 {
 411         u32 i;
 412
 413         p_dev->dp_level = dp_level;
 414         p_dev->dp_module = dp_module;
 415         p_dev->dp_ctx = dp_ctx;
 416         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 417                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 418
 419                 p_hwfn->dp_level = dp_level;
 420                 p_hwfn->dp_module = dp_module;
 421                 p_hwfn->dp_ctx = dp_ctx;
 422         }
 423 }
 424
 425 void ecore_init_struct(struct ecore_dev *p_dev)
 426 {
 427         u8 i;
 428
 429         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 430                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 431
 432                 p_hwfn->p_dev = p_dev;
 433                 p_hwfn->my_id = i;
 434                 p_hwfn->b_active = false;
 435
 436 #ifdef CONFIG_ECORE_LOCK_ALLOC
 437                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 438 #endif
 439                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 440         }
 441
 442         /* hwfn 0 is always active */
 443         p_dev->hwfns[0].b_active = true;
 444
 445         /* set the default cache alignment to 128 (may be overridden later) */
 446         p_dev->cache_shift = 7;
 447 }
 448
 449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 450 {
 451         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 452
 453         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 454         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 455         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 456         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 457 }
 458
 459 void ecore_resc_free(struct ecore_dev *p_dev)
 460 {
 461         int i;
 462
 463         if (IS_VF(p_dev)) {
 464                 for_each_hwfn(p_dev, i)
 465                         ecore_l2_free(&p_dev->hwfns[i]);
 466                 return;
 467         }
 468
 469         OSAL_FREE(p_dev, p_dev->fw_data);
 470
 471         OSAL_FREE(p_dev, p_dev->reset_stats);
 472
 473         for_each_hwfn(p_dev, i) {
 474                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 475
 476                 ecore_cxt_mngr_free(p_hwfn);
 477                 ecore_qm_info_free(p_hwfn);
 478                 ecore_spq_free(p_hwfn);
 479                 ecore_eq_free(p_hwfn);
 480                 ecore_consq_free(p_hwfn);
 481                 ecore_int_free(p_hwfn);
 482                 ecore_iov_free(p_hwfn);
 483                 ecore_l2_free(p_hwfn);
 484                 ecore_dmae_info_free(p_hwfn);
 485                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 486                 /* @@@TBD Flush work-queue ? */
 487
 488                 /* destroy doorbell recovery mechanism */
 489                 ecore_db_recovery_teardown(p_hwfn);
 490         }
 491 }
 492
 493 /******************** QM initialization *******************/
 494
 495 /* bitmaps for indicating active traffic classes.
 496  * Special case for Arrowhead 4 port
 497  */
 498 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 499 #define ACTIVE_TCS_BMAP 0x9f
 500 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 501 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 502
 503 /* determines the physical queue flags for a given PF. */
 504 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 505 {
 506         u32 flags;
 507
 508         /* common flags */
 509         flags = PQ_FLAGS_LB;
 510
 511         /* feature flags */
 512         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 513                 flags |= PQ_FLAGS_VFS;
 514
 515         /* protocol flags */
 516         switch (p_hwfn->hw_info.personality) {
 517         case ECORE_PCI_ETH:
 518                 flags |= PQ_FLAGS_MCOS;
 519                 break;
 520         case ECORE_PCI_FCOE:
 521                 flags |= PQ_FLAGS_OFLD;
 522                 break;
 523         case ECORE_PCI_ISCSI:
 524                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 525                 break;
 526         case ECORE_PCI_ETH_ROCE:
 527                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 528                 break;
 529         case ECORE_PCI_ETH_IWARP:
 530                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 531                          PQ_FLAGS_OFLD;
 532                 break;
 533         default:
 534                 DP_ERR(p_hwfn, "unknown personality %d\n",
 535                        p_hwfn->hw_info.personality);
 536                 return 0;
 537         }
 538         return flags;
 539 }
 540
 541 /* Getters for resource amounts necessary for qm initialization */
 542 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 543 {
 544         return p_hwfn->hw_info.num_hw_tc;
 545 }
 546
 547 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 548 {
 549         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 550                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 551 }
 552
 553 #define NUM_DEFAULT_RLS 1
 554
 555 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 556 {
 557         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 558
 559         /* @DPDK */
 560         /* num RLs can't exceed resource amount of rls or vports or the
 561          * dcqcn qps
 562          */
 563         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 564                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 565
 566         /* make sure after we reserve the default and VF rls we'll have
 567          * something left
 568          */
 569         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 570                 DP_NOTICE(p_hwfn, false,
 571                           "no rate limiters left for PF rate limiting"
 572                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 573                 return 0;
 574         }
 575
 576         /* subtract rls necessary for VFs and one default one for the PF */
 577         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 578
 579         return num_pf_rls;
 580 }
 581
 582 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 583 {
 584         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 585
 586         /* all pqs share the same vport (hence the 1 below), except for vfs
 587          * and pf_rl pqs
 588          */
 589         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 590                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 591                (!!(PQ_FLAGS_VFS & pq_flags)) *
 592                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 593 }
 594
 595 /* calc amount of PQs according to the requested flags */
 596 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 597 {
 598         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 599
 600         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 601                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 602                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 603                 ecore_init_qm_get_num_tcs(p_hwfn) +
 604                (!!(PQ_FLAGS_LB & pq_flags)) +
 605                (!!(PQ_FLAGS_OOO & pq_flags)) +
 606                (!!(PQ_FLAGS_ACK & pq_flags)) +
 607                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 608                (!!(PQ_FLAGS_VFS & pq_flags)) *
 609                 ecore_init_qm_get_num_vfs(p_hwfn);
 610 }
 611
 612 /* initialize the top level QM params */
 613 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 614 {
 615         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 616         bool four_port;
 617
 618         /* pq and vport bases for this PF */
 619         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 620         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 621
 622         /* rate limiting and weighted fair queueing are always enabled */
 623         qm_info->vport_rl_en = 1;
 624         qm_info->vport_wfq_en = 1;
 625
 626         /* TC config is different for AH 4 port */
 627         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 628
 629         /* in AH 4 port we have fewer TCs per port */
 630         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 631                                                      NUM_OF_PHYS_TCS;
 632
 633         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 634          * 4 otherwise
 635          */
 636         if (!qm_info->ooo_tc)
 637                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 638                                               DCBX_TCP_OOO_TC;
 639 }
 640
 641 /* initialize qm vport params */
 642 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 643 {
 644         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 645         u8 i;
 646
 647         /* all vports participate in weighted fair queueing */
 648         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 649                 qm_info->qm_vport_params[i].vport_wfq = 1;
 650 }
 651
 652 /* initialize qm port params */
 653 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 654 {
 655         /* Initialize qm port parameters */
 656         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 657
 658         /* indicate how ooo and high pri traffic is dealt with */
 659         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 660                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 661
 662         for (i = 0; i < num_ports; i++) {
 663                 struct init_qm_port_params *p_qm_port =
 664                         &p_hwfn->qm_info.qm_port_params[i];
 665
 666                 p_qm_port->active = 1;
 667                 p_qm_port->active_phys_tcs = active_phys_tcs;
 668                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 669                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 670         }
 671 }
 672
 673 /* Reset the params which must be reset for qm init. QM init may be called as
 674  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 675  * params may be affected by the init but would simply recalculate to the same
 676  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 677  * affected as these amounts stay the same.
 678  */
 679 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 680 {
 681         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 682
 683         qm_info->num_pqs = 0;
 684         qm_info->num_vports = 0;
 685         qm_info->num_pf_rls = 0;
 686         qm_info->num_vf_pqs = 0;
 687         qm_info->first_vf_pq = 0;
 688         qm_info->first_mcos_pq = 0;
 689         qm_info->first_rl_pq = 0;
 690 }
 691
 692 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 693 {
 694         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 695
 696         qm_info->num_vports++;
 697
 698         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 699                 DP_ERR(p_hwfn,
 700                        "vport overflow! qm_info->num_vports %d,"
 701                        " qm_init_get_num_vports() %d\n",
 702                        qm_info->num_vports,
 703                        ecore_init_qm_get_num_vports(p_hwfn));
 704 }
 705
 706 /* initialize a single pq and manage qm_info resources accounting.
 707  * The pq_init_flags param determines whether the PQ is rate limited
 708  * (for VF or PF)
 709  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 710  * shared)
 711  */
 712
 713 /* flags for pq init */
 714 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 715 #define PQ_INIT_PF_RL           (1 << 1)
 716 #define PQ_INIT_VF_RL           (1 << 2)
 717
 718 /* defines for pq init */
 719 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 720 #define PQ_INIT_DEFAULT_TC              0
 721 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 722
 723 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 724                              struct ecore_qm_info *qm_info,
 725                              u8 tc, u32 pq_init_flags)
 726 {
 727         u16 pq_idx = qm_info->num_pqs, max_pq =
 728                                         ecore_init_qm_get_num_pqs(p_hwfn);
 729
 730         if (pq_idx > max_pq)
 731                 DP_ERR(p_hwfn,
 732                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 733
 734         /* init pq params */
 735         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 736                                                  qm_info->num_vports;
 737         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 738         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 739         qm_info->qm_pq_params[pq_idx].rl_valid =
 740                 (pq_init_flags & PQ_INIT_PF_RL ||
 741                  pq_init_flags & PQ_INIT_VF_RL);
 742
 743         /* qm params accounting */
 744         qm_info->num_pqs++;
 745         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 746                 qm_info->num_vports++;
 747
 748         if (pq_init_flags & PQ_INIT_PF_RL)
 749                 qm_info->num_pf_rls++;
 750
 751         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 752                 DP_ERR(p_hwfn,
 753                        "vport overflow! qm_info->num_vports %d,"
 754                        " qm_init_get_num_vports() %d\n",
 755                        qm_info->num_vports,
 756                        ecore_init_qm_get_num_vports(p_hwfn));
 757
 758         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 759                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 760                        " qm_init_get_num_pf_rls() %d\n",
 761                        qm_info->num_pf_rls,
 762                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 763 }
 764
 765 /* get pq index according to PQ_FLAGS */
 766 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 767                                              u32 pq_flags)
 768 {
 769         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 770
 771         /* Can't have multiple flags set here */
 772         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 773                                 sizeof(pq_flags)) > 1)
 774                 goto err;
 775
 776         switch (pq_flags) {
 777         case PQ_FLAGS_RLS:
 778                 return &qm_info->first_rl_pq;
 779         case PQ_FLAGS_MCOS:
 780                 return &qm_info->first_mcos_pq;
 781         case PQ_FLAGS_LB:
 782                 return &qm_info->pure_lb_pq;
 783         case PQ_FLAGS_OOO:
 784                 return &qm_info->ooo_pq;
 785         case PQ_FLAGS_ACK:
 786                 return &qm_info->pure_ack_pq;
 787         case PQ_FLAGS_OFLD:
 788                 return &qm_info->offload_pq;
 789         case PQ_FLAGS_VFS:
 790                 return &qm_info->first_vf_pq;
 791         default:
 792                 goto err;
 793         }
 794
 795 err:
 796         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 797         return OSAL_NULL;
 798 }
 799
 800 /* save pq index in qm info */
 801 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 802                                   u32 pq_flags, u16 pq_val)
 803 {
 804         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 805
 806         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 807 }
 808
 809 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 810 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 811 {
 812         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 813
 814         return *base_pq_idx + CM_TX_PQ_BASE;
 815 }
 816
 817 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 818 {
 819         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 820
 821         if (tc > max_tc)
 822                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 823
 824         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 825 }
 826
 827 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 828 {
 829         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 830
 831         if (vf > max_vf)
 832                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 833
 834         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 835 }
 836
 837 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 838 {
 839         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 840
 841         if (rl > max_rl)
 842                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 843
 844         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 845 }
 846
 847 /* Functions for creating specific types of pqs */
 848 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 849 {
 850         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 851
 852         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 853                 return;
 854
 855         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 856         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 857 }
 858
 859 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 860 {
 861         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 862
 863         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 864                 return;
 865
 866         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 867         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 868 }
 869
 870 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 871 {
 872         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 873
 874         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 875                 return;
 876
 877         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 878         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 879 }
 880
 881 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 882 {
 883         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 884
 885         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 886                 return;
 887
 888         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 889         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 890 }
 891
 892 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 893 {
 894         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 895         u8 tc_idx;
 896
 897         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 898                 return;
 899
 900         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 901         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 902                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 903 }
 904
 905 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 906 {
 907         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 908         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 909
 910         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 911                 return;
 912
 913         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 914
 915         qm_info->num_vf_pqs = num_vfs;
 916         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 917                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 918                                  PQ_INIT_VF_RL);
 919 }
 920
 921 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 922 {
 923         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 924         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 925
 926         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 927                 return;
 928
 929         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 930         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 931                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 932                                  PQ_INIT_PF_RL);
 933 }
 934
 935 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 936 {
 937         /* rate limited pqs, must come first (FW assumption) */
 938         ecore_init_qm_rl_pqs(p_hwfn);
 939
 940         /* pqs for multi cos */
 941         ecore_init_qm_mcos_pqs(p_hwfn);
 942
 943         /* pure loopback pq */
 944         ecore_init_qm_lb_pq(p_hwfn);
 945
 946         /* out of order pq */
 947         ecore_init_qm_ooo_pq(p_hwfn);
 948
 949         /* pure ack pq */
 950         ecore_init_qm_pure_ack_pq(p_hwfn);
 951
 952         /* pq for offloaded protocol */
 953         ecore_init_qm_offload_pq(p_hwfn);
 954
 955         /* done sharing vports */
 956         ecore_init_qm_advance_vport(p_hwfn);
 957
 958         /* pqs for vfs */
 959         ecore_init_qm_vf_pqs(p_hwfn);
 960 }
 961
 962 /* compare values of getters against resources amounts */
 963 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 964 {
 965         if (ecore_init_qm_get_num_vports(p_hwfn) >
 966             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 967                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 968                 return ECORE_INVAL;
 969         }
 970
 971         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 972                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 973                 return ECORE_INVAL;
 974         }
 975
 976         return ECORE_SUCCESS;
 977 }
 978
 979 /*
 980  * Function for verbose printing of the qm initialization results
 981  */
 982 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 983 {
 984         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 985         struct init_qm_vport_params *vport;
 986         struct init_qm_port_params *port;
 987         struct init_qm_pq_params *pq;
 988         int i, tc;
 989
 990         /* top level params */
 991         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 992                    "qm init top level params: start_pq %d, start_vport %d,"
 993                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 994                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 995                    qm_info->offload_pq, qm_info->pure_ack_pq);
 996         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 997                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 998                    " num_vports %d, max_phys_tcs_per_port %d\n",
 999                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1000                    qm_info->num_vf_pqs, qm_info->num_vports,
1001                    qm_info->max_phys_tcs_per_port);
1002         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1004                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1005                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1006                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1007                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1008
1009         /* port table */
1010         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1011                 port = &qm_info->qm_port_params[i];
1012                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1013                            "port idx %d, active %d, active_phys_tcs %d,"
1014                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1015                            " reserved %d\n",
1016                            i, port->active, port->active_phys_tcs,
1017                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1018                            port->reserved);
1019         }
1020
1021         /* vport table */
1022         for (i = 0; i < qm_info->num_vports; i++) {
1023                 vport = &qm_info->qm_vport_params[i];
1024                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1025                            "vport idx %d, vport_rl %d, wfq %d,"
1026                            " first_tx_pq_id [ ",
1027                            qm_info->start_vport + i, vport->vport_rl,
1028                            vport->vport_wfq);
1029                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1030                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1031                                    vport->first_tx_pq_id[tc]);
1032                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1033         }
1034
1035         /* pq table */
1036         for (i = 0; i < qm_info->num_pqs; i++) {
1037                 pq = &qm_info->qm_pq_params[i];
1038                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1039                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1040                            " rl_valid %d\n",
1041                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1042                            pq->wrr_group, pq->rl_valid);
1043         }
1044 }
1045
1046 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1047 {
1048         /* reset params required for init run */
1049         ecore_init_qm_reset_params(p_hwfn);
1050
1051         /* init QM top level params */
1052         ecore_init_qm_params(p_hwfn);
1053
1054         /* init QM port params */
1055         ecore_init_qm_port_params(p_hwfn);
1056
1057         /* init QM vport params */
1058         ecore_init_qm_vport_params(p_hwfn);
1059
1060         /* init QM physical queue params */
1061         ecore_init_qm_pq_params(p_hwfn);
1062
1063         /* display all that init */
1064         ecore_dp_init_qm_params(p_hwfn);
1065 }
1066
1067 /* This function reconfigures the QM pf on the fly.
1068  * For this purpose we:
1069  * 1. reconfigure the QM database
1070  * 2. set new values to runtime array
1071  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1072  * 4. activate init tool in QM_PF stage
1073  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1074  */
1075 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1076                                      struct ecore_ptt *p_ptt)
1077 {
1078         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1079         bool b_rc;
1080         enum _ecore_status_t rc;
1081
1082         /* initialize ecore's qm data structure */
1083         ecore_init_qm_info(p_hwfn);
1084
1085         /* stop PF's qm queues */
1086         OSAL_SPIN_LOCK(&qm_lock);
1087         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1088                                       qm_info->start_pq, qm_info->num_pqs);
1089         OSAL_SPIN_UNLOCK(&qm_lock);
1090         if (!b_rc)
1091                 return ECORE_INVAL;
1092
1093         /* clear the QM_PF runtime phase leftovers from previous init */
1094         ecore_init_clear_rt_data(p_hwfn);
1095
1096         /* prepare QM portion of runtime array */
1097         ecore_qm_init_pf(p_hwfn, p_ptt);
1098
1099         /* activate init tool on runtime array */
1100         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1101                             p_hwfn->hw_info.hw_mode);
1102         if (rc != ECORE_SUCCESS)
1103                 return rc;
1104
1105         /* start PF's qm queues */
1106         OSAL_SPIN_LOCK(&qm_lock);
1107         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1108                                       qm_info->start_pq, qm_info->num_pqs);
1109         OSAL_SPIN_UNLOCK(&qm_lock);
1110         if (!b_rc)
1111                 return ECORE_INVAL;
1112
1113         return ECORE_SUCCESS;
1114 }
1115
1116 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1117 {
1118         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1119         enum _ecore_status_t rc;
1120
1121         rc = ecore_init_qm_sanity(p_hwfn);
1122         if (rc != ECORE_SUCCESS)
1123                 goto alloc_err;
1124
1125         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1126                                             sizeof(struct init_qm_pq_params) *
1127                                             ecore_init_qm_get_num_pqs(p_hwfn));
1128         if (!qm_info->qm_pq_params)
1129                 goto alloc_err;
1130
1131         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1132                                        sizeof(struct init_qm_vport_params) *
1133                                        ecore_init_qm_get_num_vports(p_hwfn));
1134         if (!qm_info->qm_vport_params)
1135                 goto alloc_err;
1136
1137         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1138                                       sizeof(struct init_qm_port_params) *
1139                                       p_hwfn->p_dev->num_ports_in_engine);
1140         if (!qm_info->qm_port_params)
1141                 goto alloc_err;
1142
1143         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1144                                         sizeof(struct ecore_wfq_data) *
1145                                         ecore_init_qm_get_num_vports(p_hwfn));
1146         if (!qm_info->wfq_data)
1147                 goto alloc_err;
1148
1149         return ECORE_SUCCESS;
1150
1151 alloc_err:
1152         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1153         ecore_qm_info_free(p_hwfn);
1154         return ECORE_NOMEM;
1155 }
1156 /******************** End QM initialization ***************/
1157
1158 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1159 {
1160         enum _ecore_status_t rc = ECORE_SUCCESS;
1161         int i;
1162
1163         if (IS_VF(p_dev)) {
1164                 for_each_hwfn(p_dev, i) {
1165                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1166                         if (rc != ECORE_SUCCESS)
1167                                 return rc;
1168                 }
1169                 return rc;
1170         }
1171
1172         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1173                                      sizeof(*p_dev->fw_data));
1174         if (!p_dev->fw_data)
1175                 return ECORE_NOMEM;
1176
1177         for_each_hwfn(p_dev, i) {
1178                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1179                 u32 n_eqes, num_cons;
1180
1181                 /* initialize the doorbell recovery mechanism */
1182                 rc = ecore_db_recovery_setup(p_hwfn);
1183                 if (rc)
1184                         goto alloc_err;
1185
1186                 /* First allocate the context manager structure */
1187                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1188                 if (rc)
1189                         goto alloc_err;
1190
1191                 /* Set the HW cid/tid numbers (in the context manager)
1192                  * Must be done prior to any further computations.
1193                  */
1194                 rc = ecore_cxt_set_pf_params(p_hwfn);
1195                 if (rc)
1196                         goto alloc_err;
1197
1198                 rc = ecore_alloc_qm_data(p_hwfn);
1199                 if (rc)
1200                         goto alloc_err;
1201
1202                 /* init qm info */
1203                 ecore_init_qm_info(p_hwfn);
1204
1205                 /* Compute the ILT client partition */
1206                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1207                 if (rc)
1208                         goto alloc_err;
1209
1210                 /* CID map / ILT shadow table / T2
1211                  * The talbes sizes are determined by the computations above
1212                  */
1213                 rc = ecore_cxt_tables_alloc(p_hwfn);
1214                 if (rc)
1215                         goto alloc_err;
1216
1217                 /* SPQ, must follow ILT because initializes SPQ context */
1218                 rc = ecore_spq_alloc(p_hwfn);
1219                 if (rc)
1220                         goto alloc_err;
1221
1222                 /* SP status block allocation */
1223                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1224                                                            RESERVED_PTT_DPC);
1225
1226                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1227                 if (rc)
1228                         goto alloc_err;
1229
1230                 rc = ecore_iov_alloc(p_hwfn);
1231                 if (rc)
1232                         goto alloc_err;
1233
1234                 /* EQ */
1235                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1236                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1237                         /* Calculate the EQ size
1238                          * ---------------------
1239                          * Each ICID may generate up to one event at a time i.e.
1240                          * the event must be handled/cleared before a new one
1241                          * can be generated. We calculate the sum of events per
1242                          * protocol and create an EQ deep enough to handle the
1243                          * worst case:
1244                          * - Core - according to SPQ.
1245                          * - RoCE - per QP there are a couple of ICIDs, one
1246                          *        responder and one requester, each can
1247                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1248                          *        Each CQ can generate an EQE. There are 2 CQs
1249                          *        per QP => n_eqes_cq = 2 * n_qp.
1250                          *        Hence the RoCE total is 4 * n_qp or
1251                          *        2 * num_cons.
1252                          * - ENet - There can be up to two events per VF. One
1253                          *        for VF-PF channel and another for VF FLR
1254                          *        initial cleanup. The number of VFs is
1255                          *        bounded by MAX_NUM_VFS_BB, and is much
1256                          *        smaller than RoCE's so we avoid exact
1257                          *        calculation.
1258                          */
1259                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1260                                 num_cons =
1261                                     ecore_cxt_get_proto_cid_count(
1262                                                 p_hwfn,
1263                                                 PROTOCOLID_ROCE,
1264                                                 OSAL_NULL);
1265                                 num_cons *= 2;
1266                         } else {
1267                                 num_cons = ecore_cxt_get_proto_cid_count(
1268                                                 p_hwfn,
1269                                                 PROTOCOLID_IWARP,
1270                                                 OSAL_NULL);
1271                         }
1272                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1273                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1274                         num_cons =
1275                             ecore_cxt_get_proto_cid_count(p_hwfn,
1276                                                           PROTOCOLID_ISCSI,
1277                                                           OSAL_NULL);
1278                         n_eqes += 2 * num_cons;
1279                 }
1280
1281                 if (n_eqes > 0xFFFF) {
1282                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1283                                        "The maximum of a u16 chain is 0x%x\n",
1284                                n_eqes, 0xFFFF);
1285                         goto alloc_no_mem;
1286                 }
1287
1288                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1289                 if (rc)
1290                         goto alloc_err;
1291
1292                 rc = ecore_consq_alloc(p_hwfn);
1293                 if (rc)
1294                         goto alloc_err;
1295
1296                 rc = ecore_l2_alloc(p_hwfn);
1297                 if (rc != ECORE_SUCCESS)
1298                         goto alloc_err;
1299
1300                 /* DMA info initialization */
1301                 rc = ecore_dmae_info_alloc(p_hwfn);
1302                 if (rc) {
1303                         DP_NOTICE(p_hwfn, true,
1304                                   "Failed to allocate memory for dmae_info"
1305                                   " structure\n");
1306                         goto alloc_err;
1307                 }
1308
1309                 /* DCBX initialization */
1310                 rc = ecore_dcbx_info_alloc(p_hwfn);
1311                 if (rc) {
1312                         DP_NOTICE(p_hwfn, true,
1313                                   "Failed to allocate memory for dcbx structure\n");
1314                         goto alloc_err;
1315                 }
1316         }
1317
1318         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1319                                          sizeof(*p_dev->reset_stats));
1320         if (!p_dev->reset_stats) {
1321                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1322                 goto alloc_no_mem;
1323         }
1324
1325         return ECORE_SUCCESS;
1326
1327 alloc_no_mem:
1328         rc = ECORE_NOMEM;
1329 alloc_err:
1330         ecore_resc_free(p_dev);
1331         return rc;
1332 }
1333
1334 void ecore_resc_setup(struct ecore_dev *p_dev)
1335 {
1336         int i;
1337
1338         if (IS_VF(p_dev)) {
1339                 for_each_hwfn(p_dev, i)
1340                         ecore_l2_setup(&p_dev->hwfns[i]);
1341                 return;
1342         }
1343
1344         for_each_hwfn(p_dev, i) {
1345                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1346
1347                 ecore_cxt_mngr_setup(p_hwfn);
1348                 ecore_spq_setup(p_hwfn);
1349                 ecore_eq_setup(p_hwfn);
1350                 ecore_consq_setup(p_hwfn);
1351
1352                 /* Read shadow of current MFW mailbox */
1353                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1354                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1355                             p_hwfn->mcp_info->mfw_mb_cur,
1356                             p_hwfn->mcp_info->mfw_mb_length);
1357
1358                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1359
1360                 ecore_l2_setup(p_hwfn);
1361                 ecore_iov_setup(p_hwfn);
1362         }
1363 }
1364
1365 #define FINAL_CLEANUP_POLL_CNT  (100)
1366 #define FINAL_CLEANUP_POLL_TIME (10)
1367 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1368                                          struct ecore_ptt *p_ptt,
1369                                          u16 id, bool is_vf)
1370 {
1371         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1372         enum _ecore_status_t rc = ECORE_TIMEOUT;
1373
1374 #ifndef ASIC_ONLY
1375         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1376             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1377                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1378                 return ECORE_SUCCESS;
1379         }
1380 #endif
1381
1382         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1383             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1384
1385         if (is_vf)
1386                 id += 0x10;
1387
1388         command |= X_FINAL_CLEANUP_AGG_INT <<
1389             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1390         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1391         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1392         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1393
1394 /* Make sure notification is not set before initiating final cleanup */
1395
1396         if (REG_RD(p_hwfn, addr)) {
1397                 DP_NOTICE(p_hwfn, false,
1398                           "Unexpected; Found final cleanup notification");
1399                 DP_NOTICE(p_hwfn, false,
1400                           " before initiating final cleanup\n");
1401                 REG_WR(p_hwfn, addr, 0);
1402         }
1403
1404         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1405                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1406                    id, command);
1407
1408         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1409
1410         /* Poll until completion */
1411         while (!REG_RD(p_hwfn, addr) && count--)
1412                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1413
1414         if (REG_RD(p_hwfn, addr))
1415                 rc = ECORE_SUCCESS;
1416         else
1417                 DP_NOTICE(p_hwfn, true,
1418                           "Failed to receive FW final cleanup notification\n");
1419
1420         /* Cleanup afterwards */
1421         REG_WR(p_hwfn, addr, 0);
1422
1423         return rc;
1424 }
1425
1426 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1427 {
1428         int hw_mode = 0;
1429
1430         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1431                 hw_mode |= 1 << MODE_BB;
1432         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1433                 hw_mode |= 1 << MODE_K2;
1434         } else {
1435                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1436                           p_hwfn->p_dev->type);
1437                 return ECORE_INVAL;
1438         }
1439
1440         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1441         switch (p_hwfn->p_dev->num_ports_in_engine) {
1442         case 1:
1443                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1444                 break;
1445         case 2:
1446                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1447                 break;
1448         case 4:
1449                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1450                 break;
1451         default:
1452                 DP_NOTICE(p_hwfn, true,
1453                           "num_ports_in_engine = %d not supported\n",
1454                           p_hwfn->p_dev->num_ports_in_engine);
1455                 return ECORE_INVAL;
1456         }
1457
1458         switch (p_hwfn->p_dev->mf_mode) {
1459         case ECORE_MF_DEFAULT:
1460         case ECORE_MF_NPAR:
1461                 hw_mode |= 1 << MODE_MF_SI;
1462                 break;
1463         case ECORE_MF_OVLAN:
1464                 hw_mode |= 1 << MODE_MF_SD;
1465                 break;
1466         default:
1467                 DP_NOTICE(p_hwfn, true,
1468                           "Unsupported MF mode, init as DEFAULT\n");
1469                 hw_mode |= 1 << MODE_MF_SI;
1470         }
1471
1472 #ifndef ASIC_ONLY
1473         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1474                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1475                         hw_mode |= 1 << MODE_FPGA;
1476                 } else {
1477                         if (p_hwfn->p_dev->b_is_emul_full)
1478                                 hw_mode |= 1 << MODE_EMUL_FULL;
1479                         else
1480                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1481                 }
1482         } else
1483 #endif
1484                 hw_mode |= 1 << MODE_ASIC;
1485
1486         if (ECORE_IS_CMT(p_hwfn->p_dev))
1487                 hw_mode |= 1 << MODE_100G;
1488
1489         p_hwfn->hw_info.hw_mode = hw_mode;
1490
1491         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1492                    "Configuring function for hw_mode: 0x%08x\n",
1493                    p_hwfn->hw_info.hw_mode);
1494
1495         return ECORE_SUCCESS;
1496 }
1497
1498 #ifndef ASIC_ONLY
1499 /* MFW-replacement initializations for non-ASIC */
1500 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1501                                                struct ecore_ptt *p_ptt)
1502 {
1503         struct ecore_dev *p_dev = p_hwfn->p_dev;
1504         u32 pl_hv = 1;
1505         int i;
1506
1507         if (CHIP_REV_IS_EMUL(p_dev)) {
1508                 if (ECORE_IS_AH(p_dev))
1509                         pl_hv |= 0x600;
1510         }
1511
1512         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1513
1514         if (CHIP_REV_IS_EMUL(p_dev) &&
1515             (ECORE_IS_AH(p_dev)))
1516                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1517                          0x3ffffff);
1518
1519         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1520         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1521         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1522                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1523
1524         if (CHIP_REV_IS_EMUL(p_dev)) {
1525                 if (ECORE_IS_AH(p_dev)) {
1526                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1527                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1528                                  (p_dev->num_ports_in_engine >> 1));
1529
1530                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1531                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1532                 }
1533         }
1534
1535         /* Poll on RBC */
1536         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1537         for (i = 0; i < 100; i++) {
1538                 OSAL_UDELAY(50);
1539                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1540                         break;
1541         }
1542         if (i == 100)
1543                 DP_NOTICE(p_hwfn, true,
1544                           "RBC done failed to complete in PSWRQ2\n");
1545
1546         return ECORE_SUCCESS;
1547 }
1548 #endif
1549
1550 /* Init run time data for all PFs and their VFs on an engine.
1551  * TBD - for VFs - Once we have parent PF info for each VF in
1552  * shmem available as CAU requires knowledge of parent PF for each VF.
1553  */
1554 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1555 {
1556         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1557         int i, igu_sb_id;
1558
1559         for_each_hwfn(p_dev, i) {
1560                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1561                 struct ecore_igu_info *p_igu_info;
1562                 struct ecore_igu_block *p_block;
1563                 struct cau_sb_entry sb_entry;
1564
1565                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1566
1567                 for (igu_sb_id = 0;
1568                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1569                      igu_sb_id++) {
1570                         p_block = &p_igu_info->entry[igu_sb_id];
1571
1572                         if (!p_block->is_pf)
1573                                 continue;
1574
1575                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1576                                                 p_block->function_id, 0, 0);
1577                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1578                                          sb_entry);
1579                 }
1580         }
1581 }
1582
1583 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1584                                        struct ecore_ptt *p_ptt)
1585 {
1586         u32 val, wr_mbs, cache_line_size;
1587
1588         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1589         switch (val) {
1590         case 0:
1591                 wr_mbs = 128;
1592                 break;
1593         case 1:
1594                 wr_mbs = 256;
1595                 break;
1596         case 2:
1597                 wr_mbs = 512;
1598                 break;
1599         default:
1600                 DP_INFO(p_hwfn,
1601                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1602                         val);
1603                 return;
1604         }
1605
1606         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1607         switch (cache_line_size) {
1608         case 32:
1609                 val = 0;
1610                 break;
1611         case 64:
1612                 val = 1;
1613                 break;
1614         case 128:
1615                 val = 2;
1616                 break;
1617         case 256:
1618                 val = 3;
1619                 break;
1620         default:
1621                 DP_INFO(p_hwfn,
1622                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1623                         cache_line_size);
1624         }
1625
1626         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1627                 DP_INFO(p_hwfn,
1628                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1629                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1630
1631         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1632         if (val > 0) {
1633                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1634                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1635         }
1636 }
1637
1638 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1639                                                  struct ecore_ptt *p_ptt,
1640                                                  int hw_mode)
1641 {
1642         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1643         struct ecore_dev *p_dev = p_hwfn->p_dev;
1644         u8 vf_id, max_num_vfs;
1645         u16 num_pfs, pf_id;
1646         u32 concrete_fid;
1647         enum _ecore_status_t rc = ECORE_SUCCESS;
1648
1649         ecore_init_cau_rt_data(p_dev);
1650
1651         /* Program GTT windows */
1652         ecore_gtt_init(p_hwfn, p_ptt);
1653
1654 #ifndef ASIC_ONLY
1655         if (CHIP_REV_IS_EMUL(p_dev)) {
1656                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1657                 if (rc != ECORE_SUCCESS)
1658                         return rc;
1659         }
1660 #endif
1661
1662         if (p_hwfn->mcp_info) {
1663                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1664                         qm_info->pf_rl_en = 1;
1665                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1666                         qm_info->pf_wfq_en = 1;
1667         }
1668
1669         ecore_qm_common_rt_init(p_hwfn,
1670                                 p_dev->num_ports_in_engine,
1671                                 qm_info->max_phys_tcs_per_port,
1672                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1673                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1674                                 qm_info->qm_port_params);
1675
1676         ecore_cxt_hw_init_common(p_hwfn);
1677
1678         ecore_init_cache_line_size(p_hwfn, p_ptt);
1679
1680         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1681         if (rc != ECORE_SUCCESS)
1682                 return rc;
1683
1684         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1685          * need to decide with which value, maybe runtime
1686          */
1687         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1688         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1689
1690         if (ECORE_IS_BB(p_dev)) {
1691                 /* Workaround clears ROCE search for all functions to prevent
1692                  * involving non initialized function in processing ROCE packet.
1693                  */
1694                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1695                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1696                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1697                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1698                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1699                 }
1700                 /* pretend to original PF */
1701                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1702         }
1703
1704         /* Workaround for avoiding CCFC execution error when getting packets
1705          * with CRC errors, and allowing instead the invoking of the FW error
1706          * handler.
1707          * This is not done inside the init tool since it currently can't
1708          * perform a pretending to VFs.
1709          */
1710         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1711         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1712                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1713                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1714                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1715                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1716                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1717                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1718         }
1719         /* pretend to original PF */
1720         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1721
1722         return rc;
1723 }
1724
1725 #ifndef ASIC_ONLY
1726 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1727 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1728
1729 #define PMEG_IF_BYTE_COUNT      8
1730
1731 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1732                              struct ecore_ptt *p_ptt,
1733                              u32 addr, u64 data, u8 reg_type, u8 port)
1734 {
1735         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1736                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1737                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1738                    (8 << PMEG_IF_BYTE_COUNT),
1739                    (reg_type << 25) | (addr << 8) | port,
1740                    (u32)((data >> 32) & 0xffffffff),
1741                    (u32)(data & 0xffffffff));
1742
1743         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1744                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1745                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1746         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1747                  (reg_type << 25) | (addr << 8) | port);
1748         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1749         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1750                  (data >> 32) & 0xffffffff);
1751 }
1752
1753 #define XLPORT_MODE_REG (0x20a)
1754 #define XLPORT_MAC_CONTROL (0x210)
1755 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1756 #define XLPORT_ENABLE_REG (0x20b)
1757
1758 #define XLMAC_CTRL (0x600)
1759 #define XLMAC_MODE (0x601)
1760 #define XLMAC_RX_MAX_SIZE (0x608)
1761 #define XLMAC_TX_CTRL (0x604)
1762 #define XLMAC_PAUSE_CTRL (0x60d)
1763 #define XLMAC_PFC_CTRL (0x60e)
1764
1765 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1766                                     struct ecore_ptt *p_ptt)
1767 {
1768         u8 loopback = 0, port = p_hwfn->port_id * 2;
1769
1770         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1771
1772         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1773         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1774                          port);
1775         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1776         /* XLMAC: SOFT RESET */
1777         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1778         /* XLMAC: Port Speed >= 10Gbps */
1779         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1780         /* XLMAC: Max Size */
1781         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1782         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1783                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1784                          0, port);
1785         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1786         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1787                          0x30ffffc000ULL, 0, port);
1788         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1789                          port); /* XLMAC: TX_EN, RX_EN */
1790         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1791         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1792                          0x1003 | (loopback << 2), 0, port);
1793         /* Enabled Parallel PFC interface */
1794         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1795
1796         /* XLPORT port enable */
1797         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1798 }
1799
1800 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1801                                        struct ecore_ptt *p_ptt)
1802 {
1803         u8 port = p_hwfn->port_id;
1804         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1805
1806         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1807
1808         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1809                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1810                  (port <<
1811                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1812                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1813
1814         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1815                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1816
1817         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1818                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1819
1820         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1821                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1822
1823         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1824                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1825
1826         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1827                  (0xA <<
1828                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1829                  (8 <<
1830                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1831
1832         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1833                  0xa853);
1834 }
1835
1836 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1837                                  struct ecore_ptt *p_ptt)
1838 {
1839         if (ECORE_IS_AH(p_hwfn->p_dev))
1840                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1841         else /* BB */
1842                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1843 }
1844
1845 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1846                                struct ecore_ptt *p_ptt,  u8 port)
1847 {
1848         int port_offset = port ? 0x800 : 0;
1849         u32 xmac_rxctrl = 0;
1850
1851         /* Reset of XMAC */
1852         /* FIXME: move to common start */
1853         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1854                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1855         OSAL_MSLEEP(1);
1856         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1857                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1858
1859         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1860
1861         /* Set the number of ports on the Warp Core to 10G */
1862         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1863
1864         /* Soft reset of XMAC */
1865         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1866                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1867         OSAL_MSLEEP(1);
1868         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1869                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1870
1871         /* FIXME: move to common end */
1872         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1873                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1874
1875         /* Set Max packet size: initialize XMAC block register for port 0 */
1876         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1877
1878         /* CRC append for Tx packets: init XMAC block register for port 1 */
1879         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1880
1881         /* Enable TX and RX: initialize XMAC block register for port 1 */
1882         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1883                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1884         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1885                                XMAC_REG_RX_CTRL_BB + port_offset);
1886         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1887         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1888 }
1889 #endif
1890
1891 static enum _ecore_status_t
1892 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1893                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1894 {
1895         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1896         u32 min_dpis;
1897         u32 n_wids;
1898
1899         /* Calculate DPI size
1900          * ------------------
1901          * The PWM region contains Doorbell Pages. The first is reserverd for
1902          * the kernel for, e.g, L2. The others are free to be used by non-
1903          * trusted applications, typically from user space. Each page, called a
1904          * doorbell page is sectioned into windows that allow doorbells to be
1905          * issued in parallel by the kernel/application. The size of such a
1906          * window (a.k.a. WID) is 1kB.
1907          * Summary:
1908          *    1kB WID x N WIDS = DPI page size
1909          *    DPI page size x N DPIs = PWM region size
1910          * Notes:
1911          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1912          * in order to ensure that two applications won't share the same page.
1913          * It also must contain at least one WID per CPU to allow parallelism.
1914          * It also must be a power of 2, since it is stored as a bit shift.
1915          *
1916          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1917          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1918          * containing 4 WIDs.
1919          */
1920         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1921         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1922         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1923                         ~(OSAL_PAGE_SIZE - 1);
1924         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1925         dpi_count = pwm_region_size / dpi_page_size;
1926
1927         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1928         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1929
1930         /* Update hwfn */
1931         p_hwfn->dpi_size = dpi_page_size;
1932         p_hwfn->dpi_count = dpi_count;
1933
1934         /* Update registers */
1935         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1936
1937         if (dpi_count < min_dpis)
1938                 return ECORE_NORESOURCES;
1939
1940         return ECORE_SUCCESS;
1941 }
1942
1943 enum ECORE_ROCE_EDPM_MODE {
1944         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1945         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1946         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1947 };
1948
1949 static enum _ecore_status_t
1950 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1951                               struct ecore_ptt *p_ptt)
1952 {
1953         u32 pwm_regsize, norm_regsize;
1954         u32 non_pwm_conn, min_addr_reg1;
1955         u32 db_bar_size, n_cpus;
1956         u32 roce_edpm_mode;
1957         u32 pf_dems_shift;
1958         enum _ecore_status_t rc = ECORE_SUCCESS;
1959         u8 cond;
1960
1961         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1962         if (ECORE_IS_CMT(p_hwfn->p_dev))
1963                 db_bar_size /= 2;
1964
1965         /* Calculate doorbell regions
1966          * -----------------------------------
1967          * The doorbell BAR is made of two regions. The first is called normal
1968          * region and the second is called PWM region. In the normal region
1969          * each ICID has its own set of addresses so that writing to that
1970          * specific address identifies the ICID. In the Process Window Mode
1971          * region the ICID is given in the data written to the doorbell. The
1972          * above per PF register denotes the offset in the doorbell BAR in which
1973          * the PWM region begins.
1974          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1975          * non-PWM connection. The calculation below computes the total non-PWM
1976          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1977          * in units of 4,096 bytes.
1978          */
1979         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1980             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1981                                           OSAL_NULL) +
1982             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1983         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1984                                OSAL_PAGE_SIZE);
1985         min_addr_reg1 = norm_regsize / 4096;
1986         pwm_regsize = db_bar_size - norm_regsize;
1987
1988         /* Check that the normal and PWM sizes are valid */
1989         if (db_bar_size < norm_regsize) {
1990                 DP_ERR(p_hwfn->p_dev,
1991                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1992                        db_bar_size, norm_regsize);
1993                 return ECORE_NORESOURCES;
1994         }
1995         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1996                 DP_ERR(p_hwfn->p_dev,
1997                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1998                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1999                        norm_regsize);
2000                 return ECORE_NORESOURCES;
2001         }
2002
2003         /* Calculate number of DPIs */
2004         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2005         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2006             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2007                 /* Either EDPM is mandatory, or we are attempting to allocate a
2008                  * WID per CPU.
2009                  */
2010                 n_cpus = OSAL_NUM_ACTIVE_CPU();
2011                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2012         }
2013
2014         cond = ((rc != ECORE_SUCCESS) &&
2015                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2016                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2017         if (cond || p_hwfn->dcbx_no_edpm) {
2018                 /* Either EDPM is disabled from user configuration, or it is
2019                  * disabled via DCBx, or it is not mandatory and we failed to
2020                  * allocated a WID per CPU.
2021                  */
2022                 n_cpus = 1;
2023                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2024
2025                 /* If we entered this flow due to DCBX then the DPM register is
2026                  * already configured.
2027                  */
2028         }
2029
2030         DP_INFO(p_hwfn,
2031                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2032                 norm_regsize, pwm_regsize);
2033         DP_INFO(p_hwfn,
2034                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2035                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2036                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2037                 "disabled" : "enabled");
2038
2039         /* Check return codes from above calls */
2040         if (rc != ECORE_SUCCESS) {
2041                 DP_ERR(p_hwfn,
2042                        "Failed to allocate enough DPIs\n");
2043                 return ECORE_NORESOURCES;
2044         }
2045
2046         /* Update hwfn */
2047         p_hwfn->dpi_start_offset = norm_regsize;
2048
2049         /* Update registers */
2050         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2051         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2052         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2053         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2054
2055         return ECORE_SUCCESS;
2056 }
2057
2058 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2059                                                struct ecore_ptt *p_ptt,
2060                                                int hw_mode)
2061 {
2062         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2063         u32 val;
2064         enum _ecore_status_t rc = ECORE_SUCCESS;
2065         u8 i;
2066
2067         /* In CMT for non-RoCE packets - use connection based classification */
2068         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2069         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2070                 ppf_to_eng_sel[i] = val;
2071         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2072                          ppf_to_eng_sel);
2073
2074         /* In CMT the gate should be cleared by the 2nd hwfn */
2075         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2076                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2077
2078         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2079                             hw_mode);
2080         if (rc != ECORE_SUCCESS)
2081                 return rc;
2082
2083         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2084
2085 #ifndef ASIC_ONLY
2086         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2087                 return ECORE_SUCCESS;
2088
2089         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2090                 if (ECORE_IS_AH(p_hwfn->p_dev))
2091                         return ECORE_SUCCESS;
2092                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2093                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2094         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2095                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2096                         /* Activate OPTE in CMT */
2097                         u32 val;
2098
2099                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2100                         val |= 0x10;
2101                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2102                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2103                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2104                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2105                         ecore_wr(p_hwfn, p_ptt,
2106                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2107                         ecore_wr(p_hwfn, p_ptt,
2108                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2109                         ecore_wr(p_hwfn, p_ptt,
2110                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2111                                  0x55555555);
2112                 }
2113
2114                 ecore_emul_link_init(p_hwfn, p_ptt);
2115         } else {
2116                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2117         }
2118 #endif
2119
2120         return rc;
2121 }
2122
2123 static enum _ecore_status_t
2124 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2125                  struct ecore_ptt *p_ptt,
2126                  struct ecore_tunnel_info *p_tunn,
2127                  int hw_mode,
2128                  bool b_hw_start,
2129                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2130 {
2131         u8 rel_pf_id = p_hwfn->rel_pf_id;
2132         u32 prs_reg;
2133         enum _ecore_status_t rc = ECORE_SUCCESS;
2134         u16 ctrl;
2135         int pos;
2136
2137         if (p_hwfn->mcp_info) {
2138                 struct ecore_mcp_function_info *p_info;
2139
2140                 p_info = &p_hwfn->mcp_info->func_info;
2141                 if (p_info->bandwidth_min)
2142                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2143
2144                 /* Update rate limit once we'll actually have a link */
2145                 p_hwfn->qm_info.pf_rl = 100000;
2146         }
2147         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2148
2149         ecore_int_igu_init_rt(p_hwfn);
2150
2151         /* Set VLAN in NIG if needed */
2152         if (hw_mode & (1 << MODE_MF_SD)) {
2153                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2154                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2155                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2156                              p_hwfn->hw_info.ovlan);
2157         }
2158
2159         /* Enable classification by MAC if needed */
2160         if (hw_mode & (1 << MODE_MF_SI)) {
2161                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2162                            "Configuring TAGMAC_CLS_TYPE\n");
2163                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2164                              1);
2165         }
2166
2167         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2168         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2169                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2170         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2171                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2172         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2173
2174         /* perform debug configuration when chip is out of reset */
2175         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2176
2177         /* PF Init sequence */
2178         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2179         if (rc)
2180                 return rc;
2181
2182         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2183         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2184         if (rc)
2185                 return rc;
2186
2187         /* Pure runtime initializations - directly to the HW  */
2188         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2189
2190         /* PCI relaxed ordering causes a decrease in the performance on some
2191          * systems. Till a root cause is found, disable this attribute in the
2192          * PCI config space.
2193          */
2194         /* Not in use @DPDK
2195         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2196         * if (!pos) {
2197         *       DP_NOTICE(p_hwfn, true,
2198         *                 "Failed to find the PCIe Cap\n");
2199         *       return ECORE_IO;
2200         * }
2201         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2202         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2203         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2204         */
2205
2206         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2207         if (rc)
2208                 return rc;
2209         if (b_hw_start) {
2210                 /* enable interrupts */
2211                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2212                 if (rc != ECORE_SUCCESS)
2213                         return rc;
2214
2215                 /* send function start command */
2216                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2217                                        p_hwfn->p_dev->mf_mode,
2218                                        allow_npar_tx_switch);
2219                 if (rc) {
2220                         DP_NOTICE(p_hwfn, true,
2221                                   "Function start ramrod failed\n");
2222                 } else {
2223                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2224                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2225                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2226
2227                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2228                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2229                                          (1 << 2));
2230                                 ecore_wr(p_hwfn, p_ptt,
2231                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2232                                     0x100);
2233                         }
2234                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2235                                    "PRS_REG_SEARCH registers after start PFn\n");
2236                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2237                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2238                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2239                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2240                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2241                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2242                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2243                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2244                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2245                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2246                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2247                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2248                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2249                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2250                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2251                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2252                                    prs_reg);
2253                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2254                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2255                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2256                 }
2257         }
2258         return rc;
2259 }
2260
2261 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2262                                                   struct ecore_ptt *p_ptt,
2263                                                   bool b_enable)
2264 {
2265         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2266
2267         /* Configure the PF's internal FID_enable for master transactions */
2268         ecore_wr(p_hwfn, p_ptt,
2269                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2270
2271         /* Wait until value is set - try for 1 second every 50us */
2272         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2273                 val = ecore_rd(p_hwfn, p_ptt,
2274                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2275                 if (val == set_val)
2276                         break;
2277
2278                 OSAL_UDELAY(50);
2279         }
2280
2281         if (val != set_val) {
2282                 DP_NOTICE(p_hwfn, true,
2283                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2284                 return ECORE_UNKNOWN_ERROR;
2285         }
2286
2287         return ECORE_SUCCESS;
2288 }
2289
2290 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2291                                   struct ecore_ptt *p_main_ptt)
2292 {
2293         /* Read shadow of current MFW mailbox */
2294         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2295         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2296                     p_hwfn->mcp_info->mfw_mb_cur,
2297                     p_hwfn->mcp_info->mfw_mb_length);
2298 }
2299
2300 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2301                                     struct ecore_hw_init_params *p_params)
2302 {
2303         if (p_params->p_tunn) {
2304                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2305                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2306         }
2307
2308         p_hwfn->b_int_enabled = 1;
2309
2310         return ECORE_SUCCESS;
2311 }
2312
2313 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2314                                      struct ecore_ptt *p_ptt)
2315 {
2316         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2317                  1 << p_hwfn->abs_pf_id);
2318 }
2319
2320 static void
2321 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2322                            struct ecore_drv_load_params *p_drv_load)
2323 {
2324         /* Make sure that if ecore-client didn't provide inputs, all the
2325          * expected defaults are indeed zero.
2326          */
2327         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2328         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2329         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2330
2331         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2332
2333         if (p_drv_load != OSAL_NULL) {
2334                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2335                                        ECORE_DRV_ROLE_KDUMP :
2336                                        ECORE_DRV_ROLE_OS;
2337                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2338                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2339                 p_load_req->override_force_load =
2340                         p_drv_load->override_force_load;
2341         }
2342 }
2343
2344 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2345                                    struct ecore_hw_init_params *p_params)
2346 {
2347         struct ecore_load_req_params load_req_params;
2348         u32 load_code, resp, param, drv_mb_param;
2349         bool b_default_mtu = true;
2350         struct ecore_hwfn *p_hwfn;
2351         enum _ecore_status_t rc = ECORE_SUCCESS;
2352         int i;
2353
2354         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2355                 DP_NOTICE(p_dev, false,
2356                           "MSI mode is not supported for CMT devices\n");
2357                 return ECORE_INVAL;
2358         }
2359
2360         if (IS_PF(p_dev)) {
2361                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2362                 if (rc != ECORE_SUCCESS)
2363                         return rc;
2364         }
2365
2366         for_each_hwfn(p_dev, i) {
2367                 p_hwfn = &p_dev->hwfns[i];
2368
2369                 /* If management didn't provide a default, set one of our own */
2370                 if (!p_hwfn->hw_info.mtu) {
2371                         p_hwfn->hw_info.mtu = 1500;
2372                         b_default_mtu = false;
2373                 }
2374
2375                 if (IS_VF(p_dev)) {
2376                         ecore_vf_start(p_hwfn, p_params);
2377                         continue;
2378                 }
2379
2380                 rc = ecore_calc_hw_mode(p_hwfn);
2381                 if (rc != ECORE_SUCCESS)
2382                         return rc;
2383
2384                 ecore_fill_load_req_params(&load_req_params,
2385                                            p_params->p_drv_load_params);
2386                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2387                                         &load_req_params);
2388                 if (rc != ECORE_SUCCESS) {
2389                         DP_NOTICE(p_hwfn, true,
2390                                   "Failed sending a LOAD_REQ command\n");
2391                         return rc;
2392                 }
2393
2394                 load_code = load_req_params.load_code;
2395                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2396                            "Load request was sent. Load code: 0x%x\n",
2397                            load_code);
2398
2399                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2400
2401                 /* CQ75580:
2402                  * When coming back from hiberbate state, the registers from
2403                  * which shadow is read initially are not initialized. It turns
2404                  * out that these registers get initialized during the call to
2405                  * ecore_mcp_load_req request. So we need to reread them here
2406                  * to get the proper shadow register value.
2407                  * Note: This is a workaround for the missing MFW
2408                  * initialization. It may be removed once the implementation
2409                  * is done.
2410                  */
2411                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2412
2413                 /* Only relevant for recovery:
2414                  * Clear the indication after the LOAD_REQ command is responded
2415                  * by the MFW.
2416                  */
2417                 p_dev->recov_in_prog = false;
2418
2419                 p_hwfn->first_on_engine = (load_code ==
2420                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2421
2422                 if (!qm_lock_init) {
2423                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2424                         qm_lock_init = true;
2425                 }
2426
2427                 /* Clean up chip from previous driver if such remains exist.
2428                  * This is not needed when the PF is the first one on the
2429                  * engine, since afterwards we are going to init the FW.
2430                  */
2431                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2432                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2433                                                  p_hwfn->rel_pf_id, false);
2434                         if (rc != ECORE_SUCCESS) {
2435                                 ecore_hw_err_notify(p_hwfn,
2436                                                     ECORE_HW_ERR_RAMROD_FAIL);
2437                                 goto load_err;
2438                         }
2439                 }
2440
2441                 /* Log and clean previous pglue_b errors if such exist */
2442                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2443                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2444
2445                 /* Enable the PF's internal FID_enable in the PXP */
2446                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2447                                                   true);
2448                 if (rc != ECORE_SUCCESS)
2449                         goto load_err;
2450
2451                 switch (load_code) {
2452                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2453                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2454                                                   p_hwfn->hw_info.hw_mode);
2455                         if (rc != ECORE_SUCCESS)
2456                                 break;
2457                         /* Fall into */
2458                 case FW_MSG_CODE_DRV_LOAD_PORT:
2459                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2460                                                 p_hwfn->hw_info.hw_mode);
2461                         if (rc != ECORE_SUCCESS)
2462                                 break;
2463                         /* Fall into */
2464                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2465                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2466                                               p_params->p_tunn,
2467                                               p_hwfn->hw_info.hw_mode,
2468                                               p_params->b_hw_start,
2469                                               p_params->int_mode,
2470                                               p_params->allow_npar_tx_switch);
2471                         break;
2472                 default:
2473                         DP_NOTICE(p_hwfn, false,
2474                                   "Unexpected load code [0x%08x]", load_code);
2475                         rc = ECORE_NOTIMPL;
2476                         break;
2477                 }
2478
2479                 if (rc != ECORE_SUCCESS) {
2480                         DP_NOTICE(p_hwfn, true,
2481                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2482                                   load_code, rc);
2483                         goto load_err;
2484                 }
2485
2486                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2487                 if (rc != ECORE_SUCCESS)
2488                         return rc;
2489
2490                 /* send DCBX attention request command */
2491                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2492                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2493                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2494                                    DRV_MSG_CODE_SET_DCBX,
2495                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2496                                    &param);
2497                 if (rc != ECORE_SUCCESS) {
2498                         DP_NOTICE(p_hwfn, true,
2499                                   "Failed to send DCBX attention request\n");
2500                         return rc;
2501                 }
2502
2503                 p_hwfn->hw_init_done = true;
2504         }
2505
2506         if (IS_PF(p_dev)) {
2507                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2508                 drv_mb_param = STORM_FW_VERSION;
2509                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2510                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2511                                    drv_mb_param, &resp, &param);
2512                 if (rc != ECORE_SUCCESS)
2513                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2514
2515                 if (!b_default_mtu)
2516                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2517                                                       p_hwfn->hw_info.mtu);
2518                 if (rc != ECORE_SUCCESS)
2519                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2520
2521                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2522                                                       p_hwfn->p_main_ptt,
2523                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2524                 if (rc != ECORE_SUCCESS)
2525                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2526         }
2527
2528         return rc;
2529
2530 load_err:
2531         /* The MFW load lock should be released regardless of success or failure
2532          * of initialization.
2533          * TODO: replace this with an attempt to send cancel_load.
2534          */
2535         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2536         return rc;
2537 }
2538
2539 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2540 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2541                                  struct ecore_hwfn *p_hwfn,
2542                                  struct ecore_ptt *p_ptt)
2543 {
2544         int i;
2545
2546         /* close timers */
2547         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2548         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2549         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2550                                                                         i++) {
2551                 if ((!ecore_rd(p_hwfn, p_ptt,
2552                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2553                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2554                         break;
2555
2556                 /* Dependent on number of connection/tasks, possibly
2557                  * 1ms sleep is required between polls
2558                  */
2559                 OSAL_MSLEEP(1);
2560         }
2561
2562         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2563                 return;
2564
2565         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2566                   " [Connection %02x Tasks %02x]\n",
2567                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2568                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2569 }
2570
2571 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2572 {
2573         int j;
2574
2575         for_each_hwfn(p_dev, j) {
2576                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2577                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2578
2579                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2580         }
2581 }
2582
2583 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2584                                                  struct ecore_ptt *p_ptt,
2585                                                  u32 addr, u32 expected_val)
2586 {
2587         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2588
2589         if (val != expected_val) {
2590                 DP_NOTICE(p_hwfn, true,
2591                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2592                           addr, val, expected_val);
2593                 return ECORE_UNKNOWN_ERROR;
2594         }
2595
2596         return ECORE_SUCCESS;
2597 }
2598
2599 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2600 {
2601         struct ecore_hwfn *p_hwfn;
2602         struct ecore_ptt *p_ptt;
2603         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2604         int j;
2605
2606         for_each_hwfn(p_dev, j) {
2607                 p_hwfn = &p_dev->hwfns[j];
2608                 p_ptt = p_hwfn->p_main_ptt;
2609
2610                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2611
2612                 if (IS_VF(p_dev)) {
2613                         ecore_vf_pf_int_cleanup(p_hwfn);
2614                         rc = ecore_vf_pf_reset(p_hwfn);
2615                         if (rc != ECORE_SUCCESS) {
2616                                 DP_NOTICE(p_hwfn, true,
2617                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2618                                           rc);
2619                                 rc2 = ECORE_UNKNOWN_ERROR;
2620                         }
2621                         continue;
2622                 }
2623
2624                 /* mark the hw as uninitialized... */
2625                 p_hwfn->hw_init_done = false;
2626
2627                 /* Send unload command to MCP */
2628                 if (!p_dev->recov_in_prog) {
2629                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2630                         if (rc != ECORE_SUCCESS) {
2631                                 DP_NOTICE(p_hwfn, true,
2632                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2633                                           rc);
2634                                 rc2 = ECORE_UNKNOWN_ERROR;
2635                         }
2636                 }
2637
2638                 OSAL_DPC_SYNC(p_hwfn);
2639
2640                 /* After this point no MFW attentions are expected, e.g. prevent
2641                  * race between pf stop and dcbx pf update.
2642                  */
2643
2644                 rc = ecore_sp_pf_stop(p_hwfn);
2645                 if (rc != ECORE_SUCCESS) {
2646                         DP_NOTICE(p_hwfn, true,
2647                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2648                                   rc);
2649                         rc2 = ECORE_UNKNOWN_ERROR;
2650                 }
2651
2652                 /* perform debug action after PF stop was sent */
2653                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2654
2655                 /* close NIG to BRB gate */
2656                 ecore_wr(p_hwfn, p_ptt,
2657                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2658
2659                 /* close parser */
2660                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2661                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2662                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2663                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2664                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2665
2666                 /* @@@TBD - clean transmission queues (5.b) */
2667                 /* @@@TBD - clean BTB (5.c) */
2668
2669                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2670
2671                 /* @@@TBD - verify DMAE requests are done (8) */
2672
2673                 /* Disable Attention Generation */
2674                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2675                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2676                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2677                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2678                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2679                 if (rc != ECORE_SUCCESS) {
2680                         DP_NOTICE(p_hwfn, true,
2681                                   "Failed to return IGU CAM to default\n");
2682                         rc2 = ECORE_UNKNOWN_ERROR;
2683                 }
2684
2685                 /* Need to wait 1ms to guarantee SBs are cleared */
2686                 OSAL_MSLEEP(1);
2687
2688                 if (!p_dev->recov_in_prog) {
2689                         ecore_verify_reg_val(p_hwfn, p_ptt,
2690                                              QM_REG_USG_CNT_PF_TX, 0);
2691                         ecore_verify_reg_val(p_hwfn, p_ptt,
2692                                              QM_REG_USG_CNT_PF_OTHER, 0);
2693                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2694                 }
2695
2696                 /* Disable PF in HW blocks */
2697                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2698                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2699
2700                 if (!p_dev->recov_in_prog) {
2701                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2702                         if (rc != ECORE_SUCCESS) {
2703                                 DP_NOTICE(p_hwfn, true,
2704                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2705                                           rc);
2706                                 rc2 = ECORE_UNKNOWN_ERROR;
2707                         }
2708                 }
2709         } /* hwfn loop */
2710
2711         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2712                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2713                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2714
2715                  /* Clear the PF's internal FID_enable in the PXP.
2716                   * In CMT this should only be done for first hw-function, and
2717                   * only after all transactions have stopped for all active
2718                   * hw-functions.
2719                   */
2720                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2721                                                   false);
2722                 if (rc != ECORE_SUCCESS) {
2723                         DP_NOTICE(p_hwfn, true,
2724                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2725                                   rc);
2726                         rc2 = ECORE_UNKNOWN_ERROR;
2727                 }
2728         }
2729
2730         return rc2;
2731 }
2732
2733 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2734 {
2735         int j;
2736
2737         for_each_hwfn(p_dev, j) {
2738                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2739                 struct ecore_ptt *p_ptt;
2740
2741                 if (IS_VF(p_dev)) {
2742                         ecore_vf_pf_int_cleanup(p_hwfn);
2743                         continue;
2744                 }
2745                 p_ptt = ecore_ptt_acquire(p_hwfn);
2746                 if (!p_ptt)
2747                         return ECORE_AGAIN;
2748
2749                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2750                            "Shutting down the fastpath\n");
2751
2752                 ecore_wr(p_hwfn, p_ptt,
2753                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2754
2755                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2756                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2757                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2758                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2759                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2760
2761                 /* @@@TBD - clean transmission queues (5.b) */
2762                 /* @@@TBD - clean BTB (5.c) */
2763
2764                 /* @@@TBD - verify DMAE requests are done (8) */
2765
2766                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2767                 /* Need to wait 1ms to guarantee SBs are cleared */
2768                 OSAL_MSLEEP(1);
2769                 ecore_ptt_release(p_hwfn, p_ptt);
2770         }
2771
2772         return ECORE_SUCCESS;
2773 }
2774
2775 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2776 {
2777         struct ecore_ptt *p_ptt;
2778
2779         if (IS_VF(p_hwfn->p_dev))
2780                 return ECORE_SUCCESS;
2781
2782         p_ptt = ecore_ptt_acquire(p_hwfn);
2783         if (!p_ptt)
2784                 return ECORE_AGAIN;
2785
2786         /* If roce info is allocated it means roce is initialized and should
2787          * be enabled in searcher.
2788          */
2789         if (p_hwfn->p_rdma_info) {
2790                 if (p_hwfn->b_rdma_enabled_in_prs)
2791                         ecore_wr(p_hwfn, p_ptt,
2792                                  p_hwfn->rdma_prs_search_reg, 0x1);
2793                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2794         }
2795
2796         /* Re-open incoming traffic */
2797         ecore_wr(p_hwfn, p_ptt,
2798                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2799         ecore_ptt_release(p_hwfn, p_ptt);
2800
2801         return ECORE_SUCCESS;
2802 }
2803
2804 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2805 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2806 {
2807         ecore_ptt_pool_free(p_hwfn);
2808         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2809 }
2810
2811 /* Setup bar access */
2812 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2813 {
2814         /* clear indirect access */
2815         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2816                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2817                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2818                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2819                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2820                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2821                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2822                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2823                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2824         } else {
2825                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2826                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2827                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2828                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2829                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2830                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2831                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2832                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2833         }
2834
2835         /* Clean previous pglue_b errors if such exist */
2836         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2837
2838         /* enable internal target-read */
2839         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2840                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2841 }
2842
2843 static void get_function_id(struct ecore_hwfn *p_hwfn)
2844 {
2845         /* ME Register */
2846         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2847                                                   PXP_PF_ME_OPAQUE_ADDR);
2848
2849         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2850
2851         /* Bits 16-19 from the ME registers are the pf_num */
2852         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2853         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2854                                       PXP_CONCRETE_FID_PFID);
2855         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2856                                     PXP_CONCRETE_FID_PORT);
2857
2858         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2859                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2860                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2861 }
2862
2863 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2864 {
2865         u32 *feat_num = p_hwfn->hw_info.feat_num;
2866         struct ecore_sb_cnt_info sb_cnt;
2867         u32 non_l2_sbs = 0;
2868
2869         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2870         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2871
2872         /* L2 Queues require each: 1 status block. 1 L2 queue */
2873         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2874                 /* Start by allocating VF queues, then PF's */
2875                 feat_num[ECORE_VF_L2_QUE] =
2876                         OSAL_MIN_T(u32,
2877                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2878                                    sb_cnt.iov_cnt);
2879                 feat_num[ECORE_PF_L2_QUE] =
2880                         OSAL_MIN_T(u32,
2881                                    sb_cnt.cnt - non_l2_sbs,
2882                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2883                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2884         }
2885
2886         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2887                                              RESC_NUM(p_hwfn,
2888                                                       ECORE_CMDQS_CQS));
2889         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2890                                               RESC_NUM(p_hwfn,
2891                                                        ECORE_CMDQS_CQS));
2892
2893         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2894                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2895                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2896                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2897                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2898                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2899                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2900                    (int)sb_cnt.cnt);
2901 }
2902
2903 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2904 {
2905         switch (res_id) {
2906         case ECORE_L2_QUEUE:
2907                 return "L2_QUEUE";
2908         case ECORE_VPORT:
2909                 return "VPORT";
2910         case ECORE_RSS_ENG:
2911                 return "RSS_ENG";
2912         case ECORE_PQ:
2913                 return "PQ";
2914         case ECORE_RL:
2915                 return "RL";
2916         case ECORE_MAC:
2917                 return "MAC";
2918         case ECORE_VLAN:
2919                 return "VLAN";
2920         case ECORE_RDMA_CNQ_RAM:
2921                 return "RDMA_CNQ_RAM";
2922         case ECORE_ILT:
2923                 return "ILT";
2924         case ECORE_LL2_QUEUE:
2925                 return "LL2_QUEUE";
2926         case ECORE_CMDQS_CQS:
2927                 return "CMDQS_CQS";
2928         case ECORE_RDMA_STATS_QUEUE:
2929                 return "RDMA_STATS_QUEUE";
2930         case ECORE_BDQ:
2931                 return "BDQ";
2932         case ECORE_SB:
2933                 return "SB";
2934         default:
2935                 return "UNKNOWN_RESOURCE";
2936         }
2937 }
2938
2939 static enum _ecore_status_t
2940 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2941                               struct ecore_ptt *p_ptt,
2942                               enum ecore_resources res_id,
2943                               u32 resc_max_val,
2944                               u32 *p_mcp_resp)
2945 {
2946         enum _ecore_status_t rc;
2947
2948         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2949                                         resc_max_val, p_mcp_resp);
2950         if (rc != ECORE_SUCCESS) {
2951                 DP_NOTICE(p_hwfn, true,
2952                           "MFW response failure for a max value setting of resource %d [%s]\n",
2953                           res_id, ecore_hw_get_resc_name(res_id));
2954                 return rc;
2955         }
2956
2957         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2958                 DP_INFO(p_hwfn,
2959                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2960                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2961
2962         return ECORE_SUCCESS;
2963 }
2964
2965 static enum _ecore_status_t
2966 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2967                             struct ecore_ptt *p_ptt)
2968 {
2969         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2970         u32 resc_max_val, mcp_resp;
2971         u8 res_id;
2972         enum _ecore_status_t rc;
2973
2974         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2975                 /* @DPDK */
2976                 switch (res_id) {
2977                 case ECORE_LL2_QUEUE:
2978                 case ECORE_RDMA_CNQ_RAM:
2979                 case ECORE_RDMA_STATS_QUEUE:
2980                 case ECORE_BDQ:
2981                         resc_max_val = 0;
2982                         break;
2983                 default:
2984                         continue;
2985                 }
2986
2987                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2988                                                    resc_max_val, &mcp_resp);
2989                 if (rc != ECORE_SUCCESS)
2990                         return rc;
2991
2992                 /* There's no point to continue to the next resource if the
2993                  * command is not supported by the MFW.
2994                  * We do continue if the command is supported but the resource
2995                  * is unknown to the MFW. Such a resource will be later
2996                  * configured with the default allocation values.
2997                  */
2998                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2999                         return ECORE_NOTIMPL;
3000         }
3001
3002         return ECORE_SUCCESS;
3003 }
3004
3005 static
3006 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3007                                             enum ecore_resources res_id,
3008                                             u32 *p_resc_num, u32 *p_resc_start)
3009 {
3010         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3011         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3012
3013         switch (res_id) {
3014         case ECORE_L2_QUEUE:
3015                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3016                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3017                 break;
3018         case ECORE_VPORT:
3019                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3020                                  MAX_NUM_VPORTS_BB) / num_funcs;
3021                 break;
3022         case ECORE_RSS_ENG:
3023                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3024                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3025                 break;
3026         case ECORE_PQ:
3027                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3028                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3029                 break;
3030         case ECORE_RL:
3031                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3032                 break;
3033         case ECORE_MAC:
3034         case ECORE_VLAN:
3035                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3036                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3037                 break;
3038         case ECORE_ILT:
3039                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3040                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3041                 break;
3042         case ECORE_LL2_QUEUE:
3043                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3044                 break;
3045         case ECORE_RDMA_CNQ_RAM:
3046         case ECORE_CMDQS_CQS:
3047                 /* CNQ/CMDQS are the same resource */
3048                 /* @DPDK */
3049                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3050                 break;
3051         case ECORE_RDMA_STATS_QUEUE:
3052                 /* @DPDK */
3053                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3054                                  MAX_NUM_VPORTS_BB) / num_funcs;
3055                 break;
3056         case ECORE_BDQ:
3057                 /* @DPDK */
3058                 *p_resc_num = 0;
3059                 break;
3060         default:
3061                 break;
3062         }
3063
3064
3065         switch (res_id) {
3066         case ECORE_BDQ:
3067                 if (!*p_resc_num)
3068                         *p_resc_start = 0;
3069                 break;
3070         case ECORE_SB:
3071                 /* Since we want its value to reflect whether MFW supports
3072                  * the new scheme, have a default of 0.
3073                  */
3074                 *p_resc_num = 0;
3075                 break;
3076         default:
3077                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3078                 break;
3079         }
3080
3081         return ECORE_SUCCESS;
3082 }
3083
3084 static enum _ecore_status_t
3085 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3086                          bool drv_resc_alloc)
3087 {
3088         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3089         u32 mcp_resp, *p_resc_num, *p_resc_start;
3090         enum _ecore_status_t rc;
3091
3092         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3093         p_resc_start = &RESC_START(p_hwfn, res_id);
3094
3095         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3096                                     &dflt_resc_start);
3097         if (rc != ECORE_SUCCESS) {
3098                 DP_ERR(p_hwfn,
3099                        "Failed to get default amount for resource %d [%s]\n",
3100                         res_id, ecore_hw_get_resc_name(res_id));
3101                 return rc;
3102         }
3103
3104 #ifndef ASIC_ONLY
3105         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3106                 *p_resc_num = dflt_resc_num;
3107                 *p_resc_start = dflt_resc_start;
3108                 goto out;
3109         }
3110 #endif
3111
3112         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3113                                      &mcp_resp, p_resc_num, p_resc_start);
3114         if (rc != ECORE_SUCCESS) {
3115                 DP_NOTICE(p_hwfn, true,
3116                           "MFW response failure for an allocation request for"
3117                           " resource %d [%s]\n",
3118                           res_id, ecore_hw_get_resc_name(res_id));
3119                 return rc;
3120         }
3121
3122         /* Default driver values are applied in the following cases:
3123          * - The resource allocation MB command is not supported by the MFW
3124          * - There is an internal error in the MFW while processing the request
3125          * - The resource ID is unknown to the MFW
3126          */
3127         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3128                 DP_INFO(p_hwfn,
3129                         "Failed to receive allocation info for resource %d [%s]."
3130                         " mcp_resp = 0x%x. Applying default values"
3131                         " [%d,%d].\n",
3132                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3133                         dflt_resc_num, dflt_resc_start);
3134
3135                 *p_resc_num = dflt_resc_num;
3136                 *p_resc_start = dflt_resc_start;
3137                 goto out;
3138         }
3139
3140         if ((*p_resc_num != dflt_resc_num ||
3141              *p_resc_start != dflt_resc_start) &&
3142             res_id != ECORE_SB) {
3143                 DP_INFO(p_hwfn,
3144                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3145                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3146                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3147                         drv_resc_alloc ? " - Applying default values" : "");
3148                 if (drv_resc_alloc) {
3149                         *p_resc_num = dflt_resc_num;
3150                         *p_resc_start = dflt_resc_start;
3151                 }
3152         }
3153 out:
3154         return ECORE_SUCCESS;
3155 }
3156
3157 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3158                                                    bool drv_resc_alloc)
3159 {
3160         enum _ecore_status_t rc;
3161         u8 res_id;
3162
3163         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3164                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3165                 if (rc != ECORE_SUCCESS)
3166                         return rc;
3167         }
3168
3169         return ECORE_SUCCESS;
3170 }
3171
3172 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3173                                               struct ecore_ptt *p_ptt,
3174                                               bool drv_resc_alloc)
3175 {
3176         struct ecore_resc_unlock_params resc_unlock_params;
3177         struct ecore_resc_lock_params resc_lock_params;
3178         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3179         u8 res_id;
3180         enum _ecore_status_t rc;
3181 #ifndef ASIC_ONLY
3182         u32 *resc_start = p_hwfn->hw_info.resc_start;
3183         u32 *resc_num = p_hwfn->hw_info.resc_num;
3184         /* For AH, an equal share of the ILT lines between the maximal number of
3185          * PFs is not enough for RoCE. This would be solved by the future
3186          * resource allocation scheme, but isn't currently present for
3187          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3188          * to work - the BB number of ILT lines divided by its max PFs number.
3189          */
3190         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3191 #endif
3192
3193         /* Setting the max values of the soft resources and the following
3194          * resources allocation queries should be atomic. Since several PFs can
3195          * run in parallel - a resource lock is needed.
3196          * If either the resource lock or resource set value commands are not
3197          * supported - skip the the max values setting, release the lock if
3198          * needed, and proceed to the queries. Other failures, including a
3199          * failure to acquire the lock, will cause this function to fail.
3200          * Old drivers that don't acquire the lock can run in parallel, and
3201          * their allocation values won't be affected by the updated max values.
3202          */
3203         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3204                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3205
3206         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3207         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3208                 return rc;
3209         } else if (rc == ECORE_NOTIMPL) {
3210                 DP_INFO(p_hwfn,
3211                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3212         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3213                 DP_NOTICE(p_hwfn, false,
3214                           "Failed to acquire the resource lock for the resource allocation commands\n");
3215                 rc = ECORE_BUSY;
3216                 goto unlock_and_exit;
3217         } else {
3218                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3219                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3220                         DP_NOTICE(p_hwfn, false,
3221                                   "Failed to set the max values of the soft resources\n");
3222                         goto unlock_and_exit;
3223                 } else if (rc == ECORE_NOTIMPL) {
3224                         DP_INFO(p_hwfn,
3225                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3226                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3227                                                    &resc_unlock_params);
3228                         if (rc != ECORE_SUCCESS)
3229                                 DP_INFO(p_hwfn,
3230                                         "Failed to release the resource lock for the resource allocation commands\n");
3231                 }
3232         }
3233
3234         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3235         if (rc != ECORE_SUCCESS)
3236                 goto unlock_and_exit;
3237
3238         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3239                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3240                                            &resc_unlock_params);
3241                 if (rc != ECORE_SUCCESS)
3242                         DP_INFO(p_hwfn,
3243                                 "Failed to release the resource lock for the resource allocation commands\n");
3244         }
3245
3246 #ifndef ASIC_ONLY
3247         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3248                 /* Reduced build contains less PQs */
3249                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3250                         resc_num[ECORE_PQ] = 32;
3251                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3252                             p_hwfn->enabled_func_idx;
3253                 }
3254
3255                 /* For AH emulation, since we have a possible maximal number of
3256                  * 16 enabled PFs, in case there are not enough ILT lines -
3257                  * allocate only first PF as RoCE and have all the other ETH
3258                  * only with less ILT lines.
3259                  */
3260                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3261                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3262                                                          resc_num[ECORE_ILT],
3263                                                          roce_min_ilt_lines);
3264         }
3265
3266         /* Correct the common ILT calculation if PF0 has more */
3267         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3268             p_hwfn->p_dev->b_is_emul_full &&
3269             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3270                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3271                     resc_num[ECORE_ILT];
3272 #endif
3273
3274         /* Sanity for ILT */
3275         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3276             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3277                 DP_NOTICE(p_hwfn, true,
3278                           "Can't assign ILT pages [%08x,...,%08x]\n",
3279                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3280                                                                   ECORE_ILT) -
3281                           1);
3282                 return ECORE_INVAL;
3283         }
3284
3285         /* This will also learn the number of SBs from MFW */
3286         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3287                 return ECORE_INVAL;
3288
3289         ecore_hw_set_feat(p_hwfn);
3290
3291         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3292                    "The numbers for each resource are:\n");
3293         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3294                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3295                            ecore_hw_get_resc_name(res_id),
3296                            RESC_NUM(p_hwfn, res_id),
3297                            RESC_START(p_hwfn, res_id));
3298
3299         return ECORE_SUCCESS;
3300
3301 unlock_and_exit:
3302         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3303                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3304                                       &resc_unlock_params);
3305         return rc;
3306 }
3307
3308 static enum _ecore_status_t
3309 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3310                       struct ecore_ptt *p_ptt,
3311                       struct ecore_hw_prepare_params *p_params)
3312 {
3313         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3314         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3315         struct ecore_mcp_link_capabilities *p_caps;
3316         struct ecore_mcp_link_params *link;
3317         enum _ecore_status_t rc;
3318
3319         /* Read global nvm_cfg address */
3320         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3321
3322         /* Verify MCP has initialized it */
3323         if (!nvm_cfg_addr) {
3324                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3325                 if (p_params->b_relaxed_probe)
3326                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3327                 return ECORE_INVAL;
3328         }
3329
3330 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3331
3332         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3333
3334         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3335             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
3336                                                        core_cfg);
3337
3338         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3339
3340         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3341                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3342         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3343                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3344                 break;
3345         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3346                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3347                 break;
3348         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3349                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3350                 break;
3351         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3352                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3353                 break;
3354         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3355                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3356                 break;
3357         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3358                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3359                 break;
3360         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3361                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3362                 break;
3363         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3364                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3365                 break;
3366         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3367                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3368                 break;
3369         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3370                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3371                 break;
3372         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3373                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3374                 break;
3375         default:
3376                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3377                           core_cfg);
3378                 break;
3379         }
3380
3381         /* Read DCBX configuration */
3382         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3383                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3384         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3385                              port_cfg_addr +
3386                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3387         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3388                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3389         switch (dcbx_mode) {
3390         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3391                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3392                 break;
3393         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3394                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3395                 break;
3396         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3397                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3398                 break;
3399         default:
3400                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3401         }
3402
3403         /* Read default link configuration */
3404         link = &p_hwfn->mcp_info->link_input;
3405         p_caps = &p_hwfn->mcp_info->link_capabilities;
3406         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3407             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3408         link_temp = ecore_rd(p_hwfn, p_ptt,
3409                              port_cfg_addr +
3410                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3411         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3412         link->speed.advertised_speeds = link_temp;
3413         p_caps->speed_capabilities = link->speed.advertised_speeds;
3414
3415         link_temp = ecore_rd(p_hwfn, p_ptt,
3416                              port_cfg_addr +
3417                              OFFSETOF(struct nvm_cfg1_port, link_settings));
3418         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3419                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3420         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3421                 link->speed.autoneg = true;
3422                 break;
3423         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3424                 link->speed.forced_speed = 1000;
3425                 break;
3426         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3427                 link->speed.forced_speed = 10000;
3428                 break;
3429         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3430                 link->speed.forced_speed = 25000;
3431                 break;
3432         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3433                 link->speed.forced_speed = 40000;
3434                 break;
3435         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3436                 link->speed.forced_speed = 50000;
3437                 break;
3438         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3439                 link->speed.forced_speed = 100000;
3440                 break;
3441         default:
3442                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3443         }
3444
3445         p_caps->default_speed = link->speed.forced_speed;
3446         p_caps->default_speed_autoneg = link->speed.autoneg;
3447
3448         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3449         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3450         link->pause.autoneg = !!(link_temp &
3451                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3452         link->pause.forced_rx = !!(link_temp &
3453                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3454         link->pause.forced_tx = !!(link_temp &
3455                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3456         link->loopback_mode = 0;
3457
3458         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3459                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3460                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3461                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3462                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3463                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3464                 link->eee.enable = true;
3465                 switch (link_temp) {
3466                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3467                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3468                         link->eee.enable = false;
3469                         break;
3470                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3471                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3472                         break;
3473                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3474                         p_caps->eee_lpi_timer =
3475                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3476                         break;
3477                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3478                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3479                         break;
3480                 }
3481
3482                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3483                 link->eee.tx_lpi_enable = link->eee.enable;
3484                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3485         } else {
3486                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3487         }
3488
3489         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3490                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3491                    link->speed.forced_speed, link->speed.advertised_speeds,
3492                    link->speed.autoneg, link->pause.autoneg,
3493                    p_caps->default_eee, p_caps->eee_lpi_timer);
3494
3495         /* Read Multi-function information from shmem */
3496         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3497             OFFSETOF(struct nvm_cfg1, glob) +
3498             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3499
3500         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3501
3502         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3503             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3504
3505         switch (mf_mode) {
3506         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3507                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3508                 break;
3509         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3510                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3511                 break;
3512         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3513                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3514                 break;
3515         }
3516         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3517                 p_hwfn->p_dev->mf_mode);
3518
3519         /* Read Multi-function information from shmem */
3520         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3521             OFFSETOF(struct nvm_cfg1, glob) +
3522             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3523
3524         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3525         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3526                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3527                              &p_hwfn->hw_info.device_capabilities);
3528         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3529                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3530                              &p_hwfn->hw_info.device_capabilities);
3531         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3532                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3533                              &p_hwfn->hw_info.device_capabilities);
3534         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3535                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3536                              &p_hwfn->hw_info.device_capabilities);
3537         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3538                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3539                              &p_hwfn->hw_info.device_capabilities);
3540
3541         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3542         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3543                 rc = ECORE_SUCCESS;
3544                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3545         }
3546
3547         return rc;
3548 }
3549
3550 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3551                                 struct ecore_ptt *p_ptt)
3552 {
3553         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3554         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3555         struct ecore_dev *p_dev = p_hwfn->p_dev;
3556
3557         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3558
3559         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3560          * in the other bits are selected.
3561          * Bits 1-15 are for functions 1-15, respectively, and their value is
3562          * '0' only for enabled functions (function 0 always exists and
3563          * enabled).
3564          * In case of CMT in BB, only the "even" functions are enabled, and thus
3565          * the number of functions for both hwfns is learnt from the same bits.
3566          */
3567         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3568                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3569                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3570         } else { /* E5 */
3571                 reg_function_hide = 0;
3572         }
3573
3574         if (reg_function_hide & 0x1) {
3575                 if (ECORE_IS_BB(p_dev)) {
3576                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3577                                 num_funcs = 0;
3578                                 eng_mask = 0xaaaa;
3579                         } else {
3580                                 num_funcs = 1;
3581                                 eng_mask = 0x5554;
3582                         }
3583                 } else {
3584                         num_funcs = 1;
3585                         eng_mask = 0xfffe;
3586                 }
3587
3588                 /* Get the number of the enabled functions on the engine */
3589                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3590                 while (tmp) {
3591                         if (tmp & 0x1)
3592                                 num_funcs++;
3593                         tmp >>= 0x1;
3594                 }
3595
3596                 /* Get the PF index within the enabled functions */
3597                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3598                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3599                 while (tmp) {
3600                         if (tmp & 0x1)
3601                                 enabled_func_idx--;
3602                         tmp >>= 0x1;
3603                 }
3604         }
3605
3606         p_hwfn->num_funcs_on_engine = num_funcs;
3607         p_hwfn->enabled_func_idx = enabled_func_idx;
3608
3609 #ifndef ASIC_ONLY
3610         if (CHIP_REV_IS_FPGA(p_dev)) {
3611                 DP_NOTICE(p_hwfn, false,
3612                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3613                 p_hwfn->num_funcs_on_engine = 4;
3614         }
3615 #endif
3616
3617         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3618                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3619                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3620                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3621 }
3622
3623 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3624                                       struct ecore_ptt *p_ptt)
3625 {
3626         struct ecore_dev *p_dev = p_hwfn->p_dev;
3627         u32 port_mode;
3628
3629 #ifndef ASIC_ONLY
3630         /* Read the port mode */
3631         if (CHIP_REV_IS_FPGA(p_dev))
3632                 port_mode = 4;
3633         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3634                 /* In CMT on emulation, assume 1 port */
3635                 port_mode = 1;
3636         else
3637 #endif
3638         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3639
3640         if (port_mode < 3) {
3641                 p_dev->num_ports_in_engine = 1;
3642         } else if (port_mode <= 5) {
3643                 p_dev->num_ports_in_engine = 2;
3644         } else {
3645                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3646                           p_dev->num_ports_in_engine);
3647
3648                 /* Default num_ports_in_engine to something */
3649                 p_dev->num_ports_in_engine = 1;
3650         }
3651 }
3652
3653 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3654                                          struct ecore_ptt *p_ptt)
3655 {
3656         struct ecore_dev *p_dev = p_hwfn->p_dev;
3657         u32 port;
3658         int i;
3659
3660         p_dev->num_ports_in_engine = 0;
3661
3662 #ifndef ASIC_ONLY
3663         if (CHIP_REV_IS_EMUL(p_dev)) {
3664                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3665                 switch ((port & 0xf000) >> 12) {
3666                 case 1:
3667                         p_dev->num_ports_in_engine = 1;
3668                         break;
3669                 case 3:
3670                         p_dev->num_ports_in_engine = 2;
3671                         break;
3672                 case 0xf:
3673                         p_dev->num_ports_in_engine = 4;
3674                         break;
3675                 default:
3676                         DP_NOTICE(p_hwfn, false,
3677                                   "Unknown port mode in ECO_RESERVED %08x\n",
3678                                   port);
3679                 }
3680         } else
3681 #endif
3682                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3683                         port = ecore_rd(p_hwfn, p_ptt,
3684                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3685                                         (i * 4));
3686                         if (port & 1)
3687                                 p_dev->num_ports_in_engine++;
3688                 }
3689
3690         if (!p_dev->num_ports_in_engine) {
3691                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3692
3693                 /* Default num_ports_in_engine to something */
3694                 p_dev->num_ports_in_engine = 1;
3695         }
3696 }
3697
3698 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3699                                    struct ecore_ptt *p_ptt)
3700 {
3701         struct ecore_dev *p_dev = p_hwfn->p_dev;
3702
3703         /* Determine the number of ports per engine */
3704         if (ECORE_IS_BB(p_dev))
3705                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3706         else
3707                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3708
3709         /* Get the total number of ports of the device */
3710         if (ECORE_IS_CMT(p_dev)) {
3711                 /* In CMT there is always only one port */
3712                 p_dev->num_ports = 1;
3713 #ifndef ASIC_ONLY
3714         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3715                 p_dev->num_ports = p_dev->num_ports_in_engine *
3716                                    ecore_device_num_engines(p_dev);
3717 #endif
3718         } else {
3719                 u32 addr, global_offsize, global_addr;
3720
3721                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3722                                             PUBLIC_GLOBAL);
3723                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3724                 global_addr = SECTION_ADDR(global_offsize, 0);
3725                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3726                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3727         }
3728 }
3729
3730 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3731                                    struct ecore_ptt *p_ptt)
3732 {
3733         struct ecore_mcp_link_capabilities *p_caps;
3734         u32 eee_status;
3735
3736         p_caps = &p_hwfn->mcp_info->link_capabilities;
3737         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3738                 return;
3739
3740         p_caps->eee_speed_caps = 0;
3741         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3742                               OFFSETOF(struct public_port, eee_status));
3743         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3744                         EEE_SUPPORTED_SPEED_OFFSET;
3745         if (eee_status & EEE_1G_SUPPORTED)
3746                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3747         if (eee_status & EEE_10G_ADV)
3748                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3749 }
3750
3751 static enum _ecore_status_t
3752 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3753                   enum ecore_pci_personality personality,
3754                   struct ecore_hw_prepare_params *p_params)
3755 {
3756         bool drv_resc_alloc = p_params->drv_resc_alloc;
3757         enum _ecore_status_t rc;
3758
3759         /* Since all information is common, only first hwfns should do this */
3760         if (IS_LEAD_HWFN(p_hwfn)) {
3761                 rc = ecore_iov_hw_info(p_hwfn);
3762                 if (rc != ECORE_SUCCESS) {
3763                         if (p_params->b_relaxed_probe)
3764                                 p_params->p_relaxed_res =
3765                                                 ECORE_HW_PREPARE_BAD_IOV;
3766                         else
3767                                 return rc;
3768                 }
3769         }
3770
3771         if (IS_LEAD_HWFN(p_hwfn))
3772                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3773
3774         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3775
3776 #ifndef ASIC_ONLY
3777         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3778 #endif
3779         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3780         if (rc != ECORE_SUCCESS)
3781                 return rc;
3782 #ifndef ASIC_ONLY
3783         }
3784 #endif
3785
3786         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3787         if (rc != ECORE_SUCCESS) {
3788                 if (p_params->b_relaxed_probe)
3789                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3790                 else
3791                         return rc;
3792         }
3793
3794 #ifndef ASIC_ONLY
3795         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3796 #endif
3797                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3798                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3799 #ifndef ASIC_ONLY
3800         } else {
3801                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3802
3803                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3804                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3805         }
3806 #endif
3807
3808         if (ecore_mcp_is_init(p_hwfn)) {
3809                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3810                         p_hwfn->hw_info.ovlan =
3811                             p_hwfn->mcp_info->func_info.ovlan;
3812
3813                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3814
3815                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3816         }
3817
3818         if (personality != ECORE_PCI_DEFAULT) {
3819                 p_hwfn->hw_info.personality = personality;
3820         } else if (ecore_mcp_is_init(p_hwfn)) {
3821                 enum ecore_pci_personality protocol;
3822
3823                 protocol = p_hwfn->mcp_info->func_info.protocol;
3824                 p_hwfn->hw_info.personality = protocol;
3825         }
3826
3827 #ifndef ASIC_ONLY
3828         /* To overcome ILT lack for emulation, until at least until we'll have
3829          * a definite answer from system about it, allow only PF0 to be RoCE.
3830          */
3831         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3832                 if (!p_hwfn->rel_pf_id)
3833                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3834                 else
3835                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3836         }
3837 #endif
3838
3839         /* although in BB some constellations may support more than 4 tcs,
3840          * that can result in performance penalty in some cases. 4
3841          * represents a good tradeoff between performance and flexibility.
3842          */
3843         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3844
3845         /* start out with a single active tc. This can be increased either
3846          * by dcbx negotiation or by upper layer driver
3847          */
3848         p_hwfn->hw_info.num_active_tc = 1;
3849
3850         ecore_get_num_funcs(p_hwfn, p_ptt);
3851
3852         if (ecore_mcp_is_init(p_hwfn))
3853                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3854
3855         /* In case of forcing the driver's default resource allocation, calling
3856          * ecore_hw_get_resc() should come after initializing the personality
3857          * and after getting the number of functions, since the calculation of
3858          * the resources/features depends on them.
3859          * This order is not harmful if not forcing.
3860          */
3861         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3862         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3863                 rc = ECORE_SUCCESS;
3864                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3865         }
3866
3867         return rc;
3868 }
3869
3870 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3871                                                struct ecore_ptt *p_ptt)
3872 {
3873         struct ecore_dev *p_dev = p_hwfn->p_dev;
3874         u16 device_id_mask;
3875         u32 tmp;
3876
3877         /* Read Vendor Id / Device Id */
3878         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3879                                   &p_dev->vendor_id);
3880         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3881                                   &p_dev->device_id);
3882
3883         /* Determine type */
3884         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3885         switch (device_id_mask) {
3886         case ECORE_DEV_ID_MASK_BB:
3887                 p_dev->type = ECORE_DEV_TYPE_BB;
3888                 break;
3889         case ECORE_DEV_ID_MASK_AH:
3890                 p_dev->type = ECORE_DEV_TYPE_AH;
3891                 break;
3892         default:
3893                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3894                           p_dev->device_id);
3895                 return ECORE_ABORTED;
3896         }
3897
3898         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3899         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3900         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3901         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3902
3903         /* Learn number of HW-functions */
3904         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3905
3906         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3907                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3908                 p_dev->num_hwfns = 2;
3909         } else {
3910                 p_dev->num_hwfns = 1;
3911         }
3912
3913 #ifndef ASIC_ONLY
3914         if (CHIP_REV_IS_EMUL(p_dev)) {
3915                 /* For some reason we have problems with this register
3916                  * in B0 emulation; Simply assume no CMT
3917                  */
3918                 DP_NOTICE(p_dev->hwfns, false,
3919                           "device on emul - assume no CMT\n");
3920                 p_dev->num_hwfns = 1;
3921         }
3922 #endif
3923
3924         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3925         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3926         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3927         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3928
3929         DP_INFO(p_dev->hwfns,
3930                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3931                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3932                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3933                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3934                 p_dev->chip_metal);
3935
3936         if (ECORE_IS_BB_A0(p_dev)) {
3937                 DP_NOTICE(p_dev->hwfns, false,
3938                           "The chip type/rev (BB A0) is not supported!\n");
3939                 return ECORE_ABORTED;
3940         }
3941 #ifndef ASIC_ONLY
3942         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3943                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3944
3945         if (CHIP_REV_IS_EMUL(p_dev)) {
3946                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3947                 if (tmp & (1 << 29)) {
3948                         DP_NOTICE(p_hwfn, false,
3949                                   "Emulation: Running on a FULL build\n");
3950                         p_dev->b_is_emul_full = true;
3951                 } else {
3952                         DP_NOTICE(p_hwfn, false,
3953                                   "Emulation: Running on a REDUCED build\n");
3954                 }
3955         }
3956 #endif
3957
3958         return ECORE_SUCCESS;
3959 }
3960
3961 #ifndef LINUX_REMOVE
3962 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3963 {
3964         int j;
3965
3966         if (IS_VF(p_dev))
3967                 return;
3968
3969         for_each_hwfn(p_dev, j) {
3970                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3971
3972                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3973                            "Mark hw/fw uninitialized\n");
3974
3975                 p_hwfn->hw_init_done = false;
3976
3977                 ecore_ptt_invalidate(p_hwfn);
3978         }
3979 }
3980 #endif
3981
3982 static enum _ecore_status_t
3983 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3984                         void OSAL_IOMEM * p_regview,
3985                         void OSAL_IOMEM * p_doorbells,
3986                         struct ecore_hw_prepare_params *p_params)
3987 {
3988         struct ecore_mdump_retain_data mdump_retain;
3989         struct ecore_dev *p_dev = p_hwfn->p_dev;
3990         struct ecore_mdump_info mdump_info;
3991         enum _ecore_status_t rc = ECORE_SUCCESS;
3992
3993         /* Split PCI bars evenly between hwfns */
3994         p_hwfn->regview = p_regview;
3995         p_hwfn->doorbells = p_doorbells;
3996
3997         if (IS_VF(p_dev))
3998                 return ecore_vf_hw_prepare(p_hwfn);
3999
4000         /* Validate that chip access is feasible */
4001         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4002                 DP_ERR(p_hwfn,
4003                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4004                 if (p_params->b_relaxed_probe)
4005                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4006                 return ECORE_INVAL;
4007         }
4008
4009         get_function_id(p_hwfn);
4010
4011         /* Allocate PTT pool */
4012         rc = ecore_ptt_pool_alloc(p_hwfn);
4013         if (rc) {
4014                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4015                 if (p_params->b_relaxed_probe)
4016                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4017                 goto err0;
4018         }
4019
4020         /* Allocate the main PTT */
4021         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4022
4023         /* First hwfn learns basic information, e.g., number of hwfns */
4024         if (!p_hwfn->my_id) {
4025                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4026                 if (rc != ECORE_SUCCESS) {
4027                         if (p_params->b_relaxed_probe)
4028                                 p_params->p_relaxed_res =
4029                                         ECORE_HW_PREPARE_FAILED_DEV;
4030                         goto err1;
4031                 }
4032         }
4033
4034         ecore_hw_hwfn_prepare(p_hwfn);
4035
4036         /* Initialize MCP structure */
4037         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4038         if (rc) {
4039                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4040                 if (p_params->b_relaxed_probe)
4041                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4042                 goto err1;
4043         }
4044
4045         /* Read the device configuration information from the HW and SHMEM */
4046         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4047                                p_params->personality, p_params);
4048         if (rc) {
4049                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4050                 goto err2;
4051         }
4052
4053         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4054          * called, since among others it sets the ports number in an engine.
4055          */
4056         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4057             !p_dev->recov_in_prog) {
4058                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4059                 if (rc != ECORE_SUCCESS)
4060                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4061         }
4062
4063         /* Check if mdump logs/data are present and update the epoch value */
4064         if (IS_LEAD_HWFN(p_hwfn)) {
4065 #ifndef ASIC_ONLY
4066                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4067 #endif
4068                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4069                                               &mdump_info);
4070                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4071                         DP_NOTICE(p_hwfn, false,
4072                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4073
4074                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4075                                                 &mdump_retain);
4076                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4077                         DP_NOTICE(p_hwfn, false,
4078                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4079                                   mdump_retain.epoch, mdump_retain.pf,
4080                                   mdump_retain.status);
4081
4082                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4083                                            p_params->epoch);
4084 #ifndef ASIC_ONLY
4085                 }
4086 #endif
4087         }
4088
4089         /* Allocate the init RT array and initialize the init-ops engine */
4090         rc = ecore_init_alloc(p_hwfn);
4091         if (rc) {
4092                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4093                 if (p_params->b_relaxed_probe)
4094                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4095                 goto err2;
4096         }
4097 #ifndef ASIC_ONLY
4098         if (CHIP_REV_IS_FPGA(p_dev)) {
4099                 DP_NOTICE(p_hwfn, false,
4100                           "FPGA: workaround; Prevent DMAE parities\n");
4101                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4102                          7);
4103
4104                 DP_NOTICE(p_hwfn, false,
4105                           "FPGA: workaround: Set VF bar0 size\n");
4106                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4107                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4108         }
4109 #endif
4110
4111         return rc;
4112 err2:
4113         if (IS_LEAD_HWFN(p_hwfn))
4114                 ecore_iov_free_hw_info(p_dev);
4115         ecore_mcp_free(p_hwfn);
4116 err1:
4117         ecore_hw_hwfn_free(p_hwfn);
4118 err0:
4119         return rc;
4120 }
4121
4122 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4123                                       struct ecore_hw_prepare_params *p_params)
4124 {
4125         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4126         enum _ecore_status_t rc;
4127
4128         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4129         p_dev->allow_mdump = p_params->allow_mdump;
4130
4131         if (p_params->b_relaxed_probe)
4132                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4133
4134         /* Store the precompiled init data ptrs */
4135         if (IS_PF(p_dev))
4136                 ecore_init_iro_array(p_dev);
4137
4138         /* Initialize the first hwfn - will learn number of hwfns */
4139         rc = ecore_hw_prepare_single(p_hwfn,
4140                                      p_dev->regview,
4141                                      p_dev->doorbells, p_params);
4142         if (rc != ECORE_SUCCESS)
4143                 return rc;
4144
4145         p_params->personality = p_hwfn->hw_info.personality;
4146
4147         /* initilalize 2nd hwfn if necessary */
4148         if (ECORE_IS_CMT(p_dev)) {
4149                 void OSAL_IOMEM *p_regview, *p_doorbell;
4150                 u8 OSAL_IOMEM *addr;
4151
4152                 /* adjust bar offset for second engine */
4153                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4154                                         ecore_hw_bar_size(p_hwfn,
4155                                                           p_hwfn->p_main_ptt,
4156                                                           BAR_ID_0) / 2;
4157                 p_regview = (void OSAL_IOMEM *)addr;
4158
4159                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4160                                         ecore_hw_bar_size(p_hwfn,
4161                                                           p_hwfn->p_main_ptt,
4162                                                           BAR_ID_1) / 2;
4163                 p_doorbell = (void OSAL_IOMEM *)addr;
4164
4165                 /* prepare second hw function */
4166                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4167                                              p_doorbell, p_params);
4168
4169                 /* in case of error, need to free the previously
4170                  * initiliazed hwfn 0.
4171                  */
4172                 if (rc != ECORE_SUCCESS) {
4173                         if (p_params->b_relaxed_probe)
4174                                 p_params->p_relaxed_res =
4175                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4176
4177                         if (IS_PF(p_dev)) {
4178                                 ecore_init_free(p_hwfn);
4179                                 ecore_mcp_free(p_hwfn);
4180                                 ecore_hw_hwfn_free(p_hwfn);
4181                         } else {
4182                                 DP_NOTICE(p_dev, true,
4183                                           "What do we need to free when VF hwfn1 init fails\n");
4184                         }
4185                         return rc;
4186                 }
4187         }
4188
4189         return rc;
4190 }
4191
4192 void ecore_hw_remove(struct ecore_dev *p_dev)
4193 {
4194         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4195         int i;
4196
4197         if (IS_PF(p_dev))
4198                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4199                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4200
4201         for_each_hwfn(p_dev, i) {
4202                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4203
4204                 if (IS_VF(p_dev)) {
4205                         ecore_vf_pf_release(p_hwfn);
4206                         continue;
4207                 }
4208
4209                 ecore_init_free(p_hwfn);
4210                 ecore_hw_hwfn_free(p_hwfn);
4211                 ecore_mcp_free(p_hwfn);
4212
4213 #ifdef CONFIG_ECORE_LOCK_ALLOC
4214                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4215 #endif
4216         }
4217
4218         ecore_iov_free_hw_info(p_dev);
4219 }
4220
4221 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4222                                       struct ecore_chain *p_chain)
4223 {
4224         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4225         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4226         struct ecore_chain_next *p_next;
4227         u32 size, i;
4228
4229         if (!p_virt)
4230                 return;
4231
4232         size = p_chain->elem_size * p_chain->usable_per_page;
4233
4234         for (i = 0; i < p_chain->page_cnt; i++) {
4235                 if (!p_virt)
4236                         break;
4237
4238                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4239                 p_virt_next = p_next->next_virt;
4240                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4241
4242                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4243                                        ECORE_CHAIN_PAGE_SIZE);
4244
4245                 p_virt = p_virt_next;
4246                 p_phys = p_phys_next;
4247         }
4248 }
4249
4250 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4251                                     struct ecore_chain *p_chain)
4252 {
4253         if (!p_chain->p_virt_addr)
4254                 return;
4255
4256         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4257                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4258 }
4259
4260 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4261                                  struct ecore_chain *p_chain)
4262 {
4263         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4264         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4265         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4266
4267         if (!pp_virt_addr_tbl)
4268                 return;
4269
4270         if (!p_pbl_virt)
4271                 goto out;
4272
4273         for (i = 0; i < page_cnt; i++) {
4274                 if (!pp_virt_addr_tbl[i])
4275                         break;
4276
4277                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4278                                        *(dma_addr_t *)p_pbl_virt,
4279                                        ECORE_CHAIN_PAGE_SIZE);
4280
4281                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4282         }
4283
4284         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4285
4286         if (!p_chain->b_external_pbl)
4287                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4288                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4289 out:
4290         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4291 }
4292
4293 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4294 {
4295         switch (p_chain->mode) {
4296         case ECORE_CHAIN_MODE_NEXT_PTR:
4297                 ecore_chain_free_next_ptr(p_dev, p_chain);
4298                 break;
4299         case ECORE_CHAIN_MODE_SINGLE:
4300                 ecore_chain_free_single(p_dev, p_chain);
4301                 break;
4302         case ECORE_CHAIN_MODE_PBL:
4303                 ecore_chain_free_pbl(p_dev, p_chain);
4304                 break;
4305         }
4306 }
4307
4308 static enum _ecore_status_t
4309 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4310                                enum ecore_chain_cnt_type cnt_type,
4311                                osal_size_t elem_size, u32 page_cnt)
4312 {
4313         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4314
4315         /* The actual chain size can be larger than the maximal possible value
4316          * after rounding up the requested elements number to pages, and after
4317          * taking into acount the unusuable elements (next-ptr elements).
4318          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4319          * size/capacity fields are of a u32 type.
4320          */
4321         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4322              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4323             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4324              chain_size > ECORE_U32_MAX)) {
4325                 DP_NOTICE(p_dev, true,
4326                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4327                           (unsigned long)chain_size);
4328                 return ECORE_INVAL;
4329         }
4330
4331         return ECORE_SUCCESS;
4332 }
4333
4334 static enum _ecore_status_t
4335 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4336 {
4337         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4338         dma_addr_t p_phys = 0;
4339         u32 i;
4340
4341         for (i = 0; i < p_chain->page_cnt; i++) {
4342                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4343                                                  ECORE_CHAIN_PAGE_SIZE);
4344                 if (!p_virt) {
4345                         DP_NOTICE(p_dev, true,
4346                                   "Failed to allocate chain memory\n");
4347                         return ECORE_NOMEM;
4348                 }
4349
4350                 if (i == 0) {
4351                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4352                         ecore_chain_reset(p_chain);
4353                 } else {
4354                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4355                                                        p_virt, p_phys);
4356                 }
4357
4358                 p_virt_prev = p_virt;
4359         }
4360         /* Last page's next element should point to the beginning of the
4361          * chain.
4362          */
4363         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4364                                        p_chain->p_virt_addr,
4365                                        p_chain->p_phys_addr);
4366
4367         return ECORE_SUCCESS;
4368 }
4369
4370 static enum _ecore_status_t
4371 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4372 {
4373         dma_addr_t p_phys = 0;
4374         void *p_virt = OSAL_NULL;
4375
4376         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4377         if (!p_virt) {
4378                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4379                 return ECORE_NOMEM;
4380         }
4381
4382         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4383         ecore_chain_reset(p_chain);
4384
4385         return ECORE_SUCCESS;
4386 }
4387
4388 static enum _ecore_status_t
4389 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4390                       struct ecore_chain *p_chain,
4391                       struct ecore_chain_ext_pbl *ext_pbl)
4392 {
4393         void *p_virt = OSAL_NULL;
4394         u8 *p_pbl_virt = OSAL_NULL;
4395         void **pp_virt_addr_tbl = OSAL_NULL;
4396         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4397         u32 page_cnt = p_chain->page_cnt, size, i;
4398
4399         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4400         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4401         if (!pp_virt_addr_tbl) {
4402                 DP_NOTICE(p_dev, true,
4403                           "Failed to allocate memory for the chain virtual addresses table\n");
4404                 return ECORE_NOMEM;
4405         }
4406
4407         /* The allocation of the PBL table is done with its full size, since it
4408          * is expected to be successive.
4409          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4410          * failure, since pp_virt_addr_tbl was previously allocated, and it
4411          * should be saved to allow its freeing during the error flow.
4412          */
4413         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4414
4415         if (ext_pbl == OSAL_NULL) {
4416                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4417         } else {
4418                 p_pbl_virt = ext_pbl->p_pbl_virt;
4419                 p_pbl_phys = ext_pbl->p_pbl_phys;
4420                 p_chain->b_external_pbl = true;
4421         }
4422
4423         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4424                                  pp_virt_addr_tbl);
4425         if (!p_pbl_virt) {
4426                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4427                 return ECORE_NOMEM;
4428         }
4429
4430         for (i = 0; i < page_cnt; i++) {
4431                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4432                                                  ECORE_CHAIN_PAGE_SIZE);
4433                 if (!p_virt) {
4434                         DP_NOTICE(p_dev, true,
4435                                   "Failed to allocate chain memory\n");
4436                         return ECORE_NOMEM;
4437                 }
4438
4439                 if (i == 0) {
4440                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4441                         ecore_chain_reset(p_chain);
4442                 }
4443
4444                 /* Fill the PBL table with the physical address of the page */
4445                 *(dma_addr_t *)p_pbl_virt = p_phys;
4446                 /* Keep the virtual address of the page */
4447                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4448
4449                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4450         }
4451
4452         return ECORE_SUCCESS;
4453 }
4454
4455 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4456                                        enum ecore_chain_use_mode intended_use,
4457                                        enum ecore_chain_mode mode,
4458                                        enum ecore_chain_cnt_type cnt_type,
4459                                        u32 num_elems, osal_size_t elem_size,
4460                                        struct ecore_chain *p_chain,
4461                                        struct ecore_chain_ext_pbl *ext_pbl)
4462 {
4463         u32 page_cnt;
4464         enum _ecore_status_t rc = ECORE_SUCCESS;
4465
4466         if (mode == ECORE_CHAIN_MODE_SINGLE)
4467                 page_cnt = 1;
4468         else
4469                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4470
4471         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4472                                             page_cnt);
4473         if (rc) {
4474                 DP_NOTICE(p_dev, true,
4475                           "Cannot allocate a chain with the given arguments:\n"
4476                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4477                           intended_use, mode, cnt_type, num_elems, elem_size);
4478                 return rc;
4479         }
4480
4481         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4482                                 mode, cnt_type, p_dev->dp_ctx);
4483
4484         switch (mode) {
4485         case ECORE_CHAIN_MODE_NEXT_PTR:
4486                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4487                 break;
4488         case ECORE_CHAIN_MODE_SINGLE:
4489                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4490                 break;
4491         case ECORE_CHAIN_MODE_PBL:
4492                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4493                 break;
4494         }
4495         if (rc)
4496                 goto nomem;
4497
4498         return ECORE_SUCCESS;
4499
4500 nomem:
4501         ecore_chain_free(p_dev, p_chain);
4502         return rc;
4503 }
4504
4505 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4506                                        u16 src_id, u16 *dst_id)
4507 {
4508         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4509                 u16 min, max;
4510
4511                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4512                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4513                 DP_NOTICE(p_hwfn, true,
4514                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4515                           src_id, min, max);
4516
4517                 return ECORE_INVAL;
4518         }
4519
4520         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4521
4522         return ECORE_SUCCESS;
4523 }
4524
4525 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4526                                     u8 src_id, u8 *dst_id)
4527 {
4528         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4529                 u8 min, max;
4530
4531                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4532                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4533                 DP_NOTICE(p_hwfn, true,
4534                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4535                           src_id, min, max);
4536
4537                 return ECORE_INVAL;
4538         }
4539
4540         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4541
4542         return ECORE_SUCCESS;
4543 }
4544
4545 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4546                                       u8 src_id, u8 *dst_id)
4547 {
4548         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4549                 u8 min, max;
4550
4551                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4552                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4553                 DP_NOTICE(p_hwfn, true,
4554                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4555                           src_id, min, max);
4556
4557                 return ECORE_INVAL;
4558         }
4559
4560         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4561
4562         return ECORE_SUCCESS;
4563 }
4564
4565 static enum _ecore_status_t
4566 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4567                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4568                                u32 *p_entry_num)
4569 {
4570         u32 en;
4571         int i;
4572
4573         /* Find a free entry and utilize it */
4574         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4575                 en = ecore_rd(p_hwfn, p_ptt,
4576                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4577                               i * sizeof(u32));
4578                 if (en)
4579                         continue;
4580                 ecore_wr(p_hwfn, p_ptt,
4581                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4582                          2 * i * sizeof(u32), low);
4583                 ecore_wr(p_hwfn, p_ptt,
4584                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4585                          (2 * i + 1) * sizeof(u32), high);
4586                 ecore_wr(p_hwfn, p_ptt,
4587                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4588                          i * sizeof(u32), 0);
4589                 ecore_wr(p_hwfn, p_ptt,
4590                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4591                          i * sizeof(u32), 0);
4592                 ecore_wr(p_hwfn, p_ptt,
4593                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4594                          i * sizeof(u32), 1);
4595                 break;
4596         }
4597
4598         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4599                 return ECORE_NORESOURCES;
4600
4601         *p_entry_num = i;
4602
4603         return ECORE_SUCCESS;
4604 }
4605
4606 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4607                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4608 {
4609         u32 high, low, entry_num;
4610         enum _ecore_status_t rc;
4611
4612         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4613                 return ECORE_SUCCESS;
4614
4615         high = p_filter[1] | (p_filter[0] << 8);
4616         low = p_filter[5] | (p_filter[4] << 8) |
4617               (p_filter[3] << 16) | (p_filter[2] << 24);
4618
4619         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4620                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4621                                                     &entry_num);
4622         if (rc != ECORE_SUCCESS) {
4623                 DP_NOTICE(p_hwfn, false,
4624                           "Failed to find an empty LLH filter to utilize\n");
4625                 return rc;
4626         }
4627
4628         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4629                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4630                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4631                    p_filter[4], p_filter[5], entry_num);
4632
4633         return ECORE_SUCCESS;
4634 }
4635
4636 static enum _ecore_status_t
4637 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4638                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4639                                   u32 *p_entry_num)
4640 {
4641         int i;
4642
4643         /* Find the entry and clean it */
4644         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4645                 if (ecore_rd(p_hwfn, p_ptt,
4646                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4647                              2 * i * sizeof(u32)) != low)
4648                         continue;
4649                 if (ecore_rd(p_hwfn, p_ptt,
4650                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4651                              (2 * i + 1) * sizeof(u32)) != high)
4652                         continue;
4653
4654                 ecore_wr(p_hwfn, p_ptt,
4655                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4656                 ecore_wr(p_hwfn, p_ptt,
4657                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4658                          2 * i * sizeof(u32), 0);
4659                 ecore_wr(p_hwfn, p_ptt,
4660                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4661                          (2 * i + 1) * sizeof(u32), 0);
4662                 break;
4663         }
4664
4665         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4666                 return ECORE_INVAL;
4667
4668         *p_entry_num = i;
4669
4670         return ECORE_SUCCESS;
4671 }
4672
4673 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4674                              struct ecore_ptt *p_ptt, u8 *p_filter)
4675 {
4676         u32 high, low, entry_num;
4677         enum _ecore_status_t rc;
4678
4679         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4680                 return;
4681
4682         high = p_filter[1] | (p_filter[0] << 8);
4683         low = p_filter[5] | (p_filter[4] << 8) |
4684               (p_filter[3] << 16) | (p_filter[2] << 24);
4685
4686         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4687                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4688                                                        low, &entry_num);
4689         if (rc != ECORE_SUCCESS) {
4690                 DP_NOTICE(p_hwfn, false,
4691                           "Tried to remove a non-configured filter\n");
4692                 return;
4693         }
4694
4695
4696         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4697                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4698                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4699                    p_filter[4], p_filter[5], entry_num);
4700 }
4701
4702 static enum _ecore_status_t
4703 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4704                                     struct ecore_ptt *p_ptt,
4705                                     enum ecore_llh_port_filter_type_t type,
4706                                     u32 high, u32 low, u32 *p_entry_num)
4707 {
4708         u32 en;
4709         int i;
4710
4711         /* Find a free entry and utilize it */
4712         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4713                 en = ecore_rd(p_hwfn, p_ptt,
4714                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4715                               i * sizeof(u32));
4716                 if (en)
4717                         continue;
4718                 ecore_wr(p_hwfn, p_ptt,
4719                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4720                          2 * i * sizeof(u32), low);
4721                 ecore_wr(p_hwfn, p_ptt,
4722                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4723                          (2 * i + 1) * sizeof(u32), high);
4724                 ecore_wr(p_hwfn, p_ptt,
4725                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4726                          i * sizeof(u32), 1);
4727                 ecore_wr(p_hwfn, p_ptt,
4728                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4729                          i * sizeof(u32), 1 << type);
4730                 ecore_wr(p_hwfn, p_ptt,
4731                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4732                 break;
4733         }
4734
4735         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4736                 return ECORE_NORESOURCES;
4737
4738         *p_entry_num = i;
4739
4740         return ECORE_SUCCESS;
4741 }
4742
4743 enum _ecore_status_t
4744 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4745                               struct ecore_ptt *p_ptt,
4746                               u16 source_port_or_eth_type,
4747                               u16 dest_port,
4748                               enum ecore_llh_port_filter_type_t type)
4749 {
4750         u32 high, low, entry_num;
4751         enum _ecore_status_t rc;
4752
4753         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4754                 return ECORE_SUCCESS;
4755
4756         high = 0;
4757         low = 0;
4758
4759         switch (type) {
4760         case ECORE_LLH_FILTER_ETHERTYPE:
4761                 high = source_port_or_eth_type;
4762                 break;
4763         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4764         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4765                 low = source_port_or_eth_type << 16;
4766                 break;
4767         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4768         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4769                 low = dest_port;
4770                 break;
4771         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4772         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4773                 low = (source_port_or_eth_type << 16) | dest_port;
4774                 break;
4775         default:
4776                 DP_NOTICE(p_hwfn, true,
4777                           "Non valid LLH protocol filter type %d\n", type);
4778                 return ECORE_INVAL;
4779         }
4780
4781         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4782                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4783                                                          high, low, &entry_num);
4784         if (rc != ECORE_SUCCESS) {
4785                 DP_NOTICE(p_hwfn, false,
4786                           "Failed to find an empty LLH filter to utilize\n");
4787                 return rc;
4788         }
4789         switch (type) {
4790         case ECORE_LLH_FILTER_ETHERTYPE:
4791                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4792                            "ETH type %x is added at %d\n",
4793                            source_port_or_eth_type, entry_num);
4794                 break;
4795         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4796                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4797                            "TCP src port %x is added at %d\n",
4798                            source_port_or_eth_type, entry_num);
4799                 break;
4800         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4801                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4802                            "UDP src port %x is added at %d\n",
4803                            source_port_or_eth_type, entry_num);
4804                 break;
4805         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4806                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4807                            "TCP dst port %x is added at %d\n", dest_port,
4808                            entry_num);
4809                 break;
4810         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4811                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4812                            "UDP dst port %x is added at %d\n", dest_port,
4813                            entry_num);
4814                 break;
4815         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4816                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4817                            "TCP src/dst ports %x/%x are added at %d\n",
4818                            source_port_or_eth_type, dest_port, entry_num);
4819                 break;
4820         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4821                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4822                            "UDP src/dst ports %x/%x are added at %d\n",
4823                            source_port_or_eth_type, dest_port, entry_num);
4824                 break;
4825         }
4826
4827         return ECORE_SUCCESS;
4828 }
4829
4830 static enum _ecore_status_t
4831 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4832                                        struct ecore_ptt *p_ptt,
4833                                        enum ecore_llh_port_filter_type_t type,
4834                                        u32 high, u32 low, u32 *p_entry_num)
4835 {
4836         int i;
4837
4838         /* Find the entry and clean it */
4839         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4840                 if (!ecore_rd(p_hwfn, p_ptt,
4841                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4842                               i * sizeof(u32)))
4843                         continue;
4844                 if (!ecore_rd(p_hwfn, p_ptt,
4845                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4846                               i * sizeof(u32)))
4847                         continue;
4848                 if (!(ecore_rd(p_hwfn, p_ptt,
4849                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4850                                i * sizeof(u32)) & (1 << type)))
4851                         continue;
4852                 if (ecore_rd(p_hwfn, p_ptt,
4853                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4854                              2 * i * sizeof(u32)) != low)
4855                         continue;
4856                 if (ecore_rd(p_hwfn, p_ptt,
4857                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4858                              (2 * i + 1) * sizeof(u32)) != high)
4859                         continue;
4860
4861                 ecore_wr(p_hwfn, p_ptt,
4862                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4863                 ecore_wr(p_hwfn, p_ptt,
4864                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4865                          i * sizeof(u32), 0);
4866                 ecore_wr(p_hwfn, p_ptt,
4867                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4868                          i * sizeof(u32), 0);
4869                 ecore_wr(p_hwfn, p_ptt,
4870                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4871                          2 * i * sizeof(u32), 0);
4872                 ecore_wr(p_hwfn, p_ptt,
4873                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4874                          (2 * i + 1) * sizeof(u32), 0);
4875                 break;
4876         }
4877
4878         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4879                 return ECORE_INVAL;
4880
4881         *p_entry_num = i;
4882
4883         return ECORE_SUCCESS;
4884 }
4885
4886 void
4887 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4888                                  struct ecore_ptt *p_ptt,
4889                                  u16 source_port_or_eth_type,
4890                                  u16 dest_port,
4891                                  enum ecore_llh_port_filter_type_t type)
4892 {
4893         u32 high, low, entry_num;
4894         enum _ecore_status_t rc;
4895
4896         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4897                 return;
4898
4899         high = 0;
4900         low = 0;
4901
4902         switch (type) {
4903         case ECORE_LLH_FILTER_ETHERTYPE:
4904                 high = source_port_or_eth_type;
4905                 break;
4906         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4907         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4908                 low = source_port_or_eth_type << 16;
4909                 break;
4910         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4911         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4912                 low = dest_port;
4913                 break;
4914         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4915         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4916                 low = (source_port_or_eth_type << 16) | dest_port;
4917                 break;
4918         default:
4919                 DP_NOTICE(p_hwfn, true,
4920                           "Non valid LLH protocol filter type %d\n", type);
4921                 return;
4922         }
4923
4924         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4925                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4926                                                             high, low,
4927                                                             &entry_num);
4928         if (rc != ECORE_SUCCESS) {
4929                 DP_NOTICE(p_hwfn, false,
4930                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4931                           type, source_port_or_eth_type, dest_port);
4932                 return;
4933         }
4934
4935         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4936                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4937                    type, source_port_or_eth_type, dest_port, entry_num);
4938 }
4939
4940 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4941                                               struct ecore_ptt *p_ptt)
4942 {
4943         int i;
4944
4945         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4946                 return;
4947
4948         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4949                 ecore_wr(p_hwfn, p_ptt,
4950                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4951                          i * sizeof(u32), 0);
4952                 ecore_wr(p_hwfn, p_ptt,
4953                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4954                          2 * i * sizeof(u32), 0);
4955                 ecore_wr(p_hwfn, p_ptt,
4956                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4957                          (2 * i + 1) * sizeof(u32), 0);
4958         }
4959 }
4960
4961 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4962                              struct ecore_ptt *p_ptt)
4963 {
4964         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4965                 return;
4966
4967         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4968                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4969 }
4970
4971 enum _ecore_status_t
4972 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4973                                   struct ecore_ptt *p_ptt)
4974 {
4975         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4976                 ecore_wr(p_hwfn, p_ptt,
4977                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4978                          1 << p_hwfn->abs_pf_id / 2);
4979                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4980                 return ECORE_SUCCESS;
4981         }
4982
4983         DP_NOTICE(p_hwfn, false,
4984                   "This function can't be set as default\n");
4985         return ECORE_INVAL;
4986 }
4987
4988 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4989                                                struct ecore_ptt *p_ptt,
4990                                                u32 hw_addr, void *p_eth_qzone,
4991                                                osal_size_t eth_qzone_size,
4992                                                u8 timeset)
4993 {
4994         struct coalescing_timeset *p_coal_timeset;
4995
4996         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4997                 DP_NOTICE(p_hwfn, true,
4998                           "Coalescing configuration not enabled\n");
4999                 return ECORE_INVAL;
5000         }
5001
5002         p_coal_timeset = p_eth_qzone;
5003         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5004         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5005         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5006         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5007
5008         return ECORE_SUCCESS;
5009 }
5010
5011 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5012                                               u16 rx_coal, u16 tx_coal,
5013                                               void *p_handle)
5014 {
5015         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5016         enum _ecore_status_t rc = ECORE_SUCCESS;
5017         struct ecore_ptt *p_ptt;
5018
5019         /* TODO - Configuring a single queue's coalescing but
5020          * claiming all queues are abiding same configuration
5021          * for PF and VF both.
5022          */
5023
5024         if (IS_VF(p_hwfn->p_dev))
5025                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5026                                                 tx_coal, p_cid);
5027
5028         p_ptt = ecore_ptt_acquire(p_hwfn);
5029         if (!p_ptt)
5030                 return ECORE_AGAIN;
5031
5032         if (rx_coal) {
5033                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5034                 if (rc)
5035                         goto out;
5036                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5037         }
5038
5039         if (tx_coal) {
5040                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5041                 if (rc)
5042                         goto out;
5043                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5044         }
5045 out:
5046         ecore_ptt_release(p_hwfn, p_ptt);
5047
5048         return rc;
5049 }
5050
5051 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5052                                             struct ecore_ptt *p_ptt,
5053                                             u16 coalesce,
5054                                             struct ecore_queue_cid *p_cid)
5055 {
5056         struct ustorm_eth_queue_zone eth_qzone;
5057         u8 timeset, timer_res;
5058         u32 address;
5059         enum _ecore_status_t rc;
5060
5061         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5062         if (coalesce <= 0x7F) {
5063                 timer_res = 0;
5064         } else if (coalesce <= 0xFF) {
5065                 timer_res = 1;
5066         } else if (coalesce <= 0x1FF) {
5067                 timer_res = 2;
5068         } else {
5069                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5070                 return ECORE_INVAL;
5071         }
5072         timeset = (u8)(coalesce >> timer_res);
5073
5074         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5075                                      p_cid->sb_igu_id, false);
5076         if (rc != ECORE_SUCCESS)
5077                 goto out;
5078
5079         address = BAR0_MAP_REG_USDM_RAM +
5080                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5081
5082         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5083                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5084         if (rc != ECORE_SUCCESS)
5085                 goto out;
5086
5087 out:
5088         return rc;
5089 }
5090
5091 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5092                                             struct ecore_ptt *p_ptt,
5093                                             u16 coalesce,
5094                                             struct ecore_queue_cid *p_cid)
5095 {
5096         struct xstorm_eth_queue_zone eth_qzone;
5097         u8 timeset, timer_res;
5098         u32 address;
5099         enum _ecore_status_t rc;
5100
5101         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5102         if (coalesce <= 0x7F) {
5103                 timer_res = 0;
5104         } else if (coalesce <= 0xFF) {
5105                 timer_res = 1;
5106         } else if (coalesce <= 0x1FF) {
5107                 timer_res = 2;
5108         } else {
5109                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5110                 return ECORE_INVAL;
5111         }
5112
5113         timeset = (u8)(coalesce >> timer_res);
5114
5115         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5116                                      p_cid->sb_igu_id, true);
5117         if (rc != ECORE_SUCCESS)
5118                 goto out;
5119
5120         address = BAR0_MAP_REG_XSDM_RAM +
5121                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5122
5123         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5124                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5125 out:
5126         return rc;
5127 }
5128
5129 /* Calculate final WFQ values for all vports and configure it.
5130  * After this configuration each vport must have
5131  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5132  */
5133 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5134                                                struct ecore_ptt *p_ptt,
5135                                                u32 min_pf_rate)
5136 {
5137         struct init_qm_vport_params *vport_params;
5138         int i;
5139
5140         vport_params = p_hwfn->qm_info.qm_vport_params;
5141
5142         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5143                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5144
5145                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5146                     min_pf_rate;
5147                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5148                                      vport_params[i].first_tx_pq_id,
5149                                      vport_params[i].vport_wfq);
5150         }
5151 }
5152
5153 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5154 {
5155         int i;
5156
5157         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5158                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5159 }
5160
5161 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5162                                              struct ecore_ptt *p_ptt)
5163 {
5164         struct init_qm_vport_params *vport_params;
5165         int i;
5166
5167         vport_params = p_hwfn->qm_info.qm_vport_params;
5168
5169         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5170                 ecore_init_wfq_default_param(p_hwfn);
5171                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5172                                      vport_params[i].first_tx_pq_id,
5173                                      vport_params[i].vport_wfq);
5174         }
5175 }
5176
5177 /* This function performs several validations for WFQ
5178  * configuration and required min rate for a given vport
5179  * 1. req_rate must be greater than one percent of min_pf_rate.
5180  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5181  *    rates to get less than one percent of min_pf_rate.
5182  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5183  */
5184 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5185                                                  u16 vport_id, u32 req_rate,
5186                                                  u32 min_pf_rate)
5187 {
5188         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5189         int non_requested_count = 0, req_count = 0, i, num_vports;
5190
5191         num_vports = p_hwfn->qm_info.num_vports;
5192
5193 /* Accounting for the vports which are configured for WFQ explicitly */
5194
5195         for (i = 0; i < num_vports; i++) {
5196                 u32 tmp_speed;
5197
5198                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5199                         req_count++;
5200                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5201                         total_req_min_rate += tmp_speed;
5202                 }
5203         }
5204
5205         /* Include current vport data as well */
5206         req_count++;
5207         total_req_min_rate += req_rate;
5208         non_requested_count = num_vports - req_count;
5209
5210         /* validate possible error cases */
5211         if (req_rate > min_pf_rate) {
5212                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5213                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5214                            vport_id, req_rate, min_pf_rate);
5215                 return ECORE_INVAL;
5216         }
5217
5218         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5219                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5220                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5221                            vport_id, req_rate, min_pf_rate);
5222                 return ECORE_INVAL;
5223         }
5224
5225         /* TBD - for number of vports greater than 100 */
5226         if (num_vports > ECORE_WFQ_UNIT) {
5227                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5228                            "Number of vports is greater than %d\n",
5229                            ECORE_WFQ_UNIT);
5230                 return ECORE_INVAL;
5231         }
5232
5233         if (total_req_min_rate > min_pf_rate) {
5234                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5235                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5236                            total_req_min_rate, min_pf_rate);
5237                 return ECORE_INVAL;
5238         }
5239
5240         /* Data left for non requested vports */
5241         total_left_rate = min_pf_rate - total_req_min_rate;
5242         left_rate_per_vp = total_left_rate / non_requested_count;
5243
5244         /* validate if non requested get < 1% of min bw */
5245         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5246                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5247                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5248                            left_rate_per_vp, min_pf_rate);
5249                 return ECORE_INVAL;
5250         }
5251
5252         /* now req_rate for given vport passes all scenarios.
5253          * assign final wfq rates to all vports.
5254          */
5255         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5256         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5257
5258         for (i = 0; i < num_vports; i++) {
5259                 if (p_hwfn->qm_info.wfq_data[i].configured)
5260                         continue;
5261
5262                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5263         }
5264
5265         return ECORE_SUCCESS;
5266 }
5267
5268 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5269                                        struct ecore_ptt *p_ptt,
5270                                        u16 vp_id, u32 rate)
5271 {
5272         struct ecore_mcp_link_state *p_link;
5273         int rc = ECORE_SUCCESS;
5274
5275         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5276
5277         if (!p_link->min_pf_rate) {
5278                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5279                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5280                 return rc;
5281         }
5282
5283         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5284
5285         if (rc == ECORE_SUCCESS)
5286                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5287                                                    p_link->min_pf_rate);
5288         else
5289                 DP_NOTICE(p_hwfn, false,
5290                           "Validation failed while configuring min rate\n");
5291
5292         return rc;
5293 }
5294
5295 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5296                                                    struct ecore_ptt *p_ptt,
5297                                                    u32 min_pf_rate)
5298 {
5299         bool use_wfq = false;
5300         int rc = ECORE_SUCCESS;
5301         u16 i;
5302
5303         /* Validate all pre configured vports for wfq */
5304         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5305                 u32 rate;
5306
5307                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5308                         continue;
5309
5310                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5311                 use_wfq = true;
5312
5313                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5314                 if (rc != ECORE_SUCCESS) {
5315                         DP_NOTICE(p_hwfn, false,
5316                                   "WFQ validation failed while configuring min rate\n");
5317                         break;
5318                 }
5319         }
5320
5321         if (rc == ECORE_SUCCESS && use_wfq)
5322                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5323         else
5324                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5325
5326         return rc;
5327 }
5328
5329 /* Main API for ecore clients to configure vport min rate.
5330  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5331  * rate - Speed in Mbps needs to be assigned to a given vport.
5332  */
5333 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5334 {
5335         int i, rc = ECORE_INVAL;
5336
5337         /* TBD - for multiple hardware functions - that is 100 gig */
5338         if (ECORE_IS_CMT(p_dev)) {
5339                 DP_NOTICE(p_dev, false,
5340                           "WFQ configuration is not supported for this device\n");
5341                 return rc;
5342         }
5343
5344         for_each_hwfn(p_dev, i) {
5345                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5346                 struct ecore_ptt *p_ptt;
5347
5348                 p_ptt = ecore_ptt_acquire(p_hwfn);
5349                 if (!p_ptt)
5350                         return ECORE_TIMEOUT;
5351
5352                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5353
5354                 if (rc != ECORE_SUCCESS) {
5355                         ecore_ptt_release(p_hwfn, p_ptt);
5356                         return rc;
5357                 }
5358
5359                 ecore_ptt_release(p_hwfn, p_ptt);
5360         }
5361
5362         return rc;
5363 }
5364
5365 /* API to configure WFQ from mcp link change */
5366 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5367                                            struct ecore_ptt *p_ptt,
5368                                            u32 min_pf_rate)
5369 {
5370         int i;
5371
5372         /* TBD - for multiple hardware functions - that is 100 gig */
5373         if (ECORE_IS_CMT(p_dev)) {
5374                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5375                            "WFQ configuration is not supported for this device\n");
5376                 return;
5377         }
5378
5379         for_each_hwfn(p_dev, i) {
5380                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5381
5382                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5383                                                         min_pf_rate);
5384         }
5385 }
5386
5387 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5388                                        struct ecore_ptt *p_ptt,
5389                                        struct ecore_mcp_link_state *p_link,
5390                                        u8 max_bw)
5391 {
5392         int rc = ECORE_SUCCESS;
5393
5394         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5395
5396         if (!p_link->line_speed && (max_bw != 100))
5397                 return rc;
5398
5399         p_link->speed = (p_link->line_speed * max_bw) / 100;
5400         p_hwfn->qm_info.pf_rl = p_link->speed;
5401
5402         /* Since the limiter also affects Tx-switched traffic, we don't want it
5403          * to limit such traffic in case there's no actual limit.
5404          * In that case, set limit to imaginary high boundary.
5405          */
5406         if (max_bw == 100)
5407                 p_hwfn->qm_info.pf_rl = 100000;
5408
5409         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5410                               p_hwfn->qm_info.pf_rl);
5411
5412         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5413                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5414                    p_link->speed);
5415
5416         return rc;
5417 }
5418
5419 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5420 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5421 {
5422         int i, rc = ECORE_INVAL;
5423
5424         if (max_bw < 1 || max_bw > 100) {
5425                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5426                 return rc;
5427         }
5428
5429         for_each_hwfn(p_dev, i) {
5430                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5431                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5432                 struct ecore_mcp_link_state *p_link;
5433                 struct ecore_ptt *p_ptt;
5434
5435                 p_link = &p_lead->mcp_info->link_output;
5436
5437                 p_ptt = ecore_ptt_acquire(p_hwfn);
5438                 if (!p_ptt)
5439                         return ECORE_TIMEOUT;
5440
5441                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5442                                                         p_link, max_bw);
5443
5444                 ecore_ptt_release(p_hwfn, p_ptt);
5445
5446                 if (rc != ECORE_SUCCESS)
5447                         break;
5448         }
5449
5450         return rc;
5451 }
5452
5453 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5454                                        struct ecore_ptt *p_ptt,
5455                                        struct ecore_mcp_link_state *p_link,
5456                                        u8 min_bw)
5457 {
5458         int rc = ECORE_SUCCESS;
5459
5460         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5461         p_hwfn->qm_info.pf_wfq = min_bw;
5462
5463         if (!p_link->line_speed)
5464                 return rc;
5465
5466         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5467
5468         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5469
5470         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5471                    "Configured MIN bandwidth to be %d Mb/sec\n",
5472                    p_link->min_pf_rate);
5473
5474         return rc;
5475 }
5476
5477 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5478 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5479 {
5480         int i, rc = ECORE_INVAL;
5481
5482         if (min_bw < 1 || min_bw > 100) {
5483                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5484                 return rc;
5485         }
5486
5487         for_each_hwfn(p_dev, i) {
5488                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5489                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5490                 struct ecore_mcp_link_state *p_link;
5491                 struct ecore_ptt *p_ptt;
5492
5493                 p_link = &p_lead->mcp_info->link_output;
5494
5495                 p_ptt = ecore_ptt_acquire(p_hwfn);
5496                 if (!p_ptt)
5497                         return ECORE_TIMEOUT;
5498
5499                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5500                                                         p_link, min_bw);
5501                 if (rc != ECORE_SUCCESS) {
5502                         ecore_ptt_release(p_hwfn, p_ptt);
5503                         return rc;
5504                 }
5505
5506                 if (p_link->min_pf_rate) {
5507                         u32 min_rate = p_link->min_pf_rate;
5508
5509                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5510                                                                      p_ptt,
5511                                                                      min_rate);
5512                 }
5513
5514                 ecore_ptt_release(p_hwfn, p_ptt);
5515         }
5516
5517         return rc;
5518 }
5519
5520 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5521 {
5522         struct ecore_mcp_link_state *p_link;
5523
5524         p_link = &p_hwfn->mcp_info->link_output;
5525
5526         if (p_link->min_pf_rate)
5527                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5528
5529         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5530                     sizeof(*p_hwfn->qm_info.wfq_data) *
5531                     p_hwfn->qm_info.num_vports);
5532 }
5533
5534 int ecore_device_num_engines(struct ecore_dev *p_dev)
5535 {
5536         return ECORE_IS_BB(p_dev) ? 2 : 1;
5537 }
5538
5539 int ecore_device_num_ports(struct ecore_dev *p_dev)
5540 {
5541         return p_dev->num_ports;
5542 }
5543
5544 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5545                           __le16 *fw_mid,
5546                           __le16 *fw_lsb,
5547                           u8 *mac)
5548 {
5549         ((u8 *)fw_msb)[0] = mac[1];
5550         ((u8 *)fw_msb)[1] = mac[0];
5551         ((u8 *)fw_mid)[0] = mac[3];
5552         ((u8 *)fw_mid)[1] = mac[2];
5553         ((u8 *)fw_lsb)[0] = mac[5];
5554         ((u8 *)fw_lsb)[1] = mac[4];
5555 }