drivers/net/qede/base/ecore_int.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_spq.h"
  12 #include "reg_addr.h"
  13 #include "ecore_gtt_reg_addr.h"
  14 #include "ecore_init_ops.h"
  15 #include "ecore_rt_defs.h"
  16 #include "ecore_int.h"
  17 #include "reg_addr.h"
  18 #include "ecore_hw.h"
  19 #include "ecore_sriov.h"
  20 #include "ecore_vf.h"
  21 #include "ecore_hw_defs.h"
  22 #include "ecore_hsi_common.h"
  23 #include "ecore_mcp.h"
  24
  25 struct ecore_pi_info {
  26         ecore_int_comp_cb_t comp_cb;
  27         void *cookie;           /* Will be sent to the compl cb function */
  28 };
  29
  30 struct ecore_sb_sp_info {
  31         struct ecore_sb_info sb_info;
  32         /* per protocol index data */
  33         struct ecore_pi_info pi_info_arr[PIS_PER_SB];
  34 };
  35
  36 enum ecore_attention_type {
  37         ECORE_ATTN_TYPE_ATTN,
  38         ECORE_ATTN_TYPE_PARITY,
  39 };
  40
  41 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  42         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  43
  44 struct aeu_invert_reg_bit {
  45         char bit_name[30];
  46
  47 #define ATTENTION_PARITY                (1 << 0)
  48
  49 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  50 #define ATTENTION_LENGTH_SHIFT          (4)
  51 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  52                                          ATTENTION_LENGTH_SHIFT)
  53 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  54 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  55 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  56                                          ATTENTION_PARITY)
  57
  58 /* Multiple bits start with this offset */
  59 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  60 #define ATTENTION_OFFSET_SHIFT          (12)
  61
  62 #define ATTENTION_BB_MASK               (0x00700000)
  63 #define ATTENTION_BB_SHIFT              (20)
  64 #define ATTENTION_BB(value)             ((value) << ATTENTION_BB_SHIFT)
  65 #define ATTENTION_BB_DIFFERENT          (1 << 23)
  66
  67 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  68         unsigned int flags;
  69
  70         /* Callback to call if attention will be triggered */
  71         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  72
  73         enum block_id block_index;
  74 };
  75
  76 struct aeu_invert_reg {
  77         struct aeu_invert_reg_bit bits[32];
  78 };
  79
  80 #define MAX_ATTN_GRPS           (8)
  81 #define NUM_ATTN_REGS           (9)
  82
  83 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  84 {
  85         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  86
  87         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  88         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  89
  90         return ECORE_SUCCESS;
  91 }
  92
  93 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
  99 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
 100 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
 101 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 102 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 103 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 115 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 116 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 117 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 118 {
 119         u32 tmp =
 120             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 121                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 122
 123         /* Disabled VF access */
 124         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 125                 u32 addr, data;
 126
 127                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 128                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 129                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 130                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 131                 DP_INFO(p_hwfn->p_dev,
 132                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 133                         " Write [0x%02x] Addr [0x%08x]\n",
 134                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 135                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 136                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 137                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 138                         (u8)((data &
 139                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 140                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 141                         (u8)((data &
 142                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 143                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 144                         (u8)((data &
 145                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 146                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 147                         addr);
 148         }
 149
 150         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 151                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 152         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 153                 u32 addr, data, length;
 154
 155                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 156                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 157                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 158                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 159                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 160                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 161
 162                 DP_INFO(p_hwfn->p_dev,
 163                         "Incorrect access to %08x of length %08x - PF [%02x]"
 164                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 165                         " Byte-Enable [%04x] [%08x]\n",
 166                         addr, length,
 167                         (u8)((data &
 168                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 169                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 170                         (u8)((data &
 171                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 172                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 173                         (u8)((data &
 174                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 175                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 176                         (u8)((data &
 177                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 178                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 179                         (u8)((data &
 180                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 181                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 182                         (u8)((data &
 183                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 184                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 185                         data);
 186         }
 187
 188         /* TODO - We know 'some' of these are legal due to virtualization,
 189          * but is it true for all of them?
 190          */
 191         return ECORE_SUCCESS;
 192 }
 193
 194 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 195 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 196 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 197 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 198 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 199 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 200 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 201 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 202 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 203 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 204 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 205 static const char *grc_timeout_attn_master_to_str(u8 master)
 206 {
 207         switch (master) {
 208         case 1:
 209                 return "PXP";
 210         case 2:
 211                 return "MCP";
 212         case 3:
 213                 return "MSDM";
 214         case 4:
 215                 return "PSDM";
 216         case 5:
 217                 return "YSDM";
 218         case 6:
 219                 return "USDM";
 220         case 7:
 221                 return "TSDM";
 222         case 8:
 223                 return "XSDM";
 224         case 9:
 225                 return "DBU";
 226         case 10:
 227                 return "DMAE";
 228         default:
 229                 return "Unknown";
 230         }
 231 }
 232
 233 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 234 {
 235         u32 tmp, tmp2;
 236
 237         /* We've already cleared the timeout interrupt register, so we learn
 238          * of interrupts via the validity register
 239          */
 240         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 241                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 242         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
 243                 goto out;
 244
 245         /* Read the GRC timeout information */
 246         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 247                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 248         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 249                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 250
 251         DP_NOTICE(p_hwfn->p_dev, false,
 252                   "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 253                   tmp2, tmp,
 254                   (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
 255                                                        : "Read from",
 256                   (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 257                   grc_timeout_attn_master_to_str(
 258                         (tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
 259                          ECORE_GRC_ATTENTION_MASTER_SHIFT),
 260                   (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 261                   (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 262                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 263                   ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 264                   (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 265                   ECORE_GRC_ATTENTION_VF_SHIFT);
 266
 267 out:
 268         /* Regardles of anything else, clean the validity bit */
 269         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 270                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 271         return ECORE_SUCCESS;
 272 }
 273
 274 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 275 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 276 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 277 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 278 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 279 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 280 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 281 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 282 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 283 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 284 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 285 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 286 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 287
 288 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 289                                                    struct ecore_ptt *p_ptt)
 290 {
 291         u32 tmp;
 292
 293         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 294         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 295                 u32 addr_lo, addr_hi, details;
 296
 297                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 298                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 299                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 300                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 301                 details = ecore_rd(p_hwfn, p_ptt,
 302                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 303
 304                 DP_NOTICE(p_hwfn, false,
 305                           "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 306                           addr_hi, addr_lo, details,
 307                           (u8)((details &
 308                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 309                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 310                           (u8)((details &
 311                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 312                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 313                           (u8)((details &
 314                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 315                           tmp,
 316                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 317                                 1 : 0),
 318                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 319                                 1 : 0),
 320                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 321                                 1 : 0));
 322         }
 323
 324         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 325         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 326                 u32 addr_lo, addr_hi, details;
 327
 328                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 329                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 330                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 331                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 332                 details = ecore_rd(p_hwfn, p_ptt,
 333                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 334
 335                 DP_NOTICE(p_hwfn, false,
 336                           "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 337                           addr_hi, addr_lo, details,
 338                           (u8)((details &
 339                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 340                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 341                           (u8)((details &
 342                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 343                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 344                           (u8)((details &
 345                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 346                           tmp,
 347                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 348                                 1 : 0),
 349                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 350                                 1 : 0),
 351                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 352                                 1 : 0));
 353         }
 354
 355         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 356         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 357                 DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp);
 358
 359         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 360         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 361                 u32 addr_hi, addr_lo;
 362
 363                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 364                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 365                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 366                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 367
 368                 DP_NOTICE(p_hwfn, false,
 369                           "ICPL erorr - %08x [Address %08x:%08x]\n",
 370                           tmp, addr_hi, addr_lo);
 371         }
 372
 373         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 374         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 375                 u32 addr_hi, addr_lo, details;
 376
 377                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 378                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 379                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 380                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 381                 details = ecore_rd(p_hwfn, p_ptt,
 382                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 383
 384                 DP_NOTICE(p_hwfn, false,
 385                           "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 386                           details, tmp, addr_hi, addr_lo);
 387         }
 388
 389         /* Clear the indications */
 390         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 391
 392         return ECORE_SUCCESS;
 393 }
 394
 395 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 396 {
 397         return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);
 398 }
 399
 400 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 401 {
 402         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 403
 404         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 405
 406         return ECORE_INVAL;
 407 }
 408
 409 static enum _ecore_status_t
 410 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 411 {
 412         DP_INFO(p_hwfn, "General attention 35!\n");
 413
 414         return ECORE_SUCCESS;
 415 }
 416
 417 #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
 418 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
 419 #define ECORE_DORQ_ATTENTION_SIZE_MASK   (0x7f0000)
 420 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT  (16)
 421
 422 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 423 {
 424         u32 reason;
 425
 426         reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
 427             ECORE_DORQ_ATTENTION_REASON_MASK;
 428         if (reason) {
 429                 u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 430                                        DORQ_REG_DB_DROP_DETAILS);
 431
 432                 DP_INFO(p_hwfn->p_dev,
 433                         "DORQ db_drop: address 0x%08x Opaque FID 0x%04x"
 434                         " Size [bytes] 0x%08x Reason: 0x%08x\n",
 435                         ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 436                                  DORQ_REG_DB_DROP_DETAILS_ADDRESS),
 437                         (u16)(details & ECORE_DORQ_ATTENTION_OPAQUE_MASK),
 438                         ((details & ECORE_DORQ_ATTENTION_SIZE_MASK) >>
 439                          ECORE_DORQ_ATTENTION_SIZE_SHIFT) * 4, reason);
 440         }
 441
 442         return ECORE_INVAL;
 443 }
 444
 445 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 446 {
 447 #ifndef ASIC_ONLY
 448         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 449                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 450                                    TM_REG_INT_STS_1);
 451
 452                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 453                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 454                         return ECORE_INVAL;
 455
 456                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 457                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 458                         DP_INFO(p_hwfn,
 459                                 "TM attention on emulation - most likely"
 460                                 " results of clock-ratios\n");
 461                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 462                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 463                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 464                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 465
 466                 return ECORE_SUCCESS;
 467         }
 468 #endif
 469
 470         return ECORE_INVAL;
 471 }
 472
 473 /* Instead of major changes to the data-structure, we have a some 'special'
 474  * identifiers for sources that changed meaning between adapters.
 475  */
 476 enum aeu_invert_reg_special_type {
 477         AEU_INVERT_REG_SPECIAL_CNIG_0,
 478         AEU_INVERT_REG_SPECIAL_CNIG_1,
 479         AEU_INVERT_REG_SPECIAL_CNIG_2,
 480         AEU_INVERT_REG_SPECIAL_CNIG_3,
 481         AEU_INVERT_REG_SPECIAL_MAX,
 482 };
 483
 484 static struct aeu_invert_reg_bit
 485 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 486         {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 487         {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 488         {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 489         {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 490 };
 491
 492 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 493 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 494         {
 495          {                      /* After Invert 1 */
 496           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 497            MAX_BLOCK_ID},
 498           }
 499          },
 500
 501         {
 502          {                      /* After Invert 2 */
 503           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 504           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 505           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,
 506            BLOCK_PGLUE_B},
 507           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 508           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 509           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 510           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 511           {"SW timers #%d",
 512            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 513            OSAL_NULL, MAX_BLOCK_ID},
 514           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 515            BLOCK_PGLCS},
 516           }
 517          },
 518
 519         {
 520          {                      /* After Invert 3 */
 521           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 522            MAX_BLOCK_ID},
 523           }
 524          },
 525
 526         {
 527          {                      /* After Invert 4 */
 528           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 529            ecore_fw_assertion, MAX_BLOCK_ID},
 530           {"General Attention %d",
 531            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 532            OSAL_NULL, MAX_BLOCK_ID},
 533           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 534            ecore_general_attention_35, MAX_BLOCK_ID},
 535           {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 536                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
 537                          OSAL_NULL, BLOCK_NWS},
 538           {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 539                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
 540                             OSAL_NULL, BLOCK_NWS},
 541           {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 542                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
 543                          OSAL_NULL, BLOCK_NWM},
 544           {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 545                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
 546                             OSAL_NULL, BLOCK_NWM},
 547           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 548           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 549           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 550           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 551           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 552           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 553           {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 554            MAX_BLOCK_ID},
 555           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 556           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 557           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 558           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 559           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 560           }
 561          },
 562
 563         {
 564          {                      /* After Invert 5 */
 565           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 566           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 567           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 568           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 569           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 570           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 571           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 572           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 573           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 574           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 575           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 576           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 577           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 578           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 579           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 580           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 581           }
 582          },
 583
 584         {
 585          {                      /* After Invert 6 */
 586           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 587           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 588           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 589           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 590           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 591           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 592           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 593           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 594           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 595           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 596           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 597           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 598           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 599           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 600           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 601           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 602           }
 603          },
 604
 605         {
 606          {                      /* After Invert 7 */
 607           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 608           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 609           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 610           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 611           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 612           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 613           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 614           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 615           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 616           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 617           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 618           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 619           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 620           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 621           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 622           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 623           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 624           }
 625          },
 626
 627         {
 628          {                      /* After Invert 8 */
 629           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 630           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 631           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 632           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 633           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 634           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 635           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 636           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 637           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 638           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 639           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 640           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 641           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 642           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 643           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 644           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 645           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 646           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 647           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 648           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 649           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 650            MAX_BLOCK_ID},
 651           }
 652          },
 653
 654         {
 655          {                      /* After Invert 9 */
 656           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 657           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 658            MAX_BLOCK_ID},
 659           {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 660           {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 661           {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 662            MAX_BLOCK_ID},
 663           }
 664          },
 665
 666 };
 667
 668 static struct aeu_invert_reg_bit *
 669 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
 670                         struct aeu_invert_reg_bit *p_bit)
 671 {
 672         if (!ECORE_IS_BB(p_hwfn->p_dev))
 673                 return p_bit;
 674
 675         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 676                 return p_bit;
 677
 678         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 679                                   ATTENTION_BB_SHIFT];
 680 }
 681
 682 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
 683                                      struct aeu_invert_reg_bit *p_bit)
 684 {
 685         return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
 686                   ATTENTION_PARITY);
 687 }
 688
 689 #define ATTN_STATE_BITS         (0xfff)
 690 #define ATTN_BITS_MASKABLE      (0x3ff)
 691 struct ecore_sb_attn_info {
 692         /* Virtual & Physical address of the SB */
 693         struct atten_status_block *sb_attn;
 694         dma_addr_t sb_phys;
 695
 696         /* Last seen running index */
 697         u16 index;
 698
 699         /* A mask of the AEU bits resulting in a parity error */
 700         u32 parity_mask[NUM_ATTN_REGS];
 701
 702         /* A pointer to the attention description structure */
 703         struct aeu_invert_reg *p_aeu_desc;
 704
 705         /* Previously asserted attentions, which are still unasserted */
 706         u16 known_attn;
 707
 708         /* Cleanup address for the link's general hw attention */
 709         u32 mfw_attn_addr;
 710 };
 711
 712 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 713                                  struct ecore_sb_attn_info *p_sb_desc)
 714 {
 715         u16 rc = 0, index;
 716
 717         OSAL_MMIOWB(p_hwfn->p_dev);
 718
 719         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 720         if (p_sb_desc->index != index) {
 721                 p_sb_desc->index = index;
 722                 rc = ECORE_SB_ATT_IDX;
 723         }
 724
 725         OSAL_MMIOWB(p_hwfn->p_dev);
 726
 727         return rc;
 728 }
 729
 730 /**
 731  * @brief ecore_int_assertion - handles asserted attention bits
 732  *
 733  * @param p_hwfn
 734  * @param asserted_bits newly asserted bits
 735  * @return enum _ecore_status_t
 736  */
 737 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 738                                                 u16 asserted_bits)
 739 {
 740         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 741         u32 igu_mask;
 742
 743         /* Mask the source of the attention in the IGU */
 744         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 745                             IGU_REG_ATTENTION_ENABLE);
 746         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 747                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 748         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 749         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 750
 751         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 752                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 753                    sb_attn_sw->known_attn,
 754                    sb_attn_sw->known_attn | asserted_bits);
 755         sb_attn_sw->known_attn |= asserted_bits;
 756
 757         /* Handle MCP events */
 758         if (asserted_bits & 0x100) {
 759                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 760                 /* Clean the MCP attention */
 761                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 762                          sb_attn_sw->mfw_attn_addr, 0);
 763         }
 764
 765         /* FIXME - this will change once we'll have GOOD gtt definitions */
 766         DIRECT_REG_WR(p_hwfn,
 767                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 768                       GTT_BAR0_MAP_REG_IGU_CMD +
 769                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 770                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 771
 772         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 773                    asserted_bits);
 774
 775         return ECORE_SUCCESS;
 776 }
 777
 778 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 779                                  enum block_id id, enum dbg_attn_type type,
 780                                  bool b_clear)
 781 {
 782         /* @DPDK */
 783         DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
 784 }
 785
 786 /**
 787  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 788  * cause of the attention
 789  *
 790  * @param p_hwfn
 791  * @param p_aeu - descriptor of an AEU bit which caused the attention
 792  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 793  *  this bit to this group.
 794  * @param bit_index - index of this bit in the aeu_en_reg
 795  *
 796  * @return enum _ecore_status_t
 797  */
 798 static enum _ecore_status_t
 799 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 800                               struct aeu_invert_reg_bit *p_aeu,
 801                               u32 aeu_en_reg,
 802                               const char *p_bit_name,
 803                               u32 bitmask)
 804 {
 805         enum _ecore_status_t rc = ECORE_INVAL;
 806         bool b_fatal = false;
 807
 808         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 809                 p_bit_name, bitmask);
 810
 811         /* Call callback before clearing the interrupt status */
 812         if (p_aeu->cb) {
 813                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 814                         p_bit_name);
 815                 rc = p_aeu->cb(p_hwfn);
 816         }
 817
 818         if (rc != ECORE_SUCCESS)
 819                 b_fatal = true;
 820
 821         /* Print HW block interrupt registers */
 822         if (p_aeu->block_index != MAX_BLOCK_ID) {
 823                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 824                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 825 }
 826
 827         /* @DPDK */
 828         /* Reach assertion if attention is fatal */
 829         if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) {
 830                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 831                           p_bit_name);
 832
 833                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 834         }
 835
 836         /* Prevent this Attention from being asserted in the future */
 837         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 838             p_hwfn->p_dev->attn_clr_en) {
 839                 u32 val;
 840                 u32 mask = ~bitmask;
 841                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 842                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 843                 DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
 844                         p_bit_name);
 845         }
 846
 847         return rc;
 848 }
 849
 850 /**
 851  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 852  *
 853  * @param p_hwfn
 854  * @param p_aeu - descriptor of an AEU bit which caused the parity
 855  * @param aeu_en_reg - address of the AEU enable register
 856  * @param bit_index
 857  */
 858 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 859                                          struct aeu_invert_reg_bit *p_aeu,
 860                                          u32 aeu_en_reg, u8 bit_index)
 861 {
 862         u32 block_id = p_aeu->block_index, mask, val;
 863
 864         DP_NOTICE(p_hwfn->p_dev, false,
 865                   "%s parity attention is set [address 0x%08x, bit %d]\n",
 866                   p_aeu->bit_name, aeu_en_reg, bit_index);
 867
 868         if (block_id != MAX_BLOCK_ID) {
 869                 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
 870
 871                 /* In A0, there's a single parity bit for several blocks */
 872                 if (block_id == BLOCK_BTB) {
 873                         ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
 874                                              ATTN_TYPE_PARITY, false);
 875                         ecore_int_attn_print(p_hwfn, BLOCK_MCP,
 876                                              ATTN_TYPE_PARITY, false);
 877                 }
 878         }
 879
 880         /* Prevent this parity error from being re-asserted */
 881         mask = ~(0x1 << bit_index);
 882         val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 883         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
 884         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
 885                 p_aeu->bit_name);
 886 }
 887
 888 /**
 889  * @brief - handles deassertion of previously asserted attentions.
 890  *
 891  * @param p_hwfn
 892  * @param deasserted_bits - newly deasserted bits
 893  * @return enum _ecore_status_t
 894  *
 895  */
 896 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
 897                                                   u16 deasserted_bits)
 898 {
 899         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 900         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
 901         u8 i, j, k, bit_idx;
 902         enum _ecore_status_t rc = ECORE_SUCCESS;
 903
 904         /* Read the attention registers in the AEU */
 905         for (i = 0; i < NUM_ATTN_REGS; i++) {
 906                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 907                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
 908                                           i * 0x4);
 909                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 910                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
 911         }
 912
 913         /* Handle parity attentions first */
 914         for (i = 0; i < NUM_ATTN_REGS; i++) {
 915                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
 916                 u32 parities;
 917
 918                 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
 919                 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
 920                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
 921
 922                 /* Skip register in which no parity bit is currently set */
 923                 if (!parities)
 924                         continue;
 925
 926                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 927                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
 928
 929                         if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
 930                             !!(parities & (1 << bit_idx)))
 931                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
 932                                                              aeu_en, bit_idx);
 933
 934                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
 935                 }
 936         }
 937
 938         /* Find non-parity cause for attention and act */
 939         for (k = 0; k < MAX_ATTN_GRPS; k++) {
 940                 struct aeu_invert_reg_bit *p_aeu;
 941
 942                 /* Handle only groups whose attention is currently deasserted */
 943                 if (!(deasserted_bits & (1 << k)))
 944                         continue;
 945
 946                 for (i = 0; i < NUM_ATTN_REGS; i++) {
 947                         u32 bits;
 948
 949                         aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
 950                                  i * sizeof(u32) +
 951                                  k * sizeof(u32) * NUM_ATTN_REGS;
 952                         en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
 953                         bits = aeu_inv_arr[i] & en;
 954
 955                         /* Skip if no bit from this group is currently set */
 956                         if (!bits)
 957                                 continue;
 958
 959                         /* Find all set bits from current register which belong
 960                          * to current group, making them responsible for the
 961                          * previous assertion.
 962                          */
 963                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 964                                 unsigned long int bitmask;
 965                                 u8 bit, bit_len;
 966
 967                                 /* Need to account bits with changed meaning */
 968                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
 969
 970                                 bit = bit_idx;
 971                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
 972                                 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
 973                                         /* Skip Parity */
 974                                         bit++;
 975                                         bit_len--;
 976                                 }
 977
 978                                 /* Find the bits relating to HW-block, then
 979                                  * shift so they'll become LSB.
 980                                  */
 981                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
 982                                 bitmask >>= bit;
 983
 984                                 if (bitmask) {
 985                                         u32 flags = p_aeu->flags;
 986                                         char bit_name[30];
 987                                         u8 num;
 988
 989                                         num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
 990                                                                 bit_len);
 991
 992                                         /* Some bits represent more than a
 993                                          * a single interrupt. Correctly print
 994                                          * their name.
 995                                          */
 996                                         if (ATTENTION_LENGTH(flags) > 2 ||
 997                                             ((flags & ATTENTION_PAR_INT) &&
 998                                             ATTENTION_LENGTH(flags) > 1))
 999                                                 OSAL_SNPRINTF(bit_name, 30,
1000                                                               p_aeu->bit_name,
1001                                                               num);
1002                                         else
1003                                                 OSAL_STRNCPY(bit_name,
1004                                                              p_aeu->bit_name,
1005                                                              30);
1006
1007                                         /* We now need to pass bitmask in its
1008                                          * correct position.
1009                                          */
1010                                         bitmask <<= bit;
1011
1012                                         /* Handle source of the attention */
1013                                         ecore_int_deassertion_aeu_bit(p_hwfn,
1014                                                                       p_aeu,
1015                                                                       aeu_en,
1016                                                                       bit_name,
1017                                                                       bitmask);
1018                                 }
1019
1020                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1021                         }
1022                 }
1023         }
1024
1025         /* Clear IGU indication for the deasserted bits */
1026         /* FIXME - this will change once we'll have GOOD gtt definitions */
1027         DIRECT_REG_WR(p_hwfn,
1028                       (u8 OSAL_IOMEM *) p_hwfn->regview +
1029                       GTT_BAR0_MAP_REG_IGU_CMD +
1030                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1031                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1032
1033         /* Unmask deasserted attentions in IGU */
1034         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1035                             IGU_REG_ATTENTION_ENABLE);
1036         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1037         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1038
1039         /* Clear deassertion from inner state */
1040         sb_attn_sw->known_attn &= ~deasserted_bits;
1041
1042         return rc;
1043 }
1044
1045 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1046 {
1047         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1048         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1049         u16 index = 0, asserted_bits, deasserted_bits;
1050         u32 attn_bits = 0, attn_acks = 0;
1051         enum _ecore_status_t rc = ECORE_SUCCESS;
1052
1053         /* Read current attention bits/acks - safeguard against attentions
1054          * by guaranting work on a synchronized timeframe
1055          */
1056         do {
1057                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1058                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1059                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1060         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1061         p_sb_attn->sb_index = index;
1062
1063         /* Attention / Deassertion are meaningful (and in correct state)
1064          * only when they differ and consistent with known state - deassertion
1065          * when previous attention & current ack, and assertion when current
1066          * attention with no previous attention
1067          */
1068         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1069             ~p_sb_attn_sw->known_attn;
1070         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1071             p_sb_attn_sw->known_attn;
1072
1073         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1074                 DP_INFO(p_hwfn,
1075                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1076                         index, attn_bits, attn_acks, asserted_bits,
1077                         deasserted_bits, p_sb_attn_sw->known_attn);
1078         else if (asserted_bits == 0x100)
1079                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1080         else
1081                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1082                            "MFW indication [deassertion]\n");
1083
1084         if (asserted_bits) {
1085                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1086                 if (rc)
1087                         return rc;
1088         }
1089
1090         if (deasserted_bits)
1091                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1092
1093         return rc;
1094 }
1095
1096 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1097                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1098 {
1099         struct igu_prod_cons_update igu_ack = { 0 };
1100
1101         igu_ack.sb_id_and_flags =
1102             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1103              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1104              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1105              (IGU_SEG_ACCESS_ATTN <<
1106               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1107
1108         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1109
1110         /* Both segments (interrupts & acks) are written to same place address;
1111          * Need to guarantee all commands will be received (in-order) by HW.
1112          */
1113         OSAL_MMIOWB(p_hwfn->p_dev);
1114         OSAL_BARRIER(p_hwfn->p_dev);
1115 }
1116
1117 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1118 {
1119         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1120         struct ecore_pi_info *pi_info = OSAL_NULL;
1121         struct ecore_sb_attn_info *sb_attn;
1122         struct ecore_sb_info *sb_info;
1123         int arr_size;
1124         u16 rc = 0;
1125
1126         if (!p_hwfn)
1127                 return;
1128
1129         if (!p_hwfn->p_sp_sb) {
1130                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1131                 return;
1132         }
1133
1134         sb_info = &p_hwfn->p_sp_sb->sb_info;
1135         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1136         if (!sb_info) {
1137                 DP_ERR(p_hwfn->p_dev,
1138                        "Status block is NULL - cannot ack interrupts\n");
1139                 return;
1140         }
1141
1142         if (!p_hwfn->p_sb_attn) {
1143                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1144                 return;
1145         }
1146         sb_attn = p_hwfn->p_sb_attn;
1147
1148         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1149                    p_hwfn, p_hwfn->my_id);
1150
1151         /* Disable ack for def status block. Required both for msix +
1152          * inta in non-mask mode, in inta does no harm.
1153          */
1154         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1155
1156         /* Gather Interrupts/Attentions information */
1157         if (!sb_info->sb_virt) {
1158                 DP_ERR(p_hwfn->p_dev,
1159                        "Interrupt Status block is NULL -"
1160                        " cannot check for new interrupts!\n");
1161         } else {
1162                 u32 tmp_index = sb_info->sb_ack;
1163                 rc = ecore_sb_update_sb_idx(sb_info);
1164                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1165                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1166                            tmp_index, sb_info->sb_ack);
1167         }
1168
1169         if (!sb_attn || !sb_attn->sb_attn) {
1170                 DP_ERR(p_hwfn->p_dev,
1171                        "Attentions Status block is NULL -"
1172                        " cannot check for new attentions!\n");
1173         } else {
1174                 u16 tmp_index = sb_attn->index;
1175
1176                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1177                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1178                            "Attention indices: 0x%08x --> 0x%08x\n",
1179                            tmp_index, sb_attn->index);
1180         }
1181
1182         /* Check if we expect interrupts at this time. if not just ack them */
1183         if (!(rc & ECORE_SB_EVENT_MASK)) {
1184                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1185                 return;
1186         }
1187
1188 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1189
1190         if (!p_hwfn->p_dpc_ptt) {
1191                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1192                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1193                 return;
1194         }
1195
1196         if (rc & ECORE_SB_ATT_IDX)
1197                 ecore_int_attentions(p_hwfn);
1198
1199         if (rc & ECORE_SB_IDX) {
1200                 int pi;
1201
1202                 /* Since we only looked at the SB index, it's possible more
1203                  * than a single protocol-index on the SB incremented.
1204                  * Iterate over all configured protocol indices and check
1205                  * whether something happened for each.
1206                  */
1207                 for (pi = 0; pi < arr_size; pi++) {
1208                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1209                         if (pi_info->comp_cb != OSAL_NULL)
1210                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1211                 }
1212         }
1213
1214         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1215                 /* This should be done before the interrupts are enabled,
1216                  * since otherwise a new attention will be generated.
1217                  */
1218                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1219         }
1220
1221         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1222 }
1223
1224 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1225 {
1226         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1227
1228         if (!p_sb)
1229                 return;
1230
1231         if (p_sb->sb_attn) {
1232                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1233                                        p_sb->sb_phys,
1234                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1235         }
1236         OSAL_FREE(p_hwfn->p_dev, p_sb);
1237 }
1238
1239 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1240                                     struct ecore_ptt *p_ptt)
1241 {
1242         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1243
1244         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1245
1246         sb_info->index = 0;
1247         sb_info->known_attn = 0;
1248
1249         /* Configure Attention Status Block in IGU */
1250         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1251                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1252         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1253                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1254 }
1255
1256 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1257                                    struct ecore_ptt *p_ptt,
1258                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1259 {
1260         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1261         int i, j, k;
1262
1263         sb_info->sb_attn = sb_virt_addr;
1264         sb_info->sb_phys = sb_phy_addr;
1265
1266         /* Set the pointer to the AEU descriptors */
1267         sb_info->p_aeu_desc = aeu_descs;
1268
1269         /* Calculate Parity Masks */
1270         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1271         for (i = 0; i < NUM_ATTN_REGS; i++) {
1272                 /* j is array index, k is bit index */
1273                 for (j = 0, k = 0; k < 32; j++) {
1274                         struct aeu_invert_reg_bit *p_aeu;
1275
1276                         p_aeu = &aeu_descs[i].bits[j];
1277                         if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1278                                 sb_info->parity_mask[i] |= 1 << k;
1279
1280                         k += ATTENTION_LENGTH(p_aeu->flags);
1281                 }
1282                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1283                            "Attn Mask [Reg %d]: 0x%08x\n",
1284                            i, sb_info->parity_mask[i]);
1285         }
1286
1287         /* Set the address of cleanup for the mcp attention */
1288         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1289             MISC_REG_AEU_GENERAL_ATTN_0;
1290
1291         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1292 }
1293
1294 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1295                                                     struct ecore_ptt *p_ptt)
1296 {
1297         struct ecore_dev *p_dev = p_hwfn->p_dev;
1298         struct ecore_sb_attn_info *p_sb;
1299         dma_addr_t p_phys = 0;
1300         void *p_virt;
1301
1302         /* SB struct */
1303         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1304         if (!p_sb) {
1305                 DP_NOTICE(p_dev, true,
1306                           "Failed to allocate `struct ecore_sb_attn_info'\n");
1307                 return ECORE_NOMEM;
1308         }
1309
1310         /* SB ring  */
1311         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1312                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1313         if (!p_virt) {
1314                 DP_NOTICE(p_dev, true,
1315                           "Failed to allocate status block (attentions)\n");
1316                 OSAL_FREE(p_dev, p_sb);
1317                 return ECORE_NOMEM;
1318         }
1319
1320         /* Attention setup */
1321         p_hwfn->p_sb_attn = p_sb;
1322         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1323
1324         return ECORE_SUCCESS;
1325 }
1326
1327 /* coalescing timeout = timeset << (timer_res + 1) */
1328 #define ECORE_CAU_DEF_RX_USECS 24
1329 #define ECORE_CAU_DEF_TX_USECS 48
1330
1331 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1332                              struct cau_sb_entry *p_sb_entry,
1333                              u8 pf_id, u16 vf_number, u8 vf_valid)
1334 {
1335         struct ecore_dev *p_dev = p_hwfn->p_dev;
1336         u32 cau_state;
1337         u8 timer_res;
1338
1339         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1340
1341         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1342         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1343         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1344         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1345         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1346
1347         cau_state = CAU_HC_DISABLE_STATE;
1348
1349         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1350                 cau_state = CAU_HC_ENABLE_STATE;
1351                 if (!p_dev->rx_coalesce_usecs)
1352                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1353                 if (!p_dev->tx_coalesce_usecs)
1354                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1355         }
1356
1357         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1358         if (p_dev->rx_coalesce_usecs <= 0x7F)
1359                 timer_res = 0;
1360         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1361                 timer_res = 1;
1362         else
1363                 timer_res = 2;
1364         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1365
1366         if (p_dev->tx_coalesce_usecs <= 0x7F)
1367                 timer_res = 0;
1368         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1369                 timer_res = 1;
1370         else
1371                 timer_res = 2;
1372         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1373
1374         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1375         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1376 }
1377
1378 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1379                                    struct ecore_ptt *p_ptt,
1380                                    u16 igu_sb_id, u32 pi_index,
1381                                    enum ecore_coalescing_fsm coalescing_fsm,
1382                                    u8 timeset)
1383 {
1384         struct cau_pi_entry pi_entry;
1385         u32 sb_offset, pi_offset;
1386
1387         if (IS_VF(p_hwfn->p_dev))
1388                 return;/* @@@TBD MichalK- VF CAU... */
1389
1390         sb_offset = igu_sb_id * PIS_PER_SB;
1391         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1392
1393         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1394         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1395                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1396         else
1397                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1398
1399         pi_offset = sb_offset + pi_index;
1400         if (p_hwfn->hw_init_done) {
1401                 ecore_wr(p_hwfn, p_ptt,
1402                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1403                          *((u32 *)&(pi_entry)));
1404         } else {
1405                 STORE_RT_REG(p_hwfn,
1406                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1407                              *((u32 *)&(pi_entry)));
1408         }
1409 }
1410
1411 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1412                            struct ecore_ptt *p_ptt,
1413                            struct ecore_sb_info *p_sb, u32 pi_index,
1414                            enum ecore_coalescing_fsm coalescing_fsm,
1415                            u8 timeset)
1416 {
1417         _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1418                                pi_index, coalescing_fsm, timeset);
1419 }
1420
1421 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1422                            struct ecore_ptt *p_ptt,
1423                            dma_addr_t sb_phys, u16 igu_sb_id,
1424                            u16 vf_number, u8 vf_valid)
1425 {
1426         struct cau_sb_entry sb_entry;
1427
1428         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1429                                 vf_number, vf_valid);
1430
1431         if (p_hwfn->hw_init_done) {
1432                 /* Wide-bus, initialize via DMAE */
1433                 u64 phys_addr = (u64)sb_phys;
1434
1435                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1436                                     (u64)(osal_uintptr_t)&phys_addr,
1437                                     CAU_REG_SB_ADDR_MEMORY +
1438                                     igu_sb_id * sizeof(u64), 2, 0);
1439                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1440                                     (u64)(osal_uintptr_t)&sb_entry,
1441                                     CAU_REG_SB_VAR_MEMORY +
1442                                     igu_sb_id * sizeof(u64), 2, 0);
1443         } else {
1444                 /* Initialize Status Block Address */
1445                 STORE_RT_REG_AGG(p_hwfn,
1446                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1447                                  igu_sb_id * 2, sb_phys);
1448
1449                 STORE_RT_REG_AGG(p_hwfn,
1450                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1451                                  igu_sb_id * 2, sb_entry);
1452         }
1453
1454         /* Configure pi coalescing if set */
1455         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1456                 /* eth will open queues for all tcs, so configure all of them
1457                  * properly, rather than just the active ones
1458                  */
1459                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1460
1461                 u8 timeset, timer_res;
1462                 u8 i;
1463
1464                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1465                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1466                         timer_res = 0;
1467                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1468                         timer_res = 1;
1469                 else
1470                         timer_res = 2;
1471                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1472                 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1473                                        ECORE_COAL_RX_STATE_MACHINE,
1474                                        timeset);
1475
1476                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1477                         timer_res = 0;
1478                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1479                         timer_res = 1;
1480                 else
1481                         timer_res = 2;
1482                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1483                 for (i = 0; i < num_tc; i++) {
1484                         _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1485                                                igu_sb_id, TX_PI(i),
1486                                                ECORE_COAL_TX_STATE_MACHINE,
1487                                                timeset);
1488                 }
1489         }
1490 }
1491
1492 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1493                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1494 {
1495         /* zero status block and ack counter */
1496         sb_info->sb_ack = 0;
1497         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1498
1499         if (IS_PF(p_hwfn->p_dev))
1500                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1501                                       sb_info->igu_sb_id, 0, 0);
1502 }
1503
1504 struct ecore_igu_block *
1505 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1506 {
1507         struct ecore_igu_block *p_block;
1508         u16 igu_id;
1509
1510         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1511              igu_id++) {
1512                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1513
1514                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1515                     !(p_block->status & ECORE_IGU_STATUS_FREE))
1516                         continue;
1517
1518                 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1519                     b_is_pf)
1520                         return p_block;
1521         }
1522
1523         return OSAL_NULL;
1524 }
1525
1526 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1527                                   u16 vector_id)
1528 {
1529         struct ecore_igu_block *p_block;
1530         u16 igu_id;
1531
1532         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1533              igu_id++) {
1534                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1535
1536                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1537                     !p_block->is_pf ||
1538                     p_block->vector_number != vector_id)
1539                         continue;
1540
1541                 return igu_id;
1542         }
1543
1544         return ECORE_SB_INVALID_IDX;
1545 }
1546
1547 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1548 {
1549         u16 igu_sb_id;
1550
1551         /* Assuming continuous set of IGU SBs dedicated for given PF */
1552         if (sb_id == ECORE_SP_SB_ID)
1553                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1554         else if (IS_PF(p_hwfn->p_dev))
1555                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1556         else
1557                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1558
1559         if (igu_sb_id == ECORE_SB_INVALID_IDX)
1560                 DP_NOTICE(p_hwfn, true,
1561                           "Slowpath SB vector %04x doesn't exist\n",
1562                           sb_id);
1563         else if (sb_id == ECORE_SP_SB_ID)
1564                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1565                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1566         else
1567                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1568                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1569
1570         return igu_sb_id;
1571 }
1572
1573 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1574                                        struct ecore_ptt *p_ptt,
1575                                        struct ecore_sb_info *sb_info,
1576                                        void *sb_virt_addr,
1577                                        dma_addr_t sb_phy_addr, u16 sb_id)
1578 {
1579         sb_info->sb_virt = sb_virt_addr;
1580         sb_info->sb_phys = sb_phy_addr;
1581
1582         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1583
1584         if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1585                 return ECORE_INVAL;
1586
1587         /* Let the igu info reference the client's SB info */
1588         if (sb_id != ECORE_SP_SB_ID) {
1589                 if (IS_PF(p_hwfn->p_dev)) {
1590                         struct ecore_igu_info *p_info;
1591                         struct ecore_igu_block *p_block;
1592
1593                         p_info = p_hwfn->hw_info.p_igu_info;
1594                         p_block = &p_info->entry[sb_info->igu_sb_id];
1595
1596                         p_block->sb_info = sb_info;
1597                         p_block->status &= ~ECORE_IGU_STATUS_FREE;
1598                         p_info->usage.free_cnt--;
1599                 } else {
1600                         ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1601                 }
1602         }
1603 #ifdef ECORE_CONFIG_DIRECT_HWFN
1604         sb_info->p_hwfn = p_hwfn;
1605 #endif
1606         sb_info->p_dev = p_hwfn->p_dev;
1607
1608         /* The igu address will hold the absolute address that needs to be
1609          * written to for a specific status block
1610          */
1611         if (IS_PF(p_hwfn->p_dev)) {
1612                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1613                     GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1614
1615         } else {
1616                 sb_info->igu_addr =
1617                     (u8 OSAL_IOMEM *)p_hwfn->regview +
1618                     PXP_VF_BAR0_START_IGU +
1619                     ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1620         }
1621
1622         sb_info->flags |= ECORE_SB_INFO_INIT;
1623
1624         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1625
1626         return ECORE_SUCCESS;
1627 }
1628
1629 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1630                                           struct ecore_sb_info *sb_info,
1631                                           u16 sb_id)
1632 {
1633         struct ecore_igu_info *p_info;
1634         struct ecore_igu_block *p_block;
1635
1636         if (sb_info == OSAL_NULL)
1637                 return ECORE_SUCCESS;
1638
1639         /* zero status block and ack counter */
1640         sb_info->sb_ack = 0;
1641         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1642
1643         if (IS_VF(p_hwfn->p_dev)) {
1644                 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1645                 return ECORE_SUCCESS;
1646         }
1647
1648         p_info = p_hwfn->hw_info.p_igu_info;
1649         p_block = &p_info->entry[sb_info->igu_sb_id];
1650
1651         /* Vector 0 is reserved to Default SB */
1652         if (p_block->vector_number == 0) {
1653                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1654                 return ECORE_INVAL;
1655         }
1656
1657         /* Lose reference to client's SB info, and fix counters */
1658         p_block->sb_info = OSAL_NULL;
1659         p_block->status |= ECORE_IGU_STATUS_FREE;
1660         p_info->usage.free_cnt++;
1661
1662         return ECORE_SUCCESS;
1663 }
1664
1665 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1666 {
1667         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1668
1669         if (!p_sb)
1670                 return;
1671
1672         if (p_sb->sb_info.sb_virt) {
1673                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1674                                        p_sb->sb_info.sb_virt,
1675                                        p_sb->sb_info.sb_phys,
1676                                        SB_ALIGNED_SIZE(p_hwfn));
1677         }
1678
1679         OSAL_FREE(p_hwfn->p_dev, p_sb);
1680 }
1681
1682 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1683                                                   struct ecore_ptt *p_ptt)
1684 {
1685         struct ecore_sb_sp_info *p_sb;
1686         dma_addr_t p_phys = 0;
1687         void *p_virt;
1688
1689         /* SB struct */
1690         p_sb =
1691             OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1692                        sizeof(*p_sb));
1693         if (!p_sb) {
1694                 DP_NOTICE(p_hwfn, true,
1695                           "Failed to allocate `struct ecore_sb_info'\n");
1696                 return ECORE_NOMEM;
1697         }
1698
1699         /* SB ring  */
1700         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1701                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1702         if (!p_virt) {
1703                 DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
1704                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1705                 return ECORE_NOMEM;
1706         }
1707
1708         /* Status Block setup */
1709         p_hwfn->p_sp_sb = p_sb;
1710         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1711                           p_virt, p_phys, ECORE_SP_SB_ID);
1712
1713         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1714
1715         return ECORE_SUCCESS;
1716 }
1717
1718 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1719                                            ecore_int_comp_cb_t comp_cb,
1720                                            void *cookie,
1721                                            u8 *sb_idx, __le16 **p_fw_cons)
1722 {
1723         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1724         enum _ecore_status_t rc = ECORE_NOMEM;
1725         u8 pi;
1726
1727         /* Look for a free index */
1728         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1729                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1730                         continue;
1731
1732                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1733                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1734                 *sb_idx = pi;
1735                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1736                 rc = ECORE_SUCCESS;
1737                 break;
1738         }
1739
1740         return rc;
1741 }
1742
1743 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1744 {
1745         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1746
1747         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1748                 return ECORE_NOMEM;
1749
1750         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1751         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1752         return ECORE_SUCCESS;
1753 }
1754
1755 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1756 {
1757         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1758 }
1759
1760 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1761                               struct ecore_ptt *p_ptt,
1762                               enum ecore_int_mode int_mode)
1763 {
1764         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1765
1766 #ifndef ASIC_ONLY
1767         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1768                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1769                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1770         }
1771 #endif
1772
1773         p_hwfn->p_dev->int_mode = int_mode;
1774         switch (p_hwfn->p_dev->int_mode) {
1775         case ECORE_INT_MODE_INTA:
1776                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1777                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1778                 break;
1779
1780         case ECORE_INT_MODE_MSI:
1781                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1782                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1783                 break;
1784
1785         case ECORE_INT_MODE_MSIX:
1786                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1787                 break;
1788         case ECORE_INT_MODE_POLL:
1789                 break;
1790         }
1791
1792         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1793 }
1794
1795 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1796                                       struct ecore_ptt *p_ptt)
1797 {
1798 #ifndef ASIC_ONLY
1799         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1800                 DP_INFO(p_hwfn,
1801                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1802                 return;
1803         }
1804 #endif
1805
1806         /* Configure AEU signal change to produce attentions */
1807         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1808         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1809         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1810         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1811
1812         /* Flush the writes to IGU */
1813         OSAL_MMIOWB(p_hwfn->p_dev);
1814
1815         /* Unmask AEU signals toward IGU */
1816         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1817 }
1818
1819 enum _ecore_status_t
1820 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1821                           enum ecore_int_mode int_mode)
1822 {
1823         enum _ecore_status_t rc = ECORE_SUCCESS;
1824         u32 tmp;
1825
1826         /* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
1827          * attentions. Since we're waiting for BRCM answer regarding this
1828          * attention, in the meanwhile we simply mask it.
1829          */
1830         tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
1831         tmp &= ~0x800;
1832         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
1833
1834         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1835
1836         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1837                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1838                 if (rc != ECORE_SUCCESS) {
1839                         DP_NOTICE(p_hwfn, true,
1840                                   "Slowpath IRQ request failed\n");
1841                         return ECORE_NORESOURCES;
1842                 }
1843                 p_hwfn->b_int_requested = true;
1844         }
1845
1846         /* Enable interrupt Generation */
1847         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1848
1849         p_hwfn->b_int_enabled = 1;
1850
1851         return rc;
1852 }
1853
1854 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1855                                struct ecore_ptt *p_ptt)
1856 {
1857         p_hwfn->b_int_enabled = 0;
1858
1859         if (IS_VF(p_hwfn->p_dev))
1860                 return;
1861
1862         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1863 }
1864
1865 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1866 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1867                                      struct ecore_ptt *p_ptt,
1868                                      u32 igu_sb_id,
1869                                      bool cleanup_set,
1870                                      u16 opaque_fid)
1871 {
1872         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1873         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1874         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1875         u8 type = 0;            /* FIXME MichalS type??? */
1876
1877         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1878                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1879
1880         /* USE Control Command Register to perform cleanup. There is an
1881          * option to do this using IGU bar, but then it can't be used for VFs.
1882          */
1883
1884         /* Set the data field */
1885         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1886         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1887         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1888
1889         /* Set the control register */
1890         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1891         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1892         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1893
1894         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1895
1896         OSAL_BARRIER(p_hwfn->p_dev);
1897
1898         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1899
1900         /* Flush the write to IGU */
1901         OSAL_MMIOWB(p_hwfn->p_dev);
1902
1903         /* calculate where to read the status bit from */
1904         sb_bit = 1 << (igu_sb_id % 32);
1905         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
1906
1907         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
1908
1909         /* Now wait for the command to complete */
1910         while (--sleep_cnt) {
1911                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
1912                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1913                         break;
1914                 OSAL_MSLEEP(5);
1915         }
1916
1917         if (!sleep_cnt)
1918                 DP_NOTICE(p_hwfn, true,
1919                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1920                           val, igu_sb_id);
1921 }
1922
1923 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
1924                                        struct ecore_ptt *p_ptt,
1925                                        u16 igu_sb_id, u16 opaque, bool b_set)
1926 {
1927         struct ecore_igu_block *p_block;
1928         int pi, i;
1929
1930         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
1931         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1932                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
1933                    igu_sb_id, p_block->function_id, p_block->is_pf,
1934                    p_block->vector_number);
1935
1936         /* Set */
1937         if (b_set)
1938                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
1939
1940         /* Clear */
1941         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
1942
1943         /* Wait for the IGU SB to cleanup */
1944         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1945                 u32 val;
1946
1947                 val = ecore_rd(p_hwfn, p_ptt,
1948                                IGU_REG_WRITE_DONE_PENDING +
1949                                ((igu_sb_id / 32) * 4));
1950                 if (val & (1 << (igu_sb_id % 32)))
1951                         OSAL_UDELAY(10);
1952                 else
1953                         break;
1954         }
1955         if (i == IGU_CLEANUP_SLEEP_LENGTH)
1956                 DP_NOTICE(p_hwfn, true,
1957                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1958                           igu_sb_id);
1959
1960         /* Clear the CAU for the SB */
1961         for (pi = 0; pi < 12; pi++)
1962                 ecore_wr(p_hwfn, p_ptt,
1963                          CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
1964 }
1965
1966 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
1967                                 struct ecore_ptt *p_ptt,
1968                                 bool b_set, bool b_slowpath)
1969 {
1970         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
1971         struct ecore_igu_block *p_block;
1972         u16 igu_sb_id = 0;
1973         u32 val = 0;
1974
1975         /* @@@TBD MichalK temporary... should be moved to init-tool... */
1976         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1977         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1978         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1979         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1980         /* end temporary */
1981
1982         for (igu_sb_id = 0;
1983              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1984              igu_sb_id++) {
1985                 p_block = &p_info->entry[igu_sb_id];
1986
1987                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1988                     !p_block->is_pf ||
1989                     (p_block->status & ECORE_IGU_STATUS_DSB))
1990                         continue;
1991
1992                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
1993                                                   p_hwfn->hw_info.opaque_fid,
1994                                                   b_set);
1995         }
1996
1997         if (b_slowpath)
1998                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
1999                                                   p_info->igu_dsb_id,
2000                                                   p_hwfn->hw_info.opaque_fid,
2001                                                   b_set);
2002 }
2003
2004 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2005                             struct ecore_ptt *p_ptt)
2006 {
2007         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2008         struct ecore_igu_block *p_block;
2009         int pf_sbs, vf_sbs;
2010         u16 igu_sb_id;
2011         u32 val, rval;
2012
2013         if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2014                 /* We're using an old MFW - have to prevent any switching
2015                  * of SBs between PF and VFs as later driver wouldn't be
2016                  * able to tell which belongs to which.
2017                  */
2018                 p_info->b_allow_pf_vf_change = false;
2019         } else {
2020                 /* Use the numbers the MFW have provided -
2021                  * don't forget MFW accounts for the default SB as well.
2022                  */
2023                 p_info->b_allow_pf_vf_change = true;
2024
2025                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2026                         DP_INFO(p_hwfn,
2027                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2028                                 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2029                                 p_info->usage.cnt);
2030                         p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2031                 }
2032
2033                 /* TODO - how do we learn about VF SBs from MFW? */
2034                 if (IS_PF_SRIOV(p_hwfn)) {
2035                         u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2036
2037                         if (vfs != p_info->usage.iov_cnt)
2038                                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2039                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2040                                            p_info->usage.iov_cnt, vfs);
2041
2042                         /* At this point we know how many SBs we have totally
2043                          * in IGU + number of PF SBs. So we can validate that
2044                          * we'd have sufficient for VF.
2045                          */
2046                         if (vfs > p_info->usage.free_cnt +
2047                                   p_info->usage.free_cnt_iov -
2048                                   p_info->usage.cnt) {
2049                                 DP_NOTICE(p_hwfn, true,
2050                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2051                                           p_info->usage.free_cnt +
2052                                           p_info->usage.free_cnt_iov,
2053                                           p_info->usage.cnt, vfs);
2054                                 return ECORE_INVAL;
2055                         }
2056                 }
2057         }
2058
2059         /* Cap the number of VFs SBs by the number of VFs */
2060         if (IS_PF_SRIOV(p_hwfn))
2061                 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2062
2063         /* Mark all SBs as free, now in the right PF/VFs division */
2064         p_info->usage.free_cnt = p_info->usage.cnt;
2065         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2066         p_info->usage.orig = p_info->usage.cnt;
2067         p_info->usage.iov_orig = p_info->usage.iov_cnt;
2068
2069         /* We now proceed to re-configure the IGU cam to reflect the initial
2070          * configuration. We can start with the Default SB.
2071          */
2072         pf_sbs = p_info->usage.cnt;
2073         vf_sbs = p_info->usage.iov_cnt;
2074
2075         for (igu_sb_id = p_info->igu_dsb_id;
2076              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2077              igu_sb_id++) {
2078                 p_block = &p_info->entry[igu_sb_id];
2079                 val = 0;
2080
2081                 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2082                         continue;
2083
2084                 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2085                         p_block->function_id = p_hwfn->rel_pf_id;
2086                         p_block->is_pf = 1;
2087                         p_block->vector_number = 0;
2088                         p_block->status = ECORE_IGU_STATUS_VALID |
2089                                           ECORE_IGU_STATUS_PF |
2090                                           ECORE_IGU_STATUS_DSB;
2091                 } else if (pf_sbs) {
2092                         pf_sbs--;
2093                         p_block->function_id = p_hwfn->rel_pf_id;
2094                         p_block->is_pf = 1;
2095                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
2096                         p_block->status = ECORE_IGU_STATUS_VALID |
2097                                           ECORE_IGU_STATUS_PF |
2098                                           ECORE_IGU_STATUS_FREE;
2099                 } else if (vf_sbs) {
2100                         p_block->function_id =
2101                                 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2102                                 p_info->usage.iov_cnt - vf_sbs;
2103                         p_block->is_pf = 0;
2104                         p_block->vector_number = 0;
2105                         p_block->status = ECORE_IGU_STATUS_VALID |
2106                                           ECORE_IGU_STATUS_FREE;
2107                         vf_sbs--;
2108                 } else {
2109                         p_block->function_id = 0;
2110                         p_block->is_pf = 0;
2111                         p_block->vector_number = 0;
2112                 }
2113
2114                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2115                           p_block->function_id);
2116                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2117                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2118                           p_block->vector_number);
2119
2120                 /* VF entries would be enabled when VF is initializaed */
2121                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2122
2123                 rval = ecore_rd(p_hwfn, p_ptt,
2124                                 IGU_REG_MAPPING_MEMORY +
2125                                 sizeof(u32) * igu_sb_id);
2126
2127                 if (rval != val) {
2128                         ecore_wr(p_hwfn, p_ptt,
2129                                  IGU_REG_MAPPING_MEMORY +
2130                                  sizeof(u32) * igu_sb_id,
2131                                  val);
2132
2133                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2134                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2135                                    igu_sb_id, p_block->function_id,
2136                                    p_block->is_pf, p_block->vector_number,
2137                                    rval, val);
2138                 }
2139         }
2140
2141         return 0;
2142 }
2143
2144 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2145                                     struct ecore_ptt *p_ptt)
2146 {
2147         struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2148
2149         /* Return all the usage indications to default prior to the reset;
2150          * The reset expects the !orig to reflect the initial status of the
2151          * SBs, and would re-calculate the originals based on those.
2152          */
2153         p_cnt->cnt = p_cnt->orig;
2154         p_cnt->free_cnt = p_cnt->orig;
2155         p_cnt->iov_cnt = p_cnt->iov_orig;
2156         p_cnt->free_cnt_iov = p_cnt->iov_orig;
2157         p_cnt->orig = 0;
2158         p_cnt->iov_orig = 0;
2159
2160         /* TODO - we probably need to re-configure the CAU as well... */
2161         return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2162 }
2163
2164 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2165                                          struct ecore_ptt *p_ptt,
2166                                          u16 igu_sb_id)
2167 {
2168         u32 val = ecore_rd(p_hwfn, p_ptt,
2169                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2170         struct ecore_igu_block *p_block;
2171
2172         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2173
2174         /* Fill the block information */
2175         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2176         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2177         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2178
2179         p_block->igu_sb_id = igu_sb_id;
2180 }
2181
2182 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2183                                             struct ecore_ptt *p_ptt)
2184 {
2185         struct ecore_igu_info *p_igu_info;
2186         struct ecore_igu_block *p_block;
2187         u32 min_vf = 0, max_vf = 0;
2188         u16 igu_sb_id;
2189
2190         p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2191                                                  GFP_KERNEL,
2192                                                  sizeof(*p_igu_info));
2193         if (!p_hwfn->hw_info.p_igu_info)
2194                 return ECORE_NOMEM;
2195         p_igu_info = p_hwfn->hw_info.p_igu_info;
2196
2197         /* Distinguish between existent and onn-existent default SB */
2198         p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2199
2200         /* Find the range of VF ids whose SB belong to this PF */
2201         if (p_hwfn->p_dev->p_iov_info) {
2202                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2203
2204                 min_vf = p_iov->first_vf_in_pf;
2205                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2206         }
2207
2208         for (igu_sb_id = 0;
2209              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2210              igu_sb_id++) {
2211                 /* Read current entry; Notice it might not belong to this PF */
2212                 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2213                 p_block = &p_igu_info->entry[igu_sb_id];
2214
2215                 if ((p_block->is_pf) &&
2216                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2217                         p_block->status = ECORE_IGU_STATUS_PF |
2218                                           ECORE_IGU_STATUS_VALID |
2219                                           ECORE_IGU_STATUS_FREE;
2220
2221                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2222                                 p_igu_info->usage.cnt++;
2223                 } else if (!(p_block->is_pf) &&
2224                            (p_block->function_id >= min_vf) &&
2225                            (p_block->function_id < max_vf)) {
2226                         /* Available for VFs of this PF */
2227                         p_block->status = ECORE_IGU_STATUS_VALID |
2228                                           ECORE_IGU_STATUS_FREE;
2229
2230                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2231                                 p_igu_info->usage.iov_cnt++;
2232                 }
2233
2234                 /* Mark the First entry belonging to the PF or its VFs
2235                  * as the default SB [we'll reset IGU prior to first usage].
2236                  */
2237                 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2238                     (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2239                         p_igu_info->igu_dsb_id = igu_sb_id;
2240                         p_block->status |= ECORE_IGU_STATUS_DSB;
2241                 }
2242
2243                 /* While this isn't suitable for all clients, limit number
2244                  * of prints by having each PF print only its entries with the
2245                  * exception of PF0 which would print everything.
2246                  */
2247                 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2248                     (p_hwfn->abs_pf_id == 0))
2249                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2250                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2251                                    igu_sb_id, p_block->function_id,
2252                                    p_block->is_pf, p_block->vector_number);
2253         }
2254
2255         if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2256                 DP_NOTICE(p_hwfn, true,
2257                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2258                           p_igu_info->igu_dsb_id);
2259                 return ECORE_INVAL;
2260         }
2261
2262         /* All non default SB are considered free at this point */
2263         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2264         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2265
2266         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2267                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2268                    p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2269                    p_igu_info->usage.iov_cnt);
2270
2271         return ECORE_SUCCESS;
2272 }
2273
2274 enum _ecore_status_t
2275 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2276                           u16 sb_id, bool b_to_vf)
2277 {
2278         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2279         struct ecore_igu_block *p_block = OSAL_NULL;
2280         u16 igu_sb_id = 0, vf_num = 0;
2281         u32 val = 0;
2282
2283         if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2284                 return ECORE_INVAL;
2285
2286         if (sb_id == ECORE_SP_SB_ID)
2287                 return ECORE_INVAL;
2288
2289         if (!p_info->b_allow_pf_vf_change) {
2290                 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2291                 return ECORE_INVAL;
2292         }
2293
2294         /* If we're moving a SB from PF to VF, the client had to specify
2295          * which vector it wants to move.
2296          */
2297         if (b_to_vf) {
2298                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2299                 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2300                         return ECORE_INVAL;
2301         }
2302
2303         /* If we're moving a SB from VF to PF, need to validate there isn't
2304          * already a line configured for that vector.
2305          */
2306         if (!b_to_vf) {
2307                 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2308                     ECORE_SB_INVALID_IDX)
2309                         return ECORE_INVAL;
2310         }
2311
2312         /* We need to validate that the SB can actually be relocated.
2313          * This would also handle the previous case where we've explicitly
2314          * stated which IGU SB needs to move.
2315          */
2316         for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2317              igu_sb_id++) {
2318                 p_block = &p_info->entry[igu_sb_id];
2319
2320                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2321                     !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2322                     (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2323                         if (b_to_vf)
2324                                 return ECORE_INVAL;
2325                         else
2326                                 continue;
2327                 }
2328
2329                 break;
2330         }
2331
2332         if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2333                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2334                            "Failed to find a free SB to move\n");
2335                 return ECORE_INVAL;
2336         }
2337
2338         /* At this point, p_block points to the SB we want to relocate */
2339         if (b_to_vf) {
2340                 p_block->status &= ~ECORE_IGU_STATUS_PF;
2341
2342                 /* It doesn't matter which VF number we choose, since we're
2343                  * going to disable the line; But let's keep it in range.
2344                  */
2345                 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2346
2347                 p_block->function_id = (u8)vf_num;
2348                 p_block->is_pf = 0;
2349                 p_block->vector_number = 0;
2350
2351                 p_info->usage.cnt--;
2352                 p_info->usage.free_cnt--;
2353                 p_info->usage.iov_cnt++;
2354                 p_info->usage.free_cnt_iov++;
2355
2356                 /* TODO - if SBs aren't really the limiting factor,
2357                  * then it might not be accurate [in the since that
2358                  * we might not need decrement the feature].
2359                  */
2360                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2361                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2362         } else {
2363                 p_block->status |= ECORE_IGU_STATUS_PF;
2364                 p_block->function_id = p_hwfn->rel_pf_id;
2365                 p_block->is_pf = 1;
2366                 p_block->vector_number = sb_id + 1;
2367
2368                 p_info->usage.cnt++;
2369                 p_info->usage.free_cnt++;
2370                 p_info->usage.iov_cnt--;
2371                 p_info->usage.free_cnt_iov--;
2372
2373                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2374                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2375         }
2376
2377         /* Update the IGU and CAU with the new configuration */
2378         SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2379                   p_block->function_id);
2380         SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2381         SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2382         SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2383                   p_block->vector_number);
2384
2385         ecore_wr(p_hwfn, p_ptt,
2386                  IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2387                  val);
2388
2389         ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2390                               igu_sb_id, vf_num,
2391                               p_block->is_pf ? 0 : 1);
2392
2393         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2394                    "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2395                    igu_sb_id, p_block->function_id,
2396                    p_block->is_pf, p_block->vector_number);
2397
2398         return ECORE_SUCCESS;
2399 }
2400
2401 /**
2402  * @brief Initialize igu runtime registers
2403  *
2404  * @param p_hwfn
2405  */
2406 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2407 {
2408         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2409
2410         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2411 }
2412
2413 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2414                           IGU_CMD_INT_ACK_BASE)
2415 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2416                           IGU_CMD_INT_ACK_BASE)
2417 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2418 {
2419         u32 intr_status_hi = 0, intr_status_lo = 0;
2420         u64 intr_status = 0;
2421
2422         intr_status_lo = REG_RD(p_hwfn,
2423                                 GTT_BAR0_MAP_REG_IGU_CMD +
2424                                 LSB_IGU_CMD_ADDR * 8);
2425         intr_status_hi = REG_RD(p_hwfn,
2426                                 GTT_BAR0_MAP_REG_IGU_CMD +
2427                                 MSB_IGU_CMD_ADDR * 8);
2428         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2429
2430         return intr_status;
2431 }
2432
2433 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2434 {
2435         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2436         p_hwfn->b_sp_dpc_enabled = true;
2437 }
2438
2439 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2440 {
2441         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2442         if (!p_hwfn->sp_dpc)
2443                 return ECORE_NOMEM;
2444
2445         return ECORE_SUCCESS;
2446 }
2447
2448 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2449 {
2450         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2451 }
2452
2453 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2454                                      struct ecore_ptt *p_ptt)
2455 {
2456         enum _ecore_status_t rc = ECORE_SUCCESS;
2457
2458         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2459         if (rc != ECORE_SUCCESS) {
2460                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2461                 return rc;
2462         }
2463
2464         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2465         if (rc != ECORE_SUCCESS) {
2466                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2467                 return rc;
2468         }
2469
2470         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2471         if (rc != ECORE_SUCCESS)
2472                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2473
2474         return rc;
2475 }
2476
2477 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2478 {
2479         ecore_int_sp_sb_free(p_hwfn);
2480         ecore_int_sb_attn_free(p_hwfn);
2481         ecore_int_sp_dpc_free(p_hwfn);
2482 }
2483
2484 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2485 {
2486         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2487                 return;
2488
2489         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2490         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2491         ecore_int_sp_dpc_setup(p_hwfn);
2492 }
2493
2494 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2495                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2496 {
2497         struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2498
2499         if (!p_igu_info || !p_sb_cnt_info)
2500                 return;
2501
2502         OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2503                     sizeof(*p_sb_cnt_info));
2504 }
2505
2506 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2507 {
2508         int i;
2509
2510         for_each_hwfn(p_dev, i)
2511                 p_dev->hwfns[i].b_int_requested = false;
2512 }
2513
2514 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2515 {
2516         p_dev->attn_clr_en = clr_enable;
2517 }
2518
2519 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2520                                              struct ecore_ptt *p_ptt,
2521                                              u8 timer_res, u16 sb_id, bool tx)
2522 {
2523         struct cau_sb_entry sb_entry;
2524         enum _ecore_status_t rc;
2525
2526         if (!p_hwfn->hw_init_done) {
2527                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2528                 return ECORE_INVAL;
2529         }
2530
2531         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2532                                  sb_id * sizeof(u64),
2533                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2534         if (rc != ECORE_SUCCESS) {
2535                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2536                 return rc;
2537         }
2538
2539         if (tx)
2540                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2541         else
2542                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2543
2544         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2545                                  (u64)(osal_uintptr_t)&sb_entry,
2546                                  CAU_REG_SB_VAR_MEMORY +
2547                                  sb_id * sizeof(u64), 2, 0);
2548         if (rc != ECORE_SUCCESS) {
2549                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2550                 return rc;
2551         }
2552
2553         return rc;
2554 }
2555
2556 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2557                                           struct ecore_ptt *p_ptt,
2558                                           struct ecore_sb_info *p_sb,
2559                                           struct ecore_sb_info_dbg *p_info)
2560 {
2561         u16 sbid = p_sb->igu_sb_id;
2562         int i;
2563
2564         if (IS_VF(p_hwfn->p_dev))
2565                 return ECORE_INVAL;
2566
2567         if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2568                 return ECORE_INVAL;
2569
2570         p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2571                                     IGU_REG_PRODUCER_MEMORY + sbid * 4);
2572         p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2573                                     IGU_REG_CONSUMER_MEM + sbid * 4);
2574
2575         for (i = 0; i < PIS_PER_SB; i++)
2576                 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2577                                               CAU_REG_PI_MEMORY +
2578                                               sbid * 4 * PIS_PER_SB +  i * 4);
2579
2580         return ECORE_SUCCESS;
2581 }