drivers/net/qede/base/ecore_l2.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_chain.h"
  15 #include "ecore_spq.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_l2.h"
  19 #include "ecore_sp_commands.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "reg_addr.h"
  23 #include "ecore_int.h"
  24 #include "ecore_hw.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_sriov.h"
  27 #include "ecore_mcp.h"
  28
  29 #define ECORE_MAX_SGES_NUM 16
  30 #define CRC32_POLY 0x1edc6f41
  31
  32 enum _ecore_status_t
  33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
  34                          struct ecore_sp_vport_start_params *p_params)
  35 {
  36         struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
  37         struct ecore_spq_entry *p_ent = OSAL_NULL;
  38         enum _ecore_status_t rc = ECORE_NOTIMPL;
  39         struct ecore_sp_init_data init_data;
  40         u8 abs_vport_id = 0;
  41         u16 rx_mode = 0;
  42
  43         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  44         if (rc != ECORE_SUCCESS)
  45                 return rc;
  46
  47         /* Get SPQ entry */
  48         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
  49         init_data.cid = ecore_spq_get_cid(p_hwfn);
  50         init_data.opaque_fid = p_params->opaque_fid;
  51         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
  52
  53         rc = ecore_sp_init_request(p_hwfn, &p_ent,
  54                                    ETH_RAMROD_VPORT_START,
  55                                    PROTOCOLID_ETH, &init_data);
  56         if (rc != ECORE_SUCCESS)
  57                 return rc;
  58
  59         p_ramrod = &p_ent->ramrod.vport_start;
  60         p_ramrod->vport_id = abs_vport_id;
  61
  62         p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
  63         p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  64         p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  65         p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  66         p_ramrod->untagged = p_params->only_untagged;
  67         p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
  68
  69         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  70         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  71
  72         p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
  73
  74         /* TPA related fields */
  75         OSAL_MEMSET(&p_ramrod->tpa_param, 0,
  76                     sizeof(struct eth_vport_tpa_param));
  77         p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  78
  79         switch (p_params->tpa_mode) {
  80         case ECORE_TPA_MODE_GRO:
  81                 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  82                 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  83                 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  84                 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  85                 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  86                 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  87                 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  88                 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  89                 break;
  90         default:
  91                 break;
  92         }
  93
  94         p_ramrod->tx_switching_en = p_params->tx_switching;
  95 #ifndef ASIC_ONLY
  96         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
  97                 p_ramrod->tx_switching_en = 0;
  98 #endif
  99
 100         /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
 101         p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
 102                                                     p_params->concrete_fid);
 103
 104         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 105 }
 106
 107 enum _ecore_status_t
 108 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
 109                      struct ecore_sp_vport_start_params *p_params)
 110 {
 111         if (IS_VF(p_hwfn->p_dev))
 112                 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
 113                                                p_params->mtu,
 114                                                p_params->remove_inner_vlan,
 115                                                p_params->tpa_mode,
 116                                                p_params->max_buffers_per_cqe,
 117                                                p_params->only_untagged);
 118
 119         return ecore_sp_eth_vport_start(p_hwfn, p_params);
 120 }
 121
 122 static enum _ecore_status_t
 123 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
 124                           struct vport_update_ramrod_data *p_ramrod,
 125                           struct ecore_rss_params *p_rss)
 126 {
 127         enum _ecore_status_t rc = ECORE_SUCCESS;
 128         struct eth_vport_rss_config *p_config;
 129         u16 abs_l2_queue = 0;
 130         int i;
 131
 132         if (!p_rss) {
 133                 p_ramrod->common.update_rss_flg = 0;
 134                 return rc;
 135         }
 136         p_config = &p_ramrod->rss_config;
 137
 138         OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
 139                           ETH_RSS_IND_TABLE_ENTRIES_NUM);
 140
 141         rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
 142         if (rc != ECORE_SUCCESS)
 143                 return rc;
 144
 145         p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
 146         p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
 147         p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
 148         p_config->update_rss_key = p_rss->update_rss_key;
 149
 150         p_config->rss_mode = p_rss->rss_enable ?
 151             ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
 152
 153         p_config->capabilities = 0;
 154
 155         SET_FIELD(p_config->capabilities,
 156                   ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
 157                   !!(p_rss->rss_caps & ECORE_RSS_IPV4));
 158         SET_FIELD(p_config->capabilities,
 159                   ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
 160                   !!(p_rss->rss_caps & ECORE_RSS_IPV6));
 161         SET_FIELD(p_config->capabilities,
 162                   ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
 163                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
 164         SET_FIELD(p_config->capabilities,
 165                   ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
 166                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
 167         SET_FIELD(p_config->capabilities,
 168                   ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
 169                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
 170         SET_FIELD(p_config->capabilities,
 171                   ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
 172                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
 173         p_config->tbl_size = p_rss->rss_table_size_log;
 174         p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
 175
 176         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 177                    "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
 178                    p_ramrod->common.update_rss_flg,
 179                    p_config->rss_mode,
 180                    p_config->update_rss_capabilities,
 181                    p_config->capabilities,
 182                    p_config->update_rss_ind_table, p_config->update_rss_key);
 183
 184         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 185                 rc = ecore_fw_l2_queue(p_hwfn,
 186                                        (u8)p_rss->rss_ind_table[i],
 187                                        &abs_l2_queue);
 188                 if (rc != ECORE_SUCCESS)
 189                         return rc;
 190
 191                 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
 192                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
 193                            i, p_config->indirection_table[i]);
 194         }
 195
 196         for (i = 0; i < 10; i++)
 197                 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
 198
 199         return rc;
 200 }
 201
 202 static void
 203 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
 204                             struct vport_update_ramrod_data *p_ramrod,
 205                             struct ecore_filter_accept_flags flags)
 206 {
 207         p_ramrod->common.update_rx_mode_flg = flags.update_rx_mode_config;
 208         p_ramrod->common.update_tx_mode_flg = flags.update_tx_mode_config;
 209
 210 #ifndef ASIC_ONLY
 211         /* On B0 emulation we cannot enable Tx, since this would cause writes
 212          * to PVFC HW block which isn't implemented in emulation.
 213          */
 214         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 215                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 216                            "Non-Asic - prevent Tx mode in vport update\n");
 217                 p_ramrod->common.update_tx_mode_flg = 0;
 218         }
 219 #endif
 220
 221         /* Set Rx mode accept flags */
 222         if (p_ramrod->common.update_rx_mode_flg) {
 223                 __le16 *state = &p_ramrod->rx_mode.state;
 224                 u8 accept_filter = flags.rx_accept_filter;
 225
 226 /*
 227  *              SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
 228  *                        !!(accept_filter & ECORE_ACCEPT_NONE));
 229  */
 230 /*
 231  *              SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL,
 232  *                        (!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) &&
 233  *                         !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
 234  */
 235                 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
 236                           !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
 237                             !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
 238
 239                 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
 240                           !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
 241 /*
 242  *              SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
 243  *                        !!(accept_filter & ECORE_ACCEPT_NONE));
 244  */
 245                 SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
 246                           !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
 247                             !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 248
 249                 SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
 250                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 251                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 252
 253                 SET_FIELD(*state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
 254                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 255
 256                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 257                            "p_ramrod->rx_mode.state = 0x%x\n",
 258                            p_ramrod->rx_mode.state);
 259         }
 260
 261         /* Set Tx mode accept flags */
 262         if (p_ramrod->common.update_tx_mode_flg) {
 263                 __le16 *state = &p_ramrod->tx_mode.state;
 264                 u8 accept_filter = flags.tx_accept_filter;
 265
 266                 SET_FIELD(*state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
 267                           !!(accept_filter & ECORE_ACCEPT_NONE));
 268
 269                 SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
 270                           !!(accept_filter & ECORE_ACCEPT_NONE));
 271
 272                 SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
 273                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 274                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 275
 276                 SET_FIELD(*state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
 277                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 278
 279                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 280                            "p_ramrod->tx_mode.state = 0x%x\n",
 281                            p_ramrod->tx_mode.state);
 282         }
 283 }
 284
 285 static void
 286 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
 287                               struct vport_update_ramrod_data *p_ramrod,
 288                               struct ecore_sge_tpa_params *p_params)
 289 {
 290         struct eth_vport_tpa_param *p_tpa;
 291
 292         if (!p_params) {
 293                 p_ramrod->common.update_tpa_param_flg = 0;
 294                 p_ramrod->common.update_tpa_en_flg = 0;
 295                 p_ramrod->common.update_tpa_param_flg = 0;
 296                 return;
 297         }
 298
 299         p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
 300         p_tpa = &p_ramrod->tpa_param;
 301         p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
 302         p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
 303         p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
 304         p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
 305
 306         p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
 307         p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
 308         p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
 309         p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
 310         p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
 311         p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
 312         p_tpa->tpa_max_size = p_params->tpa_max_size;
 313         p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
 314         p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
 315 }
 316
 317 static void
 318 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
 319                           struct vport_update_ramrod_data *p_ramrod,
 320                           struct ecore_sp_vport_update_params *p_params)
 321 {
 322         int i;
 323
 324         OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
 325                     sizeof(p_ramrod->approx_mcast.bins));
 326
 327         if (!p_params->update_approx_mcast_flg)
 328                 return;
 329
 330         p_ramrod->common.update_approx_mcast_flg = 1;
 331         for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
 332                 u32 *p_bins = (u32 *)p_params->bins;
 333
 334                 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
 335         }
 336 }
 337
 338 enum _ecore_status_t
 339 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
 340                       struct ecore_sp_vport_update_params *p_params,
 341                       enum spq_mode comp_mode,
 342                       struct ecore_spq_comp_cb *p_comp_data)
 343 {
 344         struct ecore_rss_params *p_rss_params = p_params->rss_params;
 345         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
 346         struct ecore_spq_entry *p_ent = OSAL_NULL;
 347         enum _ecore_status_t rc = ECORE_NOTIMPL;
 348         struct ecore_sp_init_data init_data;
 349         u8 abs_vport_id = 0, val;
 350         u16 wordval;
 351
 352         if (IS_VF(p_hwfn->p_dev)) {
 353                 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
 354                 return rc;
 355         }
 356
 357         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 358         if (rc != ECORE_SUCCESS)
 359                 return rc;
 360
 361         /* Get SPQ entry */
 362         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 363         init_data.cid = ecore_spq_get_cid(p_hwfn);
 364         init_data.opaque_fid = p_params->opaque_fid;
 365         init_data.comp_mode = comp_mode;
 366         init_data.p_comp_data = p_comp_data;
 367
 368         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 369                                    ETH_RAMROD_VPORT_UPDATE,
 370                                    PROTOCOLID_ETH, &init_data);
 371         if (rc != ECORE_SUCCESS)
 372                 return rc;
 373
 374         /* Copy input params to ramrod according to FW struct */
 375         p_ramrod = &p_ent->ramrod.vport_update;
 376
 377         p_ramrod->common.vport_id = abs_vport_id;
 378
 379         p_ramrod->common.rx_active_flg = p_params->vport_active_rx_flg;
 380         p_ramrod->common.tx_active_flg = p_params->vport_active_tx_flg;
 381         val = p_params->update_vport_active_rx_flg;
 382         p_ramrod->common.update_rx_active_flg = val;
 383         val = p_params->update_vport_active_tx_flg;
 384         p_ramrod->common.update_tx_active_flg = val;
 385         val = p_params->update_inner_vlan_removal_flg;
 386         p_ramrod->common.update_inner_vlan_removal_en_flg = val;
 387         val = p_params->inner_vlan_removal_flg;
 388         p_ramrod->common.inner_vlan_removal_en = val;
 389         val = p_params->silent_vlan_removal_flg;
 390         p_ramrod->common.silent_vlan_removal_en = val;
 391         val = p_params->update_tx_switching_flg;
 392         p_ramrod->common.update_tx_switching_en_flg = val;
 393         val = p_params->update_default_vlan_enable_flg;
 394         p_ramrod->common.update_default_vlan_en_flg = val;
 395         p_ramrod->common.default_vlan_en = p_params->default_vlan_enable_flg;
 396         val = p_params->update_default_vlan_flg;
 397         p_ramrod->common.update_default_vlan_flg = val;
 398         wordval = p_params->default_vlan;
 399         p_ramrod->common.default_vlan = OSAL_CPU_TO_LE16(wordval);
 400
 401         p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
 402
 403 #ifndef ASIC_ONLY
 404         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 405                 if (p_ramrod->common.tx_switching_en ||
 406                     p_ramrod->common.update_tx_switching_en_flg) {
 407                         DP_NOTICE(p_hwfn, false,
 408                                   "FPGA - why are we seeing tx-switching? Overriding it\n");
 409                         p_ramrod->common.tx_switching_en = 0;
 410                         p_ramrod->common.update_tx_switching_en_flg = 1;
 411                 }
 412 #endif
 413
 414         val = p_params->update_anti_spoofing_en_flg;
 415         p_ramrod->common.update_anti_spoofing_en_flg = val;
 416         p_ramrod->common.anti_spoofing_en = p_params->anti_spoofing_en;
 417         p_ramrod->common.accept_any_vlan = p_params->accept_any_vlan;
 418         val = p_params->update_accept_any_vlan_flg;
 419         p_ramrod->common.update_accept_any_vlan_flg = val;
 420
 421         rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
 422         if (rc != ECORE_SUCCESS) {
 423                 /* Return spq entry which is taken in ecore_sp_init_request() */
 424                 ecore_spq_return_entry(p_hwfn, p_ent);
 425                 return rc;
 426         }
 427
 428         /* Update mcast bins for VFs, PF doesn't use this functionality */
 429         ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
 430
 431         ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
 432         ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
 433                                       p_params->sge_tpa_params);
 434         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 435 }
 436
 437 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
 438                                          u16 opaque_fid, u8 vport_id)
 439 {
 440         struct vport_stop_ramrod_data *p_ramrod;
 441         struct ecore_sp_init_data init_data;
 442         struct ecore_spq_entry *p_ent;
 443         enum _ecore_status_t rc;
 444         u8 abs_vport_id = 0;
 445
 446         if (IS_VF(p_hwfn->p_dev))
 447                 return ecore_vf_pf_vport_stop(p_hwfn);
 448
 449         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 450         if (rc != ECORE_SUCCESS)
 451                 return rc;
 452
 453         /* Get SPQ entry */
 454         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 455         init_data.cid = ecore_spq_get_cid(p_hwfn);
 456         init_data.opaque_fid = opaque_fid;
 457         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 458
 459         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 460                                    ETH_RAMROD_VPORT_STOP,
 461                                    PROTOCOLID_ETH, &init_data);
 462         if (rc != ECORE_SUCCESS)
 463                 return rc;
 464
 465         p_ramrod = &p_ent->ramrod.vport_stop;
 466         p_ramrod->vport_id = abs_vport_id;
 467
 468         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 469 }
 470
 471 static enum _ecore_status_t
 472 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
 473                          struct ecore_filter_accept_flags *p_accept_flags)
 474 {
 475         struct ecore_sp_vport_update_params s_params;
 476
 477         OSAL_MEMSET(&s_params, 0, sizeof(s_params));
 478         OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
 479                     sizeof(struct ecore_filter_accept_flags));
 480
 481         return ecore_vf_pf_vport_update(p_hwfn, &s_params);
 482 }
 483
 484 enum _ecore_status_t
 485 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
 486                         u8 vport,
 487                         struct ecore_filter_accept_flags accept_flags,
 488                         u8 update_accept_any_vlan,
 489                         u8 accept_any_vlan,
 490                         enum spq_mode comp_mode,
 491                         struct ecore_spq_comp_cb *p_comp_data)
 492 {
 493         struct ecore_sp_vport_update_params update_params;
 494         int i, rc;
 495
 496         /* Prepare and send the vport rx_mode change */
 497         OSAL_MEMSET(&update_params, 0, sizeof(update_params));
 498         update_params.vport_id = vport;
 499         update_params.accept_flags = accept_flags;
 500         update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
 501         update_params.accept_any_vlan = accept_any_vlan;
 502
 503         for_each_hwfn(p_dev, i) {
 504                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 505
 506                 update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 507
 508                 if (IS_VF(p_dev)) {
 509                         rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
 510                         if (rc != ECORE_SUCCESS)
 511                                 return rc;
 512                         continue;
 513                 }
 514
 515                 rc = ecore_sp_vport_update(p_hwfn, &update_params,
 516                                            comp_mode, p_comp_data);
 517                 if (rc != ECORE_SUCCESS) {
 518                         DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
 519                         return rc;
 520                 }
 521
 522                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 523                            "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
 524                            accept_flags.rx_accept_filter,
 525                            accept_flags.tx_accept_filter);
 526
 527                 if (update_accept_any_vlan)
 528                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 529                                    "accept_any_vlan=%d configured\n",
 530                                    accept_any_vlan);
 531         }
 532
 533         return 0;
 534 }
 535
 536 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
 537                                        struct ecore_hw_cid_data *p_cid_data)
 538 {
 539         if (!p_cid_data->b_cid_allocated)
 540                 return;
 541
 542         ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
 543         p_cid_data->b_cid_allocated = false;
 544 }
 545
 546 enum _ecore_status_t
 547 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
 548                               u16 opaque_fid,
 549                               u32 cid,
 550                               u16 rx_queue_id,
 551                               u8 vport_id,
 552                               u8 stats_id,
 553                               u16 sb,
 554                               u8 sb_index,
 555                               u16 bd_max_bytes,
 556                               dma_addr_t bd_chain_phys_addr,
 557                               dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
 558 {
 559         struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 560         struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 561         struct ecore_spq_entry *p_ent = OSAL_NULL;
 562         enum _ecore_status_t rc = ECORE_NOTIMPL;
 563         struct ecore_sp_init_data init_data;
 564         u16 abs_rx_q_id = 0;
 565         u8 abs_vport_id = 0;
 566
 567         /* Store information for the stop */
 568         p_rx_cid->cid = cid;
 569         p_rx_cid->opaque_fid = opaque_fid;
 570         p_rx_cid->vport_id = vport_id;
 571
 572         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 573         if (rc != ECORE_SUCCESS)
 574                 return rc;
 575
 576         rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
 577         if (rc != ECORE_SUCCESS)
 578                 return rc;
 579
 580         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 581                    "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 582                    opaque_fid, cid, rx_queue_id, vport_id, sb);
 583
 584         /* Get SPQ entry */
 585         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 586         init_data.cid = cid;
 587         init_data.opaque_fid = opaque_fid;
 588         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 589
 590         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 591                                    ETH_RAMROD_RX_QUEUE_START,
 592                                    PROTOCOLID_ETH, &init_data);
 593         if (rc != ECORE_SUCCESS)
 594                 return rc;
 595
 596         p_ramrod = &p_ent->ramrod.rx_queue_start;
 597
 598         p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
 599         p_ramrod->sb_index = sb_index;
 600         p_ramrod->vport_id = abs_vport_id;
 601         p_ramrod->stats_counter_id = stats_id;
 602         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 603         p_ramrod->complete_cqe_flg = 0;
 604         p_ramrod->complete_event_flg = 1;
 605
 606         p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
 607         DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
 608
 609         p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
 610         DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
 611
 612         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 613 }
 614
 615 enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
 616                                                  u16 opaque_fid,
 617                                                  u8 rx_queue_id,
 618                                                  u8 vport_id,
 619                                                  u8 stats_id,
 620                                                  u16 sb,
 621                                                  u8 sb_index,
 622                                                  u16 bd_max_bytes,
 623                                                  dma_addr_t bd_chain_phys_addr,
 624                                                  dma_addr_t cqe_pbl_addr,
 625                                                  u16 cqe_pbl_size,
 626                                                  void OSAL_IOMEM * *pp_prod)
 627 {
 628         struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 629         u8 abs_stats_id = 0;
 630         u16 abs_l2_queue = 0;
 631         enum _ecore_status_t rc;
 632         u64 init_prod_val = 0;
 633
 634         if (IS_VF(p_hwfn->p_dev)) {
 635                 return ecore_vf_pf_rxq_start(p_hwfn,
 636                                              rx_queue_id,
 637                                              sb,
 638                                              sb_index,
 639                                              bd_max_bytes,
 640                                              bd_chain_phys_addr,
 641                                              cqe_pbl_addr,
 642                                              cqe_pbl_size, pp_prod);
 643         }
 644
 645         rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_l2_queue);
 646         if (rc != ECORE_SUCCESS)
 647                 return rc;
 648
 649         rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
 650         if (rc != ECORE_SUCCESS)
 651                 return rc;
 652
 653         *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
 654             GTT_BAR0_MAP_REG_MSDM_RAM + MSTORM_PRODS_OFFSET(abs_l2_queue);
 655
 656         /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
 657         __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
 658                           (u32 *)(&init_prod_val));
 659
 660         /* Allocate a CID for the queue */
 661         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid);
 662         if (rc != ECORE_SUCCESS) {
 663                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 664                 return rc;
 665         }
 666         p_rx_cid->b_cid_allocated = true;
 667
 668         rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
 669                                            opaque_fid,
 670                                            p_rx_cid->cid,
 671                                            rx_queue_id,
 672                                            vport_id,
 673                                            abs_stats_id,
 674                                            sb,
 675                                            sb_index,
 676                                            bd_max_bytes,
 677                                            bd_chain_phys_addr,
 678                                            cqe_pbl_addr, cqe_pbl_size);
 679
 680         if (rc != ECORE_SUCCESS)
 681                 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 682
 683         return rc;
 684 }
 685
 686 enum _ecore_status_t
 687 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
 688                               u16 rx_queue_id,
 689                               u8 num_rxqs,
 690                               u8 complete_cqe_flg,
 691                               u8 complete_event_flg,
 692                               enum spq_mode comp_mode,
 693                               struct ecore_spq_comp_cb *p_comp_data)
 694 {
 695         struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
 696         struct ecore_spq_entry *p_ent = OSAL_NULL;
 697         enum _ecore_status_t rc = ECORE_NOTIMPL;
 698         struct ecore_sp_init_data init_data;
 699         struct ecore_hw_cid_data *p_rx_cid;
 700         u16 qid, abs_rx_q_id = 0;
 701         u8 i;
 702
 703         if (IS_VF(p_hwfn->p_dev))
 704                 return ecore_vf_pf_rxqs_update(p_hwfn,
 705                                                rx_queue_id,
 706                                                num_rxqs,
 707                                                complete_cqe_flg,
 708                                                complete_event_flg);
 709
 710         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 711         init_data.comp_mode = comp_mode;
 712         init_data.p_comp_data = p_comp_data;
 713
 714         for (i = 0; i < num_rxqs; i++) {
 715                 qid = rx_queue_id + i;
 716                 p_rx_cid = &p_hwfn->p_rx_cids[qid];
 717
 718                 /* Get SPQ entry */
 719                 init_data.cid = p_rx_cid->cid;
 720                 init_data.opaque_fid = p_rx_cid->opaque_fid;
 721
 722                 rc = ecore_sp_init_request(p_hwfn, &p_ent,
 723                                            ETH_RAMROD_RX_QUEUE_UPDATE,
 724                                            PROTOCOLID_ETH, &init_data);
 725                 if (rc != ECORE_SUCCESS)
 726                         return rc;
 727
 728                 p_ramrod = &p_ent->ramrod.rx_queue_update;
 729
 730                 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 731                 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
 732                 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 733                 p_ramrod->complete_cqe_flg = complete_cqe_flg;
 734                 p_ramrod->complete_event_flg = complete_event_flg;
 735
 736                 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 737                 if (rc)
 738                         return rc;
 739         }
 740
 741         return rc;
 742 }
 743
 744 enum _ecore_status_t
 745 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
 746                            u16 rx_queue_id,
 747                            bool eq_completion_only, bool cqe_completion)
 748 {
 749         struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 750         struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
 751         struct ecore_spq_entry *p_ent = OSAL_NULL;
 752         enum _ecore_status_t rc = ECORE_NOTIMPL;
 753         struct ecore_sp_init_data init_data;
 754         u16 abs_rx_q_id = 0;
 755
 756         if (IS_VF(p_hwfn->p_dev))
 757                 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
 758                                             cqe_completion);
 759
 760         /* Get SPQ entry */
 761         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 762         init_data.cid = p_rx_cid->cid;
 763         init_data.opaque_fid = p_rx_cid->opaque_fid;
 764         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 765
 766         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 767                                    ETH_RAMROD_RX_QUEUE_STOP,
 768                                    PROTOCOLID_ETH, &init_data);
 769         if (rc != ECORE_SUCCESS)
 770                 return rc;
 771
 772         p_ramrod = &p_ent->ramrod.rx_queue_stop;
 773
 774         ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 775         ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
 776         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 777
 778         /* Cleaning the queue requires the completion to arrive there.
 779          * In addition, VFs require the answer to come as eqe to PF.
 780          */
 781         p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
 782                                           p_hwfn->hw_info.opaque_fid) &&
 783                                       !eq_completion_only) || cqe_completion;
 784         p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
 785                                          p_hwfn->hw_info.opaque_fid) ||
 786             eq_completion_only;
 787
 788         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 789         if (rc != ECORE_SUCCESS)
 790                 return rc;
 791
 792         ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 793
 794         return rc;
 795 }
 796
 797 enum _ecore_status_t
 798 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
 799                               u16 opaque_fid,
 800                               u16 tx_queue_id,
 801                               u32 cid,
 802                               u8 vport_id,
 803                               u8 stats_id,
 804                               u16 sb,
 805                               u8 sb_index,
 806                               dma_addr_t pbl_addr,
 807                               u16 pbl_size,
 808                               union ecore_qm_pq_params *p_pq_params)
 809 {
 810         struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 811         struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 812         struct ecore_spq_entry *p_ent = OSAL_NULL;
 813         enum _ecore_status_t rc = ECORE_NOTIMPL;
 814         struct ecore_sp_init_data init_data;
 815         u16 pq_id, abs_tx_q_id = 0;
 816         u8 abs_vport_id;
 817
 818         /* Store information for the stop */
 819         p_tx_cid->cid = cid;
 820         p_tx_cid->opaque_fid = opaque_fid;
 821
 822         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 823         if (rc != ECORE_SUCCESS)
 824                 return rc;
 825
 826         rc = ecore_fw_l2_queue(p_hwfn, tx_queue_id, &abs_tx_q_id);
 827         if (rc != ECORE_SUCCESS)
 828                 return rc;
 829
 830         /* Get SPQ entry */
 831         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 832         init_data.cid = cid;
 833         init_data.opaque_fid = opaque_fid;
 834         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 835
 836         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 837                                    ETH_RAMROD_TX_QUEUE_START,
 838                                    PROTOCOLID_ETH, &init_data);
 839         if (rc != ECORE_SUCCESS)
 840                 return rc;
 841
 842         p_ramrod = &p_ent->ramrod.tx_queue_start;
 843         p_ramrod->vport_id = abs_vport_id;
 844
 845         p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
 846         p_ramrod->sb_index = sb_index;
 847         p_ramrod->stats_counter_id = stats_id;
 848
 849         p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
 850
 851         p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
 852         p_ramrod->pbl_base_addr.hi = DMA_HI_LE(pbl_addr);
 853         p_ramrod->pbl_base_addr.lo = DMA_LO_LE(pbl_addr);
 854
 855         pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
 856         p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
 857
 858         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 859 }
 860
 861 enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
 862                                                  u16 opaque_fid,
 863                                                  u16 tx_queue_id,
 864                                                  u8 vport_id,
 865                                                  u8 stats_id,
 866                                                  u16 sb,
 867                                                  u8 sb_index,
 868                                                  dma_addr_t pbl_addr,
 869                                                  u16 pbl_size,
 870                                                  void OSAL_IOMEM * *pp_doorbell)
 871 {
 872         struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 873         union ecore_qm_pq_params pq_params;
 874         enum _ecore_status_t rc;
 875         u8 abs_stats_id = 0;
 876
 877         if (IS_VF(p_hwfn->p_dev)) {
 878                 return ecore_vf_pf_txq_start(p_hwfn,
 879                                              tx_queue_id,
 880                                              sb,
 881                                              sb_index,
 882                                              pbl_addr, pbl_size, pp_doorbell);
 883         }
 884
 885         rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
 886         if (rc != ECORE_SUCCESS)
 887                 return rc;
 888
 889         OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
 890         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
 891
 892         /* Allocate a CID for the queue */
 893         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
 894         if (rc != ECORE_SUCCESS) {
 895                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 896                 return rc;
 897         }
 898         p_tx_cid->b_cid_allocated = true;
 899
 900         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 901                    "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 902                    opaque_fid, p_tx_cid->cid, tx_queue_id, vport_id, sb);
 903
 904         /* TODO - set tc in the pq_params for multi-cos */
 905         rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
 906                                            opaque_fid,
 907                                            tx_queue_id,
 908                                            p_tx_cid->cid,
 909                                            vport_id,
 910                                            abs_stats_id,
 911                                            sb,
 912                                            sb_index,
 913                                            pbl_addr, pbl_size, &pq_params);
 914
 915         *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
 916             DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
 917
 918         if (rc != ECORE_SUCCESS)
 919                 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 920
 921         return rc;
 922 }
 923
 924 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
 925 {
 926         return ECORE_NOTIMPL;
 927 }
 928
 929 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
 930                                                 u16 tx_queue_id)
 931 {
 932         struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 933         struct tx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
 934         struct ecore_spq_entry *p_ent = OSAL_NULL;
 935         enum _ecore_status_t rc = ECORE_NOTIMPL;
 936         struct ecore_sp_init_data init_data;
 937
 938         if (IS_VF(p_hwfn->p_dev))
 939                 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
 940
 941         /* Get SPQ entry */
 942         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 943         init_data.cid = p_tx_cid->cid;
 944         init_data.opaque_fid = p_tx_cid->opaque_fid;
 945         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 946
 947         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 948                                    ETH_RAMROD_TX_QUEUE_STOP,
 949                                    PROTOCOLID_ETH, &init_data);
 950         if (rc != ECORE_SUCCESS)
 951                 return rc;
 952
 953         p_ramrod = &p_ent->ramrod.tx_queue_stop;
 954
 955         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 956         if (rc != ECORE_SUCCESS)
 957                 return rc;
 958
 959         ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 960         return rc;
 961 }
 962
 963 static enum eth_filter_action
 964 ecore_filter_action(enum ecore_filter_opcode opcode)
 965 {
 966         enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
 967
 968         switch (opcode) {
 969         case ECORE_FILTER_ADD:
 970                 action = ETH_FILTER_ACTION_ADD;
 971                 break;
 972         case ECORE_FILTER_REMOVE:
 973                 action = ETH_FILTER_ACTION_REMOVE;
 974                 break;
 975         case ECORE_FILTER_FLUSH:
 976                 action = ETH_FILTER_ACTION_REMOVE_ALL;
 977                 break;
 978         default:
 979                 action = MAX_ETH_FILTER_ACTION;
 980         }
 981
 982         return action;
 983 }
 984
 985 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
 986                                   __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
 987 {
 988         ((u8 *)fw_msb)[0] = mac[1];
 989         ((u8 *)fw_msb)[1] = mac[0];
 990         ((u8 *)fw_mid)[0] = mac[3];
 991         ((u8 *)fw_mid)[1] = mac[2];
 992         ((u8 *)fw_lsb)[0] = mac[5];
 993         ((u8 *)fw_lsb)[1] = mac[4];
 994 }
 995
 996 static enum _ecore_status_t
 997 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
 998                           u16 opaque_fid,
 999                           struct ecore_filter_ucast *p_filter_cmd,
1000                           struct vport_filter_update_ramrod_data **pp_ramrod,
1001                           struct ecore_spq_entry **pp_ent,
1002                           enum spq_mode comp_mode,
1003                           struct ecore_spq_comp_cb *p_comp_data)
1004 {
1005         struct vport_filter_update_ramrod_data *p_ramrod;
1006         u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1007         struct eth_filter_cmd *p_first_filter;
1008         struct eth_filter_cmd *p_second_filter;
1009         struct ecore_sp_init_data init_data;
1010         enum eth_filter_action action;
1011         enum _ecore_status_t rc;
1012
1013         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1014                             &vport_to_remove_from);
1015         if (rc != ECORE_SUCCESS)
1016                 return rc;
1017
1018         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1019                             &vport_to_add_to);
1020         if (rc != ECORE_SUCCESS)
1021                 return rc;
1022
1023         /* Get SPQ entry */
1024         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1025         init_data.cid = ecore_spq_get_cid(p_hwfn);
1026         init_data.opaque_fid = opaque_fid;
1027         init_data.comp_mode = comp_mode;
1028         init_data.p_comp_data = p_comp_data;
1029
1030         rc = ecore_sp_init_request(p_hwfn, pp_ent,
1031                                    ETH_RAMROD_FILTERS_UPDATE,
1032                                    PROTOCOLID_ETH, &init_data);
1033         if (rc != ECORE_SUCCESS)
1034                 return rc;
1035
1036         *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1037         p_ramrod = *pp_ramrod;
1038         p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1039         p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1040
1041 #ifndef ASIC_ONLY
1042         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1043                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1044                            "Non-Asic - prevent Tx filters\n");
1045                 p_ramrod->filter_cmd_hdr.tx = 0;
1046         }
1047 #endif
1048
1049         switch (p_filter_cmd->opcode) {
1050         case ECORE_FILTER_REPLACE:
1051         case ECORE_FILTER_MOVE:
1052                 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1053                 break;
1054         default:
1055                 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1056                 break;
1057         }
1058
1059         p_first_filter = &p_ramrod->filter_cmds[0];
1060         p_second_filter = &p_ramrod->filter_cmds[1];
1061
1062         switch (p_filter_cmd->type) {
1063         case ECORE_FILTER_MAC:
1064                 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1065                 break;
1066         case ECORE_FILTER_VLAN:
1067                 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1068                 break;
1069         case ECORE_FILTER_MAC_VLAN:
1070                 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1071                 break;
1072         case ECORE_FILTER_INNER_MAC:
1073                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1074                 break;
1075         case ECORE_FILTER_INNER_VLAN:
1076                 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1077                 break;
1078         case ECORE_FILTER_INNER_PAIR:
1079                 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1080                 break;
1081         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1082                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1083                 break;
1084         case ECORE_FILTER_MAC_VNI_PAIR:
1085                 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1086                 break;
1087         case ECORE_FILTER_VNI:
1088                 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1089                 break;
1090         }
1091
1092         if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1093             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1094             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1095             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1096             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1097             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1098                 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1099                                       &p_first_filter->mac_mid,
1100                                       &p_first_filter->mac_lsb,
1101                                       (u8 *)p_filter_cmd->mac);
1102
1103         if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1104             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1105             (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1106             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1107                 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1108
1109         if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1110             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1111             (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1112                 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1113
1114         if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1115                 p_second_filter->type = p_first_filter->type;
1116                 p_second_filter->mac_msb = p_first_filter->mac_msb;
1117                 p_second_filter->mac_mid = p_first_filter->mac_mid;
1118                 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1119                 p_second_filter->vlan_id = p_first_filter->vlan_id;
1120                 p_second_filter->vni = p_first_filter->vni;
1121
1122                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1123
1124                 p_first_filter->vport_id = vport_to_remove_from;
1125
1126                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1127                 p_second_filter->vport_id = vport_to_add_to;
1128         } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1129                 p_first_filter->vport_id = vport_to_add_to;
1130                 OSAL_MEMCPY(p_second_filter, p_first_filter,
1131                             sizeof(*p_second_filter));
1132                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1133                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1134         } else {
1135                 action = ecore_filter_action(p_filter_cmd->opcode);
1136
1137                 if (action == MAX_ETH_FILTER_ACTION) {
1138                         DP_NOTICE(p_hwfn, true,
1139                                   "%d is not supported yet\n",
1140                                   p_filter_cmd->opcode);
1141                         return ECORE_NOTIMPL;
1142                 }
1143
1144                 p_first_filter->action = action;
1145                 p_first_filter->vport_id =
1146                     (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1147                     vport_to_remove_from : vport_to_add_to;
1148         }
1149
1150         return ECORE_SUCCESS;
1151 }
1152
1153 enum _ecore_status_t
1154 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1155                           u16 opaque_fid,
1156                           struct ecore_filter_ucast *p_filter_cmd,
1157                           enum spq_mode comp_mode,
1158                           struct ecore_spq_comp_cb *p_comp_data)
1159 {
1160         struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1161         struct ecore_spq_entry *p_ent = OSAL_NULL;
1162         struct eth_filter_cmd_header *p_header;
1163         enum _ecore_status_t rc;
1164
1165         rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1166                                        &p_ramrod, &p_ent,
1167                                        comp_mode, p_comp_data);
1168         if (rc != ECORE_SUCCESS) {
1169                 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1170                 return rc;
1171         }
1172         p_header = &p_ramrod->filter_cmd_hdr;
1173         p_header->assert_on_error = p_filter_cmd->assert_on_error;
1174
1175         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1176         if (rc != ECORE_SUCCESS) {
1177                 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1178                 return rc;
1179         }
1180
1181         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1182                    "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1183                    (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1184                    ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1185                     "REMOVE" :
1186                     ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1187                      "MOVE" : "REPLACE")),
1188                    (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1189                    ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1190                     "VLAN" : "MAC & VLAN"),
1191                    p_ramrod->filter_cmd_hdr.cmd_cnt,
1192                    p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1193         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1194                    "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1195                    p_filter_cmd->vport_to_add_to,
1196                    p_filter_cmd->vport_to_remove_from,
1197                    p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1198                    p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1199                    p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1200                    p_filter_cmd->vlan);
1201
1202         return ECORE_SUCCESS;
1203 }
1204
1205 /*******************************************************************************
1206  * Description:
1207  *         Calculates crc 32 on a buffer
1208  *         Note: crc32_length MUST be aligned to 8
1209  * Return:
1210  ******************************************************************************/
1211 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1212                              u32 crc32_length, u32 crc32_seed, u8 complement)
1213 {
1214         u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1215         u8 msb = 0, current_byte = 0;
1216
1217         if ((crc32_packet == OSAL_NULL) ||
1218             (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1219                 return crc32_result;
1220         }
1221
1222         for (byte = 0; byte < crc32_length; byte++) {
1223                 current_byte = crc32_packet[byte];
1224                 for (bit = 0; bit < 8; bit++) {
1225                         msb = (u8)(crc32_result >> 31);
1226                         crc32_result = crc32_result << 1;
1227                         if (msb != (0x1 & (current_byte >> bit))) {
1228                                 crc32_result = crc32_result ^ CRC32_POLY;
1229                                 crc32_result |= 1;
1230                         }
1231                 }
1232         }
1233
1234         return crc32_result;
1235 }
1236
1237 static OSAL_INLINE u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1238 {
1239         u32 packet_buf[2] = { 0 };
1240
1241         OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1242         return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1243 }
1244
1245 u8 ecore_mcast_bin_from_mac(u8 *mac)
1246 {
1247         u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1248                                   mac, ETH_ALEN);
1249
1250         return crc & 0xff;
1251 }
1252
1253 static enum _ecore_status_t
1254 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1255                           u16 opaque_fid,
1256                           struct ecore_filter_mcast *p_filter_cmd,
1257                           enum spq_mode comp_mode,
1258                           struct ecore_spq_comp_cb *p_comp_data)
1259 {
1260         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1261         unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1262         struct ecore_spq_entry *p_ent = OSAL_NULL;
1263         struct ecore_sp_init_data init_data;
1264         enum _ecore_status_t rc;
1265         u8 abs_vport_id = 0;
1266         int i;
1267
1268         rc = ecore_fw_vport(p_hwfn,
1269                             (p_filter_cmd->opcode == ECORE_FILTER_ADD) ?
1270                             p_filter_cmd->vport_to_add_to :
1271                             p_filter_cmd->vport_to_remove_from, &abs_vport_id);
1272         if (rc != ECORE_SUCCESS)
1273                 return rc;
1274
1275         /* Get SPQ entry */
1276         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1277         init_data.cid = ecore_spq_get_cid(p_hwfn);
1278         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1279         init_data.comp_mode = comp_mode;
1280         init_data.p_comp_data = p_comp_data;
1281
1282         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1283                                    ETH_RAMROD_VPORT_UPDATE,
1284                                    PROTOCOLID_ETH, &init_data);
1285         if (rc != ECORE_SUCCESS) {
1286                 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1287                 return rc;
1288         }
1289
1290         p_ramrod = &p_ent->ramrod.vport_update;
1291         p_ramrod->common.update_approx_mcast_flg = 1;
1292
1293         /* explicitly clear out the entire vector */
1294         OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1295                     0, sizeof(p_ramrod->approx_mcast.bins));
1296         OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1297                     ETH_MULTICAST_MAC_BINS_IN_REGS);
1298
1299         if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1300                 /* filter ADD op is explicit set op and it removes
1301                  *  any existing filters for the vport.
1302                  */
1303                 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1304                         u32 bit;
1305
1306                         bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1307                         OSAL_SET_BIT(bit, bins);
1308                 }
1309
1310                 /* Convert to correct endianity */
1311                 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1312                         struct vport_update_ramrod_mcast *p_ramrod_bins;
1313                         u32 *p_bins = (u32 *)bins;
1314
1315                         p_ramrod_bins = &p_ramrod->approx_mcast;
1316                         p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1317                 }
1318         }
1319
1320         p_ramrod->common.vport_id = abs_vport_id;
1321
1322         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1323         if (rc != ECORE_SUCCESS)
1324                 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1325
1326         return rc;
1327 }
1328
1329 enum _ecore_status_t
1330 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1331                        struct ecore_filter_mcast *p_filter_cmd,
1332                        enum spq_mode comp_mode,
1333                        struct ecore_spq_comp_cb *p_comp_data)
1334 {
1335         enum _ecore_status_t rc = ECORE_SUCCESS;
1336         int i;
1337
1338         /* only ADD and REMOVE operations are supported for multi-cast */
1339         if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1340              (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1341             (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1342                 return ECORE_INVAL;
1343         }
1344
1345         for_each_hwfn(p_dev, i) {
1346                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1347
1348                 if (IS_VF(p_dev)) {
1349                         ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1350                         continue;
1351                 }
1352
1353                 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1354                                                p_hwfn->hw_info.opaque_fid,
1355                                                p_filter_cmd,
1356                                                comp_mode, p_comp_data);
1357                 if (rc != ECORE_SUCCESS)
1358                         break;
1359         }
1360
1361         return rc;
1362 }
1363
1364 enum _ecore_status_t
1365 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1366                        struct ecore_filter_ucast *p_filter_cmd,
1367                        enum spq_mode comp_mode,
1368                        struct ecore_spq_comp_cb *p_comp_data)
1369 {
1370         enum _ecore_status_t rc = ECORE_SUCCESS;
1371         int i;
1372
1373         for_each_hwfn(p_dev, i) {
1374                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1375
1376                 if (IS_VF(p_dev)) {
1377                         rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1378                         continue;
1379                 }
1380
1381                 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1382                                                p_hwfn->hw_info.opaque_fid,
1383                                                p_filter_cmd,
1384                                                comp_mode, p_comp_data);
1385                 if (rc != ECORE_SUCCESS)
1386                         break;
1387         }
1388
1389         return rc;
1390 }
1391
1392 /* IOV related */
1393 enum _ecore_status_t ecore_sp_vf_start(struct ecore_hwfn *p_hwfn,
1394                                        u32 concrete_vfid, u16 opaque_vfid)
1395 {
1396         struct vf_start_ramrod_data *p_ramrod = OSAL_NULL;
1397         struct ecore_spq_entry *p_ent = OSAL_NULL;
1398         enum _ecore_status_t rc = ECORE_NOTIMPL;
1399         struct ecore_sp_init_data init_data;
1400
1401         /* Get SPQ entry */
1402         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1403         init_data.cid = ecore_spq_get_cid(p_hwfn);
1404         init_data.opaque_fid = opaque_vfid;
1405         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1406
1407         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1408                                    COMMON_RAMROD_VF_START,
1409                                    PROTOCOLID_COMMON, &init_data);
1410         if (rc != ECORE_SUCCESS)
1411                 return rc;
1412
1413         p_ramrod = &p_ent->ramrod.vf_start;
1414
1415         p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
1416         p_ramrod->opaque_fid = OSAL_CPU_TO_LE16(opaque_vfid);
1417
1418         switch (p_hwfn->hw_info.personality) {
1419         case ECORE_PCI_ETH:
1420                 p_ramrod->personality = PERSONALITY_ETH;
1421                 break;
1422         default:
1423                 DP_NOTICE(p_hwfn, true, "Unknown VF personality %d\n",
1424                           p_hwfn->hw_info.personality);
1425                 return ECORE_INVAL;
1426         }
1427
1428         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1429 }
1430
1431 enum _ecore_status_t ecore_sp_vf_update(struct ecore_hwfn *p_hwfn)
1432 {
1433         return ECORE_NOTIMPL;
1434 }
1435
1436 enum _ecore_status_t ecore_sp_vf_stop(struct ecore_hwfn *p_hwfn,
1437                                       u32 concrete_vfid, u16 opaque_vfid)
1438 {
1439         enum _ecore_status_t rc = ECORE_NOTIMPL;
1440         struct vf_stop_ramrod_data *p_ramrod = OSAL_NULL;
1441         struct ecore_spq_entry *p_ent = OSAL_NULL;
1442         struct ecore_sp_init_data init_data;
1443
1444         /* Get SPQ entry */
1445         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1446         init_data.cid = ecore_spq_get_cid(p_hwfn);
1447         init_data.opaque_fid = opaque_vfid;
1448         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1449
1450         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1451                                    COMMON_RAMROD_VF_STOP,
1452                                    PROTOCOLID_COMMON, &init_data);
1453         if (rc != ECORE_SUCCESS)
1454                 return rc;
1455
1456         p_ramrod = &p_ent->ramrod.vf_stop;
1457
1458         p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
1459
1460         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1461 }
1462
1463 /* Statistics related code */
1464 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1465                                              u32 *p_addr, u32 *p_len,
1466                                              u16 statistics_bin)
1467 {
1468         if (IS_PF(p_hwfn->p_dev)) {
1469                 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1470                     PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1471                 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1472         } else {
1473                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1474                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1475
1476                 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1477                 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1478         }
1479 }
1480
1481 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1482                                      struct ecore_ptt *p_ptt,
1483                                      struct ecore_eth_stats *p_stats,
1484                                      u16 statistics_bin)
1485 {
1486         struct eth_pstorm_per_queue_stat pstats;
1487         u32 pstats_addr = 0, pstats_len = 0;
1488
1489         __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1490                                          statistics_bin);
1491
1492         OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1493         ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1494
1495         p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1496         p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1497         p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1498         p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1499         p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1500         p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1501         p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1502 }
1503
1504 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1505                                      struct ecore_ptt *p_ptt,
1506                                      struct ecore_eth_stats *p_stats,
1507                                      u16 statistics_bin)
1508 {
1509         struct tstorm_per_port_stat tstats;
1510         u32 tstats_addr, tstats_len;
1511
1512         if (IS_PF(p_hwfn->p_dev)) {
1513                 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1514                     TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1515                 tstats_len = sizeof(struct tstorm_per_port_stat);
1516         } else {
1517                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1518                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1519
1520                 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1521                 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1522         }
1523
1524         OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1525         ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1526
1527         p_stats->mftag_filter_discards +=
1528             HILO_64_REGPAIR(tstats.mftag_filter_discard);
1529         p_stats->mac_filter_discards +=
1530             HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1531 }
1532
1533 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1534                                              u32 *p_addr, u32 *p_len,
1535                                              u16 statistics_bin)
1536 {
1537         if (IS_PF(p_hwfn->p_dev)) {
1538                 *p_addr = BAR0_MAP_REG_USDM_RAM +
1539                     USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1540                 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1541         } else {
1542                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1543                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1544
1545                 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1546                 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1547         }
1548 }
1549
1550 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1551                                      struct ecore_ptt *p_ptt,
1552                                      struct ecore_eth_stats *p_stats,
1553                                      u16 statistics_bin)
1554 {
1555         struct eth_ustorm_per_queue_stat ustats;
1556         u32 ustats_addr = 0, ustats_len = 0;
1557
1558         __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1559                                          statistics_bin);
1560
1561         OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1562         ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1563
1564         p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1565         p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1566         p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1567         p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1568         p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1569         p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1570 }
1571
1572 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1573                                              u32 *p_addr, u32 *p_len,
1574                                              u16 statistics_bin)
1575 {
1576         if (IS_PF(p_hwfn->p_dev)) {
1577                 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1578                     MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1579                 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1580         } else {
1581                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1582                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1583
1584                 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1585                 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1586         }
1587 }
1588
1589 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1590                                      struct ecore_ptt *p_ptt,
1591                                      struct ecore_eth_stats *p_stats,
1592                                      u16 statistics_bin)
1593 {
1594         struct eth_mstorm_per_queue_stat mstats;
1595         u32 mstats_addr = 0, mstats_len = 0;
1596
1597         __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1598                                          statistics_bin);
1599
1600         OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1601         ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1602
1603         p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1604         p_stats->packet_too_big_discard +=
1605             HILO_64_REGPAIR(mstats.packet_too_big_discard);
1606         p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1607         p_stats->tpa_coalesced_pkts +=
1608             HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1609         p_stats->tpa_coalesced_events +=
1610             HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1611         p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1612         p_stats->tpa_coalesced_bytes +=
1613             HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1614 }
1615
1616 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1617                                          struct ecore_ptt *p_ptt,
1618                                          struct ecore_eth_stats *p_stats)
1619 {
1620         struct port_stats port_stats;
1621         int j;
1622
1623         OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1624
1625         ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1626                           p_hwfn->mcp_info->port_addr +
1627                           OFFSETOF(struct public_port, stats),
1628                           sizeof(port_stats));
1629
1630         p_stats->rx_64_byte_packets += port_stats.pmm.r64;
1631         p_stats->rx_65_to_127_byte_packets += port_stats.pmm.r127;
1632         p_stats->rx_128_to_255_byte_packets += port_stats.pmm.r255;
1633         p_stats->rx_256_to_511_byte_packets += port_stats.pmm.r511;
1634         p_stats->rx_512_to_1023_byte_packets += port_stats.pmm.r1023;
1635         p_stats->rx_1024_to_1518_byte_packets += port_stats.pmm.r1518;
1636         p_stats->rx_1519_to_1522_byte_packets += port_stats.pmm.r1522;
1637         p_stats->rx_1519_to_2047_byte_packets += port_stats.pmm.r2047;
1638         p_stats->rx_2048_to_4095_byte_packets += port_stats.pmm.r4095;
1639         p_stats->rx_4096_to_9216_byte_packets += port_stats.pmm.r9216;
1640         p_stats->rx_9217_to_16383_byte_packets += port_stats.pmm.r16383;
1641         p_stats->rx_crc_errors += port_stats.pmm.rfcs;
1642         p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1643         p_stats->rx_pause_frames += port_stats.pmm.rxpf;
1644         p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
1645         p_stats->rx_align_errors += port_stats.pmm.raln;
1646         p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
1647         p_stats->rx_oversize_packets += port_stats.pmm.rovr;
1648         p_stats->rx_jabbers += port_stats.pmm.rjbr;
1649         p_stats->rx_undersize_packets += port_stats.pmm.rund;
1650         p_stats->rx_fragments += port_stats.pmm.rfrg;
1651         p_stats->tx_64_byte_packets += port_stats.pmm.t64;
1652         p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1653         p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1654         p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1655         p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1656         p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1657         p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1658         p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1659         p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1660         p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1661         p_stats->tx_pause_frames += port_stats.pmm.txpf;
1662         p_stats->tx_pfc_frames += port_stats.pmm.txpp;
1663         p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1664         p_stats->tx_total_collisions += port_stats.pmm.tncl;
1665         p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
1666         p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1667         p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1668         p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1669         p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1670         p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
1671         p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1672         p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1673         p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1674         p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1675         for (j = 0; j < 8; j++) {
1676                 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1677                 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1678         }
1679 }
1680
1681 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1682                              struct ecore_ptt *p_ptt,
1683                              struct ecore_eth_stats *stats,
1684                              u16 statistics_bin, bool b_get_port_stats)
1685 {
1686         __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1687         __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1688         __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1689         __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1690
1691 #ifndef ASIC_ONLY
1692         /* Avoid getting PORT stats for emulation. */
1693         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1694                 return;
1695 #endif
1696
1697         if (b_get_port_stats && p_hwfn->mcp_info)
1698                 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1699 }
1700
1701 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1702                                    struct ecore_eth_stats *stats)
1703 {
1704         u8 fw_vport = 0;
1705         int i;
1706
1707         OSAL_MEMSET(stats, 0, sizeof(*stats));
1708
1709         for_each_hwfn(p_dev, i) {
1710                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1711                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1712                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1713
1714                 if (IS_PF(p_dev)) {
1715                         /* The main vport index is relative first */
1716                         if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1717                                 DP_ERR(p_hwfn, "No vport available!\n");
1718                                 goto out;
1719                         }
1720                 }
1721
1722                 if (IS_PF(p_dev) && !p_ptt) {
1723                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1724                         continue;
1725                 }
1726
1727                 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1728                                         IS_PF(p_dev) ? true : false);
1729
1730 out:
1731                 if (IS_PF(p_dev))
1732                         ecore_ptt_release(p_hwfn, p_ptt);
1733         }
1734 }
1735
1736 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1737                            struct ecore_eth_stats *stats)
1738 {
1739         u32 i;
1740
1741         if (!p_dev) {
1742                 OSAL_MEMSET(stats, 0, sizeof(*stats));
1743                 return;
1744         }
1745
1746         _ecore_get_vport_stats(p_dev, stats);
1747
1748         if (!p_dev->reset_stats)
1749                 return;
1750
1751         /* Reduce the statistics baseline */
1752         for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1753                 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1754 }
1755
1756 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1757 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1758 {
1759         int i;
1760
1761         for_each_hwfn(p_dev, i) {
1762                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1763                 struct eth_mstorm_per_queue_stat mstats;
1764                 struct eth_ustorm_per_queue_stat ustats;
1765                 struct eth_pstorm_per_queue_stat pstats;
1766                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1767                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1768                 u32 addr = 0, len = 0;
1769
1770                 if (IS_PF(p_dev) && !p_ptt) {
1771                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1772                         continue;
1773                 }
1774
1775                 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1776                 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1777                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1778
1779                 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1780                 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1781                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1782
1783                 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1784                 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1785                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1786
1787                 if (IS_PF(p_dev))
1788                         ecore_ptt_release(p_hwfn, p_ptt);
1789         }
1790
1791         /* PORT statistics are not necessarily reset, so we need to
1792          * read and create a baseline for future statistics.
1793          */
1794         if (!p_dev->reset_stats)
1795                 DP_INFO(p_dev, "Reset stats not allocated\n");
1796         else
1797                 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
1798 }