drivers/net/qede/base/ecore_l2.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_chain.h"
  15 #include "ecore_spq.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_l2.h"
  19 #include "ecore_sp_commands.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "reg_addr.h"
  23 #include "ecore_int.h"
  24 #include "ecore_hw.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_sriov.h"
  27 #include "ecore_mcp.h"
  28
  29 #define ECORE_MAX_SGES_NUM 16
  30 #define CRC32_POLY 0x1edc6f41
  31
  32 struct ecore_l2_info {
  33         u32 queues;
  34         unsigned long **pp_qid_usage;
  35
  36         /* The lock is meant to synchronize access to the qid usage */
  37         osal_mutex_t lock;
  38 };
  39
  40 enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn)
  41 {
  42         struct ecore_l2_info *p_l2_info;
  43         unsigned long **pp_qids;
  44         u32 i;
  45
  46         if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
  47                 return ECORE_SUCCESS;
  48
  49         p_l2_info = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_l2_info));
  50         if (!p_l2_info)
  51                 return ECORE_NOMEM;
  52         p_hwfn->p_l2_info = p_l2_info;
  53
  54         if (IS_PF(p_hwfn->p_dev)) {
  55                 p_l2_info->queues = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
  56         } else {
  57                 u8 rx = 0, tx = 0;
  58
  59                 ecore_vf_get_num_rxqs(p_hwfn, &rx);
  60                 ecore_vf_get_num_txqs(p_hwfn, &tx);
  61
  62                 p_l2_info->queues = (u32)OSAL_MAX_T(u8, rx, tx);
  63         }
  64
  65         pp_qids = OSAL_VZALLOC(p_hwfn->p_dev,
  66                                sizeof(unsigned long *) *
  67                                p_l2_info->queues);
  68         if (pp_qids == OSAL_NULL)
  69                 return ECORE_NOMEM;
  70         p_l2_info->pp_qid_usage = pp_qids;
  71
  72         for (i = 0; i < p_l2_info->queues; i++) {
  73                 pp_qids[i] = OSAL_VZALLOC(p_hwfn->p_dev,
  74                                           MAX_QUEUES_PER_QZONE / 8);
  75                 if (pp_qids[i] == OSAL_NULL)
  76                         return ECORE_NOMEM;
  77         }
  78
  79 #ifdef CONFIG_ECORE_LOCK_ALLOC
  80         OSAL_MUTEX_ALLOC(p_hwfn, &p_l2_info->lock);
  81 #endif
  82
  83         return ECORE_SUCCESS;
  84 }
  85
  86 void ecore_l2_setup(struct ecore_hwfn *p_hwfn)
  87 {
  88         if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
  89                 return;
  90
  91         OSAL_MUTEX_INIT(&p_hwfn->p_l2_info->lock);
  92 }
  93
  94 void ecore_l2_free(struct ecore_hwfn *p_hwfn)
  95 {
  96         u32 i;
  97
  98         if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
  99                 return;
 100
 101         if (p_hwfn->p_l2_info == OSAL_NULL)
 102                 return;
 103
 104         if (p_hwfn->p_l2_info->pp_qid_usage == OSAL_NULL)
 105                 goto out_l2_info;
 106
 107         /* Free until hit first uninitialized entry */
 108         for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
 109                 if (p_hwfn->p_l2_info->pp_qid_usage[i] == OSAL_NULL)
 110                         break;
 111                 OSAL_VFREE(p_hwfn->p_dev,
 112                            p_hwfn->p_l2_info->pp_qid_usage[i]);
 113         }
 114
 115 #ifdef CONFIG_ECORE_LOCK_ALLOC
 116         /* Lock is last to initialize, if everything else was */
 117         if (i == p_hwfn->p_l2_info->queues)
 118                 OSAL_MUTEX_DEALLOC(&p_hwfn->p_l2_info->lock);
 119 #endif
 120
 121         OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info->pp_qid_usage);
 122
 123 out_l2_info:
 124         OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info);
 125         p_hwfn->p_l2_info = OSAL_NULL;
 126 }
 127
 128 /* TODO - we'll need locking around these... */
 129 static bool ecore_eth_queue_qid_usage_add(struct ecore_hwfn *p_hwfn,
 130                                           struct ecore_queue_cid *p_cid)
 131 {
 132         struct ecore_l2_info *p_l2_info = p_hwfn->p_l2_info;
 133         u16 queue_id = p_cid->rel.queue_id;
 134         bool b_rc = true;
 135         u8 first;
 136
 137         OSAL_MUTEX_ACQUIRE(&p_l2_info->lock);
 138
 139         if (queue_id > p_l2_info->queues) {
 140                 DP_NOTICE(p_hwfn, true,
 141                           "Requested to increase usage for qzone %04x out of %08x\n",
 142                           queue_id, p_l2_info->queues);
 143                 b_rc = false;
 144                 goto out;
 145         }
 146
 147         first = (u8)OSAL_FIND_FIRST_ZERO_BIT(p_l2_info->pp_qid_usage[queue_id],
 148                                              MAX_QUEUES_PER_QZONE);
 149         if (first >= MAX_QUEUES_PER_QZONE) {
 150                 b_rc = false;
 151                 goto out;
 152         }
 153
 154         OSAL_SET_BIT(first, p_l2_info->pp_qid_usage[queue_id]);
 155         p_cid->qid_usage_idx = first;
 156
 157 out:
 158         OSAL_MUTEX_RELEASE(&p_l2_info->lock);
 159         return b_rc;
 160 }
 161
 162 static void ecore_eth_queue_qid_usage_del(struct ecore_hwfn *p_hwfn,
 163                                           struct ecore_queue_cid *p_cid)
 164 {
 165         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_l2_info->lock);
 166
 167         OSAL_CLEAR_BIT(p_cid->qid_usage_idx,
 168                        p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
 169
 170         OSAL_MUTEX_RELEASE(&p_hwfn->p_l2_info->lock);
 171 }
 172
 173 void ecore_eth_queue_cid_release(struct ecore_hwfn *p_hwfn,
 174                                  struct ecore_queue_cid *p_cid)
 175 {
 176         bool b_legacy_vf = !!(p_cid->vf_legacy &
 177                               ECORE_QCID_LEGACY_VF_CID);
 178
 179         /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF.
 180          * For legacy vf-queues, the CID doesn't go through here.
 181          */
 182         if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
 183                 _ecore_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
 184
 185         /* VFs maintain the index inside queue-zone on their own */
 186         if (p_cid->vfid == ECORE_QUEUE_CID_PF)
 187                 ecore_eth_queue_qid_usage_del(p_hwfn, p_cid);
 188
 189         OSAL_VFREE(p_hwfn->p_dev, p_cid);
 190 }
 191
 192 /* The internal is only meant to be directly called by PFs initializeing CIDs
 193  * for their VFs.
 194  */
 195 static struct ecore_queue_cid *
 196 _ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn,
 197                         u16 opaque_fid, u32 cid,
 198                         struct ecore_queue_start_common_params *p_params,
 199                         bool b_is_rx,
 200                         struct ecore_queue_cid_vf_params *p_vf_params)
 201 {
 202         struct ecore_queue_cid *p_cid;
 203         enum _ecore_status_t rc;
 204
 205         p_cid = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_cid));
 206         if (p_cid == OSAL_NULL)
 207                 return OSAL_NULL;
 208
 209         p_cid->opaque_fid = opaque_fid;
 210         p_cid->cid = cid;
 211         p_cid->p_owner = p_hwfn;
 212
 213         /* Fill in parameters */
 214         p_cid->rel.vport_id = p_params->vport_id;
 215         p_cid->rel.queue_id = p_params->queue_id;
 216         p_cid->rel.stats_id = p_params->stats_id;
 217         p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
 218         p_cid->b_is_rx = b_is_rx;
 219         p_cid->sb_idx = p_params->sb_idx;
 220
 221         /* Fill-in bits related to VFs' queues if information was provided */
 222         if (p_vf_params != OSAL_NULL) {
 223                 p_cid->vfid = p_vf_params->vfid;
 224                 p_cid->vf_qid = p_vf_params->vf_qid;
 225                 p_cid->vf_legacy = p_vf_params->vf_legacy;
 226         } else {
 227                 p_cid->vfid = ECORE_QUEUE_CID_PF;
 228         }
 229
 230         /* Don't try calculating the absolute indices for VFs */
 231         if (IS_VF(p_hwfn->p_dev)) {
 232                 p_cid->abs = p_cid->rel;
 233
 234                 goto out;
 235         }
 236
 237         /* Calculate the engine-absolute indices of the resources.
 238          * The would guarantee they're valid later on.
 239          * In some cases [SBs] we already have the right values.
 240          */
 241         rc = ecore_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
 242         if (rc != ECORE_SUCCESS)
 243                 goto fail;
 244
 245         rc = ecore_fw_l2_queue(p_hwfn, p_cid->rel.queue_id,
 246                                &p_cid->abs.queue_id);
 247         if (rc != ECORE_SUCCESS)
 248                 goto fail;
 249
 250         /* In case of a PF configuring its VF's queues, the stats-id is already
 251          * absolute [since there's a single index that's suitable per-VF].
 252          */
 253         if (p_cid->vfid == ECORE_QUEUE_CID_PF) {
 254                 rc = ecore_fw_vport(p_hwfn, p_cid->rel.stats_id,
 255                                     &p_cid->abs.stats_id);
 256                 if (rc != ECORE_SUCCESS)
 257                         goto fail;
 258         } else {
 259                 p_cid->abs.stats_id = p_cid->rel.stats_id;
 260         }
 261
 262 out:
 263         /* VF-images have provided the qid_usage_idx on their own.
 264          * Otherwise, we need to allocate a unique one.
 265          */
 266         if (!p_vf_params) {
 267                 if (!ecore_eth_queue_qid_usage_add(p_hwfn, p_cid))
 268                         goto fail;
 269         } else {
 270                 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
 271         }
 272
 273         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 274                    "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
 275                    p_cid->opaque_fid, p_cid->cid,
 276                    p_cid->rel.vport_id, p_cid->abs.vport_id,
 277                    p_cid->rel.queue_id, p_cid->qid_usage_idx,
 278                    p_cid->abs.queue_id,
 279                    p_cid->rel.stats_id, p_cid->abs.stats_id,
 280                    p_cid->sb_igu_id, p_cid->sb_idx);
 281
 282         return p_cid;
 283
 284 fail:
 285         OSAL_VFREE(p_hwfn->p_dev, p_cid);
 286         return OSAL_NULL;
 287 }
 288
 289 struct ecore_queue_cid *
 290 ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
 291                        struct ecore_queue_start_common_params *p_params,
 292                        bool b_is_rx,
 293                        struct ecore_queue_cid_vf_params *p_vf_params)
 294 {
 295         struct ecore_queue_cid *p_cid;
 296         u8 vfid = ECORE_CXT_PF_CID;
 297         bool b_legacy_vf = false;
 298         u32 cid = 0;
 299
 300         /* In case of legacy VFs, The CID can be derived from the additional
 301          * VF parameters - the VF assumes queue X uses CID X, so we can simply
 302          * use the vf_qid for this purpose as well.
 303          */
 304         if (p_vf_params) {
 305                 vfid = p_vf_params->vfid;
 306
 307                 if (p_vf_params->vf_legacy &
 308                     ECORE_QCID_LEGACY_VF_CID) {
 309                         b_legacy_vf = true;
 310                         cid = p_vf_params->vf_qid;
 311                 }
 312         }
 313
 314         /* Get a unique firmware CID for this queue, in case it's a PF.
 315          * VF's don't need a CID as the queue configuration will be done
 316          * by PF.
 317          */
 318         if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf) {
 319                 if (_ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
 320                                            &cid, vfid) != ECORE_SUCCESS) {
 321                         DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 322                         return OSAL_NULL;
 323                 }
 324         }
 325
 326         p_cid = _ecore_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
 327                                         p_params, b_is_rx, p_vf_params);
 328         if ((p_cid == OSAL_NULL) && IS_PF(p_hwfn->p_dev) && !b_legacy_vf)
 329                 _ecore_cxt_release_cid(p_hwfn, cid, vfid);
 330
 331         return p_cid;
 332 }
 333
 334 static struct ecore_queue_cid *
 335 ecore_eth_queue_to_cid_pf(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
 336                           bool b_is_rx,
 337                           struct ecore_queue_start_common_params *p_params)
 338 {
 339         return ecore_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
 340                                       OSAL_NULL);
 341 }
 342
 343 enum _ecore_status_t
 344 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
 345                          struct ecore_sp_vport_start_params *p_params)
 346 {
 347         struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
 348         struct ecore_spq_entry *p_ent = OSAL_NULL;
 349         struct ecore_sp_init_data init_data;
 350         u16 rx_mode = 0, tx_err = 0;
 351         u8 abs_vport_id = 0;
 352         enum _ecore_status_t rc = ECORE_NOTIMPL;
 353
 354         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 355         if (rc != ECORE_SUCCESS)
 356                 return rc;
 357
 358         /* Get SPQ entry */
 359         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 360         init_data.cid = ecore_spq_get_cid(p_hwfn);
 361         init_data.opaque_fid = p_params->opaque_fid;
 362         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 363
 364         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 365                                    ETH_RAMROD_VPORT_START,
 366                                    PROTOCOLID_ETH, &init_data);
 367         if (rc != ECORE_SUCCESS)
 368                 return rc;
 369
 370         p_ramrod = &p_ent->ramrod.vport_start;
 371         p_ramrod->vport_id = abs_vport_id;
 372
 373         p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
 374         p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
 375         p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
 376         p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
 377         p_ramrod->untagged = p_params->only_untagged;
 378         p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
 379
 380         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
 381         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
 382
 383         p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
 384
 385         /* Handle requests for strict behavior on transmission errors */
 386         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE,
 387                   p_params->b_err_illegal_vlan_mode ?
 388                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 389         SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL,
 390                   p_params->b_err_small_pkt ?
 391                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 392         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR,
 393                   p_params->b_err_anti_spoof ?
 394                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 395         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS,
 396                   p_params->b_err_illegal_inband_mode ?
 397                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 398         SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG,
 399                   p_params->b_err_vlan_insert_with_inband ?
 400                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 401         SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION,
 402                   p_params->b_err_big_pkt ?
 403                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 404         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME,
 405                   p_params->b_err_ctrl_frame ?
 406                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
 407         p_ramrod->tx_err_behav.values = OSAL_CPU_TO_LE16(tx_err);
 408
 409         /* TPA related fields */
 410         OSAL_MEMSET(&p_ramrod->tpa_param, 0,
 411                     sizeof(struct eth_vport_tpa_param));
 412         p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
 413
 414         switch (p_params->tpa_mode) {
 415         case ECORE_TPA_MODE_GRO:
 416                 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 417                 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
 418                 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
 419                 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
 420                 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
 421                 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
 422                 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
 423                 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
 424                 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
 425                 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
 426                 break;
 427         default:
 428                 break;
 429         }
 430
 431         p_ramrod->tx_switching_en = p_params->tx_switching;
 432 #ifndef ASIC_ONLY
 433         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
 434                 p_ramrod->tx_switching_en = 0;
 435 #endif
 436
 437         p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
 438         p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
 439
 440         /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
 441         p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_params->concrete_fid);
 442
 443         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 444 }
 445
 446 enum _ecore_status_t
 447 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
 448                      struct ecore_sp_vport_start_params *p_params)
 449 {
 450         if (IS_VF(p_hwfn->p_dev))
 451                 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
 452                                                p_params->mtu,
 453                                                p_params->remove_inner_vlan,
 454                                                p_params->tpa_mode,
 455                                                p_params->max_buffers_per_cqe,
 456                                                p_params->only_untagged);
 457
 458         return ecore_sp_eth_vport_start(p_hwfn, p_params);
 459 }
 460
 461 static enum _ecore_status_t
 462 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
 463                           struct vport_update_ramrod_data *p_ramrod,
 464                           struct ecore_rss_params *p_rss)
 465 {
 466         struct eth_vport_rss_config *p_config;
 467         int i, table_size;
 468         enum _ecore_status_t rc = ECORE_SUCCESS;
 469
 470         if (!p_rss) {
 471                 p_ramrod->common.update_rss_flg = 0;
 472                 return rc;
 473         }
 474         p_config = &p_ramrod->rss_config;
 475
 476         OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
 477                           ETH_RSS_IND_TABLE_ENTRIES_NUM);
 478
 479         rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
 480         if (rc != ECORE_SUCCESS)
 481                 return rc;
 482
 483         p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
 484         p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
 485         p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
 486         p_config->update_rss_key = p_rss->update_rss_key;
 487
 488         p_config->rss_mode = p_rss->rss_enable ?
 489             ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
 490
 491         p_config->capabilities = 0;
 492
 493         SET_FIELD(p_config->capabilities,
 494                   ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
 495                   !!(p_rss->rss_caps & ECORE_RSS_IPV4));
 496         SET_FIELD(p_config->capabilities,
 497                   ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
 498                   !!(p_rss->rss_caps & ECORE_RSS_IPV6));
 499         SET_FIELD(p_config->capabilities,
 500                   ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
 501                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
 502         SET_FIELD(p_config->capabilities,
 503                   ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
 504                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
 505         SET_FIELD(p_config->capabilities,
 506                   ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
 507                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
 508         SET_FIELD(p_config->capabilities,
 509                   ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
 510                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
 511         p_config->tbl_size = p_rss->rss_table_size_log;
 512         p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
 513
 514         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 515                    "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
 516                    p_ramrod->common.update_rss_flg,
 517                    p_config->rss_mode,
 518                    p_config->update_rss_capabilities,
 519                    p_config->capabilities,
 520                    p_config->update_rss_ind_table, p_config->update_rss_key);
 521
 522         table_size = OSAL_MIN_T(int, ECORE_RSS_IND_TABLE_SIZE,
 523                                 1 << p_config->tbl_size);
 524         for (i = 0; i < table_size; i++) {
 525                 struct ecore_queue_cid *p_queue = p_rss->rss_ind_table[i];
 526
 527                 if (!p_queue)
 528                         return ECORE_INVAL;
 529
 530                 p_config->indirection_table[i] =
 531                                 OSAL_CPU_TO_LE16(p_queue->abs.queue_id);
 532         }
 533
 534         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 535                    "Configured RSS indirection table [%d entries]:\n",
 536                    table_size);
 537         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i += 0x10) {
 538                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 539                            "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
 540                            OSAL_LE16_TO_CPU(p_config->indirection_table[i]),
 541                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 1]),
 542                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 2]),
 543                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 3]),
 544                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 4]),
 545                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 5]),
 546                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 6]),
 547                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 7]),
 548                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 8]),
 549                            OSAL_LE16_TO_CPU(p_config->indirection_table[i + 9]),
 550                           OSAL_LE16_TO_CPU(p_config->indirection_table[i + 10]),
 551                           OSAL_LE16_TO_CPU(p_config->indirection_table[i + 11]),
 552                           OSAL_LE16_TO_CPU(p_config->indirection_table[i + 12]),
 553                           OSAL_LE16_TO_CPU(p_config->indirection_table[i + 13]),
 554                           OSAL_LE16_TO_CPU(p_config->indirection_table[i + 14]),
 555                          OSAL_LE16_TO_CPU(p_config->indirection_table[i + 15]));
 556         }
 557
 558         for (i = 0; i < 10; i++)
 559                 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
 560
 561         return rc;
 562 }
 563
 564 static void
 565 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
 566                             struct vport_update_ramrod_data *p_ramrod,
 567                             struct ecore_filter_accept_flags accept_flags)
 568 {
 569         p_ramrod->common.update_rx_mode_flg =
 570                                         accept_flags.update_rx_mode_config;
 571         p_ramrod->common.update_tx_mode_flg =
 572                                         accept_flags.update_tx_mode_config;
 573
 574 #ifndef ASIC_ONLY
 575         /* On B0 emulation we cannot enable Tx, since this would cause writes
 576          * to PVFC HW block which isn't implemented in emulation.
 577          */
 578         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 579                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 580                            "Non-Asic - prevent Tx mode in vport update\n");
 581                 p_ramrod->common.update_tx_mode_flg = 0;
 582         }
 583 #endif
 584
 585         /* Set Rx mode accept flags */
 586         if (p_ramrod->common.update_rx_mode_flg) {
 587                 u8 accept_filter = accept_flags.rx_accept_filter;
 588                 u16 state = 0;
 589
 590                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
 591                           !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
 592                            !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
 593
 594                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
 595                           !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
 596
 597                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
 598                           !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
 599                             !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 600
 601                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
 602                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 603                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 604
 605                 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
 606                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 607
 608                 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
 609                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 610                            "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n",
 611                            p_ramrod->common.vport_id, state);
 612         }
 613
 614         /* Set Tx mode accept flags */
 615         if (p_ramrod->common.update_tx_mode_flg) {
 616                 u8 accept_filter = accept_flags.tx_accept_filter;
 617                 u16 state = 0;
 618
 619                 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
 620                           !!(accept_filter & ECORE_ACCEPT_NONE));
 621
 622                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
 623                           !!(accept_filter & ECORE_ACCEPT_NONE));
 624
 625                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
 626                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 627                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 628
 629                 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
 630                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 631
 632                 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
 633                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 634                            "vport[%02x] p_ramrod->tx_mode.state = 0x%x\n",
 635                            p_ramrod->common.vport_id, state);
 636         }
 637 }
 638
 639 static void
 640 ecore_sp_vport_update_sge_tpa(struct vport_update_ramrod_data *p_ramrod,
 641                               struct ecore_sge_tpa_params *p_params)
 642 {
 643         struct eth_vport_tpa_param *p_tpa;
 644
 645         if (!p_params) {
 646                 p_ramrod->common.update_tpa_param_flg = 0;
 647                 p_ramrod->common.update_tpa_en_flg = 0;
 648                 p_ramrod->common.update_tpa_param_flg = 0;
 649                 return;
 650         }
 651
 652         p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
 653         p_tpa = &p_ramrod->tpa_param;
 654         p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
 655         p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
 656         p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
 657         p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
 658
 659         p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
 660         p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
 661         p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
 662         p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
 663         p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
 664         p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
 665         p_tpa->tpa_max_size = p_params->tpa_max_size;
 666         p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
 667         p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
 668 }
 669
 670 static void
 671 ecore_sp_update_mcast_bin(struct vport_update_ramrod_data *p_ramrod,
 672                           struct ecore_sp_vport_update_params *p_params)
 673 {
 674         int i;
 675
 676         OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
 677                     sizeof(p_ramrod->approx_mcast.bins));
 678
 679         if (!p_params->update_approx_mcast_flg)
 680                 return;
 681
 682         p_ramrod->common.update_approx_mcast_flg = 1;
 683         for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
 684                 u32 *p_bins = (u32 *)p_params->bins;
 685
 686                 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
 687         }
 688 }
 689
 690 enum _ecore_status_t
 691 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
 692                       struct ecore_sp_vport_update_params *p_params,
 693                       enum spq_mode comp_mode,
 694                       struct ecore_spq_comp_cb *p_comp_data)
 695 {
 696         struct ecore_rss_params *p_rss_params = p_params->rss_params;
 697         struct vport_update_ramrod_data_cmn *p_cmn;
 698         struct ecore_sp_init_data init_data;
 699         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
 700         struct ecore_spq_entry *p_ent = OSAL_NULL;
 701         u8 abs_vport_id = 0, val;
 702         enum _ecore_status_t rc = ECORE_NOTIMPL;
 703
 704         if (IS_VF(p_hwfn->p_dev)) {
 705                 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
 706                 return rc;
 707         }
 708
 709         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 710         if (rc != ECORE_SUCCESS)
 711                 return rc;
 712
 713         /* Get SPQ entry */
 714         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 715         init_data.cid = ecore_spq_get_cid(p_hwfn);
 716         init_data.opaque_fid = p_params->opaque_fid;
 717         init_data.comp_mode = comp_mode;
 718         init_data.p_comp_data = p_comp_data;
 719
 720         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 721                                    ETH_RAMROD_VPORT_UPDATE,
 722                                    PROTOCOLID_ETH, &init_data);
 723         if (rc != ECORE_SUCCESS)
 724                 return rc;
 725
 726         /* Copy input params to ramrod according to FW struct */
 727         p_ramrod = &p_ent->ramrod.vport_update;
 728         p_cmn = &p_ramrod->common;
 729
 730         p_cmn->vport_id = abs_vport_id;
 731
 732         p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
 733         p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
 734         p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
 735         p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
 736
 737         p_cmn->accept_any_vlan = p_params->accept_any_vlan;
 738         val = p_params->update_accept_any_vlan_flg;
 739         p_cmn->update_accept_any_vlan_flg = val;
 740
 741         p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
 742         val = p_params->update_inner_vlan_removal_flg;
 743         p_cmn->update_inner_vlan_removal_en_flg = val;
 744
 745         p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
 746         val = p_params->update_default_vlan_enable_flg;
 747         p_cmn->update_default_vlan_en_flg = val;
 748
 749         p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
 750         p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
 751
 752         p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
 753
 754         p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
 755
 756 #ifndef ASIC_ONLY
 757         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 758                 if (p_ramrod->common.tx_switching_en ||
 759                     p_ramrod->common.update_tx_switching_en_flg) {
 760                         DP_NOTICE(p_hwfn, false,
 761                                   "FPGA - why are we seeing tx-switching? Overriding it\n");
 762                         p_ramrod->common.tx_switching_en = 0;
 763                         p_ramrod->common.update_tx_switching_en_flg = 1;
 764                 }
 765 #endif
 766         p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
 767
 768         p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
 769         val = p_params->update_anti_spoofing_en_flg;
 770         p_ramrod->common.update_anti_spoofing_en_flg = val;
 771
 772         rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
 773         if (rc != ECORE_SUCCESS) {
 774                 /* Return spq entry which is taken in ecore_sp_init_request()*/
 775                 ecore_spq_return_entry(p_hwfn, p_ent);
 776                 return rc;
 777         }
 778
 779         /* Update mcast bins for VFs, PF doesn't use this functionality */
 780         ecore_sp_update_mcast_bin(p_ramrod, p_params);
 781
 782         ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
 783         ecore_sp_vport_update_sge_tpa(p_ramrod, p_params->sge_tpa_params);
 784         if (p_params->mtu) {
 785                 p_ramrod->common.update_mtu_flg = 1;
 786                 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
 787         }
 788
 789         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 790 }
 791
 792 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
 793                                          u16 opaque_fid, u8 vport_id)
 794 {
 795         struct vport_stop_ramrod_data *p_ramrod;
 796         struct ecore_sp_init_data init_data;
 797         struct ecore_spq_entry *p_ent;
 798         u8 abs_vport_id = 0;
 799         enum _ecore_status_t rc;
 800
 801         if (IS_VF(p_hwfn->p_dev))
 802                 return ecore_vf_pf_vport_stop(p_hwfn);
 803
 804         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 805         if (rc != ECORE_SUCCESS)
 806                 return rc;
 807
 808         /* Get SPQ entry */
 809         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 810         init_data.cid = ecore_spq_get_cid(p_hwfn);
 811         init_data.opaque_fid = opaque_fid;
 812         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 813
 814         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 815                                    ETH_RAMROD_VPORT_STOP,
 816                                    PROTOCOLID_ETH, &init_data);
 817         if (rc != ECORE_SUCCESS)
 818                 return rc;
 819
 820         p_ramrod = &p_ent->ramrod.vport_stop;
 821         p_ramrod->vport_id = abs_vport_id;
 822
 823         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 824 }
 825
 826 static enum _ecore_status_t
 827 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
 828                          struct ecore_filter_accept_flags *p_accept_flags)
 829 {
 830         struct ecore_sp_vport_update_params s_params;
 831
 832         OSAL_MEMSET(&s_params, 0, sizeof(s_params));
 833         OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
 834                     sizeof(struct ecore_filter_accept_flags));
 835
 836         return ecore_vf_pf_vport_update(p_hwfn, &s_params);
 837 }
 838
 839 enum _ecore_status_t
 840 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
 841                         u8 vport,
 842                         struct ecore_filter_accept_flags accept_flags,
 843                         u8 update_accept_any_vlan,
 844                         u8 accept_any_vlan,
 845                         enum spq_mode comp_mode,
 846                         struct ecore_spq_comp_cb *p_comp_data)
 847 {
 848         struct ecore_sp_vport_update_params vport_update_params;
 849         int i, rc;
 850
 851         /* Prepare and send the vport rx_mode change */
 852         OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
 853         vport_update_params.vport_id = vport;
 854         vport_update_params.accept_flags = accept_flags;
 855         vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
 856         vport_update_params.accept_any_vlan = accept_any_vlan;
 857
 858         for_each_hwfn(p_dev, i) {
 859                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 860
 861                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 862
 863                 if (IS_VF(p_dev)) {
 864                         rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
 865                         if (rc != ECORE_SUCCESS)
 866                                 return rc;
 867                         continue;
 868                 }
 869
 870                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
 871                                            comp_mode, p_comp_data);
 872                 if (rc != ECORE_SUCCESS) {
 873                         DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
 874                         return rc;
 875                 }
 876
 877                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 878                            "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
 879                            accept_flags.rx_accept_filter,
 880                            accept_flags.tx_accept_filter);
 881
 882                 if (update_accept_any_vlan)
 883                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 884                                    "accept_any_vlan=%d configured\n",
 885                                    accept_any_vlan);
 886         }
 887
 888         return 0;
 889 }
 890
 891 enum _ecore_status_t
 892 ecore_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
 893                            struct ecore_queue_cid *p_cid,
 894                            u16 bd_max_bytes,
 895                            dma_addr_t bd_chain_phys_addr,
 896                            dma_addr_t cqe_pbl_addr,
 897                            u16 cqe_pbl_size)
 898 {
 899         struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 900         struct ecore_spq_entry *p_ent = OSAL_NULL;
 901         struct ecore_sp_init_data init_data;
 902         enum _ecore_status_t rc = ECORE_NOTIMPL;
 903
 904         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 905                    "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 906                    p_cid->opaque_fid, p_cid->cid, p_cid->abs.queue_id,
 907                    p_cid->abs.vport_id, p_cid->sb_igu_id);
 908
 909         /* Get SPQ entry */
 910         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 911         init_data.cid = p_cid->cid;
 912         init_data.opaque_fid = p_cid->opaque_fid;
 913         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 914
 915         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 916                                    ETH_RAMROD_RX_QUEUE_START,
 917                                    PROTOCOLID_ETH, &init_data);
 918         if (rc != ECORE_SUCCESS)
 919                 return rc;
 920
 921         p_ramrod = &p_ent->ramrod.rx_queue_start;
 922
 923         p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id);
 924         p_ramrod->sb_index = p_cid->sb_idx;
 925         p_ramrod->vport_id = p_cid->abs.vport_id;
 926         p_ramrod->stats_counter_id = p_cid->abs.stats_id;
 927         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
 928         p_ramrod->complete_cqe_flg = 0;
 929         p_ramrod->complete_event_flg = 1;
 930
 931         p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
 932         DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
 933
 934         p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
 935         DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
 936
 937         if (p_cid->vfid != ECORE_QUEUE_CID_PF) {
 938                 bool b_legacy_vf = !!(p_cid->vf_legacy &
 939                                       ECORE_QCID_LEGACY_VF_RX_PROD);
 940
 941                 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
 942                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 943                            "Queue%s is meant for VF rxq[%02x]\n",
 944                            b_legacy_vf ? " [legacy]" : "",
 945                            p_cid->vf_qid);
 946                 p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
 947         }
 948
 949         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 950 }
 951
 952 static enum _ecore_status_t
 953 ecore_eth_pf_rx_queue_start(struct ecore_hwfn *p_hwfn,
 954                             struct ecore_queue_cid *p_cid,
 955                             u16 bd_max_bytes,
 956                             dma_addr_t bd_chain_phys_addr,
 957                             dma_addr_t cqe_pbl_addr,
 958                             u16 cqe_pbl_size,
 959                             void OSAL_IOMEM * *pp_prod)
 960 {
 961         u32 init_prod_val = 0;
 962
 963         *pp_prod = (u8 OSAL_IOMEM *)
 964                     p_hwfn->regview +
 965                     GTT_BAR0_MAP_REG_MSDM_RAM +
 966                     MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
 967
 968         /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
 969         __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
 970                           (u32 *)(&init_prod_val));
 971
 972         return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid,
 973                                           bd_max_bytes,
 974                                           bd_chain_phys_addr,
 975                                           cqe_pbl_addr, cqe_pbl_size);
 976 }
 977
 978 enum _ecore_status_t
 979 ecore_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
 980                          u16 opaque_fid,
 981                          struct ecore_queue_start_common_params *p_params,
 982                          u16 bd_max_bytes,
 983                          dma_addr_t bd_chain_phys_addr,
 984                          dma_addr_t cqe_pbl_addr,
 985                          u16 cqe_pbl_size,
 986                          struct ecore_rxq_start_ret_params *p_ret_params)
 987 {
 988         struct ecore_queue_cid *p_cid;
 989         enum _ecore_status_t rc;
 990
 991         /* Allocate a CID for the queue */
 992         p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
 993         if (p_cid == OSAL_NULL)
 994                 return ECORE_NOMEM;
 995
 996         if (IS_PF(p_hwfn->p_dev))
 997                 rc = ecore_eth_pf_rx_queue_start(p_hwfn, p_cid,
 998                                                  bd_max_bytes,
 999                                                  bd_chain_phys_addr,
1000                                                  cqe_pbl_addr, cqe_pbl_size,
1001                                                  &p_ret_params->p_prod);
1002         else
1003                 rc = ecore_vf_pf_rxq_start(p_hwfn, p_cid,
1004                                            bd_max_bytes,
1005                                            bd_chain_phys_addr,
1006                                            cqe_pbl_addr,
1007                                            cqe_pbl_size,
1008                                            &p_ret_params->p_prod);
1009
1010         /* Provide the caller with a reference to as handler */
1011         if (rc != ECORE_SUCCESS)
1012                 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1013         else
1014                 p_ret_params->p_handle = (void *)p_cid;
1015
1016         return rc;
1017 }
1018
1019 enum _ecore_status_t
1020 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
1021                               void **pp_rxq_handles,
1022                               u8 num_rxqs,
1023                               u8 complete_cqe_flg,
1024                               u8 complete_event_flg,
1025                               enum spq_mode comp_mode,
1026                               struct ecore_spq_comp_cb *p_comp_data)
1027 {
1028         struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
1029         struct ecore_spq_entry *p_ent = OSAL_NULL;
1030         struct ecore_sp_init_data init_data;
1031         struct ecore_queue_cid *p_cid;
1032         enum _ecore_status_t rc = ECORE_NOTIMPL;
1033         u8 i;
1034
1035         if (IS_VF(p_hwfn->p_dev))
1036                 return ecore_vf_pf_rxqs_update(p_hwfn,
1037                                                (struct ecore_queue_cid **)
1038                                                pp_rxq_handles,
1039                                                num_rxqs,
1040                                                complete_cqe_flg,
1041                                                complete_event_flg);
1042
1043         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1044         init_data.comp_mode = comp_mode;
1045         init_data.p_comp_data = p_comp_data;
1046
1047         for (i = 0; i < num_rxqs; i++) {
1048                 p_cid = ((struct ecore_queue_cid **)pp_rxq_handles)[i];
1049
1050                 /* Get SPQ entry */
1051                 init_data.cid = p_cid->cid;
1052                 init_data.opaque_fid = p_cid->opaque_fid;
1053
1054                 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1055                                            ETH_RAMROD_RX_QUEUE_UPDATE,
1056                                            PROTOCOLID_ETH, &init_data);
1057                 if (rc != ECORE_SUCCESS)
1058                         return rc;
1059
1060                 p_ramrod = &p_ent->ramrod.rx_queue_update;
1061                 p_ramrod->vport_id = p_cid->abs.vport_id;
1062
1063                 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1064                 p_ramrod->complete_cqe_flg = complete_cqe_flg;
1065                 p_ramrod->complete_event_flg = complete_event_flg;
1066
1067                 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1068                 if (rc != ECORE_SUCCESS)
1069                         return rc;
1070         }
1071
1072         return rc;
1073 }
1074
1075 static enum _ecore_status_t
1076 ecore_eth_pf_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1077                            struct ecore_queue_cid *p_cid,
1078                            bool b_eq_completion_only,
1079                            bool b_cqe_completion)
1080 {
1081         struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
1082         struct ecore_spq_entry *p_ent = OSAL_NULL;
1083         struct ecore_sp_init_data init_data;
1084         enum _ecore_status_t rc;
1085
1086         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1087         init_data.cid = p_cid->cid;
1088         init_data.opaque_fid = p_cid->opaque_fid;
1089         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1090
1091         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1092                                    ETH_RAMROD_RX_QUEUE_STOP,
1093                                    PROTOCOLID_ETH, &init_data);
1094         if (rc != ECORE_SUCCESS)
1095                 return rc;
1096
1097         p_ramrod = &p_ent->ramrod.rx_queue_stop;
1098         p_ramrod->vport_id = p_cid->abs.vport_id;
1099         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1100
1101         /* Cleaning the queue requires the completion to arrive there.
1102          * In addition, VFs require the answer to come as eqe to PF.
1103          */
1104         p_ramrod->complete_cqe_flg = ((p_cid->vfid == ECORE_QUEUE_CID_PF) &&
1105                                       !b_eq_completion_only) ||
1106                                      b_cqe_completion;
1107         p_ramrod->complete_event_flg = (p_cid->vfid != ECORE_QUEUE_CID_PF) ||
1108                                        b_eq_completion_only;
1109
1110         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1111 }
1112
1113 enum _ecore_status_t ecore_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
1114                                              void *p_rxq,
1115                                              bool eq_completion_only,
1116                                              bool cqe_completion)
1117 {
1118         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_rxq;
1119         enum _ecore_status_t rc = ECORE_NOTIMPL;
1120
1121         if (IS_PF(p_hwfn->p_dev))
1122                 rc = ecore_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1123                                                 eq_completion_only,
1124                                                 cqe_completion);
1125         else
1126                 rc = ecore_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1127
1128         if (rc == ECORE_SUCCESS)
1129                 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1130         return rc;
1131 }
1132
1133 enum _ecore_status_t
1134 ecore_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
1135                            struct ecore_queue_cid *p_cid,
1136                            dma_addr_t pbl_addr, u16 pbl_size,
1137                            u16 pq_id)
1138 {
1139         struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
1140         struct ecore_spq_entry *p_ent = OSAL_NULL;
1141         struct ecore_sp_init_data init_data;
1142         enum _ecore_status_t rc = ECORE_NOTIMPL;
1143
1144         /* Get SPQ entry */
1145         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1146         init_data.cid = p_cid->cid;
1147         init_data.opaque_fid = p_cid->opaque_fid;
1148         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1149
1150         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1151                                    ETH_RAMROD_TX_QUEUE_START,
1152                                    PROTOCOLID_ETH, &init_data);
1153         if (rc != ECORE_SUCCESS)
1154                 return rc;
1155
1156         p_ramrod = &p_ent->ramrod.tx_queue_start;
1157         p_ramrod->vport_id = p_cid->abs.vport_id;
1158
1159         p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id);
1160         p_ramrod->sb_index = p_cid->sb_idx;
1161         p_ramrod->stats_counter_id = p_cid->abs.stats_id;
1162
1163         p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1164         p_ramrod->same_as_last_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id);
1165
1166         p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
1167         DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
1168
1169         p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
1170
1171         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1172 }
1173
1174 static enum _ecore_status_t
1175 ecore_eth_pf_tx_queue_start(struct ecore_hwfn *p_hwfn,
1176                             struct ecore_queue_cid *p_cid,
1177                             u8 tc,
1178                             dma_addr_t pbl_addr, u16 pbl_size,
1179                             void OSAL_IOMEM * *pp_doorbell)
1180 {
1181         enum _ecore_status_t rc;
1182
1183         /* TODO - set tc in the pq_params for multi-cos */
1184         rc = ecore_eth_txq_start_ramrod(p_hwfn, p_cid,
1185                                         pbl_addr, pbl_size,
1186                                         ecore_get_cm_pq_idx_mcos(p_hwfn, tc));
1187         if (rc != ECORE_SUCCESS)
1188                 return rc;
1189
1190         /* Provide the caller with the necessary return values */
1191         *pp_doorbell = (u8 OSAL_IOMEM *)
1192                        p_hwfn->doorbells +
1193                        DB_ADDR(p_cid->cid, DQ_DEMS_LEGACY);
1194
1195         return ECORE_SUCCESS;
1196 }
1197
1198 enum _ecore_status_t
1199 ecore_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, u16 opaque_fid,
1200                          struct ecore_queue_start_common_params *p_params,
1201                          u8 tc,
1202                          dma_addr_t pbl_addr, u16 pbl_size,
1203                          struct ecore_txq_start_ret_params *p_ret_params)
1204 {
1205         struct ecore_queue_cid *p_cid;
1206         enum _ecore_status_t rc;
1207
1208         p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
1209         if (p_cid == OSAL_NULL)
1210                 return ECORE_INVAL;
1211
1212         if (IS_PF(p_hwfn->p_dev))
1213                 rc = ecore_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1214                                                  pbl_addr, pbl_size,
1215                                                  &p_ret_params->p_doorbell);
1216         else
1217                 rc = ecore_vf_pf_txq_start(p_hwfn, p_cid,
1218                                            pbl_addr, pbl_size,
1219                                            &p_ret_params->p_doorbell);
1220
1221         if (rc != ECORE_SUCCESS)
1222                 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1223         else
1224                 p_ret_params->p_handle = (void *)p_cid;
1225
1226         return rc;
1227 }
1228
1229 static enum _ecore_status_t
1230 ecore_eth_pf_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1231                            struct ecore_queue_cid *p_cid)
1232 {
1233         struct ecore_spq_entry *p_ent = OSAL_NULL;
1234         struct ecore_sp_init_data init_data;
1235         enum _ecore_status_t rc;
1236
1237         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1238         init_data.cid = p_cid->cid;
1239         init_data.opaque_fid = p_cid->opaque_fid;
1240         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1241
1242         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1243                                    ETH_RAMROD_TX_QUEUE_STOP,
1244                                    PROTOCOLID_ETH, &init_data);
1245         if (rc != ECORE_SUCCESS)
1246                 return rc;
1247
1248         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1249 }
1250
1251 enum _ecore_status_t ecore_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
1252                                              void *p_handle)
1253 {
1254         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
1255         enum _ecore_status_t rc;
1256
1257         if (IS_PF(p_hwfn->p_dev))
1258                 rc = ecore_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1259         else
1260                 rc = ecore_vf_pf_txq_stop(p_hwfn, p_cid);
1261
1262         if (rc == ECORE_SUCCESS)
1263                 ecore_eth_queue_cid_release(p_hwfn, p_cid);
1264         return rc;
1265 }
1266
1267 static enum eth_filter_action
1268 ecore_filter_action(enum ecore_filter_opcode opcode)
1269 {
1270         enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1271
1272         switch (opcode) {
1273         case ECORE_FILTER_ADD:
1274                 action = ETH_FILTER_ACTION_ADD;
1275                 break;
1276         case ECORE_FILTER_REMOVE:
1277                 action = ETH_FILTER_ACTION_REMOVE;
1278                 break;
1279         case ECORE_FILTER_FLUSH:
1280                 action = ETH_FILTER_ACTION_REMOVE_ALL;
1281                 break;
1282         default:
1283                 action = MAX_ETH_FILTER_ACTION;
1284         }
1285
1286         return action;
1287 }
1288
1289 static enum _ecore_status_t
1290 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1291                           u16 opaque_fid,
1292                           struct ecore_filter_ucast *p_filter_cmd,
1293                           struct vport_filter_update_ramrod_data **pp_ramrod,
1294                           struct ecore_spq_entry **pp_ent,
1295                           enum spq_mode comp_mode,
1296                           struct ecore_spq_comp_cb *p_comp_data)
1297 {
1298         u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1299         struct vport_filter_update_ramrod_data *p_ramrod;
1300         struct eth_filter_cmd *p_first_filter;
1301         struct eth_filter_cmd *p_second_filter;
1302         struct ecore_sp_init_data init_data;
1303         enum eth_filter_action action;
1304         enum _ecore_status_t rc;
1305
1306         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1307                             &vport_to_remove_from);
1308         if (rc != ECORE_SUCCESS)
1309                 return rc;
1310
1311         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1312                             &vport_to_add_to);
1313         if (rc != ECORE_SUCCESS)
1314                 return rc;
1315
1316         /* Get SPQ entry */
1317         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1318         init_data.cid = ecore_spq_get_cid(p_hwfn);
1319         init_data.opaque_fid = opaque_fid;
1320         init_data.comp_mode = comp_mode;
1321         init_data.p_comp_data = p_comp_data;
1322
1323         rc = ecore_sp_init_request(p_hwfn, pp_ent,
1324                                    ETH_RAMROD_FILTERS_UPDATE,
1325                                    PROTOCOLID_ETH, &init_data);
1326         if (rc != ECORE_SUCCESS)
1327                 return rc;
1328
1329         *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1330         p_ramrod = *pp_ramrod;
1331         p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1332         p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1333
1334 #ifndef ASIC_ONLY
1335         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1336                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1337                            "Non-Asic - prevent Tx filters\n");
1338                 p_ramrod->filter_cmd_hdr.tx = 0;
1339         }
1340 #endif
1341
1342         switch (p_filter_cmd->opcode) {
1343         case ECORE_FILTER_REPLACE:
1344         case ECORE_FILTER_MOVE:
1345                 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1346                 break;
1347         default:
1348                 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1349                 break;
1350         }
1351
1352         p_first_filter = &p_ramrod->filter_cmds[0];
1353         p_second_filter = &p_ramrod->filter_cmds[1];
1354
1355         switch (p_filter_cmd->type) {
1356         case ECORE_FILTER_MAC:
1357                 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1358                 break;
1359         case ECORE_FILTER_VLAN:
1360                 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1361                 break;
1362         case ECORE_FILTER_MAC_VLAN:
1363                 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1364                 break;
1365         case ECORE_FILTER_INNER_MAC:
1366                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1367                 break;
1368         case ECORE_FILTER_INNER_VLAN:
1369                 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1370                 break;
1371         case ECORE_FILTER_INNER_PAIR:
1372                 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1373                 break;
1374         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1375                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1376                 break;
1377         case ECORE_FILTER_MAC_VNI_PAIR:
1378                 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1379                 break;
1380         case ECORE_FILTER_VNI:
1381                 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1382                 break;
1383         case ECORE_FILTER_UNUSED: /* @DPDK */
1384                 p_first_filter->type = MAX_ETH_FILTER_TYPE;
1385                 break;
1386         }
1387
1388         if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1389             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1390             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1391             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1392             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1393             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1394                 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1395                                       &p_first_filter->mac_mid,
1396                                       &p_first_filter->mac_lsb,
1397                                       (u8 *)p_filter_cmd->mac);
1398
1399         if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1400             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1401             (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1402             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1403                 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1404
1405         if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1406             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1407             (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1408                 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1409
1410         if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1411                 p_second_filter->type = p_first_filter->type;
1412                 p_second_filter->mac_msb = p_first_filter->mac_msb;
1413                 p_second_filter->mac_mid = p_first_filter->mac_mid;
1414                 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1415                 p_second_filter->vlan_id = p_first_filter->vlan_id;
1416                 p_second_filter->vni = p_first_filter->vni;
1417
1418                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1419
1420                 p_first_filter->vport_id = vport_to_remove_from;
1421
1422                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1423                 p_second_filter->vport_id = vport_to_add_to;
1424         } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1425                 p_first_filter->vport_id = vport_to_add_to;
1426                 OSAL_MEMCPY(p_second_filter, p_first_filter,
1427                             sizeof(*p_second_filter));
1428                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1429                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1430         } else {
1431                 action = ecore_filter_action(p_filter_cmd->opcode);
1432
1433                 if (action == MAX_ETH_FILTER_ACTION) {
1434                         DP_NOTICE(p_hwfn, true,
1435                                   "%d is not supported yet\n",
1436                                   p_filter_cmd->opcode);
1437                         return ECORE_NOTIMPL;
1438                 }
1439
1440                 p_first_filter->action = action;
1441                 p_first_filter->vport_id =
1442                     (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1443                     vport_to_remove_from : vport_to_add_to;
1444         }
1445
1446         return ECORE_SUCCESS;
1447 }
1448
1449 enum _ecore_status_t
1450 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1451                           u16 opaque_fid,
1452                           struct ecore_filter_ucast *p_filter_cmd,
1453                           enum spq_mode comp_mode,
1454                           struct ecore_spq_comp_cb *p_comp_data)
1455 {
1456         struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1457         struct ecore_spq_entry *p_ent = OSAL_NULL;
1458         struct eth_filter_cmd_header *p_header;
1459         enum _ecore_status_t rc;
1460
1461         rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1462                                        &p_ramrod, &p_ent,
1463                                        comp_mode, p_comp_data);
1464         if (rc != ECORE_SUCCESS) {
1465                 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1466                 return rc;
1467         }
1468         p_header = &p_ramrod->filter_cmd_hdr;
1469         p_header->assert_on_error = p_filter_cmd->assert_on_error;
1470
1471         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1472         if (rc != ECORE_SUCCESS) {
1473                 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1474                 return rc;
1475         }
1476
1477         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1478                    "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1479                    (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1480                    ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1481                     "REMOVE" :
1482                     ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1483                      "MOVE" : "REPLACE")),
1484                    (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1485                    ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1486                     "VLAN" : "MAC & VLAN"),
1487                    p_ramrod->filter_cmd_hdr.cmd_cnt,
1488                    p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1489         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1490                    "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1491                    p_filter_cmd->vport_to_add_to,
1492                    p_filter_cmd->vport_to_remove_from,
1493                    p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1494                    p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1495                    p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1496                    p_filter_cmd->vlan);
1497
1498         return ECORE_SUCCESS;
1499 }
1500
1501 /*******************************************************************************
1502  * Description:
1503  *         Calculates crc 32 on a buffer
1504  *         Note: crc32_length MUST be aligned to 8
1505  * Return:
1506  ******************************************************************************/
1507 static u32 ecore_calc_crc32c(u8 *crc32_packet, u32 crc32_length, u32 crc32_seed)
1508 {
1509         u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1510         u8 msb = 0, current_byte = 0;
1511
1512         if ((crc32_packet == OSAL_NULL) ||
1513             (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1514                 return crc32_result;
1515         }
1516
1517         for (byte = 0; byte < crc32_length; byte++) {
1518                 current_byte = crc32_packet[byte];
1519                 for (bit = 0; bit < 8; bit++) {
1520                         msb = (u8)(crc32_result >> 31);
1521                         crc32_result = crc32_result << 1;
1522                         if (msb != (0x1 & (current_byte >> bit))) {
1523                                 crc32_result = crc32_result ^ CRC32_POLY;
1524                                 crc32_result |= 1;
1525                         }
1526                 }
1527         }
1528
1529         return crc32_result;
1530 }
1531
1532 static u32 ecore_crc32c_le(u32 seed, u8 *mac)
1533 {
1534         u32 packet_buf[2] = { 0 };
1535
1536         OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1537         return ecore_calc_crc32c((u8 *)packet_buf, 8, seed);
1538 }
1539
1540 u8 ecore_mcast_bin_from_mac(u8 *mac)
1541 {
1542         u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, mac);
1543
1544         return crc & 0xff;
1545 }
1546
1547 static enum _ecore_status_t
1548 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1549                           struct ecore_filter_mcast *p_filter_cmd,
1550                           enum spq_mode comp_mode,
1551                           struct ecore_spq_comp_cb *p_comp_data)
1552 {
1553         unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1554         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1555         struct ecore_spq_entry *p_ent = OSAL_NULL;
1556         struct ecore_sp_init_data init_data;
1557         u8 abs_vport_id = 0;
1558         enum _ecore_status_t rc;
1559         int i;
1560
1561         if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1562                 rc = ecore_fw_vport(p_hwfn,
1563                                     p_filter_cmd->vport_to_add_to,
1564                                     &abs_vport_id);
1565         else
1566                 rc = ecore_fw_vport(p_hwfn,
1567                                     p_filter_cmd->vport_to_remove_from,
1568                                     &abs_vport_id);
1569         if (rc != ECORE_SUCCESS)
1570                 return rc;
1571
1572         /* Get SPQ entry */
1573         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1574         init_data.cid = ecore_spq_get_cid(p_hwfn);
1575         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1576         init_data.comp_mode = comp_mode;
1577         init_data.p_comp_data = p_comp_data;
1578
1579         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1580                                    ETH_RAMROD_VPORT_UPDATE,
1581                                    PROTOCOLID_ETH, &init_data);
1582         if (rc != ECORE_SUCCESS) {
1583                 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1584                 return rc;
1585         }
1586
1587         p_ramrod = &p_ent->ramrod.vport_update;
1588         p_ramrod->common.update_approx_mcast_flg = 1;
1589
1590         /* explicitly clear out the entire vector */
1591         OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1592                     0, sizeof(p_ramrod->approx_mcast.bins));
1593         OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1594                     ETH_MULTICAST_MAC_BINS_IN_REGS);
1595         /* filter ADD op is explicit set op and it removes
1596         *  any existing filters for the vport.
1597         */
1598         if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1599                 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1600                         u32 bit;
1601
1602                         bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1603                         OSAL_SET_BIT(bit, bins);
1604                 }
1605
1606                 /* Convert to correct endianity */
1607                 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1608                         struct vport_update_ramrod_mcast *p_ramrod_bins;
1609                         u32 *p_bins = (u32 *)bins;
1610
1611                         p_ramrod_bins = &p_ramrod->approx_mcast;
1612                         p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1613                 }
1614         }
1615
1616         p_ramrod->common.vport_id = abs_vport_id;
1617
1618         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1619         if (rc != ECORE_SUCCESS)
1620                 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1621
1622         return rc;
1623 }
1624
1625 enum _ecore_status_t
1626 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1627                        struct ecore_filter_mcast *p_filter_cmd,
1628                        enum spq_mode comp_mode,
1629                        struct ecore_spq_comp_cb *p_comp_data)
1630 {
1631         enum _ecore_status_t rc = ECORE_SUCCESS;
1632         int i;
1633
1634         /* only ADD and REMOVE operations are supported for multi-cast */
1635         if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1636              (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1637             (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1638                 return ECORE_INVAL;
1639         }
1640
1641         for_each_hwfn(p_dev, i) {
1642                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1643
1644                 if (IS_VF(p_dev)) {
1645                         ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1646                         continue;
1647                 }
1648
1649                 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1650                                                p_filter_cmd,
1651                                                comp_mode, p_comp_data);
1652                 if (rc != ECORE_SUCCESS)
1653                         break;
1654         }
1655
1656         return rc;
1657 }
1658
1659 enum _ecore_status_t
1660 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1661                        struct ecore_filter_ucast *p_filter_cmd,
1662                        enum spq_mode comp_mode,
1663                        struct ecore_spq_comp_cb *p_comp_data)
1664 {
1665         enum _ecore_status_t rc = ECORE_SUCCESS;
1666         int i;
1667
1668         for_each_hwfn(p_dev, i) {
1669                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1670                 u16 opaque_fid;
1671
1672                 if (IS_VF(p_dev)) {
1673                         rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1674                         continue;
1675                 }
1676
1677                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1678                 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1679                                                opaque_fid,
1680                                                p_filter_cmd,
1681                                                comp_mode, p_comp_data);
1682                 if (rc != ECORE_SUCCESS)
1683                         break;
1684         }
1685
1686         return rc;
1687 }
1688
1689 /* Statistics related code */
1690 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1691                                              u32 *p_addr, u32 *p_len,
1692                                              u16 statistics_bin)
1693 {
1694         if (IS_PF(p_hwfn->p_dev)) {
1695                 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1696                     PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1697                 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1698         } else {
1699                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1700                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1701
1702                 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1703                 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1704         }
1705 }
1706
1707 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1708                                      struct ecore_ptt *p_ptt,
1709                                      struct ecore_eth_stats *p_stats,
1710                                      u16 statistics_bin)
1711 {
1712         struct eth_pstorm_per_queue_stat pstats;
1713         u32 pstats_addr = 0, pstats_len = 0;
1714
1715         __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1716                                          statistics_bin);
1717
1718         OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1719         ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1720
1721         p_stats->common.tx_ucast_bytes +=
1722                 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1723         p_stats->common.tx_mcast_bytes +=
1724                 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1725         p_stats->common.tx_bcast_bytes +=
1726                 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1727         p_stats->common.tx_ucast_pkts +=
1728                 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1729         p_stats->common.tx_mcast_pkts +=
1730                 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1731         p_stats->common.tx_bcast_pkts +=
1732                 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1733         p_stats->common.tx_err_drop_pkts +=
1734                 HILO_64_REGPAIR(pstats.error_drop_pkts);
1735 }
1736
1737 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1738                                      struct ecore_ptt *p_ptt,
1739                                      struct ecore_eth_stats *p_stats)
1740 {
1741         struct tstorm_per_port_stat tstats;
1742         u32 tstats_addr, tstats_len;
1743
1744         if (IS_PF(p_hwfn->p_dev)) {
1745                 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1746                     TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1747                 tstats_len = sizeof(struct tstorm_per_port_stat);
1748         } else {
1749                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1750                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1751
1752                 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1753                 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1754         }
1755
1756         OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1757         ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1758
1759         p_stats->common.mftag_filter_discards +=
1760                 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1761         p_stats->common.mac_filter_discards +=
1762                 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1763 }
1764
1765 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1766                                              u32 *p_addr, u32 *p_len,
1767                                              u16 statistics_bin)
1768 {
1769         if (IS_PF(p_hwfn->p_dev)) {
1770                 *p_addr = BAR0_MAP_REG_USDM_RAM +
1771                     USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1772                 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1773         } else {
1774                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1775                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1776
1777                 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1778                 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1779         }
1780 }
1781
1782 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1783                                      struct ecore_ptt *p_ptt,
1784                                      struct ecore_eth_stats *p_stats,
1785                                      u16 statistics_bin)
1786 {
1787         struct eth_ustorm_per_queue_stat ustats;
1788         u32 ustats_addr = 0, ustats_len = 0;
1789
1790         __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1791                                          statistics_bin);
1792
1793         OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1794         ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1795
1796         p_stats->common.rx_ucast_bytes +=
1797                 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1798         p_stats->common.rx_mcast_bytes +=
1799                 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1800         p_stats->common.rx_bcast_bytes +=
1801                 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1802         p_stats->common.rx_ucast_pkts +=
1803                 HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1804         p_stats->common.rx_mcast_pkts +=
1805                 HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1806         p_stats->common.rx_bcast_pkts +=
1807                 HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1808 }
1809
1810 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1811                                              u32 *p_addr, u32 *p_len,
1812                                              u16 statistics_bin)
1813 {
1814         if (IS_PF(p_hwfn->p_dev)) {
1815                 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1816                     MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1817                 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1818         } else {
1819                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1820                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1821
1822                 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1823                 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1824         }
1825 }
1826
1827 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1828                                      struct ecore_ptt *p_ptt,
1829                                      struct ecore_eth_stats *p_stats,
1830                                      u16 statistics_bin)
1831 {
1832         struct eth_mstorm_per_queue_stat mstats;
1833         u32 mstats_addr = 0, mstats_len = 0;
1834
1835         __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1836                                          statistics_bin);
1837
1838         OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1839         ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1840
1841         p_stats->common.no_buff_discards +=
1842                 HILO_64_REGPAIR(mstats.no_buff_discard);
1843         p_stats->common.packet_too_big_discard +=
1844                 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1845         p_stats->common.ttl0_discard +=
1846                 HILO_64_REGPAIR(mstats.ttl0_discard);
1847         p_stats->common.tpa_coalesced_pkts +=
1848                 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1849         p_stats->common.tpa_coalesced_events +=
1850                 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1851         p_stats->common.tpa_aborts_num +=
1852                 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1853         p_stats->common.tpa_coalesced_bytes +=
1854                 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1855 }
1856
1857 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1858                                          struct ecore_ptt *p_ptt,
1859                                          struct ecore_eth_stats *p_stats)
1860 {
1861         struct ecore_eth_stats_common *p_common = &p_stats->common;
1862         struct port_stats port_stats;
1863         int j;
1864
1865         OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1866
1867         ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1868                           p_hwfn->mcp_info->port_addr +
1869                           OFFSETOF(struct public_port, stats),
1870                           sizeof(port_stats));
1871
1872         p_common->rx_64_byte_packets += port_stats.eth.r64;
1873         p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1874         p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1875         p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1876         p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1877         p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1878         p_common->rx_crc_errors += port_stats.eth.rfcs;
1879         p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1880         p_common->rx_pause_frames += port_stats.eth.rxpf;
1881         p_common->rx_pfc_frames += port_stats.eth.rxpp;
1882         p_common->rx_align_errors += port_stats.eth.raln;
1883         p_common->rx_carrier_errors += port_stats.eth.rfcr;
1884         p_common->rx_oversize_packets += port_stats.eth.rovr;
1885         p_common->rx_jabbers += port_stats.eth.rjbr;
1886         p_common->rx_undersize_packets += port_stats.eth.rund;
1887         p_common->rx_fragments += port_stats.eth.rfrg;
1888         p_common->tx_64_byte_packets += port_stats.eth.t64;
1889         p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1890         p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1891         p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1892         p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1893         p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1894         p_common->tx_pause_frames += port_stats.eth.txpf;
1895         p_common->tx_pfc_frames += port_stats.eth.txpp;
1896         p_common->rx_mac_bytes += port_stats.eth.rbyte;
1897         p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1898         p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1899         p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1900         p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1901         p_common->tx_mac_bytes += port_stats.eth.tbyte;
1902         p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1903         p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1904         p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1905         p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
1906         for (j = 0; j < 8; j++) {
1907                 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1908                 p_common->brb_discards += port_stats.brb.brb_discard[j];
1909         }
1910
1911         if (ECORE_IS_BB(p_hwfn->p_dev)) {
1912                 struct ecore_eth_stats_bb *p_bb = &p_stats->bb;
1913
1914                 p_bb->rx_1519_to_1522_byte_packets +=
1915                         port_stats.eth.u0.bb0.r1522;
1916                 p_bb->rx_1519_to_2047_byte_packets +=
1917                         port_stats.eth.u0.bb0.r2047;
1918                 p_bb->rx_2048_to_4095_byte_packets +=
1919                         port_stats.eth.u0.bb0.r4095;
1920                 p_bb->rx_4096_to_9216_byte_packets +=
1921                         port_stats.eth.u0.bb0.r9216;
1922                 p_bb->rx_9217_to_16383_byte_packets +=
1923                         port_stats.eth.u0.bb0.r16383;
1924                 p_bb->tx_1519_to_2047_byte_packets +=
1925                         port_stats.eth.u1.bb1.t2047;
1926                 p_bb->tx_2048_to_4095_byte_packets +=
1927                         port_stats.eth.u1.bb1.t4095;
1928                 p_bb->tx_4096_to_9216_byte_packets +=
1929                         port_stats.eth.u1.bb1.t9216;
1930                 p_bb->tx_9217_to_16383_byte_packets +=
1931                         port_stats.eth.u1.bb1.t16383;
1932                 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1933                 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1934         } else {
1935                 struct ecore_eth_stats_ah *p_ah = &p_stats->ah;
1936
1937                 p_ah->rx_1519_to_max_byte_packets +=
1938                         port_stats.eth.u0.ah0.r1519_to_max;
1939                 p_ah->tx_1519_to_max_byte_packets =
1940                         port_stats.eth.u1.ah1.t1519_to_max;
1941         }
1942 }
1943
1944 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1945                              struct ecore_ptt *p_ptt,
1946                              struct ecore_eth_stats *stats,
1947                              u16 statistics_bin, bool b_get_port_stats)
1948 {
1949         __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1950         __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1951         __ecore_get_vport_tstats(p_hwfn, p_ptt, stats);
1952         __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1953
1954 #ifndef ASIC_ONLY
1955         /* Avoid getting PORT stats for emulation. */
1956         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1957                 return;
1958 #endif
1959
1960         if (b_get_port_stats && p_hwfn->mcp_info)
1961                 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1962 }
1963
1964 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1965                                    struct ecore_eth_stats *stats)
1966 {
1967         u8 fw_vport = 0;
1968         int i;
1969
1970         OSAL_MEMSET(stats, 0, sizeof(*stats));
1971
1972         for_each_hwfn(p_dev, i) {
1973                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1974                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1975                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1976                 bool b_get_port_stats;
1977
1978                 if (IS_PF(p_dev)) {
1979                         /* The main vport index is relative first */
1980                         if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1981                                 DP_ERR(p_hwfn, "No vport available!\n");
1982                                 goto out;
1983                         }
1984                 }
1985
1986                 if (IS_PF(p_dev) && !p_ptt) {
1987                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1988                         continue;
1989                 }
1990
1991                 b_get_port_stats = IS_PF(p_dev) && IS_LEAD_HWFN(p_hwfn);
1992                 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1993                                         b_get_port_stats);
1994
1995 out:
1996                 if (IS_PF(p_dev) && p_ptt)
1997                         ecore_ptt_release(p_hwfn, p_ptt);
1998         }
1999 }
2000
2001 void ecore_get_vport_stats(struct ecore_dev *p_dev,
2002                            struct ecore_eth_stats *stats)
2003 {
2004         u32 i;
2005
2006         if (!p_dev) {
2007                 OSAL_MEMSET(stats, 0, sizeof(*stats));
2008                 return;
2009         }
2010
2011         _ecore_get_vport_stats(p_dev, stats);
2012
2013         if (!p_dev->reset_stats)
2014                 return;
2015
2016         /* Reduce the statistics baseline */
2017         for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
2018                 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
2019 }
2020
2021 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
2022 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
2023 {
2024         int i;
2025
2026         for_each_hwfn(p_dev, i) {
2027                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2028                 struct eth_mstorm_per_queue_stat mstats;
2029                 struct eth_ustorm_per_queue_stat ustats;
2030                 struct eth_pstorm_per_queue_stat pstats;
2031                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
2032                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
2033                 u32 addr = 0, len = 0;
2034
2035                 if (IS_PF(p_dev) && !p_ptt) {
2036                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
2037                         continue;
2038                 }
2039
2040                 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
2041                 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
2042                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
2043
2044                 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
2045                 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
2046                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
2047
2048                 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
2049                 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
2050                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
2051
2052                 if (IS_PF(p_dev))
2053                         ecore_ptt_release(p_hwfn, p_ptt);
2054         }
2055
2056         /* PORT statistics are not necessarily reset, so we need to
2057          * read and create a baseline for future statistics.
2058          */
2059         if (!p_dev->reset_stats)
2060                 DP_INFO(p_dev, "Reset stats not allocated\n");
2061         else
2062                 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
2063 }
2064
2065 void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
2066                                struct ecore_ptt *p_ptt,
2067                                struct ecore_arfs_config_params *p_cfg_params)
2068 {
2069         if (p_cfg_params->arfs_enable) {
2070                 ecore_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2071                                           p_cfg_params->tcp,
2072                                           p_cfg_params->udp,
2073                                           p_cfg_params->ipv4,
2074                                           p_cfg_params->ipv6);
2075                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2076                            "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
2077                            p_cfg_params->tcp ? "Enable" : "Disable",
2078                            p_cfg_params->udp ? "Enable" : "Disable",
2079                            p_cfg_params->ipv4 ? "Enable" : "Disable",
2080                            p_cfg_params->ipv6 ? "Enable" : "Disable");
2081         } else {
2082                 ecore_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2083         }
2084         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n",
2085                    p_cfg_params->arfs_enable ? "Enable" : "Disable");
2086 }
2087
2088 enum _ecore_status_t
2089 ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn,
2090                                   struct ecore_spq_comp_cb *p_cb,
2091                                   dma_addr_t p_addr, u16 length,
2092                                   u16 qid, u8 vport_id,
2093                                   bool b_is_add)
2094 {
2095         struct rx_update_gft_filter_data *p_ramrod = OSAL_NULL;
2096         struct ecore_spq_entry *p_ent = OSAL_NULL;
2097         struct ecore_sp_init_data init_data;
2098         u16 abs_rx_q_id = 0;
2099         u8 abs_vport_id = 0;
2100         enum _ecore_status_t rc = ECORE_NOTIMPL;
2101
2102         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
2103         if (rc != ECORE_SUCCESS)
2104                 return rc;
2105
2106         rc = ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
2107         if (rc != ECORE_SUCCESS)
2108                 return rc;
2109
2110         /* Get SPQ entry */
2111         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
2112         init_data.cid = ecore_spq_get_cid(p_hwfn);
2113
2114         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2115
2116         if (p_cb) {
2117                 init_data.comp_mode = ECORE_SPQ_MODE_CB;
2118                 init_data.p_comp_data = p_cb;
2119         } else {
2120                 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
2121         }
2122
2123         rc = ecore_sp_init_request(p_hwfn, &p_ent,
2124                                    ETH_RAMROD_GFT_UPDATE_FILTER,
2125                                    PROTOCOLID_ETH, &init_data);
2126         if (rc != ECORE_SUCCESS)
2127                 return rc;
2128
2129         p_ramrod = &p_ent->ramrod.rx_update_gft;
2130
2131         DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
2132         p_ramrod->pkt_hdr_length = OSAL_CPU_TO_LE16(length);
2133         p_ramrod->rx_qid_or_action_icid = OSAL_CPU_TO_LE16(abs_rx_q_id);
2134         p_ramrod->vport_id = abs_vport_id;
2135         p_ramrod->filter_type = RFS_FILTER_TYPE;
2136         p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER
2137                                            : GFT_DELETE_FILTER;
2138
2139         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2140                    "V[%0x], Q[%04x] - %s filter from 0x%lx [length %04xb]\n",
2141                    abs_vport_id, abs_rx_q_id,
2142                    b_is_add ? "Adding" : "Removing",
2143                    (unsigned long)p_addr, length);
2144
2145         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
2146 }
2147
2148 int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn,
2149                            struct ecore_ptt *p_ptt,
2150                            struct ecore_queue_cid *p_cid,
2151                            u16 *p_rx_coal)
2152 {
2153         u32 coalesce, address, is_valid;
2154         struct cau_sb_entry sb_entry;
2155         u8 timer_res;
2156         enum _ecore_status_t rc;
2157
2158         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2159                                  p_cid->sb_igu_id * sizeof(u64),
2160                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2161         if (rc != ECORE_SUCCESS) {
2162                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2163                 return rc;
2164         }
2165
2166         timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
2167
2168         address = BAR0_MAP_REG_USDM_RAM +
2169                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2170         coalesce = ecore_rd(p_hwfn, p_ptt, address);
2171
2172         is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2173         if (!is_valid)
2174                 return ECORE_INVAL;
2175
2176         coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2177         *p_rx_coal = (u16)(coalesce << timer_res);
2178
2179         return ECORE_SUCCESS;
2180 }
2181
2182 int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn,
2183                            struct ecore_ptt *p_ptt,
2184                            struct ecore_queue_cid *p_cid,
2185                            u16 *p_tx_coal)
2186 {
2187         u32 coalesce, address, is_valid;
2188         struct cau_sb_entry sb_entry;
2189         u8 timer_res;
2190         enum _ecore_status_t rc;
2191
2192         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2193                                  p_cid->sb_igu_id * sizeof(u64),
2194                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2195         if (rc != ECORE_SUCCESS) {
2196                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2197                 return rc;
2198         }
2199
2200         timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
2201
2202         address = BAR0_MAP_REG_XSDM_RAM +
2203                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2204         coalesce = ecore_rd(p_hwfn, p_ptt, address);
2205
2206         is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2207         if (!is_valid)
2208                 return ECORE_INVAL;
2209
2210         coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2211         *p_tx_coal = (u16)(coalesce << timer_res);
2212
2213         return ECORE_SUCCESS;
2214 }
2215
2216 enum _ecore_status_t
2217 ecore_get_queue_coalesce(struct ecore_hwfn *p_hwfn, u16 *p_coal,
2218                          void *handle)
2219 {
2220         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)handle;
2221         enum _ecore_status_t rc = ECORE_SUCCESS;
2222         struct ecore_ptt *p_ptt;
2223
2224         if (IS_VF(p_hwfn->p_dev)) {
2225                 rc = ecore_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
2226                 if (rc != ECORE_SUCCESS)
2227                         DP_NOTICE(p_hwfn, false,
2228                                   "Unable to read queue calescing\n");
2229
2230                 return rc;
2231         }
2232
2233         p_ptt = ecore_ptt_acquire(p_hwfn);
2234         if (!p_ptt)
2235                 return ECORE_AGAIN;
2236
2237         if (p_cid->b_is_rx) {
2238                 rc = ecore_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2239                 if (rc != ECORE_SUCCESS)
2240                         goto out;
2241         } else {
2242                 rc = ecore_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2243                 if (rc != ECORE_SUCCESS)
2244                         goto out;
2245         }
2246
2247 out:
2248         ecore_ptt_release(p_hwfn, p_ptt);
2249
2250         return rc;
2251 }