drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23 #include "ecore_sp_commands.h"
  24 #include "ecore_cxt.h"
  25
  26 #define CHIP_MCP_RESP_ITER_US 10
  27 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  28
  29 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  30 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  31
  32 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  33         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  34                  _val)
  35
  36 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  37         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  38
  39 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  40         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  41                      OFFSETOF(struct public_drv_mb, _field), _val)
  42
  43 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  44         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  45                      OFFSETOF(struct public_drv_mb, _field))
  46
  47 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  48         DRV_ID_PDA_COMP_VER_OFFSET)
  49
  50 #define MCP_BYTES_PER_MBIT_OFFSET 17
  51
  52 #ifndef ASIC_ONLY
  53 static int loaded;
  54 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  55 #endif
  56
  57 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  58 {
  59         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  60                 return false;
  61         return true;
  62 }
  63
  64 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  65 {
  66         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  67                                         PUBLIC_PORT);
  68         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  69
  70         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  71                                                    MFW_PORT(p_hwfn));
  72         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  73                    "port_addr = 0x%x, port_id 0x%02x\n",
  74                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  75 }
  76
  77 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  78 {
  79         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  80         OSAL_BE32 tmp;
  81         u32 i;
  82
  83 #ifndef ASIC_ONLY
  84         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  85                 return;
  86 #endif
  87
  88         if (!p_hwfn->mcp_info->public_base)
  89                 return;
  90
  91         for (i = 0; i < length; i++) {
  92                 tmp = ecore_rd(p_hwfn, p_ptt,
  93                                p_hwfn->mcp_info->mfw_mb_addr +
  94                                (i << 2) + sizeof(u32));
  95
  96                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  97                     OSAL_BE32_TO_CPU(tmp);
  98         }
  99 }
 100
 101 struct ecore_mcp_cmd_elem {
 102         osal_list_entry_t list;
 103         struct ecore_mcp_mb_params *p_mb_params;
 104         u16 expected_seq_num;
 105         bool b_is_completed;
 106 };
 107
 108 /* Must be called while cmd_lock is acquired */
 109 static struct ecore_mcp_cmd_elem *
 110 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 111                        struct ecore_mcp_mb_params *p_mb_params,
 112                        u16 expected_seq_num)
 113 {
 114         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 115
 116         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 117                                  sizeof(*p_cmd_elem));
 118         if (!p_cmd_elem) {
 119                 DP_NOTICE(p_hwfn, false,
 120                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 121                 goto out;
 122         }
 123
 124         p_cmd_elem->p_mb_params = p_mb_params;
 125         p_cmd_elem->expected_seq_num = expected_seq_num;
 126         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 127 out:
 128         return p_cmd_elem;
 129 }
 130
 131 /* Must be called while cmd_lock is acquired */
 132 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 133                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 134 {
 135         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 136         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 137 }
 138
 139 /* Must be called while cmd_lock is acquired */
 140 static struct ecore_mcp_cmd_elem *
 141 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 142 {
 143         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 144
 145         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 146                                  struct ecore_mcp_cmd_elem) {
 147                 if (p_cmd_elem->expected_seq_num == seq_num)
 148                         return p_cmd_elem;
 149         }
 150
 151         return OSAL_NULL;
 152 }
 153
 154 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 155 {
 156         if (p_hwfn->mcp_info) {
 157                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 158
 159                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 160                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 161                                               &p_hwfn->mcp_info->cmd_list, list,
 162                                               struct ecore_mcp_cmd_elem) {
 163                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 164                 }
 165                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 166
 167                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 168                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 169 #ifdef CONFIG_ECORE_LOCK_ALLOC
 170                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 171                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 172 #endif
 173         }
 174
 175         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 176
 177         return ECORE_SUCCESS;
 178 }
 179
 180 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 181                                                    struct ecore_ptt *p_ptt)
 182 {
 183         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 184         u32 drv_mb_offsize, mfw_mb_offsize;
 185         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 186
 187 #ifndef ASIC_ONLY
 188         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 189                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 190                 p_info->public_base = 0;
 191                 return ECORE_INVAL;
 192         }
 193 #endif
 194
 195         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 196         if (!p_info->public_base)
 197                 return ECORE_INVAL;
 198
 199         p_info->public_base |= GRCBASE_MCP;
 200
 201         /* Calculate the driver and MFW mailbox address */
 202         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 203                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 204                                                        PUBLIC_DRV_MB));
 205         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 206         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 207                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 208                    " mcp_pf_id = 0x%x\n",
 209                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 210
 211         /* Set the MFW MB address */
 212         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 213                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 214                                                        PUBLIC_MFW_MB));
 215         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 216         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 217                                                p_info->mfw_mb_addr);
 218
 219         /* Get the current driver mailbox sequence before sending
 220          * the first command
 221          */
 222         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 223             DRV_MSG_SEQ_NUMBER_MASK;
 224
 225         /* Get current FW pulse sequence */
 226         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 227             DRV_PULSE_SEQ_MASK;
 228
 229         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 230
 231         return ECORE_SUCCESS;
 232 }
 233
 234 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 235                                         struct ecore_ptt *p_ptt)
 236 {
 237         struct ecore_mcp_info *p_info;
 238         u32 size;
 239
 240         /* Allocate mcp_info structure */
 241         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 242                                        sizeof(*p_hwfn->mcp_info));
 243         if (!p_hwfn->mcp_info)
 244                 goto err;
 245         p_info = p_hwfn->mcp_info;
 246
 247         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 248                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 249                 /* Do not free mcp_info here, since public_base indicate that
 250                  * the MCP is not initialized
 251                  */
 252                 return ECORE_SUCCESS;
 253         }
 254
 255         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 256         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 257         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 258         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 259                 goto err;
 260
 261         /* Initialize the MFW spinlocks */
 262 #ifdef CONFIG_ECORE_LOCK_ALLOC
 263         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 264         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 265 #endif
 266         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 267         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 268
 269         OSAL_LIST_INIT(&p_info->cmd_list);
 270
 271         return ECORE_SUCCESS;
 272
 273 err:
 274         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 275         ecore_mcp_free(p_hwfn);
 276         return ECORE_NOMEM;
 277 }
 278
 279 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 280                                      struct ecore_ptt *p_ptt)
 281 {
 282         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 283
 284         /* Use MCP history register to check if MCP reset occurred between init
 285          * time and now.
 286          */
 287         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 288                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 289                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 290                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 291
 292                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 293                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 294         }
 295 }
 296
 297 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 298                                      struct ecore_ptt *p_ptt)
 299 {
 300         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 301         enum _ecore_status_t rc = ECORE_SUCCESS;
 302
 303 #ifndef ASIC_ONLY
 304         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 305                 delay = EMUL_MCP_RESP_ITER_US;
 306 #endif
 307
 308         if (p_hwfn->mcp_info->b_block_cmd) {
 309                 DP_NOTICE(p_hwfn, false,
 310                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 311                 return ECORE_ABORTED;
 312         }
 313
 314         /* Ensure that only a single thread is accessing the mailbox */
 315         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 316
 317         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 318
 319         /* Set drv command along with the updated sequence */
 320         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 321         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 322         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 323
 324         do {
 325                 /* Wait for MFW response */
 326                 OSAL_UDELAY(delay);
 327                 /* Give the FW up to 500 second (50*1000*10usec) */
 328         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 329                                                 MISCS_REG_GENERIC_POR_0)) &&
 330                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 331
 332         if (org_mcp_reset_seq !=
 333             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 334                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 335                            "MCP was reset after %d usec\n", cnt * delay);
 336         } else {
 337                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 338                 rc = ECORE_AGAIN;
 339         }
 340
 341         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 342
 343         return rc;
 344 }
 345
 346 /* Must be called while cmd_lock is acquired */
 347 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 348 {
 349         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 350
 351         /* There is at most one pending command at a certain time, and if it
 352          * exists - it is placed at the HEAD of the list.
 353          */
 354         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 355                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 356                                                    struct ecore_mcp_cmd_elem,
 357                                                    list);
 358                 return !p_cmd_elem->b_is_completed;
 359         }
 360
 361         return false;
 362 }
 363
 364 /* Must be called while cmd_lock is acquired */
 365 static enum _ecore_status_t
 366 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 367 {
 368         struct ecore_mcp_mb_params *p_mb_params;
 369         struct ecore_mcp_cmd_elem *p_cmd_elem;
 370         u32 mcp_resp;
 371         u16 seq_num;
 372
 373         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 374         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 375
 376         /* Return if no new non-handled response has been received */
 377         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 378                 return ECORE_AGAIN;
 379
 380         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 381         if (!p_cmd_elem) {
 382                 DP_ERR(p_hwfn,
 383                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 384                        seq_num);
 385                 return ECORE_UNKNOWN_ERROR;
 386         }
 387
 388         p_mb_params = p_cmd_elem->p_mb_params;
 389
 390         /* Get the MFW response along with the sequence number */
 391         p_mb_params->mcp_resp = mcp_resp;
 392
 393         /* Get the MFW param */
 394         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 395
 396         /* Get the union data */
 397         if (p_mb_params->p_data_dst != OSAL_NULL &&
 398             p_mb_params->data_dst_size) {
 399                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 400                                       OFFSETOF(struct public_drv_mb,
 401                                                union_data);
 402                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 403                                   union_data_addr, p_mb_params->data_dst_size);
 404         }
 405
 406         p_cmd_elem->b_is_completed = true;
 407
 408         return ECORE_SUCCESS;
 409 }
 410
 411 /* Must be called while cmd_lock is acquired */
 412 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 413                                       struct ecore_ptt *p_ptt,
 414                                       struct ecore_mcp_mb_params *p_mb_params,
 415                                       u16 seq_num)
 416 {
 417         union drv_union_data union_data;
 418         u32 union_data_addr;
 419
 420         /* Set the union data */
 421         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 422                           OFFSETOF(struct public_drv_mb, union_data);
 423         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 424         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 425                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 426                             p_mb_params->data_src_size);
 427         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 428                         sizeof(union_data));
 429
 430         /* Set the drv param */
 431         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 432
 433         /* Set the drv command along with the sequence number */
 434         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 435
 436         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 437                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 438                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 439 }
 440
 441 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
 442                                        bool block_cmd)
 443 {
 444         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 445
 446         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 447                 block_cmd ? "Block" : "Unblock");
 448 }
 449
 450 static enum _ecore_status_t
 451 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 452                          struct ecore_mcp_mb_params *p_mb_params,
 453                          u32 max_retries, u32 delay)
 454 {
 455         struct ecore_mcp_cmd_elem *p_cmd_elem;
 456         u32 cnt = 0;
 457         u16 seq_num;
 458         enum _ecore_status_t rc = ECORE_SUCCESS;
 459
 460         /* Wait until the mailbox is non-occupied */
 461         do {
 462                 /* Exit the loop if there is no pending command, or if the
 463                  * pending command is completed during this iteration.
 464                  * The spinlock stays locked until the command is sent.
 465                  */
 466
 467                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 468
 469                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 470                         break;
 471
 472                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 473                 if (rc == ECORE_SUCCESS)
 474                         break;
 475                 else if (rc != ECORE_AGAIN)
 476                         goto err;
 477
 478                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 479                 OSAL_UDELAY(delay);
 480         } while (++cnt < max_retries);
 481
 482         if (cnt >= max_retries) {
 483                 DP_NOTICE(p_hwfn, false,
 484                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 485                           p_mb_params->cmd, p_mb_params->param);
 486                 return ECORE_AGAIN;
 487         }
 488
 489         /* Send the mailbox command */
 490         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 491         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 492         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 493         if (!p_cmd_elem) {
 494                 rc = ECORE_NOMEM;
 495                 goto err;
 496         }
 497
 498         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 499         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 500
 501         /* Wait for the MFW response */
 502         do {
 503                 /* Exit the loop if the command is already completed, or if the
 504                  * command is completed during this iteration.
 505                  * The spinlock stays locked until the list element is removed.
 506                  */
 507
 508                 OSAL_UDELAY(delay);
 509                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 510
 511                 if (p_cmd_elem->b_is_completed)
 512                         break;
 513
 514                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 515                 if (rc == ECORE_SUCCESS)
 516                         break;
 517                 else if (rc != ECORE_AGAIN)
 518                         goto err;
 519
 520                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 521         } while (++cnt < max_retries);
 522
 523         if (cnt >= max_retries) {
 524                 DP_NOTICE(p_hwfn, false,
 525                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 526                           p_mb_params->cmd, p_mb_params->param);
 527
 528                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 529                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 530                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 531
 532                 ecore_mcp_cmd_set_blocking(p_hwfn, true);
 533                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 534                 return ECORE_AGAIN;
 535         }
 536
 537         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 538         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 539
 540         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 541                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 542                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 543                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 544
 545         /* Clear the sequence number from the MFW response */
 546         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 547
 548         return ECORE_SUCCESS;
 549
 550 err:
 551         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 552         return rc;
 553 }
 554
 555 static enum _ecore_status_t
 556 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 557                         struct ecore_ptt *p_ptt,
 558                         struct ecore_mcp_mb_params *p_mb_params)
 559 {
 560         osal_size_t union_data_size = sizeof(union drv_union_data);
 561         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 562         u32 delay = CHIP_MCP_RESP_ITER_US;
 563
 564 #ifndef ASIC_ONLY
 565         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 566                 delay = EMUL_MCP_RESP_ITER_US;
 567         /* There is a built-in delay of 100usec in each MFW response read */
 568         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 569                 max_retries /= 10;
 570 #endif
 571
 572         /* MCP not initialized */
 573         if (!ecore_mcp_is_init(p_hwfn)) {
 574                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 575                 return ECORE_BUSY;
 576         }
 577
 578         if (p_mb_params->data_src_size > union_data_size ||
 579             p_mb_params->data_dst_size > union_data_size) {
 580                 DP_ERR(p_hwfn,
 581                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 582                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 583                        union_data_size);
 584                 return ECORE_INVAL;
 585         }
 586
 587         if (p_hwfn->mcp_info->b_block_cmd) {
 588                 DP_NOTICE(p_hwfn, false,
 589                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 590                           p_mb_params->cmd, p_mb_params->param);
 591                 return ECORE_ABORTED;
 592         }
 593
 594         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 595                                         delay);
 596 }
 597
 598 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 599                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 600                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 601 {
 602         struct ecore_mcp_mb_params mb_params;
 603         enum _ecore_status_t rc;
 604
 605 #ifndef ASIC_ONLY
 606         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 607                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 608                         loaded--;
 609                         loaded_port[p_hwfn->port_id]--;
 610                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 611                                    loaded);
 612                 }
 613                 return ECORE_SUCCESS;
 614         }
 615 #endif
 616
 617         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 618         mb_params.cmd = cmd;
 619         mb_params.param = param;
 620         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 621         if (rc != ECORE_SUCCESS)
 622                 return rc;
 623
 624         *o_mcp_resp = mb_params.mcp_resp;
 625         *o_mcp_param = mb_params.mcp_param;
 626
 627         return ECORE_SUCCESS;
 628 }
 629
 630 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 631                                           struct ecore_ptt *p_ptt,
 632                                           u32 cmd,
 633                                           u32 param,
 634                                           u32 *o_mcp_resp,
 635                                           u32 *o_mcp_param,
 636                                           u32 i_txn_size, u32 *i_buf)
 637 {
 638         struct ecore_mcp_mb_params mb_params;
 639         enum _ecore_status_t rc;
 640
 641         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 642         mb_params.cmd = cmd;
 643         mb_params.param = param;
 644         mb_params.p_data_src = i_buf;
 645         mb_params.data_src_size = (u8)i_txn_size;
 646         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 647         if (rc != ECORE_SUCCESS)
 648                 return rc;
 649
 650         *o_mcp_resp = mb_params.mcp_resp;
 651         *o_mcp_param = mb_params.mcp_param;
 652
 653         return ECORE_SUCCESS;
 654 }
 655
 656 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 657                                           struct ecore_ptt *p_ptt,
 658                                           u32 cmd,
 659                                           u32 param,
 660                                           u32 *o_mcp_resp,
 661                                           u32 *o_mcp_param,
 662                                           u32 *o_txn_size, u32 *o_buf)
 663 {
 664         struct ecore_mcp_mb_params mb_params;
 665         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 666         enum _ecore_status_t rc;
 667
 668         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 669         mb_params.cmd = cmd;
 670         mb_params.param = param;
 671         mb_params.p_data_dst = raw_data;
 672
 673         /* Use the maximal value since the actual one is part of the response */
 674         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 675
 676         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 677         if (rc != ECORE_SUCCESS)
 678                 return rc;
 679
 680         *o_mcp_resp = mb_params.mcp_resp;
 681         *o_mcp_param = mb_params.mcp_param;
 682
 683         *o_txn_size = *o_mcp_param;
 684         /* @DPDK */
 685         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 686
 687         return ECORE_SUCCESS;
 688 }
 689
 690 #ifndef ASIC_ONLY
 691 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 692                                     u32 *p_load_code)
 693 {
 694         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 695
 696         if (!loaded)
 697                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 698         else if (!loaded_port[p_hwfn->port_id])
 699                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 700         else
 701                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 702
 703         /* On CMT, always tell that it's engine */
 704         if (ECORE_IS_CMT(p_hwfn->p_dev))
 705                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 706
 707         *p_load_code = load_phase;
 708         loaded++;
 709         loaded_port[p_hwfn->port_id]++;
 710
 711         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 712                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 713                    *p_load_code, loaded, p_hwfn->port_id,
 714                    loaded_port[p_hwfn->port_id]);
 715 }
 716 #endif
 717
 718 static bool
 719 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 720                          enum ecore_override_force_load override_force_load)
 721 {
 722         bool can_force_load = false;
 723
 724         switch (override_force_load) {
 725         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 726                 can_force_load = true;
 727                 break;
 728         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 729                 can_force_load = false;
 730                 break;
 731         default:
 732                 can_force_load = (drv_role == DRV_ROLE_OS &&
 733                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 734                                  (drv_role == DRV_ROLE_KDUMP &&
 735                                   exist_drv_role == DRV_ROLE_OS);
 736                 break;
 737         }
 738
 739         return can_force_load;
 740 }
 741
 742 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 743                                                       struct ecore_ptt *p_ptt)
 744 {
 745         u32 resp = 0, param = 0;
 746         enum _ecore_status_t rc;
 747
 748         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 749                            &resp, &param);
 750         if (rc != ECORE_SUCCESS)
 751                 DP_NOTICE(p_hwfn, false,
 752                           "Failed to send cancel load request, rc = %d\n", rc);
 753
 754         return rc;
 755 }
 756
 757 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 758 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 759 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 760 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 761 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 762 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 763 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 764
 765 static u32 ecore_get_config_bitmap(void)
 766 {
 767         u32 config_bitmap = 0x0;
 768
 769 #ifdef CONFIG_ECORE_L2
 770         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 771 #endif
 772 #ifdef CONFIG_ECORE_SRIOV
 773         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 774 #endif
 775 #ifdef CONFIG_ECORE_ROCE
 776         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 777 #endif
 778 #ifdef CONFIG_ECORE_IWARP
 779         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 780 #endif
 781 #ifdef CONFIG_ECORE_FCOE
 782         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 783 #endif
 784 #ifdef CONFIG_ECORE_ISCSI
 785         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 786 #endif
 787 #ifdef CONFIG_ECORE_LL2
 788         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 789 #endif
 790
 791         return config_bitmap;
 792 }
 793
 794 struct ecore_load_req_in_params {
 795         u8 hsi_ver;
 796 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 797 #define ECORE_LOAD_REQ_HSI_VER_1        1
 798         u32 drv_ver_0;
 799         u32 drv_ver_1;
 800         u32 fw_ver;
 801         u8 drv_role;
 802         u8 timeout_val;
 803         u8 force_cmd;
 804         bool avoid_eng_reset;
 805 };
 806
 807 struct ecore_load_req_out_params {
 808         u32 load_code;
 809         u32 exist_drv_ver_0;
 810         u32 exist_drv_ver_1;
 811         u32 exist_fw_ver;
 812         u8 exist_drv_role;
 813         u8 mfw_hsi_ver;
 814         bool drv_exists;
 815 };
 816
 817 static enum _ecore_status_t
 818 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 819                      struct ecore_load_req_in_params *p_in_params,
 820                      struct ecore_load_req_out_params *p_out_params)
 821 {
 822         struct ecore_mcp_mb_params mb_params;
 823         struct load_req_stc load_req;
 824         struct load_rsp_stc load_rsp;
 825         u32 hsi_ver;
 826         enum _ecore_status_t rc;
 827
 828         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 829         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 830         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 831         load_req.fw_ver = p_in_params->fw_ver;
 832         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 833         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 834                       p_in_params->timeout_val);
 835         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 836         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 837                       p_in_params->avoid_eng_reset);
 838
 839         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 840                   DRV_ID_MCP_HSI_VER_CURRENT :
 841                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 842
 843         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 844         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 845         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 846         mb_params.p_data_src = &load_req;
 847         mb_params.data_src_size = sizeof(load_req);
 848         mb_params.p_data_dst = &load_rsp;
 849         mb_params.data_dst_size = sizeof(load_rsp);
 850
 851         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 852                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 853                    mb_params.param,
 854                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 855                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 856                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 857                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 858
 859         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 860                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 861                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 862                            load_req.drv_ver_0, load_req.drv_ver_1,
 863                            load_req.fw_ver, load_req.misc0,
 864                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 865                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 866                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 867                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 868
 869         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 870         if (rc != ECORE_SUCCESS) {
 871                 DP_NOTICE(p_hwfn, false,
 872                           "Failed to send load request, rc = %d\n", rc);
 873                 return rc;
 874         }
 875
 876         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 877                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 878         p_out_params->load_code = mb_params.mcp_resp;
 879
 880         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 881             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 882                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 883                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 884                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 885                            load_rsp.fw_ver, load_rsp.misc0,
 886                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 887                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 888                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 889
 890                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 891                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 892                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 893                 p_out_params->exist_drv_role =
 894                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 895                 p_out_params->mfw_hsi_ver =
 896                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 897                 p_out_params->drv_exists =
 898                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 899                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 900         }
 901
 902         return ECORE_SUCCESS;
 903 }
 904
 905 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
 906                                    u8 *p_mfw_drv_role)
 907 {
 908         switch (drv_role) {
 909         case ECORE_DRV_ROLE_OS:
 910                 *p_mfw_drv_role = DRV_ROLE_OS;
 911                 break;
 912         case ECORE_DRV_ROLE_KDUMP:
 913                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 914                 break;
 915         }
 916 }
 917
 918 enum ecore_load_req_force {
 919         ECORE_LOAD_REQ_FORCE_NONE,
 920         ECORE_LOAD_REQ_FORCE_PF,
 921         ECORE_LOAD_REQ_FORCE_ALL,
 922 };
 923
 924 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
 925                                     u8 *p_mfw_force_cmd)
 926 {
 927         switch (force_cmd) {
 928         case ECORE_LOAD_REQ_FORCE_NONE:
 929                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 930                 break;
 931         case ECORE_LOAD_REQ_FORCE_PF:
 932                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 933                 break;
 934         case ECORE_LOAD_REQ_FORCE_ALL:
 935                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 936                 break;
 937         }
 938 }
 939
 940 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 941                                         struct ecore_ptt *p_ptt,
 942                                         struct ecore_load_req_params *p_params)
 943 {
 944         struct ecore_load_req_out_params out_params;
 945         struct ecore_load_req_in_params in_params;
 946         u8 mfw_drv_role = 0, mfw_force_cmd;
 947         enum _ecore_status_t rc;
 948
 949 #ifndef ASIC_ONLY
 950         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 951                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 952                 return ECORE_SUCCESS;
 953         }
 954 #endif
 955
 956         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 957         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 958         in_params.drv_ver_0 = ECORE_VERSION;
 959         in_params.drv_ver_1 = ecore_get_config_bitmap();
 960         in_params.fw_ver = STORM_FW_VERSION;
 961         ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
 962         in_params.drv_role = mfw_drv_role;
 963         in_params.timeout_val = p_params->timeout_val;
 964         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 965         in_params.force_cmd = mfw_force_cmd;
 966         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 967
 968         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 969         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 970         if (rc != ECORE_SUCCESS)
 971                 return rc;
 972
 973         /* First handle cases where another load request should/might be sent:
 974          * - MFW expects the old interface [HSI version = 1]
 975          * - MFW responds that a force load request is required
 976          */
 977         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 978                 DP_INFO(p_hwfn,
 979                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 980
 981                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 982                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 983                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 984                                           &out_params);
 985                 if (rc != ECORE_SUCCESS)
 986                         return rc;
 987         } else if (out_params.load_code ==
 988                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 989                 if (ecore_mcp_can_force_load(in_params.drv_role,
 990                                              out_params.exist_drv_role,
 991                                              p_params->override_force_load)) {
 992                         DP_INFO(p_hwfn,
 993                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
 994                                 in_params.drv_role, in_params.fw_ver,
 995                                 in_params.drv_ver_0, in_params.drv_ver_1,
 996                                 out_params.exist_drv_role,
 997                                 out_params.exist_fw_ver,
 998                                 out_params.exist_drv_ver_0,
 999                                 out_params.exist_drv_ver_1);
1000
1001                         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1002                                                 &mfw_force_cmd);
1003
1004                         in_params.force_cmd = mfw_force_cmd;
1005                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1006                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1007                                                   &out_params);
1008                         if (rc != ECORE_SUCCESS)
1009                                 return rc;
1010                 } else {
1011                         DP_NOTICE(p_hwfn, false,
1012                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1013                                   in_params.drv_role, in_params.fw_ver,
1014                                   in_params.drv_ver_0, in_params.drv_ver_1,
1015                                   out_params.exist_drv_role,
1016                                   out_params.exist_fw_ver,
1017                                   out_params.exist_drv_ver_0,
1018                                   out_params.exist_drv_ver_1);
1019
1020                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1021                         return ECORE_BUSY;
1022                 }
1023         }
1024
1025         /* Now handle the other types of responses.
1026          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1027          * expected here after the additional revised load requests were sent.
1028          */
1029         switch (out_params.load_code) {
1030         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1031         case FW_MSG_CODE_DRV_LOAD_PORT:
1032         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1033                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1034                     out_params.drv_exists) {
1035                         /* The role and fw/driver version match, but the PF is
1036                          * already loaded and has not been unloaded gracefully.
1037                          * This is unexpected since a quasi-FLR request was
1038                          * previously sent as part of ecore_hw_prepare().
1039                          */
1040                         DP_NOTICE(p_hwfn, false,
1041                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1042                         return ECORE_INVAL;
1043                 }
1044                 break;
1045         default:
1046                 DP_NOTICE(p_hwfn, false,
1047                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1048                           out_params.load_code);
1049                 return ECORE_BUSY;
1050         }
1051
1052         p_params->load_code = out_params.load_code;
1053
1054         return ECORE_SUCCESS;
1055 }
1056
1057 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1058                                          struct ecore_ptt *p_ptt)
1059 {
1060         u32 resp = 0, param = 0;
1061         enum _ecore_status_t rc;
1062
1063         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1064                            &param);
1065         if (rc != ECORE_SUCCESS) {
1066                 DP_NOTICE(p_hwfn, false,
1067                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1068                 return rc;
1069         }
1070
1071         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1072         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1073                 DP_NOTICE(p_hwfn, false,
1074                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1075
1076         return ECORE_SUCCESS;
1077 }
1078
1079 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1080                                           struct ecore_ptt *p_ptt)
1081 {
1082         u32 wol_param, mcp_resp, mcp_param;
1083
1084         /* @DPDK */
1085         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1086
1087         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1088                              &mcp_resp, &mcp_param);
1089 }
1090
1091 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1092                                            struct ecore_ptt *p_ptt)
1093 {
1094         struct ecore_mcp_mb_params mb_params;
1095         struct mcp_mac wol_mac;
1096
1097         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1098         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1099
1100         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1101 }
1102
1103 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1104                                     struct ecore_ptt *p_ptt)
1105 {
1106         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1107                                         PUBLIC_PATH);
1108         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1109         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1110                                      ECORE_PATH_ID(p_hwfn));
1111         u32 disabled_vfs[VF_MAX_STATIC / 32];
1112         int i;
1113
1114         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1115                    "Reading Disabled VF information from [offset %08x],"
1116                    " path_addr %08x\n",
1117                    mfw_path_offsize, path_addr);
1118
1119         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1120                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1121                                            path_addr +
1122                                            OFFSETOF(struct public_path,
1123                                                     mcp_vf_disabled) +
1124                                            sizeof(u32) * i);
1125                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1126                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1127                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1128         }
1129
1130         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1131                 OSAL_VF_FLR_UPDATE(p_hwfn);
1132 }
1133
1134 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1135                                           struct ecore_ptt *p_ptt,
1136                                           u32 *vfs_to_ack)
1137 {
1138         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1139                                         PUBLIC_FUNC);
1140         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1141         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1142                                      MCP_PF_ID(p_hwfn));
1143         struct ecore_mcp_mb_params mb_params;
1144         enum _ecore_status_t rc;
1145         int i;
1146
1147         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1148                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1149                            "Acking VFs [%08x,...,%08x] - %08x\n",
1150                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1151
1152         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1153         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1154         mb_params.p_data_src = vfs_to_ack;
1155         mb_params.data_src_size = VF_MAX_STATIC / 8;
1156         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1157                                      &mb_params);
1158         if (rc != ECORE_SUCCESS) {
1159                 DP_NOTICE(p_hwfn, false,
1160                           "Failed to pass ACK for VF flr to MFW\n");
1161                 return ECORE_TIMEOUT;
1162         }
1163
1164         /* TMP - clear the ACK bits; should be done by MFW */
1165         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1166                 ecore_wr(p_hwfn, p_ptt,
1167                          func_addr +
1168                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1169                          i * sizeof(u32), 0);
1170
1171         return rc;
1172 }
1173
1174 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1175                                                 struct ecore_ptt *p_ptt)
1176 {
1177         u32 transceiver_state;
1178
1179         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1180                                      p_hwfn->mcp_info->port_addr +
1181                                      OFFSETOF(struct public_port,
1182                                               transceiver_data));
1183
1184         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1185                    "Received transceiver state update [0x%08x] from mfw"
1186                    " [Addr 0x%x]\n",
1187                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1188                                             OFFSETOF(struct public_port,
1189                                                      transceiver_data)));
1190
1191         transceiver_state = GET_MFW_FIELD(transceiver_state,
1192                                           ETH_TRANSCEIVER_STATE);
1193
1194         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1195                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1196         else
1197                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1198 }
1199
1200 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1201                                       struct ecore_ptt *p_ptt,
1202                                       struct ecore_mcp_link_state *p_link)
1203 {
1204         u32 eee_status, val;
1205
1206         p_link->eee_adv_caps = 0;
1207         p_link->eee_lp_adv_caps = 0;
1208         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1209                                      OFFSETOF(struct public_port, eee_status));
1210         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1211         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1212         if (val & EEE_1G_ADV)
1213                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1214         if (val & EEE_10G_ADV)
1215                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1216         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1217         if (val & EEE_1G_ADV)
1218                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1219         if (val & EEE_10G_ADV)
1220                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1221 }
1222
1223 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1224                                          struct ecore_ptt *p_ptt,
1225                                          bool b_reset)
1226 {
1227         struct ecore_mcp_link_state *p_link;
1228         u8 max_bw, min_bw;
1229         u32 status = 0;
1230
1231         /* Prevent SW/attentions from doing this at the same time */
1232         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1233
1234         p_link = &p_hwfn->mcp_info->link_output;
1235         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1236         if (!b_reset) {
1237                 status = ecore_rd(p_hwfn, p_ptt,
1238                                   p_hwfn->mcp_info->port_addr +
1239                                   OFFSETOF(struct public_port, link_status));
1240                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1241                            "Received link update [0x%08x] from mfw"
1242                            " [Addr 0x%x]\n",
1243                            status, (u32)(p_hwfn->mcp_info->port_addr +
1244                                           OFFSETOF(struct public_port,
1245                                                    link_status)));
1246         } else {
1247                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1248                            "Resetting link indications\n");
1249                 goto out;
1250         }
1251
1252         if (p_hwfn->b_drv_link_init)
1253                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1254         else
1255                 p_link->link_up = false;
1256
1257         p_link->full_duplex = true;
1258         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1259         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1260                 p_link->speed = 100000;
1261                 break;
1262         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1263                 p_link->speed = 50000;
1264                 break;
1265         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1266                 p_link->speed = 40000;
1267                 break;
1268         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1269                 p_link->speed = 25000;
1270                 break;
1271         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1272                 p_link->speed = 20000;
1273                 break;
1274         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1275                 p_link->speed = 10000;
1276                 break;
1277         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1278                 p_link->full_duplex = false;
1279                 /* Fall-through */
1280         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1281                 p_link->speed = 1000;
1282                 break;
1283         default:
1284                 p_link->speed = 0;
1285         }
1286
1287         /* We never store total line speed as p_link->speed is
1288          * again changes according to bandwidth allocation.
1289          */
1290         if (p_link->link_up && p_link->speed)
1291                 p_link->line_speed = p_link->speed;
1292         else
1293                 p_link->line_speed = 0;
1294
1295         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1296         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1297
1298         /* Max bandwidth configuration */
1299         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1300                                            p_link, max_bw);
1301
1302         /* Mintz bandwidth configuration */
1303         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1304                                            p_link, min_bw);
1305         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1306                                               p_link->min_pf_rate);
1307
1308         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1309         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1310         p_link->parallel_detection = !!(status &
1311                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1312         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1313
1314         p_link->partner_adv_speed |=
1315             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1316             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1317         p_link->partner_adv_speed |=
1318             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1319             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1320         p_link->partner_adv_speed |=
1321             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1322             ECORE_LINK_PARTNER_SPEED_10G : 0;
1323         p_link->partner_adv_speed |=
1324             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1325             ECORE_LINK_PARTNER_SPEED_20G : 0;
1326         p_link->partner_adv_speed |=
1327             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1328             ECORE_LINK_PARTNER_SPEED_25G : 0;
1329         p_link->partner_adv_speed |=
1330             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1331             ECORE_LINK_PARTNER_SPEED_40G : 0;
1332         p_link->partner_adv_speed |=
1333             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1334             ECORE_LINK_PARTNER_SPEED_50G : 0;
1335         p_link->partner_adv_speed |=
1336             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1337             ECORE_LINK_PARTNER_SPEED_100G : 0;
1338
1339         p_link->partner_tx_flow_ctrl_en =
1340             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1341         p_link->partner_rx_flow_ctrl_en =
1342             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1343
1344         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1345         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1346                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1347                 break;
1348         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1349                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1350                 break;
1351         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1352                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1353                 break;
1354         default:
1355                 p_link->partner_adv_pause = 0;
1356         }
1357
1358         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1359
1360         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1361                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1362
1363         OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1364 out:
1365         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1366 }
1367
1368 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1369                                         struct ecore_ptt *p_ptt, bool b_up)
1370 {
1371         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1372         struct ecore_mcp_mb_params mb_params;
1373         struct eth_phy_cfg phy_cfg;
1374         enum _ecore_status_t rc = ECORE_SUCCESS;
1375         u32 cmd;
1376
1377 #ifndef ASIC_ONLY
1378         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1379                 return ECORE_SUCCESS;
1380 #endif
1381
1382         /* Set the shmem configuration according to params */
1383         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1384         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1385         if (!params->speed.autoneg)
1386                 phy_cfg.speed = params->speed.forced_speed;
1387         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1388         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1389         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1390         phy_cfg.adv_speed = params->speed.advertised_speeds;
1391         phy_cfg.loopback_mode = params->loopback_mode;
1392
1393         /* There are MFWs that share this capability regardless of whether
1394          * this is feasible or not. And given that at the very least adv_caps
1395          * would be set internally by ecore, we want to make sure LFA would
1396          * still work.
1397          */
1398         if ((p_hwfn->mcp_info->capabilities &
1399              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1400             params->eee.enable) {
1401                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1402                 if (params->eee.tx_lpi_enable)
1403                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1404                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1405                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1406                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1407                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1408                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1409                                     EEE_TX_TIMER_USEC_OFFSET) &
1410                                         EEE_TX_TIMER_USEC_MASK;
1411         }
1412
1413         p_hwfn->b_drv_link_init = b_up;
1414
1415         if (b_up)
1416                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1417                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1418                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1419                            phy_cfg.loopback_mode);
1420         else
1421                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1422
1423         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1424         mb_params.cmd = cmd;
1425         mb_params.p_data_src = &phy_cfg;
1426         mb_params.data_src_size = sizeof(phy_cfg);
1427         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1428
1429         /* if mcp fails to respond we must abort */
1430         if (rc != ECORE_SUCCESS) {
1431                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1432                 return rc;
1433         }
1434
1435         /* Mimic link-change attention, done for several reasons:
1436          *  - On reset, there's no guarantee MFW would trigger
1437          *    an attention.
1438          *  - On initialization, older MFWs might not indicate link change
1439          *    during LFA, so we'll never get an UP indication.
1440          */
1441         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1442
1443         return ECORE_SUCCESS;
1444 }
1445
1446 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1447                                    struct ecore_ptt *p_ptt)
1448 {
1449         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1450
1451         /* TODO - Add support for VFs */
1452         if (IS_VF(p_hwfn->p_dev))
1453                 return ECORE_INVAL;
1454
1455         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1456                                                  PUBLIC_PATH);
1457         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1458         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1459
1460         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1461                                  path_addr +
1462                                  OFFSETOF(struct public_path, process_kill)) &
1463             PROCESS_KILL_COUNTER_MASK;
1464
1465         return proc_kill_cnt;
1466 }
1467
1468 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1469                                           struct ecore_ptt *p_ptt)
1470 {
1471         struct ecore_dev *p_dev = p_hwfn->p_dev;
1472         u32 proc_kill_cnt;
1473
1474         /* Prevent possible attentions/interrupts during the recovery handling
1475          * and till its load phase, during which they will be re-enabled.
1476          */
1477         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1478
1479         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1480
1481         /* The following operations should be done once, and thus in CMT mode
1482          * are carried out by only the first HW function.
1483          */
1484         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1485                 return;
1486
1487         if (p_dev->recov_in_prog) {
1488                 DP_NOTICE(p_hwfn, false,
1489                           "Ignoring the indication since a recovery"
1490                           " process is already in progress\n");
1491                 return;
1492         }
1493
1494         p_dev->recov_in_prog = true;
1495
1496         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1497         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1498
1499         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1500 }
1501
1502 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1503                                           struct ecore_ptt *p_ptt,
1504                                           enum MFW_DRV_MSG_TYPE type)
1505 {
1506         enum ecore_mcp_protocol_type stats_type;
1507         union ecore_mcp_protocol_stats stats;
1508         struct ecore_mcp_mb_params mb_params;
1509         u32 hsi_param;
1510         enum _ecore_status_t rc;
1511
1512         switch (type) {
1513         case MFW_DRV_MSG_GET_LAN_STATS:
1514                 stats_type = ECORE_MCP_LAN_STATS;
1515                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1516                 break;
1517         default:
1518                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1519                 return;
1520         }
1521
1522         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1523
1524         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1525         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1526         mb_params.param = hsi_param;
1527         mb_params.p_data_src = &stats;
1528         mb_params.data_src_size = sizeof(stats);
1529         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1530         if (rc != ECORE_SUCCESS)
1531                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1532 }
1533
1534 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1535                                     struct public_func *p_shmem_info)
1536 {
1537         struct ecore_mcp_function_info *p_info;
1538
1539         p_info = &p_hwfn->mcp_info->func_info;
1540
1541         /* TODO - bandwidth min/max should have valid values of 1-100,
1542          * as well as some indication that the feature is disabled.
1543          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1544          * limit and correct value to min `1' and max `100' if limit isn't in
1545          * range.
1546          */
1547         p_info->bandwidth_min = (p_shmem_info->config &
1548                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1549             FUNC_MF_CFG_MIN_BW_OFFSET;
1550         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1551                 DP_INFO(p_hwfn,
1552                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1553                         p_info->bandwidth_min);
1554                 p_info->bandwidth_min = 1;
1555         }
1556
1557         p_info->bandwidth_max = (p_shmem_info->config &
1558                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1559             FUNC_MF_CFG_MAX_BW_OFFSET;
1560         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1561                 DP_INFO(p_hwfn,
1562                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1563                         p_info->bandwidth_max);
1564                 p_info->bandwidth_max = 100;
1565         }
1566 }
1567
1568 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1569                                     struct ecore_ptt *p_ptt,
1570                                     struct public_func *p_data,
1571                                     int pfid)
1572 {
1573         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1574                                         PUBLIC_FUNC);
1575         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1576         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1577         u32 i, size;
1578
1579         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1580
1581         size = OSAL_MIN_T(u32, sizeof(*p_data),
1582                           SECTION_SIZE(mfw_path_offsize));
1583         for (i = 0; i < size / sizeof(u32); i++)
1584                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1585                                               func_addr + (i << 2));
1586
1587         return size;
1588 }
1589
1590 static void
1591 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1592 {
1593         struct ecore_mcp_function_info *p_info;
1594         struct public_func shmem_info;
1595         u32 resp = 0, param = 0;
1596
1597         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1598
1599         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1600
1601         p_info = &p_hwfn->mcp_info->func_info;
1602
1603         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1604
1605         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1606
1607         /* Acknowledge the MFW */
1608         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1609                       &param);
1610 }
1611
1612 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1613 {
1614         /* A single notification should be sent to upper driver in CMT mode */
1615         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1616                 return;
1617
1618         DP_NOTICE(p_hwfn, false,
1619                   "Fan failure was detected on the network interface card"
1620                   " and it's going to be shut down.\n");
1621
1622         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1623 }
1624
1625 struct ecore_mdump_cmd_params {
1626         u32 cmd;
1627         void *p_data_src;
1628         u8 data_src_size;
1629         void *p_data_dst;
1630         u8 data_dst_size;
1631         u32 mcp_resp;
1632 };
1633
1634 static enum _ecore_status_t
1635 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1636                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1637 {
1638         struct ecore_mcp_mb_params mb_params;
1639         enum _ecore_status_t rc;
1640
1641         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1642         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1643         mb_params.param = p_mdump_cmd_params->cmd;
1644         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1645         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1646         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1647         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1648         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1649         if (rc != ECORE_SUCCESS)
1650                 return rc;
1651
1652         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1653
1654         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1655                 DP_INFO(p_hwfn,
1656                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1657                         p_mdump_cmd_params->cmd);
1658                 rc = ECORE_NOTIMPL;
1659         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1660                 DP_INFO(p_hwfn,
1661                         "The mdump command is not supported by the MFW\n");
1662                 rc = ECORE_NOTIMPL;
1663         }
1664
1665         return rc;
1666 }
1667
1668 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1669                                                 struct ecore_ptt *p_ptt)
1670 {
1671         struct ecore_mdump_cmd_params mdump_cmd_params;
1672
1673         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1674         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1675
1676         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1677 }
1678
1679 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1680                                                 struct ecore_ptt *p_ptt,
1681                                                 u32 epoch)
1682 {
1683         struct ecore_mdump_cmd_params mdump_cmd_params;
1684
1685         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1686         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1687         mdump_cmd_params.p_data_src = &epoch;
1688         mdump_cmd_params.data_src_size = sizeof(epoch);
1689
1690         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1691 }
1692
1693 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1694                                              struct ecore_ptt *p_ptt)
1695 {
1696         struct ecore_mdump_cmd_params mdump_cmd_params;
1697
1698         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1699         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1700
1701         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1702 }
1703
1704 static enum _ecore_status_t
1705 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1706                            struct mdump_config_stc *p_mdump_config)
1707 {
1708         struct ecore_mdump_cmd_params mdump_cmd_params;
1709         enum _ecore_status_t rc;
1710
1711         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1712         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1713         mdump_cmd_params.p_data_dst = p_mdump_config;
1714         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1715
1716         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1717         if (rc != ECORE_SUCCESS)
1718                 return rc;
1719
1720         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1721                 DP_INFO(p_hwfn,
1722                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1723                         mdump_cmd_params.mcp_resp);
1724                 rc = ECORE_UNKNOWN_ERROR;
1725         }
1726
1727         return rc;
1728 }
1729
1730 enum _ecore_status_t
1731 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1732                          struct ecore_mdump_info *p_mdump_info)
1733 {
1734         u32 addr, global_offsize, global_addr;
1735         struct mdump_config_stc mdump_config;
1736         enum _ecore_status_t rc;
1737
1738         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1739
1740         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1741                                     PUBLIC_GLOBAL);
1742         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1743         global_addr = SECTION_ADDR(global_offsize, 0);
1744         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1745                                         global_addr +
1746                                         OFFSETOF(struct public_global,
1747                                                  mdump_reason));
1748
1749         if (p_mdump_info->reason) {
1750                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1751                 if (rc != ECORE_SUCCESS)
1752                         return rc;
1753
1754                 p_mdump_info->version = mdump_config.version;
1755                 p_mdump_info->config = mdump_config.config;
1756                 p_mdump_info->epoch = mdump_config.epoc;
1757                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1758                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1759
1760                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1761                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1762                            p_mdump_info->reason, p_mdump_info->version,
1763                            p_mdump_info->config, p_mdump_info->epoch,
1764                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1765         } else {
1766                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1767                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1768         }
1769
1770         return ECORE_SUCCESS;
1771 }
1772
1773 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1774                                                 struct ecore_ptt *p_ptt)
1775 {
1776         struct ecore_mdump_cmd_params mdump_cmd_params;
1777
1778         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1779         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1780
1781         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1782 }
1783
1784 enum _ecore_status_t
1785 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1786                            struct ecore_mdump_retain_data *p_mdump_retain)
1787 {
1788         struct ecore_mdump_cmd_params mdump_cmd_params;
1789         struct mdump_retain_data_stc mfw_mdump_retain;
1790         enum _ecore_status_t rc;
1791
1792         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1793         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1794         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1795         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1796
1797         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1798         if (rc != ECORE_SUCCESS)
1799                 return rc;
1800
1801         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1802                 DP_INFO(p_hwfn,
1803                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1804                         mdump_cmd_params.mcp_resp);
1805                 return ECORE_UNKNOWN_ERROR;
1806         }
1807
1808         p_mdump_retain->valid = mfw_mdump_retain.valid;
1809         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1810         p_mdump_retain->pf = mfw_mdump_retain.pf;
1811         p_mdump_retain->status = mfw_mdump_retain.status;
1812
1813         return ECORE_SUCCESS;
1814 }
1815
1816 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1817                                                 struct ecore_ptt *p_ptt)
1818 {
1819         struct ecore_mdump_cmd_params mdump_cmd_params;
1820
1821         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1822         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1823
1824         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1825 }
1826
1827 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1828                                             struct ecore_ptt *p_ptt)
1829 {
1830         struct ecore_mdump_retain_data mdump_retain;
1831         enum _ecore_status_t rc;
1832
1833         /* In CMT mode - no need for more than a single acknowledgment to the
1834          * MFW, and no more than a single notification to the upper driver.
1835          */
1836         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1837                 return;
1838
1839         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1840         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1841                 DP_NOTICE(p_hwfn, false,
1842                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1843                           mdump_retain.epoch, mdump_retain.pf,
1844                           mdump_retain.status);
1845         } else {
1846                 DP_NOTICE(p_hwfn, false,
1847                           "The MFW notified that a critical error occurred in the device\n");
1848         }
1849
1850         if (p_hwfn->p_dev->allow_mdump) {
1851                 DP_NOTICE(p_hwfn, false,
1852                           "Not acknowledging the notification to allow the MFW crash dump\n");
1853                 return;
1854         }
1855
1856         DP_NOTICE(p_hwfn, false,
1857                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1858         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1859         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1860 }
1861
1862 void
1863 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1864 {
1865         struct public_func shmem_info;
1866         u32 port_cfg, val;
1867
1868         if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
1869                 return;
1870
1871         OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1872         port_cfg = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1873                             OFFSETOF(struct public_port, oem_cfg_port));
1874         val = GET_MFW_FIELD(port_cfg, OEM_CFG_CHANNEL_TYPE);
1875         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1876                 DP_NOTICE(p_hwfn, false, "Incorrect UFP Channel type  %d\n",
1877                           val);
1878
1879         val = GET_MFW_FIELD(port_cfg, OEM_CFG_SCHED_TYPE);
1880         if (val == OEM_CFG_SCHED_TYPE_ETS)
1881                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_ETS;
1882         else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW)
1883                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_VNIC_BW;
1884         else
1885                 DP_NOTICE(p_hwfn, false, "Unknown UFP scheduling mode %d\n",
1886                           val);
1887
1888         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1889                                  MCP_PF_ID(p_hwfn));
1890         val = GET_MFW_FIELD(shmem_info.oem_cfg_func, OEM_CFG_FUNC_TC);
1891         p_hwfn->ufp_info.tc = (u8)val;
1892         val = GET_MFW_FIELD(shmem_info.oem_cfg_func,
1893                             OEM_CFG_FUNC_HOST_PRI_CTRL);
1894         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC)
1895                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_VNIC;
1896         else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS)
1897                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_OS;
1898         else
1899                 DP_NOTICE(p_hwfn, false, "Unknown Host priority control %d\n",
1900                           val);
1901
1902         DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1903                    "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1904                    p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1905                    p_hwfn->ufp_info.pri_type);
1906 }
1907
1908 static enum _ecore_status_t
1909 ecore_mcp_handle_ufp_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1910 {
1911         ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
1912
1913         if (p_hwfn->ufp_info.mode == ECORE_UFP_MODE_VNIC_BW) {
1914                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1915                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1916
1917                 ecore_qm_reconf(p_hwfn, p_ptt);
1918         } else {
1919                 /* Merge UFP TC with the dcbx TC data */
1920                 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1921                                             ECORE_DCBX_OPERATIONAL_MIB);
1922         }
1923
1924         /* update storm FW with negotiation results */
1925         ecore_sp_pf_update_ufp(p_hwfn);
1926
1927         return ECORE_SUCCESS;
1928 }
1929
1930 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1931                                              struct ecore_ptt *p_ptt)
1932 {
1933         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1934         enum _ecore_status_t rc = ECORE_SUCCESS;
1935         bool found = false;
1936         u16 i;
1937
1938         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1939
1940         /* Read Messages from MFW */
1941         ecore_mcp_read_mb(p_hwfn, p_ptt);
1942
1943         /* Compare current messages to old ones */
1944         for (i = 0; i < info->mfw_mb_length; i++) {
1945                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1946                         continue;
1947
1948                 found = true;
1949
1950                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1951                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1952                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1953
1954                 switch (i) {
1955                 case MFW_DRV_MSG_LINK_CHANGE:
1956                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1957                         break;
1958                 case MFW_DRV_MSG_VF_DISABLED:
1959                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1960                         break;
1961                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1962                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1963                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1964                         break;
1965                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1966                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1967                                                     ECORE_DCBX_REMOTE_MIB);
1968                         break;
1969                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1970                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1971                                                     ECORE_DCBX_OPERATIONAL_MIB);
1972                         break;
1973                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1974                         ecore_mcp_handle_ufp_event(p_hwfn, p_ptt);
1975                         break;
1976                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1977                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1978                         break;
1979                 case MFW_DRV_MSG_ERROR_RECOVERY:
1980                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1981                         break;
1982                 case MFW_DRV_MSG_GET_LAN_STATS:
1983                 case MFW_DRV_MSG_GET_FCOE_STATS:
1984                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1985                 case MFW_DRV_MSG_GET_RDMA_STATS:
1986                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1987                         break;
1988                 case MFW_DRV_MSG_BW_UPDATE:
1989                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1990                         break;
1991                 case MFW_DRV_MSG_FAILURE_DETECTED:
1992                         ecore_mcp_handle_fan_failure(p_hwfn);
1993                         break;
1994                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1995                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1996                         break;
1997                 default:
1998                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1999                         rc = ECORE_INVAL;
2000                 }
2001         }
2002
2003         /* ACK everything */
2004         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2005                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
2006
2007                 /* MFW expect answer in BE, so we force write in that format */
2008                 ecore_wr(p_hwfn, p_ptt,
2009                          info->mfw_mb_addr + sizeof(u32) +
2010                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2011                          sizeof(u32) + i * sizeof(u32), val);
2012         }
2013
2014         if (!found) {
2015                 DP_NOTICE(p_hwfn, false,
2016                           "Received an MFW message indication but no"
2017                           " new message!\n");
2018                 rc = ECORE_INVAL;
2019         }
2020
2021         /* Copy the new mfw messages into the shadow */
2022         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2023
2024         return rc;
2025 }
2026
2027 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
2028                                            struct ecore_ptt *p_ptt,
2029                                            u32 *p_mfw_ver,
2030                                            u32 *p_running_bundle_id)
2031 {
2032         u32 global_offsize;
2033
2034 #ifndef ASIC_ONLY
2035         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2036                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
2037                 return ECORE_SUCCESS;
2038         }
2039 #endif
2040
2041         if (IS_VF(p_hwfn->p_dev)) {
2042                 if (p_hwfn->vf_iov_info) {
2043                         struct pfvf_acquire_resp_tlv *p_resp;
2044
2045                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2046                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2047                         return ECORE_SUCCESS;
2048                 } else {
2049                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2050                                    "VF requested MFW version prior to ACQUIRE\n");
2051                         return ECORE_INVAL;
2052                 }
2053         }
2054
2055         global_offsize = ecore_rd(p_hwfn, p_ptt,
2056                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
2057                                                        public_base,
2058                                                        PUBLIC_GLOBAL));
2059         *p_mfw_ver =
2060             ecore_rd(p_hwfn, p_ptt,
2061                      SECTION_ADDR(global_offsize,
2062                                   0) + OFFSETOF(struct public_global, mfw_ver));
2063
2064         if (p_running_bundle_id != OSAL_NULL) {
2065                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
2066                                                 SECTION_ADDR(global_offsize,
2067                                                              0) +
2068                                                 OFFSETOF(struct public_global,
2069                                                          running_bundle_id));
2070         }
2071
2072         return ECORE_SUCCESS;
2073 }
2074
2075 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2076                                               struct ecore_ptt *p_ptt,
2077                                               u32 *p_media_type)
2078 {
2079
2080         /* TODO - Add support for VFs */
2081         if (IS_VF(p_hwfn->p_dev))
2082                 return ECORE_INVAL;
2083
2084         if (!ecore_mcp_is_init(p_hwfn)) {
2085                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2086                 return ECORE_BUSY;
2087         }
2088
2089         if (!p_ptt) {
2090                 *p_media_type = MEDIA_UNSPECIFIED;
2091                 return ECORE_INVAL;
2092         } else {
2093                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2094                                          p_hwfn->mcp_info->port_addr +
2095                                          OFFSETOF(struct public_port,
2096                                                   media_type));
2097         }
2098
2099         return ECORE_SUCCESS;
2100 }
2101
2102 /* @DPDK */
2103 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2104 static void
2105 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2106                                  enum ecore_pci_personality *p_proto)
2107 {
2108         *p_proto = ECORE_PCI_ETH;
2109
2110         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2111                    "According to Legacy capabilities, L2 personality is %08x\n",
2112                    (u32)*p_proto);
2113 }
2114
2115 /* @DPDK */
2116 static enum _ecore_status_t
2117 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2118                               struct ecore_ptt *p_ptt,
2119                               enum ecore_pci_personality *p_proto)
2120 {
2121         u32 resp = 0, param = 0;
2122         enum _ecore_status_t rc;
2123
2124         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2125                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2126                    (u32)*p_proto, resp, param);
2127         return ECORE_SUCCESS;
2128 }
2129
2130 static enum _ecore_status_t
2131 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2132                           struct public_func *p_info,
2133                           struct ecore_ptt *p_ptt,
2134                           enum ecore_pci_personality *p_proto)
2135 {
2136         enum _ecore_status_t rc = ECORE_SUCCESS;
2137
2138         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2139         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2140                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2141                     ECORE_SUCCESS)
2142                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2143                 break;
2144         default:
2145                 rc = ECORE_INVAL;
2146         }
2147
2148         return rc;
2149 }
2150
2151 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2152                                                     struct ecore_ptt *p_ptt)
2153 {
2154         struct ecore_mcp_function_info *info;
2155         struct public_func shmem_info;
2156
2157         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2158         info = &p_hwfn->mcp_info->func_info;
2159
2160         info->pause_on_host = (shmem_info.config &
2161                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2162
2163         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2164                                       &info->protocol)) {
2165                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2166                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2167                 return ECORE_INVAL;
2168         }
2169
2170         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2171
2172         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2173                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2174                 info->mac[1] = (u8)(shmem_info.mac_upper);
2175                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2176                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2177                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2178                 info->mac[5] = (u8)(shmem_info.mac_lower);
2179         } else {
2180                 /* TODO - are there protocols for which there's no MAC? */
2181                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2182         }
2183
2184         /* TODO - are these calculations true for BE machine? */
2185         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2186                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2187         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2188                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2189
2190         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2191
2192         info->mtu = (u16)shmem_info.mtu_size;
2193
2194         if (info->mtu == 0)
2195                 info->mtu = 1500;
2196
2197         info->mtu = (u16)shmem_info.mtu_size;
2198
2199         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2200                    "Read configuration from shmem: pause_on_host %02x"
2201                     " protocol %02x BW [%02x - %02x]"
2202                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2203                     " node %lx ovlan %04x\n",
2204                    info->pause_on_host, info->protocol,
2205                    info->bandwidth_min, info->bandwidth_max,
2206                    info->mac[0], info->mac[1], info->mac[2],
2207                    info->mac[3], info->mac[4], info->mac[5],
2208                    (unsigned long)info->wwn_port,
2209                    (unsigned long)info->wwn_node, info->ovlan);
2210
2211         return ECORE_SUCCESS;
2212 }
2213
2214 struct ecore_mcp_link_params
2215 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2216 {
2217         if (!p_hwfn || !p_hwfn->mcp_info)
2218                 return OSAL_NULL;
2219         return &p_hwfn->mcp_info->link_input;
2220 }
2221
2222 struct ecore_mcp_link_state
2223 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2224 {
2225         if (!p_hwfn || !p_hwfn->mcp_info)
2226                 return OSAL_NULL;
2227
2228 #ifndef ASIC_ONLY
2229         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2230                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2231                 p_hwfn->mcp_info->link_output.link_up = true;
2232         }
2233 #endif
2234
2235         return &p_hwfn->mcp_info->link_output;
2236 }
2237
2238 struct ecore_mcp_link_capabilities
2239 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2240 {
2241         if (!p_hwfn || !p_hwfn->mcp_info)
2242                 return OSAL_NULL;
2243         return &p_hwfn->mcp_info->link_capabilities;
2244 }
2245
2246 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2247                                      struct ecore_ptt *p_ptt)
2248 {
2249         u32 resp = 0, param = 0;
2250         enum _ecore_status_t rc;
2251
2252         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2253                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2254
2255         /* Wait for the drain to complete before returning */
2256         OSAL_MSLEEP(1020);
2257
2258         return rc;
2259 }
2260
2261 const struct ecore_mcp_function_info
2262 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2263 {
2264         if (!p_hwfn || !p_hwfn->mcp_info)
2265                 return OSAL_NULL;
2266         return &p_hwfn->mcp_info->func_info;
2267 }
2268
2269 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2270                                   struct ecore_ptt *p_ptt, u32 personalities)
2271 {
2272         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2273         struct public_func shmem_info;
2274         int i, count = 0, num_pfs;
2275
2276         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2277
2278         for (i = 0; i < num_pfs; i++) {
2279                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2280                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2281                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2282                         continue;
2283
2284                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2285                                               &protocol) !=
2286                     ECORE_SUCCESS)
2287                         continue;
2288
2289                 if ((1 << ((u32)protocol)) & personalities)
2290                         count++;
2291         }
2292
2293         return count;
2294 }
2295
2296 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2297                                               struct ecore_ptt *p_ptt,
2298                                               u32 *p_flash_size)
2299 {
2300         u32 flash_size;
2301
2302 #ifndef ASIC_ONLY
2303         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2304                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2305                 return ECORE_INVAL;
2306         }
2307 #endif
2308
2309         if (IS_VF(p_hwfn->p_dev))
2310                 return ECORE_INVAL;
2311
2312         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2313         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2314                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2315         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2316
2317         *p_flash_size = flash_size;
2318
2319         return ECORE_SUCCESS;
2320 }
2321
2322 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2323                                                   struct ecore_ptt *p_ptt)
2324 {
2325         struct ecore_dev *p_dev = p_hwfn->p_dev;
2326
2327         if (p_dev->recov_in_prog) {
2328                 DP_NOTICE(p_hwfn, false,
2329                           "Avoid triggering a recovery since such a process"
2330                           " is already in progress\n");
2331                 return ECORE_AGAIN;
2332         }
2333
2334         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2335         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2336
2337         return ECORE_SUCCESS;
2338 }
2339
2340 static enum _ecore_status_t
2341 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2342                             struct ecore_ptt *p_ptt,
2343                             u8 vf_id, u8 num)
2344 {
2345         u32 resp = 0, param = 0, rc_param = 0;
2346         enum _ecore_status_t rc;
2347
2348 /* Only Leader can configure MSIX, and need to take CMT into account */
2349
2350         if (!IS_LEAD_HWFN(p_hwfn))
2351                 return ECORE_SUCCESS;
2352         num *= p_hwfn->p_dev->num_hwfns;
2353
2354         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2355             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2356         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2357             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2358
2359         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2360                            &resp, &rc_param);
2361
2362         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2363                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2364                           vf_id);
2365                 rc = ECORE_INVAL;
2366         } else {
2367                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2368                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2369                             num, vf_id);
2370         }
2371
2372         return rc;
2373 }
2374
2375 static enum _ecore_status_t
2376 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2377                             struct ecore_ptt *p_ptt,
2378                             u8 num)
2379 {
2380         u32 resp = 0, param = num, rc_param = 0;
2381         enum _ecore_status_t rc;
2382
2383         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2384                            param, &resp, &rc_param);
2385
2386         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2387                 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2388                 rc = ECORE_INVAL;
2389         } else {
2390                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2391                            "Requested 0x%02x MSI-x interrupts for VFs\n",
2392                            num);
2393         }
2394
2395         return rc;
2396 }
2397
2398 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2399                                               struct ecore_ptt *p_ptt,
2400                                               u8 vf_id, u8 num)
2401 {
2402         if (ECORE_IS_BB(p_hwfn->p_dev))
2403                 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2404         else
2405                 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2406 }
2407
2408 enum _ecore_status_t
2409 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2410                            struct ecore_mcp_drv_version *p_ver)
2411 {
2412         struct ecore_mcp_mb_params mb_params;
2413         struct drv_version_stc drv_version;
2414         u32 num_words, i;
2415         void *p_name;
2416         OSAL_BE32 val;
2417         enum _ecore_status_t rc;
2418
2419 #ifndef ASIC_ONLY
2420         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2421                 return ECORE_SUCCESS;
2422 #endif
2423
2424         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2425         drv_version.version = p_ver->version;
2426         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2427         for (i = 0; i < num_words; i++) {
2428                 /* The driver name is expected to be in a big-endian format */
2429                 p_name = &p_ver->name[i * sizeof(u32)];
2430                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2431                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2432         }
2433
2434         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2435         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2436         mb_params.p_data_src = &drv_version;
2437         mb_params.data_src_size = sizeof(drv_version);
2438         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2439         if (rc != ECORE_SUCCESS)
2440                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2441
2442         return rc;
2443 }
2444
2445 /* A maximal 100 msec waiting time for the MCP to halt */
2446 #define ECORE_MCP_HALT_SLEEP_MS         10
2447 #define ECORE_MCP_HALT_MAX_RETRIES      10
2448
2449 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2450                                     struct ecore_ptt *p_ptt)
2451 {
2452         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2453         enum _ecore_status_t rc;
2454
2455         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2456                            &param);
2457         if (rc != ECORE_SUCCESS) {
2458                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2459                 return rc;
2460         }
2461
2462         do {
2463                 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2464                 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2465                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2466                         break;
2467         } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2468
2469         if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2470                 DP_NOTICE(p_hwfn, false,
2471                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2472                           ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2473                 return ECORE_BUSY;
2474         }
2475
2476         ecore_mcp_cmd_set_blocking(p_hwfn, true);
2477
2478         return ECORE_SUCCESS;
2479 }
2480
2481 #define ECORE_MCP_RESUME_SLEEP_MS       10
2482
2483 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2484                                       struct ecore_ptt *p_ptt)
2485 {
2486         u32 cpu_mode, cpu_state;
2487
2488         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2489
2490         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2491         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2492         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2493
2494         OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2495         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2496
2497         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2498                 DP_NOTICE(p_hwfn, false,
2499                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2500                           cpu_mode, cpu_state);
2501                 return ECORE_BUSY;
2502         }
2503
2504         ecore_mcp_cmd_set_blocking(p_hwfn, false);
2505
2506         return ECORE_SUCCESS;
2507 }
2508
2509 enum _ecore_status_t
2510 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2511                                    struct ecore_ptt *p_ptt,
2512                                    enum ecore_ov_client client)
2513 {
2514         enum _ecore_status_t rc;
2515         u32 resp = 0, param = 0;
2516         u32 drv_mb_param;
2517
2518         switch (client) {
2519         case ECORE_OV_CLIENT_DRV:
2520                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2521                 break;
2522         case ECORE_OV_CLIENT_USER:
2523                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2524                 break;
2525         case ECORE_OV_CLIENT_VENDOR_SPEC:
2526                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2527                 break;
2528         default:
2529                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2530                 return ECORE_INVAL;
2531         }
2532
2533         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2534                            drv_mb_param, &resp, &param);
2535         if (rc != ECORE_SUCCESS)
2536                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2537
2538         return rc;
2539 }
2540
2541 enum _ecore_status_t
2542 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2543                                  struct ecore_ptt *p_ptt,
2544                                  enum ecore_ov_driver_state drv_state)
2545 {
2546         enum _ecore_status_t rc;
2547         u32 resp = 0, param = 0;
2548         u32 drv_mb_param;
2549
2550         switch (drv_state) {
2551         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2552                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2553                 break;
2554         case ECORE_OV_DRIVER_STATE_DISABLED:
2555                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2556                 break;
2557         case ECORE_OV_DRIVER_STATE_ACTIVE:
2558                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2559                 break;
2560         default:
2561                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2562                 return ECORE_INVAL;
2563         }
2564
2565         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2566                            drv_mb_param, &resp, &param);
2567         if (rc != ECORE_SUCCESS)
2568                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2569
2570         return rc;
2571 }
2572
2573 enum _ecore_status_t
2574 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2575                          struct ecore_fc_npiv_tbl *p_table)
2576 {
2577         return 0;
2578 }
2579
2580 enum _ecore_status_t
2581 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2582                         struct ecore_ptt *p_ptt, u16 mtu)
2583 {
2584         return 0;
2585 }
2586
2587 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2588                                        struct ecore_ptt *p_ptt,
2589                                        enum ecore_led_mode mode)
2590 {
2591         u32 resp = 0, param = 0, drv_mb_param;
2592         enum _ecore_status_t rc;
2593
2594         switch (mode) {
2595         case ECORE_LED_MODE_ON:
2596                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2597                 break;
2598         case ECORE_LED_MODE_OFF:
2599                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2600                 break;
2601         case ECORE_LED_MODE_RESTORE:
2602                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2603                 break;
2604         default:
2605                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2606                 return ECORE_INVAL;
2607         }
2608
2609         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2610                            drv_mb_param, &resp, &param);
2611         if (rc != ECORE_SUCCESS)
2612                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2613
2614         return rc;
2615 }
2616
2617 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2618                                              struct ecore_ptt *p_ptt,
2619                                              u32 mask_parities)
2620 {
2621         u32 resp = 0, param = 0;
2622         enum _ecore_status_t rc;
2623
2624         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2625                            mask_parities, &resp, &param);
2626
2627         if (rc != ECORE_SUCCESS) {
2628                 DP_ERR(p_hwfn,
2629                        "MCP response failure for mask parities, aborting\n");
2630         } else if (resp != FW_MSG_CODE_OK) {
2631                 DP_ERR(p_hwfn,
2632                        "MCP did not ack mask parity request. Old MFW?\n");
2633                 rc = ECORE_INVAL;
2634         }
2635
2636         return rc;
2637 }
2638
2639 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2640                                         u8 *p_buf, u32 len)
2641 {
2642         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2643         u32 bytes_left, offset, bytes_to_copy, buf_size;
2644         u32 nvm_offset, resp, param;
2645         struct ecore_ptt *p_ptt;
2646         enum _ecore_status_t rc = ECORE_SUCCESS;
2647
2648         p_ptt = ecore_ptt_acquire(p_hwfn);
2649         if (!p_ptt)
2650                 return ECORE_BUSY;
2651
2652         bytes_left = len;
2653         offset = 0;
2654         while (bytes_left > 0) {
2655                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2656                                            MCP_DRV_NVM_BUF_LEN);
2657                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2658                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
2659                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2660                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2661                                           nvm_offset, &resp, &param, &buf_size,
2662                                           (u32 *)(p_buf + offset));
2663                 if (rc != ECORE_SUCCESS) {
2664                         DP_NOTICE(p_dev, false,
2665                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2666                                   rc);
2667                         resp = FW_MSG_CODE_ERROR;
2668                         break;
2669                 }
2670
2671                 if (resp != FW_MSG_CODE_NVM_OK) {
2672                         DP_NOTICE(p_dev, false,
2673                                   "nvm read failed, resp = 0x%08x\n", resp);
2674                         rc = ECORE_UNKNOWN_ERROR;
2675                         break;
2676                 }
2677
2678                 /* This can be a lengthy process, and it's possible scheduler
2679                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2680                  */
2681                 if (bytes_left % 0x1000 <
2682                     (bytes_left - buf_size) % 0x1000)
2683                         OSAL_MSLEEP(1);
2684
2685                 offset += buf_size;
2686                 bytes_left -= buf_size;
2687         }
2688
2689         p_dev->mcp_nvm_resp = resp;
2690         ecore_ptt_release(p_hwfn, p_ptt);
2691
2692         return rc;
2693 }
2694
2695 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2696                                         u32 addr, u8 *p_buf, u32 len)
2697 {
2698         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2699         struct ecore_ptt *p_ptt;
2700         u32 resp, param;
2701         enum _ecore_status_t rc;
2702
2703         p_ptt = ecore_ptt_acquire(p_hwfn);
2704         if (!p_ptt)
2705                 return ECORE_BUSY;
2706
2707         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2708                                   (cmd == ECORE_PHY_CORE_READ) ?
2709                                   DRV_MSG_CODE_PHY_CORE_READ :
2710                                   DRV_MSG_CODE_PHY_RAW_READ,
2711                                   addr, &resp, &param, &len, (u32 *)p_buf);
2712         if (rc != ECORE_SUCCESS)
2713                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2714
2715         p_dev->mcp_nvm_resp = resp;
2716         ecore_ptt_release(p_hwfn, p_ptt);
2717
2718         return rc;
2719 }
2720
2721 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2722 {
2723         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2724         struct ecore_ptt *p_ptt;
2725
2726         p_ptt = ecore_ptt_acquire(p_hwfn);
2727         if (!p_ptt)
2728                 return ECORE_BUSY;
2729
2730         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2731         ecore_ptt_release(p_hwfn, p_ptt);
2732
2733         return ECORE_SUCCESS;
2734 }
2735
2736 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2737 {
2738         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2739         struct ecore_ptt *p_ptt;
2740         u32 resp, param;
2741         enum _ecore_status_t rc;
2742
2743         p_ptt = ecore_ptt_acquire(p_hwfn);
2744         if (!p_ptt)
2745                 return ECORE_BUSY;
2746         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2747                            &resp, &param);
2748         p_dev->mcp_nvm_resp = resp;
2749         ecore_ptt_release(p_hwfn, p_ptt);
2750
2751         return rc;
2752 }
2753
2754 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2755                                                   u32 addr)
2756 {
2757         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2758         struct ecore_ptt *p_ptt;
2759         u32 resp, param;
2760         enum _ecore_status_t rc;
2761
2762         p_ptt = ecore_ptt_acquire(p_hwfn);
2763         if (!p_ptt)
2764                 return ECORE_BUSY;
2765         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2766                            &resp, &param);
2767         p_dev->mcp_nvm_resp = resp;
2768         ecore_ptt_release(p_hwfn, p_ptt);
2769
2770         return rc;
2771 }
2772
2773 /* rc receives ECORE_INVAL as default parameter because
2774  * it might not enter the while loop if the len is 0
2775  */
2776 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2777                                          u32 addr, u8 *p_buf, u32 len)
2778 {
2779         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2780         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2781         enum _ecore_status_t rc = ECORE_INVAL;
2782         struct ecore_ptt *p_ptt;
2783
2784         p_ptt = ecore_ptt_acquire(p_hwfn);
2785         if (!p_ptt)
2786                 return ECORE_BUSY;
2787
2788         switch (cmd) {
2789         case ECORE_PUT_FILE_DATA:
2790                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2791                 break;
2792         case ECORE_NVM_WRITE_NVRAM:
2793                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2794                 break;
2795         case ECORE_EXT_PHY_FW_UPGRADE:
2796                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2797                 break;
2798         default:
2799                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2800                           cmd);
2801                 rc = ECORE_INVAL;
2802                 goto out;
2803         }
2804
2805         buf_idx = 0;
2806         while (buf_idx < len) {
2807                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2808                                       MCP_DRV_NVM_BUF_LEN);
2809                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2810                               addr) +
2811                              buf_idx;
2812                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2813                                           &resp, &param, buf_size,
2814                                           (u32 *)&p_buf[buf_idx]);
2815                 if (rc != ECORE_SUCCESS) {
2816                         DP_NOTICE(p_dev, false,
2817                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2818                                   rc);
2819                         resp = FW_MSG_CODE_ERROR;
2820                         break;
2821                 }
2822
2823                 if (resp != FW_MSG_CODE_OK &&
2824                     resp != FW_MSG_CODE_NVM_OK &&
2825                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2826                         DP_NOTICE(p_dev, false,
2827                                   "nvm write failed, resp = 0x%08x\n", resp);
2828                         rc = ECORE_UNKNOWN_ERROR;
2829                         break;
2830                 }
2831
2832                 /* This can be a lengthy process, and it's possible scheduler
2833                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2834                  */
2835                 if (buf_idx % 0x1000 >
2836                     (buf_idx + buf_size) % 0x1000)
2837                         OSAL_MSLEEP(1);
2838
2839                 buf_idx += buf_size;
2840         }
2841
2842         p_dev->mcp_nvm_resp = resp;
2843 out:
2844         ecore_ptt_release(p_hwfn, p_ptt);
2845
2846         return rc;
2847 }
2848
2849 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2850                                          u32 addr, u8 *p_buf, u32 len)
2851 {
2852         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2853         struct ecore_ptt *p_ptt;
2854         u32 resp, param, nvm_cmd;
2855         enum _ecore_status_t rc;
2856
2857         p_ptt = ecore_ptt_acquire(p_hwfn);
2858         if (!p_ptt)
2859                 return ECORE_BUSY;
2860
2861         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2862                         DRV_MSG_CODE_PHY_RAW_WRITE;
2863         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2864                                   &resp, &param, len, (u32 *)p_buf);
2865         if (rc != ECORE_SUCCESS)
2866                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2867         p_dev->mcp_nvm_resp = resp;
2868         ecore_ptt_release(p_hwfn, p_ptt);
2869
2870         return rc;
2871 }
2872
2873 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2874                                                    u32 addr)
2875 {
2876         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2877         struct ecore_ptt *p_ptt;
2878         u32 resp, param;
2879         enum _ecore_status_t rc;
2880
2881         p_ptt = ecore_ptt_acquire(p_hwfn);
2882         if (!p_ptt)
2883                 return ECORE_BUSY;
2884
2885         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2886                            &resp, &param);
2887         p_dev->mcp_nvm_resp = resp;
2888         ecore_ptt_release(p_hwfn, p_ptt);
2889
2890         return rc;
2891 }
2892
2893 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2894                                             struct ecore_ptt *p_ptt,
2895                                             u32 port, u32 addr, u32 offset,
2896                                             u32 len, u8 *p_buf)
2897 {
2898         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2899         u32 resp, param;
2900         enum _ecore_status_t rc;
2901
2902         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2903                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2904         addr = offset;
2905         offset = 0;
2906         bytes_left = len;
2907         while (bytes_left > 0) {
2908                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2909                                            MAX_I2C_TRANSACTION_SIZE);
2910                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2911                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2912                 nvm_offset |= ((addr + offset) <<
2913                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2914                 nvm_offset |= (bytes_to_copy <<
2915                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2916                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2917                                           DRV_MSG_CODE_TRANSCEIVER_READ,
2918                                           nvm_offset, &resp, &param, &buf_size,
2919                                           (u32 *)(p_buf + offset));
2920                 if ((resp & FW_MSG_CODE_MASK) ==
2921                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2922                         return ECORE_NODEV;
2923                 } else if ((resp & FW_MSG_CODE_MASK) !=
2924                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2925                         return ECORE_UNKNOWN_ERROR;
2926
2927                 offset += buf_size;
2928                 bytes_left -= buf_size;
2929         }
2930
2931         return ECORE_SUCCESS;
2932 }
2933
2934 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2935                                              struct ecore_ptt *p_ptt,
2936                                              u32 port, u32 addr, u32 offset,
2937                                              u32 len, u8 *p_buf)
2938 {
2939         u32 buf_idx, buf_size, nvm_offset, resp, param;
2940         enum _ecore_status_t rc;
2941
2942         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2943                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2944         buf_idx = 0;
2945         while (buf_idx < len) {
2946                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2947                                       MAX_I2C_TRANSACTION_SIZE);
2948                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2949                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2950                 nvm_offset |= ((offset + buf_idx) <<
2951                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2952                 nvm_offset |= (buf_size <<
2953                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2954                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2955                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
2956                                           nvm_offset, &resp, &param, buf_size,
2957                                           (u32 *)&p_buf[buf_idx]);
2958                 if ((resp & FW_MSG_CODE_MASK) ==
2959                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2960                         return ECORE_NODEV;
2961                 } else if ((resp & FW_MSG_CODE_MASK) !=
2962                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2963                         return ECORE_UNKNOWN_ERROR;
2964
2965                 buf_idx += buf_size;
2966         }
2967
2968         return ECORE_SUCCESS;
2969 }
2970
2971 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2972                                          struct ecore_ptt *p_ptt,
2973                                          u16 gpio, u32 *gpio_val)
2974 {
2975         enum _ecore_status_t rc = ECORE_SUCCESS;
2976         u32 drv_mb_param = 0, rsp;
2977
2978         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2979
2980         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2981                            drv_mb_param, &rsp, gpio_val);
2982
2983         if (rc != ECORE_SUCCESS)
2984                 return rc;
2985
2986         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2987                 return ECORE_UNKNOWN_ERROR;
2988
2989         return ECORE_SUCCESS;
2990 }
2991
2992 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2993                                           struct ecore_ptt *p_ptt,
2994                                           u16 gpio, u16 gpio_val)
2995 {
2996         enum _ecore_status_t rc = ECORE_SUCCESS;
2997         u32 drv_mb_param = 0, param, rsp;
2998
2999         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
3000                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
3001
3002         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
3003                            drv_mb_param, &rsp, &param);
3004
3005         if (rc != ECORE_SUCCESS)
3006                 return rc;
3007
3008         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3009                 return ECORE_UNKNOWN_ERROR;
3010
3011         return ECORE_SUCCESS;
3012 }
3013
3014 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
3015                                          struct ecore_ptt *p_ptt,
3016                                          u16 gpio, u32 *gpio_direction,
3017                                          u32 *gpio_ctrl)
3018 {
3019         u32 drv_mb_param = 0, rsp, val = 0;
3020         enum _ecore_status_t rc = ECORE_SUCCESS;
3021
3022         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
3023
3024         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
3025                            drv_mb_param, &rsp, &val);
3026         if (rc != ECORE_SUCCESS)
3027                 return rc;
3028
3029         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
3030                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
3031         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
3032                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
3033
3034         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3035                 return ECORE_UNKNOWN_ERROR;
3036
3037         return ECORE_SUCCESS;
3038 }
3039
3040 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
3041                                                   struct ecore_ptt *p_ptt)
3042 {
3043         u32 drv_mb_param = 0, rsp, param;
3044         enum _ecore_status_t rc = ECORE_SUCCESS;
3045
3046         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3047                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3048
3049         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3050                            drv_mb_param, &rsp, &param);
3051
3052         if (rc != ECORE_SUCCESS)
3053                 return rc;
3054
3055         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3056             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3057                 rc = ECORE_UNKNOWN_ERROR;
3058
3059         return rc;
3060 }
3061
3062 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
3063                                                struct ecore_ptt *p_ptt)
3064 {
3065         u32 drv_mb_param, rsp, param;
3066         enum _ecore_status_t rc = ECORE_SUCCESS;
3067
3068         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3069                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3070
3071         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3072                            drv_mb_param, &rsp, &param);
3073
3074         if (rc != ECORE_SUCCESS)
3075                 return rc;
3076
3077         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3078             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3079                 rc = ECORE_UNKNOWN_ERROR;
3080
3081         return rc;
3082 }
3083
3084 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3085         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3086 {
3087         u32 drv_mb_param = 0, rsp;
3088         enum _ecore_status_t rc = ECORE_SUCCESS;
3089
3090         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3091                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3092
3093         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3094                            drv_mb_param, &rsp, num_images);
3095
3096         if (rc != ECORE_SUCCESS)
3097                 return rc;
3098
3099         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3100                 rc = ECORE_UNKNOWN_ERROR;
3101
3102         return rc;
3103 }
3104
3105 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3106         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3107         struct bist_nvm_image_att *p_image_att, u32 image_index)
3108 {
3109         u32 buf_size, nvm_offset, resp, param;
3110         enum _ecore_status_t rc;
3111
3112         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3113                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3114         nvm_offset |= (image_index <<
3115                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3116         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3117                                   nvm_offset, &resp, &param, &buf_size,
3118                                   (u32 *)p_image_att);
3119         if (rc != ECORE_SUCCESS)
3120                 return rc;
3121
3122         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3123             (p_image_att->return_code != 1))
3124                 rc = ECORE_UNKNOWN_ERROR;
3125
3126         return rc;
3127 }
3128
3129 enum _ecore_status_t
3130 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3131                                struct ecore_ptt *p_ptt,
3132                                struct ecore_temperature_info *p_temp_info)
3133 {
3134         struct ecore_temperature_sensor *p_temp_sensor;
3135         struct temperature_status_stc mfw_temp_info;
3136         struct ecore_mcp_mb_params mb_params;
3137         u32 val;
3138         enum _ecore_status_t rc;
3139         u8 i;
3140
3141         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3142         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3143         mb_params.p_data_dst = &mfw_temp_info;
3144         mb_params.data_dst_size = sizeof(mfw_temp_info);
3145         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3146         if (rc != ECORE_SUCCESS)
3147                 return rc;
3148
3149         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3150         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3151                                               ECORE_MAX_NUM_OF_SENSORS);
3152         for (i = 0; i < p_temp_info->num_sensors; i++) {
3153                 val = mfw_temp_info.sensor[i];
3154                 p_temp_sensor = &p_temp_info->sensors[i];
3155                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3156                                                  SENSOR_LOCATION_OFFSET;
3157                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3158                                                 THRESHOLD_HIGH_OFFSET;
3159                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3160                                           CRITICAL_TEMPERATURE_OFFSET;
3161                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3162                                               CURRENT_TEMP_OFFSET;
3163         }
3164
3165         return ECORE_SUCCESS;
3166 }
3167
3168 enum _ecore_status_t ecore_mcp_get_mba_versions(
3169         struct ecore_hwfn *p_hwfn,
3170         struct ecore_ptt *p_ptt,
3171         struct ecore_mba_vers *p_mba_vers)
3172 {
3173         u32 buf_size, resp, param;
3174         enum _ecore_status_t rc;
3175
3176         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3177                                   0, &resp, &param, &buf_size,
3178                                   &p_mba_vers->mba_vers[0]);
3179
3180         if (rc != ECORE_SUCCESS)
3181                 return rc;
3182
3183         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3184                 rc = ECORE_UNKNOWN_ERROR;
3185
3186         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3187                 rc = ECORE_UNKNOWN_ERROR;
3188
3189         return rc;
3190 }
3191
3192 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3193                                               struct ecore_ptt *p_ptt,
3194                                               u64 *num_events)
3195 {
3196         u32 rsp;
3197
3198         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3199                              0, &rsp, (u32 *)num_events);
3200 }
3201
3202 static enum resource_id_enum
3203 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3204 {
3205         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3206
3207         switch (res_id) {
3208         case ECORE_SB:
3209                 mfw_res_id = RESOURCE_NUM_SB_E;
3210                 break;
3211         case ECORE_L2_QUEUE:
3212                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3213                 break;
3214         case ECORE_VPORT:
3215                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3216                 break;
3217         case ECORE_RSS_ENG:
3218                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3219                 break;
3220         case ECORE_PQ:
3221                 mfw_res_id = RESOURCE_NUM_PQ_E;
3222                 break;
3223         case ECORE_RL:
3224                 mfw_res_id = RESOURCE_NUM_RL_E;
3225                 break;
3226         case ECORE_MAC:
3227         case ECORE_VLAN:
3228                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3229                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3230                 break;
3231         case ECORE_ILT:
3232                 mfw_res_id = RESOURCE_ILT_E;
3233                 break;
3234         case ECORE_LL2_QUEUE:
3235                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3236                 break;
3237         case ECORE_RDMA_CNQ_RAM:
3238         case ECORE_CMDQS_CQS:
3239                 /* CNQ/CMDQS are the same resource */
3240                 mfw_res_id = RESOURCE_CQS_E;
3241                 break;
3242         case ECORE_RDMA_STATS_QUEUE:
3243                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3244                 break;
3245         case ECORE_BDQ:
3246                 mfw_res_id = RESOURCE_BDQ_E;
3247                 break;
3248         default:
3249                 break;
3250         }
3251
3252         return mfw_res_id;
3253 }
3254
3255 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3256 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3257 #define ECORE_RESC_ALLOC_VERSION                                \
3258         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3259           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3260          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3261           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3262
3263 struct ecore_resc_alloc_in_params {
3264         u32 cmd;
3265         enum ecore_resources res_id;
3266         u32 resc_max_val;
3267 };
3268
3269 struct ecore_resc_alloc_out_params {
3270         u32 mcp_resp;
3271         u32 mcp_param;
3272         u32 resc_num;
3273         u32 resc_start;
3274         u32 vf_resc_num;
3275         u32 vf_resc_start;
3276         u32 flags;
3277 };
3278
3279 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3280
3281 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3282 {
3283         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3284         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3285         enum _ecore_status_t rc;
3286
3287         /* Allow ongoing PCIe transactions to complete */
3288         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3289
3290         /* Clear the PF's internal FID_enable in the PXP */
3291         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3292         if (rc != ECORE_SUCCESS)
3293                 DP_NOTICE(p_hwfn, false,
3294                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3295                           rc);
3296
3297         return rc;
3298 }
3299
3300 static enum _ecore_status_t
3301 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3302                               struct ecore_ptt *p_ptt,
3303                               struct ecore_resc_alloc_in_params *p_in_params,
3304                               struct ecore_resc_alloc_out_params *p_out_params)
3305 {
3306         struct ecore_mcp_mb_params mb_params;
3307         struct resource_info mfw_resc_info;
3308         enum _ecore_status_t rc;
3309
3310         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3311
3312         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3313         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3314                 DP_ERR(p_hwfn,
3315                        "Failed to match resource %d [%s] with the MFW resources\n",
3316                        p_in_params->res_id,
3317                        ecore_hw_get_resc_name(p_in_params->res_id));
3318                 return ECORE_INVAL;
3319         }
3320
3321         switch (p_in_params->cmd) {
3322         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3323                 mfw_resc_info.size = p_in_params->resc_max_val;
3324                 /* Fallthrough */
3325         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3326                 break;
3327         default:
3328                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3329                        p_in_params->cmd);
3330                 return ECORE_INVAL;
3331         }
3332
3333         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3334         mb_params.cmd = p_in_params->cmd;
3335         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3336         mb_params.p_data_src = &mfw_resc_info;
3337         mb_params.data_src_size = sizeof(mfw_resc_info);
3338         mb_params.p_data_dst = mb_params.p_data_src;
3339         mb_params.data_dst_size = mb_params.data_src_size;
3340
3341         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3342                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3343                    p_in_params->cmd, p_in_params->res_id,
3344                    ecore_hw_get_resc_name(p_in_params->res_id),
3345                    GET_MFW_FIELD(mb_params.param,
3346                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3347                    GET_MFW_FIELD(mb_params.param,
3348                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3349                    p_in_params->resc_max_val);
3350
3351         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3352         if (rc != ECORE_SUCCESS)
3353                 return rc;
3354
3355         p_out_params->mcp_resp = mb_params.mcp_resp;
3356         p_out_params->mcp_param = mb_params.mcp_param;
3357         p_out_params->resc_num = mfw_resc_info.size;
3358         p_out_params->resc_start = mfw_resc_info.offset;
3359         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3360         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3361         p_out_params->flags = mfw_resc_info.flags;
3362
3363         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3364                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3365                    GET_MFW_FIELD(p_out_params->mcp_param,
3366                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3367                    GET_MFW_FIELD(p_out_params->mcp_param,
3368                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3369                    p_out_params->resc_num, p_out_params->resc_start,
3370                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3371                    p_out_params->flags);
3372
3373         return ECORE_SUCCESS;
3374 }
3375
3376 enum _ecore_status_t
3377 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3378                            enum ecore_resources res_id, u32 resc_max_val,
3379                            u32 *p_mcp_resp)
3380 {
3381         struct ecore_resc_alloc_out_params out_params;
3382         struct ecore_resc_alloc_in_params in_params;
3383         enum _ecore_status_t rc;
3384
3385         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3386         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3387         in_params.res_id = res_id;
3388         in_params.resc_max_val = resc_max_val;
3389         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3390         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3391                                            &out_params);
3392         if (rc != ECORE_SUCCESS)
3393                 return rc;
3394
3395         *p_mcp_resp = out_params.mcp_resp;
3396
3397         return ECORE_SUCCESS;
3398 }
3399
3400 enum _ecore_status_t
3401 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3402                         enum ecore_resources res_id, u32 *p_mcp_resp,
3403                         u32 *p_resc_num, u32 *p_resc_start)
3404 {
3405         struct ecore_resc_alloc_out_params out_params;
3406         struct ecore_resc_alloc_in_params in_params;
3407         enum _ecore_status_t rc;
3408
3409         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3410         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3411         in_params.res_id = res_id;
3412         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3413         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3414                                            &out_params);
3415         if (rc != ECORE_SUCCESS)
3416                 return rc;
3417
3418         *p_mcp_resp = out_params.mcp_resp;
3419
3420         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3421                 *p_resc_num = out_params.resc_num;
3422                 *p_resc_start = out_params.resc_start;
3423         }
3424
3425         return ECORE_SUCCESS;
3426 }
3427
3428 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3429                                                struct ecore_ptt *p_ptt)
3430 {
3431         u32 mcp_resp, mcp_param;
3432
3433         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3434                              &mcp_resp, &mcp_param);
3435 }
3436
3437 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3438                                                    struct ecore_ptt *p_ptt,
3439                                                    u32 param, u32 *p_mcp_resp,
3440                                                    u32 *p_mcp_param)
3441 {
3442         enum _ecore_status_t rc;
3443
3444         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3445                            p_mcp_resp, p_mcp_param);
3446         if (rc != ECORE_SUCCESS)
3447                 return rc;
3448
3449         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3450                 DP_INFO(p_hwfn,
3451                         "The resource command is unsupported by the MFW\n");
3452                 return ECORE_NOTIMPL;
3453         }
3454
3455         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3456                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3457
3458                 DP_NOTICE(p_hwfn, false,
3459                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3460                           param, opcode);
3461                 return ECORE_INVAL;
3462         }
3463
3464         return rc;
3465 }
3466
3467 enum _ecore_status_t
3468 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3469                       struct ecore_resc_lock_params *p_params)
3470 {
3471         u32 param = 0, mcp_resp, mcp_param;
3472         u8 opcode;
3473         enum _ecore_status_t rc;
3474
3475         switch (p_params->timeout) {
3476         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3477                 opcode = RESOURCE_OPCODE_REQ;
3478                 p_params->timeout = 0;
3479                 break;
3480         case ECORE_MCP_RESC_LOCK_TO_NONE:
3481                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3482                 p_params->timeout = 0;
3483                 break;
3484         default:
3485                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3486                 break;
3487         }
3488
3489         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3490         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3491         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3492
3493         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3494                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3495                    param, p_params->timeout, opcode, p_params->resource);
3496
3497         /* Attempt to acquire the resource */
3498         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3499                                     &mcp_param);
3500         if (rc != ECORE_SUCCESS)
3501                 return rc;
3502
3503         /* Analyze the response */
3504         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3505         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3506
3507         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3508                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3509                    mcp_param, opcode, p_params->owner);
3510
3511         switch (opcode) {
3512         case RESOURCE_OPCODE_GNT:
3513                 p_params->b_granted = true;
3514                 break;
3515         case RESOURCE_OPCODE_BUSY:
3516                 p_params->b_granted = false;
3517                 break;
3518         default:
3519                 DP_NOTICE(p_hwfn, false,
3520                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3521                           mcp_param, opcode);
3522                 return ECORE_INVAL;
3523         }
3524
3525         return ECORE_SUCCESS;
3526 }
3527
3528 enum _ecore_status_t
3529 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3530                     struct ecore_resc_lock_params *p_params)
3531 {
3532         u32 retry_cnt = 0;
3533         enum _ecore_status_t rc;
3534
3535         do {
3536                 /* No need for an interval before the first iteration */
3537                 if (retry_cnt) {
3538                         if (p_params->sleep_b4_retry) {
3539                                 u16 retry_interval_in_ms =
3540                                         DIV_ROUND_UP(p_params->retry_interval,
3541                                                      1000);
3542
3543                                 OSAL_MSLEEP(retry_interval_in_ms);
3544                         } else {
3545                                 OSAL_UDELAY(p_params->retry_interval);
3546                         }
3547                 }
3548
3549                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3550                 if (rc != ECORE_SUCCESS)
3551                         return rc;
3552
3553                 if (p_params->b_granted)
3554                         break;
3555         } while (retry_cnt++ < p_params->retry_num);
3556
3557         return ECORE_SUCCESS;
3558 }
3559
3560 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3561                                       struct ecore_resc_unlock_params *p_unlock,
3562                                       enum ecore_resc_lock resource,
3563                                       bool b_is_permanent)
3564 {
3565         if (p_lock != OSAL_NULL) {
3566                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3567
3568                 /* Permanent resources don't require aging, and there's no
3569                  * point in trying to acquire them more than once since it's
3570                  * unexpected another entity would release them.
3571                  */
3572                 if (b_is_permanent) {
3573                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3574                 } else {
3575                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3576                         p_lock->retry_interval =
3577                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3578                         p_lock->sleep_b4_retry = true;
3579                 }
3580
3581                 p_lock->resource = resource;
3582         }
3583
3584         if (p_unlock != OSAL_NULL) {
3585                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3586                 p_unlock->resource = resource;
3587         }
3588 }
3589
3590 enum _ecore_status_t
3591 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3592                       struct ecore_resc_unlock_params *p_params)
3593 {
3594         u32 param = 0, mcp_resp, mcp_param;
3595         u8 opcode;
3596         enum _ecore_status_t rc;
3597
3598         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3599                                    : RESOURCE_OPCODE_RELEASE;
3600         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3601         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3602
3603         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3604                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3605                    param, opcode, p_params->resource);
3606
3607         /* Attempt to release the resource */
3608         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3609                                     &mcp_param);
3610         if (rc != ECORE_SUCCESS)
3611                 return rc;
3612
3613         /* Analyze the response */
3614         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3615
3616         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3617                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3618                    mcp_param, opcode);
3619
3620         switch (opcode) {
3621         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3622                 DP_INFO(p_hwfn,
3623                         "Resource unlock request for an already released resource [%d]\n",
3624                         p_params->resource);
3625                 /* Fallthrough */
3626         case RESOURCE_OPCODE_RELEASED:
3627                 p_params->b_released = true;
3628                 break;
3629         case RESOURCE_OPCODE_WRONG_OWNER:
3630                 p_params->b_released = false;
3631                 break;
3632         default:
3633                 DP_NOTICE(p_hwfn, false,
3634                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3635                           mcp_param, opcode);
3636                 return ECORE_INVAL;
3637         }
3638
3639         return ECORE_SUCCESS;
3640 }
3641
3642 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3643 {
3644         return !!(p_hwfn->mcp_info->capabilities &
3645                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3646 }
3647
3648 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3649                                                 struct ecore_ptt *p_ptt)
3650 {
3651         u32 mcp_resp;
3652         enum _ecore_status_t rc;
3653
3654         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3655                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3656         if (rc == ECORE_SUCCESS)
3657                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3658                            "MFW supported features: %08x\n",
3659                            p_hwfn->mcp_info->capabilities);
3660
3661         return rc;
3662 }
3663
3664 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3665                                                 struct ecore_ptt *p_ptt)
3666 {
3667         u32 mcp_resp, mcp_param, features;
3668
3669         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3670                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3671
3672         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3673                              features, &mcp_resp, &mcp_param);
3674 }
3675
3676 enum _ecore_status_t
3677 ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3678                         struct ecore_mcp_drv_attr *p_drv_attr)
3679 {
3680         struct attribute_cmd_write_stc attr_cmd_write;
3681         enum _attribute_commands_e mfw_attr_cmd;
3682         struct ecore_mcp_mb_params mb_params;
3683         enum _ecore_status_t rc;
3684
3685         switch (p_drv_attr->attr_cmd) {
3686         case ECORE_MCP_DRV_ATTR_CMD_READ:
3687                 mfw_attr_cmd = ATTRIBUTE_CMD_READ;
3688                 break;
3689         case ECORE_MCP_DRV_ATTR_CMD_WRITE:
3690                 mfw_attr_cmd = ATTRIBUTE_CMD_WRITE;
3691                 break;
3692         case ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR:
3693                 mfw_attr_cmd = ATTRIBUTE_CMD_READ_CLEAR;
3694                 break;
3695         case ECORE_MCP_DRV_ATTR_CMD_CLEAR:
3696                 mfw_attr_cmd = ATTRIBUTE_CMD_CLEAR;
3697                 break;
3698         default:
3699                 DP_NOTICE(p_hwfn, false, "Unknown attribute command %d\n",
3700                           p_drv_attr->attr_cmd);
3701                 return ECORE_INVAL;
3702         }
3703
3704         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3705         mb_params.cmd = DRV_MSG_CODE_ATTRIBUTE;
3706         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_KEY,
3707                       p_drv_attr->attr_num);
3708         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_CMD,
3709                       mfw_attr_cmd);
3710         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_WRITE) {
3711                 OSAL_MEM_ZERO(&attr_cmd_write, sizeof(attr_cmd_write));
3712                 attr_cmd_write.val = p_drv_attr->val;
3713                 attr_cmd_write.mask = p_drv_attr->mask;
3714                 attr_cmd_write.offset = p_drv_attr->offset;
3715
3716                 mb_params.p_data_src = &attr_cmd_write;
3717                 mb_params.data_src_size = sizeof(attr_cmd_write);
3718         }
3719
3720         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3721         if (rc != ECORE_SUCCESS)
3722                 return rc;
3723
3724         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3725                 DP_INFO(p_hwfn,
3726                         "The attribute command is not supported by the MFW\n");
3727                 return ECORE_NOTIMPL;
3728         } else if (mb_params.mcp_resp != FW_MSG_CODE_OK) {
3729                 DP_INFO(p_hwfn,
3730                         "Failed to send an attribute command [mcp_resp 0x%x, attr_cmd %d, attr_num %d]\n",
3731                         mb_params.mcp_resp, p_drv_attr->attr_cmd,
3732                         p_drv_attr->attr_num);
3733                 return ECORE_INVAL;
3734         }
3735
3736         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3737                    "Attribute Command: cmd %d [mfw_cmd %d], num %d, in={val 0x%08x, mask 0x%08x, offset 0x%08x}, out={val 0x%08x}\n",
3738                    p_drv_attr->attr_cmd, mfw_attr_cmd, p_drv_attr->attr_num,
3739                    p_drv_attr->val, p_drv_attr->mask, p_drv_attr->offset,
3740                    mb_params.mcp_param);
3741
3742         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ ||
3743             p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR)
3744                 p_drv_attr->val = mb_params.mcp_param;
3745
3746         return ECORE_SUCCESS;
3747 }