drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_OFFSET)
  47
  48 #define MCP_BYTES_PER_MBIT_OFFSET 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 struct ecore_mcp_cmd_elem {
 100         osal_list_entry_t list;
 101         struct ecore_mcp_mb_params *p_mb_params;
 102         u16 expected_seq_num;
 103         bool b_is_completed;
 104 };
 105
 106 /* Must be called while cmd_lock is acquired */
 107 static struct ecore_mcp_cmd_elem *
 108 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 109                        struct ecore_mcp_mb_params *p_mb_params,
 110                        u16 expected_seq_num)
 111 {
 112         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 113
 114         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 115                                  sizeof(*p_cmd_elem));
 116         if (!p_cmd_elem) {
 117                 DP_NOTICE(p_hwfn, false,
 118                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 119                 goto out;
 120         }
 121
 122         p_cmd_elem->p_mb_params = p_mb_params;
 123         p_cmd_elem->expected_seq_num = expected_seq_num;
 124         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 125 out:
 126         return p_cmd_elem;
 127 }
 128
 129 /* Must be called while cmd_lock is acquired */
 130 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 131                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 132 {
 133         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 134         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 135 }
 136
 137 /* Must be called while cmd_lock is acquired */
 138 static struct ecore_mcp_cmd_elem *
 139 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 140 {
 141         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 142
 143         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 144                                  struct ecore_mcp_cmd_elem) {
 145                 if (p_cmd_elem->expected_seq_num == seq_num)
 146                         return p_cmd_elem;
 147         }
 148
 149         return OSAL_NULL;
 150 }
 151
 152 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 153 {
 154         if (p_hwfn->mcp_info) {
 155                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 156
 157                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 158                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 159                                               &p_hwfn->mcp_info->cmd_list, list,
 160                                               struct ecore_mcp_cmd_elem) {
 161                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 162                 }
 163                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 164
 165                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 166                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 167 #ifdef CONFIG_ECORE_LOCK_ALLOC
 168                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 169                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 170 #endif
 171         }
 172
 173         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 174
 175         return ECORE_SUCCESS;
 176 }
 177
 178 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 179                                                    struct ecore_ptt *p_ptt)
 180 {
 181         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 182         u32 drv_mb_offsize, mfw_mb_offsize;
 183         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 184
 185 #ifndef ASIC_ONLY
 186         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 187                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 188                 p_info->public_base = 0;
 189                 return ECORE_INVAL;
 190         }
 191 #endif
 192
 193         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 194         if (!p_info->public_base)
 195                 return ECORE_INVAL;
 196
 197         p_info->public_base |= GRCBASE_MCP;
 198
 199         /* Calculate the driver and MFW mailbox address */
 200         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 201                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 202                                                        PUBLIC_DRV_MB));
 203         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 204         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 205                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 206                    " mcp_pf_id = 0x%x\n",
 207                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 208
 209         /* Set the MFW MB address */
 210         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 211                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 212                                                        PUBLIC_MFW_MB));
 213         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 214         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 215                                                p_info->mfw_mb_addr);
 216
 217         /* Get the current driver mailbox sequence before sending
 218          * the first command
 219          */
 220         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 221             DRV_MSG_SEQ_NUMBER_MASK;
 222
 223         /* Get current FW pulse sequence */
 224         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 225             DRV_PULSE_SEQ_MASK;
 226
 227         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 228
 229         return ECORE_SUCCESS;
 230 }
 231
 232 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 233                                         struct ecore_ptt *p_ptt)
 234 {
 235         struct ecore_mcp_info *p_info;
 236         u32 size;
 237
 238         /* Allocate mcp_info structure */
 239         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 240                                        sizeof(*p_hwfn->mcp_info));
 241         if (!p_hwfn->mcp_info)
 242                 goto err;
 243         p_info = p_hwfn->mcp_info;
 244
 245         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 246                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 247                 /* Do not free mcp_info here, since public_base indicate that
 248                  * the MCP is not initialized
 249                  */
 250                 return ECORE_SUCCESS;
 251         }
 252
 253         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 254         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 255         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 256         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 257                 goto err;
 258
 259         /* Initialize the MFW spinlocks */
 260 #ifdef CONFIG_ECORE_LOCK_ALLOC
 261         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 262         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 263 #endif
 264         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 265         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 266
 267         OSAL_LIST_INIT(&p_info->cmd_list);
 268
 269         return ECORE_SUCCESS;
 270
 271 err:
 272         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 273         ecore_mcp_free(p_hwfn);
 274         return ECORE_NOMEM;
 275 }
 276
 277 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 278                                      struct ecore_ptt *p_ptt)
 279 {
 280         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 281
 282         /* Use MCP history register to check if MCP reset occurred between init
 283          * time and now.
 284          */
 285         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 286                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 287                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 288                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 289
 290                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 291                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 292         }
 293 }
 294
 295 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 296                                      struct ecore_ptt *p_ptt)
 297 {
 298         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 299         enum _ecore_status_t rc = ECORE_SUCCESS;
 300
 301 #ifndef ASIC_ONLY
 302         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 303                 delay = EMUL_MCP_RESP_ITER_US;
 304 #endif
 305
 306         /* Ensure that only a single thread is accessing the mailbox */
 307         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 308
 309         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 310
 311         /* Set drv command along with the updated sequence */
 312         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 313         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 314         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 315
 316         do {
 317                 /* Wait for MFW response */
 318                 OSAL_UDELAY(delay);
 319                 /* Give the FW up to 500 second (50*1000*10usec) */
 320         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 321                                                 MISCS_REG_GENERIC_POR_0)) &&
 322                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 323
 324         if (org_mcp_reset_seq !=
 325             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 326                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 327                            "MCP was reset after %d usec\n", cnt * delay);
 328         } else {
 329                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 330                 rc = ECORE_AGAIN;
 331         }
 332
 333         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 334
 335         return rc;
 336 }
 337
 338 /* Must be called while cmd_lock is acquired */
 339 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 340 {
 341         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 342
 343         /* There is at most one pending command at a certain time, and if it
 344          * exists - it is placed at the HEAD of the list.
 345          */
 346         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 347                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 348                                                    struct ecore_mcp_cmd_elem,
 349                                                    list);
 350                 return !p_cmd_elem->b_is_completed;
 351         }
 352
 353         return false;
 354 }
 355
 356 /* Must be called while cmd_lock is acquired */
 357 static enum _ecore_status_t
 358 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 359 {
 360         struct ecore_mcp_mb_params *p_mb_params;
 361         struct ecore_mcp_cmd_elem *p_cmd_elem;
 362         u32 mcp_resp;
 363         u16 seq_num;
 364
 365         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 366         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 367
 368         /* Return if no new non-handled response has been received */
 369         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 370                 return ECORE_AGAIN;
 371
 372         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 373         if (!p_cmd_elem) {
 374                 DP_ERR(p_hwfn,
 375                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 376                        seq_num);
 377                 return ECORE_UNKNOWN_ERROR;
 378         }
 379
 380         p_mb_params = p_cmd_elem->p_mb_params;
 381
 382         /* Get the MFW response along with the sequence number */
 383         p_mb_params->mcp_resp = mcp_resp;
 384
 385         /* Get the MFW param */
 386         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 387
 388         /* Get the union data */
 389         if (p_mb_params->p_data_dst != OSAL_NULL &&
 390             p_mb_params->data_dst_size) {
 391                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 392                                       OFFSETOF(struct public_drv_mb,
 393                                                union_data);
 394                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 395                                   union_data_addr, p_mb_params->data_dst_size);
 396         }
 397
 398         p_cmd_elem->b_is_completed = true;
 399
 400         return ECORE_SUCCESS;
 401 }
 402
 403 /* Must be called while cmd_lock is acquired */
 404 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 405                                       struct ecore_ptt *p_ptt,
 406                                       struct ecore_mcp_mb_params *p_mb_params,
 407                                       u16 seq_num)
 408 {
 409         union drv_union_data union_data;
 410         u32 union_data_addr;
 411
 412         /* Set the union data */
 413         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 414                           OFFSETOF(struct public_drv_mb, union_data);
 415         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 416         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 417                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 418                             p_mb_params->data_src_size);
 419         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 420                         sizeof(union_data));
 421
 422         /* Set the drv param */
 423         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 424
 425         /* Set the drv command along with the sequence number */
 426         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 427
 428         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 429                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 430                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 431 }
 432
 433 static enum _ecore_status_t
 434 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 435                          struct ecore_mcp_mb_params *p_mb_params,
 436                          u32 max_retries, u32 delay)
 437 {
 438         struct ecore_mcp_cmd_elem *p_cmd_elem;
 439         u32 cnt = 0;
 440         u16 seq_num;
 441         enum _ecore_status_t rc = ECORE_SUCCESS;
 442
 443         /* Wait until the mailbox is non-occupied */
 444         do {
 445                 /* Exit the loop if there is no pending command, or if the
 446                  * pending command is completed during this iteration.
 447                  * The spinlock stays locked until the command is sent.
 448                  */
 449
 450                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 451
 452                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 453                         break;
 454
 455                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 456                 if (rc == ECORE_SUCCESS)
 457                         break;
 458                 else if (rc != ECORE_AGAIN)
 459                         goto err;
 460
 461                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 462                 OSAL_UDELAY(delay);
 463         } while (++cnt < max_retries);
 464
 465         if (cnt >= max_retries) {
 466                 DP_NOTICE(p_hwfn, false,
 467                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 468                           p_mb_params->cmd, p_mb_params->param);
 469                 return ECORE_AGAIN;
 470         }
 471
 472         /* Send the mailbox command */
 473         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 474         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 475         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 476         if (!p_cmd_elem) {
 477                 rc = ECORE_NOMEM;
 478                 goto err;
 479         }
 480
 481         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 482         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 483
 484         /* Wait for the MFW response */
 485         do {
 486                 /* Exit the loop if the command is already completed, or if the
 487                  * command is completed during this iteration.
 488                  * The spinlock stays locked until the list element is removed.
 489                  */
 490
 491                 OSAL_UDELAY(delay);
 492                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 493
 494                 if (p_cmd_elem->b_is_completed)
 495                         break;
 496
 497                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 498                 if (rc == ECORE_SUCCESS)
 499                         break;
 500                 else if (rc != ECORE_AGAIN)
 501                         goto err;
 502
 503                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 504         } while (++cnt < max_retries);
 505
 506         if (cnt >= max_retries) {
 507                 DP_NOTICE(p_hwfn, false,
 508                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 509                           p_mb_params->cmd, p_mb_params->param);
 510
 511                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 512                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 513                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 514
 515                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 516                 return ECORE_AGAIN;
 517         }
 518
 519         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 520         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 521
 522         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 523                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 524                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 525                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 526
 527         /* Clear the sequence number from the MFW response */
 528         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 529
 530         return ECORE_SUCCESS;
 531
 532 err:
 533         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 534         return rc;
 535 }
 536
 537 static enum _ecore_status_t
 538 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 539                         struct ecore_ptt *p_ptt,
 540                         struct ecore_mcp_mb_params *p_mb_params)
 541 {
 542         osal_size_t union_data_size = sizeof(union drv_union_data);
 543         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 544         u32 delay = CHIP_MCP_RESP_ITER_US;
 545
 546 #ifndef ASIC_ONLY
 547         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 548                 delay = EMUL_MCP_RESP_ITER_US;
 549         /* There is a built-in delay of 100usec in each MFW response read */
 550         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 551                 max_retries /= 10;
 552 #endif
 553
 554         /* MCP not initialized */
 555         if (!ecore_mcp_is_init(p_hwfn)) {
 556                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 557                 return ECORE_BUSY;
 558         }
 559
 560         if (p_mb_params->data_src_size > union_data_size ||
 561             p_mb_params->data_dst_size > union_data_size) {
 562                 DP_ERR(p_hwfn,
 563                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 564                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 565                        union_data_size);
 566                 return ECORE_INVAL;
 567         }
 568
 569         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 570                                         delay);
 571 }
 572
 573 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 574                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 575                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 576 {
 577         struct ecore_mcp_mb_params mb_params;
 578         enum _ecore_status_t rc;
 579
 580 #ifndef ASIC_ONLY
 581         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 582                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 583                         loaded--;
 584                         loaded_port[p_hwfn->port_id]--;
 585                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 586                                    loaded);
 587                 }
 588                 return ECORE_SUCCESS;
 589         }
 590 #endif
 591
 592         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 593         mb_params.cmd = cmd;
 594         mb_params.param = param;
 595         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 596         if (rc != ECORE_SUCCESS)
 597                 return rc;
 598
 599         *o_mcp_resp = mb_params.mcp_resp;
 600         *o_mcp_param = mb_params.mcp_param;
 601
 602         return ECORE_SUCCESS;
 603 }
 604
 605 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 606                                           struct ecore_ptt *p_ptt,
 607                                           u32 cmd,
 608                                           u32 param,
 609                                           u32 *o_mcp_resp,
 610                                           u32 *o_mcp_param,
 611                                           u32 i_txn_size, u32 *i_buf)
 612 {
 613         struct ecore_mcp_mb_params mb_params;
 614         enum _ecore_status_t rc;
 615
 616         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 617         mb_params.cmd = cmd;
 618         mb_params.param = param;
 619         mb_params.p_data_src = i_buf;
 620         mb_params.data_src_size = (u8)i_txn_size;
 621         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 622         if (rc != ECORE_SUCCESS)
 623                 return rc;
 624
 625         *o_mcp_resp = mb_params.mcp_resp;
 626         *o_mcp_param = mb_params.mcp_param;
 627
 628         return ECORE_SUCCESS;
 629 }
 630
 631 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 632                                           struct ecore_ptt *p_ptt,
 633                                           u32 cmd,
 634                                           u32 param,
 635                                           u32 *o_mcp_resp,
 636                                           u32 *o_mcp_param,
 637                                           u32 *o_txn_size, u32 *o_buf)
 638 {
 639         struct ecore_mcp_mb_params mb_params;
 640         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 641         enum _ecore_status_t rc;
 642
 643         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 644         mb_params.cmd = cmd;
 645         mb_params.param = param;
 646         mb_params.p_data_dst = raw_data;
 647
 648         /* Use the maximal value since the actual one is part of the response */
 649         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 650
 651         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 652         if (rc != ECORE_SUCCESS)
 653                 return rc;
 654
 655         *o_mcp_resp = mb_params.mcp_resp;
 656         *o_mcp_param = mb_params.mcp_param;
 657
 658         *o_txn_size = *o_mcp_param;
 659         /* @DPDK */
 660         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 661
 662         return ECORE_SUCCESS;
 663 }
 664
 665 #ifndef ASIC_ONLY
 666 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 667                                     u32 *p_load_code)
 668 {
 669         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 670
 671         if (!loaded)
 672                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 673         else if (!loaded_port[p_hwfn->port_id])
 674                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 675         else
 676                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 677
 678         /* On CMT, always tell that it's engine */
 679         if (p_hwfn->p_dev->num_hwfns > 1)
 680                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 681
 682         *p_load_code = load_phase;
 683         loaded++;
 684         loaded_port[p_hwfn->port_id]++;
 685
 686         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 687                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 688                    *p_load_code, loaded, p_hwfn->port_id,
 689                    loaded_port[p_hwfn->port_id]);
 690 }
 691 #endif
 692
 693 static bool
 694 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 695                          enum ecore_override_force_load override_force_load)
 696 {
 697         bool can_force_load = false;
 698
 699         switch (override_force_load) {
 700         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 701                 can_force_load = true;
 702                 break;
 703         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 704                 can_force_load = false;
 705                 break;
 706         default:
 707                 can_force_load = (drv_role == DRV_ROLE_OS &&
 708                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 709                                  (drv_role == DRV_ROLE_KDUMP &&
 710                                   exist_drv_role == DRV_ROLE_OS);
 711                 break;
 712         }
 713
 714         return can_force_load;
 715 }
 716
 717 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 718                                                       struct ecore_ptt *p_ptt)
 719 {
 720         u32 resp = 0, param = 0;
 721         enum _ecore_status_t rc;
 722
 723         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 724                            &resp, &param);
 725         if (rc != ECORE_SUCCESS)
 726                 DP_NOTICE(p_hwfn, false,
 727                           "Failed to send cancel load request, rc = %d\n", rc);
 728
 729         return rc;
 730 }
 731
 732 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 733 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 734 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 735 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 736 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 737 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 738 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 739
 740 static u32 ecore_get_config_bitmap(void)
 741 {
 742         u32 config_bitmap = 0x0;
 743
 744 #ifdef CONFIG_ECORE_L2
 745         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 746 #endif
 747 #ifdef CONFIG_ECORE_SRIOV
 748         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 749 #endif
 750 #ifdef CONFIG_ECORE_ROCE
 751         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 752 #endif
 753 #ifdef CONFIG_ECORE_IWARP
 754         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 755 #endif
 756 #ifdef CONFIG_ECORE_FCOE
 757         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 758 #endif
 759 #ifdef CONFIG_ECORE_ISCSI
 760         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 761 #endif
 762 #ifdef CONFIG_ECORE_LL2
 763         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 764 #endif
 765
 766         return config_bitmap;
 767 }
 768
 769 struct ecore_load_req_in_params {
 770         u8 hsi_ver;
 771 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 772 #define ECORE_LOAD_REQ_HSI_VER_1        1
 773         u32 drv_ver_0;
 774         u32 drv_ver_1;
 775         u32 fw_ver;
 776         u8 drv_role;
 777         u8 timeout_val;
 778         u8 force_cmd;
 779         bool avoid_eng_reset;
 780 };
 781
 782 struct ecore_load_req_out_params {
 783         u32 load_code;
 784         u32 exist_drv_ver_0;
 785         u32 exist_drv_ver_1;
 786         u32 exist_fw_ver;
 787         u8 exist_drv_role;
 788         u8 mfw_hsi_ver;
 789         bool drv_exists;
 790 };
 791
 792 static enum _ecore_status_t
 793 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 794                      struct ecore_load_req_in_params *p_in_params,
 795                      struct ecore_load_req_out_params *p_out_params)
 796 {
 797         struct ecore_mcp_mb_params mb_params;
 798         struct load_req_stc load_req;
 799         struct load_rsp_stc load_rsp;
 800         u32 hsi_ver;
 801         enum _ecore_status_t rc;
 802
 803         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 804         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 805         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 806         load_req.fw_ver = p_in_params->fw_ver;
 807         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 808         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 809                       p_in_params->timeout_val);
 810         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 811         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 812                       p_in_params->avoid_eng_reset);
 813
 814         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 815                   DRV_ID_MCP_HSI_VER_CURRENT :
 816                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 817
 818         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 819         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 820         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 821         mb_params.p_data_src = &load_req;
 822         mb_params.data_src_size = sizeof(load_req);
 823         mb_params.p_data_dst = &load_rsp;
 824         mb_params.data_dst_size = sizeof(load_rsp);
 825
 826         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 827                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 828                    mb_params.param,
 829                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 830                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 831                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 832                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 833
 834         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 835                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 836                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 837                            load_req.drv_ver_0, load_req.drv_ver_1,
 838                            load_req.fw_ver, load_req.misc0,
 839                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 840                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 841                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 842                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 843
 844         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 845         if (rc != ECORE_SUCCESS) {
 846                 DP_NOTICE(p_hwfn, false,
 847                           "Failed to send load request, rc = %d\n", rc);
 848                 return rc;
 849         }
 850
 851         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 852                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 853         p_out_params->load_code = mb_params.mcp_resp;
 854
 855         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 856             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 857                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 858                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 859                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 860                            load_rsp.fw_ver, load_rsp.misc0,
 861                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 862                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 863                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 864
 865                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 866                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 867                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 868                 p_out_params->exist_drv_role =
 869                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 870                 p_out_params->mfw_hsi_ver =
 871                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 872                 p_out_params->drv_exists =
 873                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 874                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 875         }
 876
 877         return ECORE_SUCCESS;
 878 }
 879
 880 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
 881                                    enum ecore_drv_role drv_role,
 882                                    u8 *p_mfw_drv_role)
 883 {
 884         switch (drv_role) {
 885         case ECORE_DRV_ROLE_OS:
 886                 *p_mfw_drv_role = DRV_ROLE_OS;
 887                 break;
 888         case ECORE_DRV_ROLE_KDUMP:
 889                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 890                 break;
 891         }
 892 }
 893
 894 enum ecore_load_req_force {
 895         ECORE_LOAD_REQ_FORCE_NONE,
 896         ECORE_LOAD_REQ_FORCE_PF,
 897         ECORE_LOAD_REQ_FORCE_ALL,
 898 };
 899
 900 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
 901                                     enum ecore_load_req_force force_cmd,
 902                                     u8 *p_mfw_force_cmd)
 903 {
 904         switch (force_cmd) {
 905         case ECORE_LOAD_REQ_FORCE_NONE:
 906                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 907                 break;
 908         case ECORE_LOAD_REQ_FORCE_PF:
 909                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 910                 break;
 911         case ECORE_LOAD_REQ_FORCE_ALL:
 912                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 913                 break;
 914         }
 915 }
 916
 917 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 918                                         struct ecore_ptt *p_ptt,
 919                                         struct ecore_load_req_params *p_params)
 920 {
 921         struct ecore_load_req_out_params out_params;
 922         struct ecore_load_req_in_params in_params;
 923         u8 mfw_drv_role = 0, mfw_force_cmd;
 924         enum _ecore_status_t rc;
 925
 926 #ifndef ASIC_ONLY
 927         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 928                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 929                 return ECORE_SUCCESS;
 930         }
 931 #endif
 932
 933         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 934         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 935         in_params.drv_ver_0 = ECORE_VERSION;
 936         in_params.drv_ver_1 = ecore_get_config_bitmap();
 937         in_params.fw_ver = STORM_FW_VERSION;
 938         ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 939         in_params.drv_role = mfw_drv_role;
 940         in_params.timeout_val = p_params->timeout_val;
 941         ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
 942                                 &mfw_force_cmd);
 943         in_params.force_cmd = mfw_force_cmd;
 944         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 945
 946         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 947         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 948         if (rc != ECORE_SUCCESS)
 949                 return rc;
 950
 951         /* First handle cases where another load request should/might be sent:
 952          * - MFW expects the old interface [HSI version = 1]
 953          * - MFW responds that a force load request is required
 954          */
 955         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 956                 DP_INFO(p_hwfn,
 957                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 958
 959                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 960                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 961                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 962                                           &out_params);
 963                 if (rc != ECORE_SUCCESS)
 964                         return rc;
 965         } else if (out_params.load_code ==
 966                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 967                 if (ecore_mcp_can_force_load(in_params.drv_role,
 968                                              out_params.exist_drv_role,
 969                                              p_params->override_force_load)) {
 970                         DP_INFO(p_hwfn,
 971                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
 972                                 in_params.drv_role, in_params.fw_ver,
 973                                 in_params.drv_ver_0, in_params.drv_ver_1,
 974                                 out_params.exist_drv_role,
 975                                 out_params.exist_fw_ver,
 976                                 out_params.exist_drv_ver_0,
 977                                 out_params.exist_drv_ver_1);
 978
 979                         ecore_get_mfw_force_cmd(p_hwfn,
 980                                                 ECORE_LOAD_REQ_FORCE_ALL,
 981                                                 &mfw_force_cmd);
 982
 983                         in_params.force_cmd = mfw_force_cmd;
 984                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 985                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 986                                                   &out_params);
 987                         if (rc != ECORE_SUCCESS)
 988                                 return rc;
 989                 } else {
 990                         DP_NOTICE(p_hwfn, false,
 991                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
 992                                   in_params.drv_role, in_params.fw_ver,
 993                                   in_params.drv_ver_0, in_params.drv_ver_1,
 994                                   out_params.exist_drv_role,
 995                                   out_params.exist_fw_ver,
 996                                   out_params.exist_drv_ver_0,
 997                                   out_params.exist_drv_ver_1);
 998
 999                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1000                         return ECORE_BUSY;
1001                 }
1002         }
1003
1004         /* Now handle the other types of responses.
1005          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1006          * expected here after the additional revised load requests were sent.
1007          */
1008         switch (out_params.load_code) {
1009         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1010         case FW_MSG_CODE_DRV_LOAD_PORT:
1011         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1012                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1013                     out_params.drv_exists) {
1014                         /* The role and fw/driver version match, but the PF is
1015                          * already loaded and has not been unloaded gracefully.
1016                          * This is unexpected since a quasi-FLR request was
1017                          * previously sent as part of ecore_hw_prepare().
1018                          */
1019                         DP_NOTICE(p_hwfn, false,
1020                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1021                         return ECORE_INVAL;
1022                 }
1023                 break;
1024         default:
1025                 DP_NOTICE(p_hwfn, false,
1026                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1027                           out_params.load_code);
1028                 return ECORE_BUSY;
1029         }
1030
1031         p_params->load_code = out_params.load_code;
1032
1033         return ECORE_SUCCESS;
1034 }
1035
1036 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1037                                          struct ecore_ptt *p_ptt)
1038 {
1039         u32 resp = 0, param = 0;
1040         enum _ecore_status_t rc;
1041
1042         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1043                            &param);
1044         if (rc != ECORE_SUCCESS) {
1045                 DP_NOTICE(p_hwfn, false,
1046                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1047                 return rc;
1048         }
1049
1050 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR     (1 << 0)
1051
1052         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1053         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1054                 DP_NOTICE(p_hwfn, false,
1055                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1056
1057         return ECORE_SUCCESS;
1058 }
1059
1060 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1061                                           struct ecore_ptt *p_ptt)
1062 {
1063         u32 wol_param, mcp_resp, mcp_param;
1064
1065         /* @DPDK */
1066         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1067
1068         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1069                              &mcp_resp, &mcp_param);
1070 }
1071
1072 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1073                                            struct ecore_ptt *p_ptt)
1074 {
1075         struct ecore_mcp_mb_params mb_params;
1076         struct mcp_mac wol_mac;
1077
1078         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1079         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1080
1081         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1082 }
1083
1084 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1085                                     struct ecore_ptt *p_ptt)
1086 {
1087         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1088                                         PUBLIC_PATH);
1089         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1090         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1091                                      ECORE_PATH_ID(p_hwfn));
1092         u32 disabled_vfs[VF_MAX_STATIC / 32];
1093         int i;
1094
1095         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1096                    "Reading Disabled VF information from [offset %08x],"
1097                    " path_addr %08x\n",
1098                    mfw_path_offsize, path_addr);
1099
1100         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1101                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1102                                            path_addr +
1103                                            OFFSETOF(struct public_path,
1104                                                     mcp_vf_disabled) +
1105                                            sizeof(u32) * i);
1106                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1107                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1108                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1109         }
1110
1111         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1112                 OSAL_VF_FLR_UPDATE(p_hwfn);
1113 }
1114
1115 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1116                                           struct ecore_ptt *p_ptt,
1117                                           u32 *vfs_to_ack)
1118 {
1119         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1120                                         PUBLIC_FUNC);
1121         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1122         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1123                                      MCP_PF_ID(p_hwfn));
1124         struct ecore_mcp_mb_params mb_params;
1125         enum _ecore_status_t rc;
1126         int i;
1127
1128         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1129                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1130                            "Acking VFs [%08x,...,%08x] - %08x\n",
1131                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1132
1133         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1134         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1135         mb_params.p_data_src = vfs_to_ack;
1136         mb_params.data_src_size = VF_MAX_STATIC / 8;
1137         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1138                                      &mb_params);
1139         if (rc != ECORE_SUCCESS) {
1140                 DP_NOTICE(p_hwfn, false,
1141                           "Failed to pass ACK for VF flr to MFW\n");
1142                 return ECORE_TIMEOUT;
1143         }
1144
1145         /* TMP - clear the ACK bits; should be done by MFW */
1146         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1147                 ecore_wr(p_hwfn, p_ptt,
1148                          func_addr +
1149                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1150                          i * sizeof(u32), 0);
1151
1152         return rc;
1153 }
1154
1155 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1156                                                 struct ecore_ptt *p_ptt)
1157 {
1158         u32 transceiver_state;
1159
1160         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1161                                      p_hwfn->mcp_info->port_addr +
1162                                      OFFSETOF(struct public_port,
1163                                               transceiver_data));
1164
1165         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1166                    "Received transceiver state update [0x%08x] from mfw"
1167                    " [Addr 0x%x]\n",
1168                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1169                                             OFFSETOF(struct public_port,
1170                                                      transceiver_data)));
1171
1172         transceiver_state = GET_MFW_FIELD(transceiver_state,
1173                                           ETH_TRANSCEIVER_STATE);
1174
1175         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1176                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1177         else
1178                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1179 }
1180
1181 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1182                                       struct ecore_ptt *p_ptt,
1183                                       struct ecore_mcp_link_state *p_link)
1184 {
1185         u32 eee_status, val;
1186
1187         p_link->eee_adv_caps = 0;
1188         p_link->eee_lp_adv_caps = 0;
1189         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1190                                      OFFSETOF(struct public_port, eee_status));
1191         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1192         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1193         if (val & EEE_1G_ADV)
1194                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1195         if (val & EEE_10G_ADV)
1196                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1197         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1198         if (val & EEE_1G_ADV)
1199                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1200         if (val & EEE_10G_ADV)
1201                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1202 }
1203
1204 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1205                                          struct ecore_ptt *p_ptt,
1206                                          bool b_reset)
1207 {
1208         struct ecore_mcp_link_state *p_link;
1209         u8 max_bw, min_bw;
1210         u32 status = 0;
1211
1212         /* Prevent SW/attentions from doing this at the same time */
1213         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1214
1215         p_link = &p_hwfn->mcp_info->link_output;
1216         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1217         if (!b_reset) {
1218                 status = ecore_rd(p_hwfn, p_ptt,
1219                                   p_hwfn->mcp_info->port_addr +
1220                                   OFFSETOF(struct public_port, link_status));
1221                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1222                            "Received link update [0x%08x] from mfw"
1223                            " [Addr 0x%x]\n",
1224                            status, (u32)(p_hwfn->mcp_info->port_addr +
1225                                           OFFSETOF(struct public_port,
1226                                                    link_status)));
1227         } else {
1228                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1229                            "Resetting link indications\n");
1230                 goto out;
1231         }
1232
1233         if (p_hwfn->b_drv_link_init)
1234                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1235         else
1236                 p_link->link_up = false;
1237
1238         p_link->full_duplex = true;
1239         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1240         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1241                 p_link->speed = 100000;
1242                 break;
1243         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1244                 p_link->speed = 50000;
1245                 break;
1246         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1247                 p_link->speed = 40000;
1248                 break;
1249         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1250                 p_link->speed = 25000;
1251                 break;
1252         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1253                 p_link->speed = 20000;
1254                 break;
1255         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1256                 p_link->speed = 10000;
1257                 break;
1258         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1259                 p_link->full_duplex = false;
1260                 /* Fall-through */
1261         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1262                 p_link->speed = 1000;
1263                 break;
1264         default:
1265                 p_link->speed = 0;
1266         }
1267
1268         /* We never store total line speed as p_link->speed is
1269          * again changes according to bandwidth allocation.
1270          */
1271         if (p_link->link_up && p_link->speed)
1272                 p_link->line_speed = p_link->speed;
1273         else
1274                 p_link->line_speed = 0;
1275
1276         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1277         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1278
1279         /* Max bandwidth configuration */
1280         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1281                                            p_link, max_bw);
1282
1283         /* Mintz bandwidth configuration */
1284         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1285                                            p_link, min_bw);
1286         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1287                                               p_link->min_pf_rate);
1288
1289         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1290         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1291         p_link->parallel_detection = !!(status &
1292                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1293         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1294
1295         p_link->partner_adv_speed |=
1296             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1297             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1298         p_link->partner_adv_speed |=
1299             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1300             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1301         p_link->partner_adv_speed |=
1302             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1303             ECORE_LINK_PARTNER_SPEED_10G : 0;
1304         p_link->partner_adv_speed |=
1305             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1306             ECORE_LINK_PARTNER_SPEED_20G : 0;
1307         p_link->partner_adv_speed |=
1308             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1309             ECORE_LINK_PARTNER_SPEED_25G : 0;
1310         p_link->partner_adv_speed |=
1311             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1312             ECORE_LINK_PARTNER_SPEED_40G : 0;
1313         p_link->partner_adv_speed |=
1314             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1315             ECORE_LINK_PARTNER_SPEED_50G : 0;
1316         p_link->partner_adv_speed |=
1317             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1318             ECORE_LINK_PARTNER_SPEED_100G : 0;
1319
1320         p_link->partner_tx_flow_ctrl_en =
1321             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1322         p_link->partner_rx_flow_ctrl_en =
1323             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1324
1325         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1326         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1327                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1328                 break;
1329         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1330                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1331                 break;
1332         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1333                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1334                 break;
1335         default:
1336                 p_link->partner_adv_pause = 0;
1337         }
1338
1339         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1340
1341         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1342                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1343
1344         OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1345 out:
1346         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1347 }
1348
1349 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1350                                         struct ecore_ptt *p_ptt, bool b_up)
1351 {
1352         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1353         struct ecore_mcp_mb_params mb_params;
1354         struct eth_phy_cfg phy_cfg;
1355         enum _ecore_status_t rc = ECORE_SUCCESS;
1356         u32 cmd;
1357
1358 #ifndef ASIC_ONLY
1359         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1360                 return ECORE_SUCCESS;
1361 #endif
1362
1363         /* Set the shmem configuration according to params */
1364         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1365         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1366         if (!params->speed.autoneg)
1367                 phy_cfg.speed = params->speed.forced_speed;
1368         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1369         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1370         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1371         phy_cfg.adv_speed = params->speed.advertised_speeds;
1372         phy_cfg.loopback_mode = params->loopback_mode;
1373
1374         /* There are MFWs that share this capability regardless of whether
1375          * this is feasible or not. And given that at the very least adv_caps
1376          * would be set internally by ecore, we want to make sure LFA would
1377          * still work.
1378          */
1379         if ((p_hwfn->mcp_info->capabilities &
1380              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1381             params->eee.enable) {
1382                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1383                 if (params->eee.tx_lpi_enable)
1384                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1385                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1386                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1387                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1388                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1389                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1390                                     EEE_TX_TIMER_USEC_OFFSET) &
1391                                         EEE_TX_TIMER_USEC_MASK;
1392         }
1393
1394         p_hwfn->b_drv_link_init = b_up;
1395
1396         if (b_up)
1397                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1398                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1399                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1400                            phy_cfg.loopback_mode);
1401         else
1402                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1403
1404         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1405         mb_params.cmd = cmd;
1406         mb_params.p_data_src = &phy_cfg;
1407         mb_params.data_src_size = sizeof(phy_cfg);
1408         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1409
1410         /* if mcp fails to respond we must abort */
1411         if (rc != ECORE_SUCCESS) {
1412                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1413                 return rc;
1414         }
1415
1416         /* Mimic link-change attention, done for several reasons:
1417          *  - On reset, there's no guarantee MFW would trigger
1418          *    an attention.
1419          *  - On initialization, older MFWs might not indicate link change
1420          *    during LFA, so we'll never get an UP indication.
1421          */
1422         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1423
1424         return rc;
1425 }
1426
1427 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1428                                    struct ecore_ptt *p_ptt)
1429 {
1430         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1431
1432         /* TODO - Add support for VFs */
1433         if (IS_VF(p_hwfn->p_dev))
1434                 return ECORE_INVAL;
1435
1436         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1437                                                  PUBLIC_PATH);
1438         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1439         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1440
1441         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1442                                  path_addr +
1443                                  OFFSETOF(struct public_path, process_kill)) &
1444             PROCESS_KILL_COUNTER_MASK;
1445
1446         return proc_kill_cnt;
1447 }
1448
1449 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1450                                           struct ecore_ptt *p_ptt)
1451 {
1452         struct ecore_dev *p_dev = p_hwfn->p_dev;
1453         u32 proc_kill_cnt;
1454
1455         /* Prevent possible attentions/interrupts during the recovery handling
1456          * and till its load phase, during which they will be re-enabled.
1457          */
1458         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1459
1460         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1461
1462         /* The following operations should be done once, and thus in CMT mode
1463          * are carried out by only the first HW function.
1464          */
1465         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1466                 return;
1467
1468         if (p_dev->recov_in_prog) {
1469                 DP_NOTICE(p_hwfn, false,
1470                           "Ignoring the indication since a recovery"
1471                           " process is already in progress\n");
1472                 return;
1473         }
1474
1475         p_dev->recov_in_prog = true;
1476
1477         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1478         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1479
1480         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1481 }
1482
1483 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1484                                           struct ecore_ptt *p_ptt,
1485                                           enum MFW_DRV_MSG_TYPE type)
1486 {
1487         enum ecore_mcp_protocol_type stats_type;
1488         union ecore_mcp_protocol_stats stats;
1489         struct ecore_mcp_mb_params mb_params;
1490         u32 hsi_param;
1491         enum _ecore_status_t rc;
1492
1493         switch (type) {
1494         case MFW_DRV_MSG_GET_LAN_STATS:
1495                 stats_type = ECORE_MCP_LAN_STATS;
1496                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1497                 break;
1498         default:
1499                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1500                 return;
1501         }
1502
1503         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1504
1505         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1506         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1507         mb_params.param = hsi_param;
1508         mb_params.p_data_src = &stats;
1509         mb_params.data_src_size = sizeof(stats);
1510         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1511         if (rc != ECORE_SUCCESS)
1512                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1513 }
1514
1515 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1516                                     struct public_func *p_shmem_info)
1517 {
1518         struct ecore_mcp_function_info *p_info;
1519
1520         p_info = &p_hwfn->mcp_info->func_info;
1521
1522         /* TODO - bandwidth min/max should have valid values of 1-100,
1523          * as well as some indication that the feature is disabled.
1524          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1525          * limit and correct value to min `1' and max `100' if limit isn't in
1526          * range.
1527          */
1528         p_info->bandwidth_min = (p_shmem_info->config &
1529                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1530             FUNC_MF_CFG_MIN_BW_OFFSET;
1531         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1532                 DP_INFO(p_hwfn,
1533                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1534                         p_info->bandwidth_min);
1535                 p_info->bandwidth_min = 1;
1536         }
1537
1538         p_info->bandwidth_max = (p_shmem_info->config &
1539                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1540             FUNC_MF_CFG_MAX_BW_OFFSET;
1541         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1542                 DP_INFO(p_hwfn,
1543                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1544                         p_info->bandwidth_max);
1545                 p_info->bandwidth_max = 100;
1546         }
1547 }
1548
1549 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1550                                     struct ecore_ptt *p_ptt,
1551                                     struct public_func *p_data,
1552                                     int pfid)
1553 {
1554         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1555                                         PUBLIC_FUNC);
1556         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1557         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1558         u32 i, size;
1559
1560         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1561
1562         size = OSAL_MIN_T(u32, sizeof(*p_data),
1563                           SECTION_SIZE(mfw_path_offsize));
1564         for (i = 0; i < size / sizeof(u32); i++)
1565                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1566                                               func_addr + (i << 2));
1567
1568         return size;
1569 }
1570
1571 static void
1572 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1573 {
1574         struct ecore_mcp_function_info *p_info;
1575         struct public_func shmem_info;
1576         u32 resp = 0, param = 0;
1577
1578         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1579
1580         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1581
1582         p_info = &p_hwfn->mcp_info->func_info;
1583
1584         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1585
1586         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1587
1588         /* Acknowledge the MFW */
1589         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1590                       &param);
1591 }
1592
1593 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1594                                          struct ecore_ptt *p_ptt)
1595 {
1596         /* A single notification should be sent to upper driver in CMT mode */
1597         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1598                 return;
1599
1600         DP_NOTICE(p_hwfn, false,
1601                   "Fan failure was detected on the network interface card"
1602                   " and it's going to be shut down.\n");
1603
1604         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1605 }
1606
1607 struct ecore_mdump_cmd_params {
1608         u32 cmd;
1609         void *p_data_src;
1610         u8 data_src_size;
1611         void *p_data_dst;
1612         u8 data_dst_size;
1613         u32 mcp_resp;
1614 };
1615
1616 static enum _ecore_status_t
1617 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1618                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1619 {
1620         struct ecore_mcp_mb_params mb_params;
1621         enum _ecore_status_t rc;
1622
1623         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1624         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1625         mb_params.param = p_mdump_cmd_params->cmd;
1626         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1627         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1628         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1629         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1630         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1631         if (rc != ECORE_SUCCESS)
1632                 return rc;
1633
1634         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1635
1636         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1637                 DP_INFO(p_hwfn,
1638                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1639                         p_mdump_cmd_params->cmd);
1640                 rc = ECORE_NOTIMPL;
1641         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1642                 DP_INFO(p_hwfn,
1643                         "The mdump command is not supported by the MFW\n");
1644                 rc = ECORE_NOTIMPL;
1645         }
1646
1647         return rc;
1648 }
1649
1650 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1651                                                 struct ecore_ptt *p_ptt)
1652 {
1653         struct ecore_mdump_cmd_params mdump_cmd_params;
1654
1655         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1656         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1657
1658         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1659 }
1660
1661 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1662                                                 struct ecore_ptt *p_ptt,
1663                                                 u32 epoch)
1664 {
1665         struct ecore_mdump_cmd_params mdump_cmd_params;
1666
1667         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1668         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1669         mdump_cmd_params.p_data_src = &epoch;
1670         mdump_cmd_params.data_src_size = sizeof(epoch);
1671
1672         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1673 }
1674
1675 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1676                                              struct ecore_ptt *p_ptt)
1677 {
1678         struct ecore_mdump_cmd_params mdump_cmd_params;
1679
1680         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1681         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1682
1683         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1684 }
1685
1686 static enum _ecore_status_t
1687 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1688                            struct mdump_config_stc *p_mdump_config)
1689 {
1690         struct ecore_mdump_cmd_params mdump_cmd_params;
1691         enum _ecore_status_t rc;
1692
1693         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1694         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1695         mdump_cmd_params.p_data_dst = p_mdump_config;
1696         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1697
1698         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1699         if (rc != ECORE_SUCCESS)
1700                 return rc;
1701
1702         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1703                 DP_INFO(p_hwfn,
1704                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1705                         mdump_cmd_params.mcp_resp);
1706                 rc = ECORE_UNKNOWN_ERROR;
1707         }
1708
1709         return rc;
1710 }
1711
1712 enum _ecore_status_t
1713 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1714                          struct ecore_mdump_info *p_mdump_info)
1715 {
1716         u32 addr, global_offsize, global_addr;
1717         struct mdump_config_stc mdump_config;
1718         enum _ecore_status_t rc;
1719
1720         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1721
1722         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1723                                     PUBLIC_GLOBAL);
1724         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1725         global_addr = SECTION_ADDR(global_offsize, 0);
1726         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1727                                         global_addr +
1728                                         OFFSETOF(struct public_global,
1729                                                  mdump_reason));
1730
1731         if (p_mdump_info->reason) {
1732                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1733                 if (rc != ECORE_SUCCESS)
1734                         return rc;
1735
1736                 p_mdump_info->version = mdump_config.version;
1737                 p_mdump_info->config = mdump_config.config;
1738                 p_mdump_info->epoch = mdump_config.epoc;
1739                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1740                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1741
1742                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1743                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1744                            p_mdump_info->reason, p_mdump_info->version,
1745                            p_mdump_info->config, p_mdump_info->epoch,
1746                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1747         } else {
1748                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1749                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1750         }
1751
1752         return ECORE_SUCCESS;
1753 }
1754
1755 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1756                                                 struct ecore_ptt *p_ptt)
1757 {
1758         struct ecore_mdump_cmd_params mdump_cmd_params;
1759
1760         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1761         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1762
1763         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1764 }
1765
1766 enum _ecore_status_t
1767 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1768                            struct ecore_mdump_retain_data *p_mdump_retain)
1769 {
1770         struct ecore_mdump_cmd_params mdump_cmd_params;
1771         struct mdump_retain_data_stc mfw_mdump_retain;
1772         enum _ecore_status_t rc;
1773
1774         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1775         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1776         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1777         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1778
1779         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1780         if (rc != ECORE_SUCCESS)
1781                 return rc;
1782
1783         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1784                 DP_INFO(p_hwfn,
1785                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1786                         mdump_cmd_params.mcp_resp);
1787                 return ECORE_UNKNOWN_ERROR;
1788         }
1789
1790         p_mdump_retain->valid = mfw_mdump_retain.valid;
1791         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1792         p_mdump_retain->pf = mfw_mdump_retain.pf;
1793         p_mdump_retain->status = mfw_mdump_retain.status;
1794
1795         return ECORE_SUCCESS;
1796 }
1797
1798 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1799                                                 struct ecore_ptt *p_ptt)
1800 {
1801         struct ecore_mdump_cmd_params mdump_cmd_params;
1802
1803         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1804         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1805
1806         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1807 }
1808
1809 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1810                                             struct ecore_ptt *p_ptt)
1811 {
1812         struct ecore_mdump_retain_data mdump_retain;
1813         enum _ecore_status_t rc;
1814
1815         /* In CMT mode - no need for more than a single acknowledgment to the
1816          * MFW, and no more than a single notification to the upper driver.
1817          */
1818         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1819                 return;
1820
1821         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1822         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1823                 DP_NOTICE(p_hwfn, false,
1824                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1825                           mdump_retain.epoch, mdump_retain.pf,
1826                           mdump_retain.status);
1827         } else {
1828                 DP_NOTICE(p_hwfn, false,
1829                           "The MFW notified that a critical error occurred in the device\n");
1830         }
1831
1832         if (p_hwfn->p_dev->allow_mdump) {
1833                 DP_NOTICE(p_hwfn, false,
1834                           "Not acknowledging the notification to allow the MFW crash dump\n");
1835                 return;
1836         }
1837
1838         DP_NOTICE(p_hwfn, false,
1839                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1840         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1841         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1842 }
1843
1844 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1845                                              struct ecore_ptt *p_ptt)
1846 {
1847         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1848         enum _ecore_status_t rc = ECORE_SUCCESS;
1849         bool found = false;
1850         u16 i;
1851
1852         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1853
1854         /* Read Messages from MFW */
1855         ecore_mcp_read_mb(p_hwfn, p_ptt);
1856
1857         /* Compare current messages to old ones */
1858         for (i = 0; i < info->mfw_mb_length; i++) {
1859                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1860                         continue;
1861
1862                 found = true;
1863
1864                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1865                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1866                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1867
1868                 switch (i) {
1869                 case MFW_DRV_MSG_LINK_CHANGE:
1870                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1871                         break;
1872                 case MFW_DRV_MSG_VF_DISABLED:
1873                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1874                         break;
1875                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1876                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1877                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1878                         break;
1879                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1880                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1881                                                     ECORE_DCBX_REMOTE_MIB);
1882                         break;
1883                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1884                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1885                                                     ECORE_DCBX_OPERATIONAL_MIB);
1886                         break;
1887                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1888                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1889                         break;
1890                 case MFW_DRV_MSG_ERROR_RECOVERY:
1891                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1892                         break;
1893                 case MFW_DRV_MSG_GET_LAN_STATS:
1894                 case MFW_DRV_MSG_GET_FCOE_STATS:
1895                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1896                 case MFW_DRV_MSG_GET_RDMA_STATS:
1897                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1898                         break;
1899                 case MFW_DRV_MSG_BW_UPDATE:
1900                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1901                         break;
1902                 case MFW_DRV_MSG_FAILURE_DETECTED:
1903                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1904                         break;
1905                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1906                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1907                         break;
1908                 default:
1909                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1910                         rc = ECORE_INVAL;
1911                 }
1912         }
1913
1914         /* ACK everything */
1915         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1916                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1917
1918                 /* MFW expect answer in BE, so we force write in that format */
1919                 ecore_wr(p_hwfn, p_ptt,
1920                          info->mfw_mb_addr + sizeof(u32) +
1921                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1922                          sizeof(u32) + i * sizeof(u32), val);
1923         }
1924
1925         if (!found) {
1926                 DP_NOTICE(p_hwfn, false,
1927                           "Received an MFW message indication but no"
1928                           " new message!\n");
1929                 rc = ECORE_INVAL;
1930         }
1931
1932         /* Copy the new mfw messages into the shadow */
1933         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1934
1935         return rc;
1936 }
1937
1938 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1939                                            struct ecore_ptt *p_ptt,
1940                                            u32 *p_mfw_ver,
1941                                            u32 *p_running_bundle_id)
1942 {
1943         u32 global_offsize;
1944
1945 #ifndef ASIC_ONLY
1946         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1947                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1948                 return ECORE_SUCCESS;
1949         }
1950 #endif
1951
1952         if (IS_VF(p_hwfn->p_dev)) {
1953                 if (p_hwfn->vf_iov_info) {
1954                         struct pfvf_acquire_resp_tlv *p_resp;
1955
1956                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1957                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1958                         return ECORE_SUCCESS;
1959                 } else {
1960                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1961                                    "VF requested MFW version prior to ACQUIRE\n");
1962                         return ECORE_INVAL;
1963                 }
1964         }
1965
1966         global_offsize = ecore_rd(p_hwfn, p_ptt,
1967                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1968                                                        public_base,
1969                                                        PUBLIC_GLOBAL));
1970         *p_mfw_ver =
1971             ecore_rd(p_hwfn, p_ptt,
1972                      SECTION_ADDR(global_offsize,
1973                                   0) + OFFSETOF(struct public_global, mfw_ver));
1974
1975         if (p_running_bundle_id != OSAL_NULL) {
1976                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1977                                                 SECTION_ADDR(global_offsize,
1978                                                              0) +
1979                                                 OFFSETOF(struct public_global,
1980                                                          running_bundle_id));
1981         }
1982
1983         return ECORE_SUCCESS;
1984 }
1985
1986 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
1987                                               struct ecore_ptt *p_ptt,
1988                                               u32 *p_media_type)
1989 {
1990
1991         /* TODO - Add support for VFs */
1992         if (IS_VF(p_hwfn->p_dev))
1993                 return ECORE_INVAL;
1994
1995         if (!ecore_mcp_is_init(p_hwfn)) {
1996                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1997                 return ECORE_BUSY;
1998         }
1999
2000         if (!p_ptt) {
2001                 *p_media_type = MEDIA_UNSPECIFIED;
2002                 return ECORE_INVAL;
2003         } else {
2004                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2005                                          p_hwfn->mcp_info->port_addr +
2006                                          OFFSETOF(struct public_port,
2007                                                   media_type));
2008         }
2009
2010         return ECORE_SUCCESS;
2011 }
2012
2013 /* @DPDK */
2014 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2015 static void
2016 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2017                                  enum ecore_pci_personality *p_proto)
2018 {
2019         *p_proto = ECORE_PCI_ETH;
2020
2021         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2022                    "According to Legacy capabilities, L2 personality is %08x\n",
2023                    (u32)*p_proto);
2024 }
2025
2026 /* @DPDK */
2027 static enum _ecore_status_t
2028 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2029                               struct ecore_ptt *p_ptt,
2030                               enum ecore_pci_personality *p_proto)
2031 {
2032         u32 resp = 0, param = 0;
2033         enum _ecore_status_t rc;
2034
2035         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2036                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2037                    (u32)*p_proto, resp, param);
2038         return ECORE_SUCCESS;
2039 }
2040
2041 static enum _ecore_status_t
2042 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2043                           struct public_func *p_info,
2044                           struct ecore_ptt *p_ptt,
2045                           enum ecore_pci_personality *p_proto)
2046 {
2047         enum _ecore_status_t rc = ECORE_SUCCESS;
2048
2049         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2050         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2051                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2052                     ECORE_SUCCESS)
2053                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2054                 break;
2055         default:
2056                 rc = ECORE_INVAL;
2057         }
2058
2059         return rc;
2060 }
2061
2062 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2063                                                     struct ecore_ptt *p_ptt)
2064 {
2065         struct ecore_mcp_function_info *info;
2066         struct public_func shmem_info;
2067
2068         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2069         info = &p_hwfn->mcp_info->func_info;
2070
2071         info->pause_on_host = (shmem_info.config &
2072                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2073
2074         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2075                                       &info->protocol)) {
2076                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2077                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2078                 return ECORE_INVAL;
2079         }
2080
2081         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2082
2083         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2084                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2085                 info->mac[1] = (u8)(shmem_info.mac_upper);
2086                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2087                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2088                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2089                 info->mac[5] = (u8)(shmem_info.mac_lower);
2090         } else {
2091                 /* TODO - are there protocols for which there's no MAC? */
2092                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2093         }
2094
2095         /* TODO - are these calculations true for BE machine? */
2096         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2097                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2098         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2099                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2100
2101         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2102
2103         info->mtu = (u16)shmem_info.mtu_size;
2104
2105         if (info->mtu == 0)
2106                 info->mtu = 1500;
2107
2108         info->mtu = (u16)shmem_info.mtu_size;
2109
2110         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2111                    "Read configuration from shmem: pause_on_host %02x"
2112                     " protocol %02x BW [%02x - %02x]"
2113                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2114                     " node %lx ovlan %04x\n",
2115                    info->pause_on_host, info->protocol,
2116                    info->bandwidth_min, info->bandwidth_max,
2117                    info->mac[0], info->mac[1], info->mac[2],
2118                    info->mac[3], info->mac[4], info->mac[5],
2119                    (unsigned long)info->wwn_port,
2120                    (unsigned long)info->wwn_node, info->ovlan);
2121
2122         return ECORE_SUCCESS;
2123 }
2124
2125 struct ecore_mcp_link_params
2126 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2127 {
2128         if (!p_hwfn || !p_hwfn->mcp_info)
2129                 return OSAL_NULL;
2130         return &p_hwfn->mcp_info->link_input;
2131 }
2132
2133 struct ecore_mcp_link_state
2134 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2135 {
2136         if (!p_hwfn || !p_hwfn->mcp_info)
2137                 return OSAL_NULL;
2138
2139 #ifndef ASIC_ONLY
2140         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2141                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2142                 p_hwfn->mcp_info->link_output.link_up = true;
2143         }
2144 #endif
2145
2146         return &p_hwfn->mcp_info->link_output;
2147 }
2148
2149 struct ecore_mcp_link_capabilities
2150 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2151 {
2152         if (!p_hwfn || !p_hwfn->mcp_info)
2153                 return OSAL_NULL;
2154         return &p_hwfn->mcp_info->link_capabilities;
2155 }
2156
2157 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2158                                      struct ecore_ptt *p_ptt)
2159 {
2160         u32 resp = 0, param = 0;
2161         enum _ecore_status_t rc;
2162
2163         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2164                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2165
2166         /* Wait for the drain to complete before returning */
2167         OSAL_MSLEEP(1020);
2168
2169         return rc;
2170 }
2171
2172 const struct ecore_mcp_function_info
2173 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2174 {
2175         if (!p_hwfn || !p_hwfn->mcp_info)
2176                 return OSAL_NULL;
2177         return &p_hwfn->mcp_info->func_info;
2178 }
2179
2180 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2181                                   struct ecore_ptt *p_ptt, u32 personalities)
2182 {
2183         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2184         struct public_func shmem_info;
2185         int i, count = 0, num_pfs;
2186
2187         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2188
2189         for (i = 0; i < num_pfs; i++) {
2190                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2191                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2192                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2193                         continue;
2194
2195                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2196                                               &protocol) !=
2197                     ECORE_SUCCESS)
2198                         continue;
2199
2200                 if ((1 << ((u32)protocol)) & personalities)
2201                         count++;
2202         }
2203
2204         return count;
2205 }
2206
2207 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2208                                               struct ecore_ptt *p_ptt,
2209                                               u32 *p_flash_size)
2210 {
2211         u32 flash_size;
2212
2213 #ifndef ASIC_ONLY
2214         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2215                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2216                 return ECORE_INVAL;
2217         }
2218 #endif
2219
2220         if (IS_VF(p_hwfn->p_dev))
2221                 return ECORE_INVAL;
2222
2223         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2224         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2225                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2226         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2227
2228         *p_flash_size = flash_size;
2229
2230         return ECORE_SUCCESS;
2231 }
2232
2233 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2234                                                   struct ecore_ptt *p_ptt)
2235 {
2236         struct ecore_dev *p_dev = p_hwfn->p_dev;
2237
2238         if (p_dev->recov_in_prog) {
2239                 DP_NOTICE(p_hwfn, false,
2240                           "Avoid triggering a recovery since such a process"
2241                           " is already in progress\n");
2242                 return ECORE_AGAIN;
2243         }
2244
2245         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2246         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2247
2248         return ECORE_SUCCESS;
2249 }
2250
2251 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2252                                               struct ecore_ptt *p_ptt,
2253                                               u8 vf_id, u8 num)
2254 {
2255         u32 resp = 0, param = 0, rc_param = 0;
2256         enum _ecore_status_t rc;
2257
2258 /* Only Leader can configure MSIX, and need to take CMT into account */
2259
2260         if (!IS_LEAD_HWFN(p_hwfn))
2261                 return ECORE_SUCCESS;
2262         num *= p_hwfn->p_dev->num_hwfns;
2263
2264         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2265             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2266         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2267             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2268
2269         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2270                            &resp, &rc_param);
2271
2272         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2273                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2274                           vf_id);
2275                 rc = ECORE_INVAL;
2276         } else {
2277                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2278                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2279                             num, vf_id);
2280         }
2281
2282         return rc;
2283 }
2284
2285 enum _ecore_status_t
2286 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2287                            struct ecore_mcp_drv_version *p_ver)
2288 {
2289         struct ecore_mcp_mb_params mb_params;
2290         struct drv_version_stc drv_version;
2291         u32 num_words, i;
2292         void *p_name;
2293         OSAL_BE32 val;
2294         enum _ecore_status_t rc;
2295
2296 #ifndef ASIC_ONLY
2297         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2298                 return ECORE_SUCCESS;
2299 #endif
2300
2301         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2302         drv_version.version = p_ver->version;
2303         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2304         for (i = 0; i < num_words; i++) {
2305                 /* The driver name is expected to be in a big-endian format */
2306                 p_name = &p_ver->name[i * sizeof(u32)];
2307                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2308                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2309         }
2310
2311         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2312         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2313         mb_params.p_data_src = &drv_version;
2314         mb_params.data_src_size = sizeof(drv_version);
2315         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2316         if (rc != ECORE_SUCCESS)
2317                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2318
2319         return rc;
2320 }
2321
2322 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2323                                     struct ecore_ptt *p_ptt)
2324 {
2325         enum _ecore_status_t rc;
2326         u32 resp = 0, param = 0;
2327
2328         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2329                            &param);
2330         if (rc != ECORE_SUCCESS)
2331                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2332
2333         return rc;
2334 }
2335
2336 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2337                                       struct ecore_ptt *p_ptt)
2338 {
2339         u32 value, cpu_mode;
2340
2341         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2342
2343         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2344         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2345         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2346         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2347
2348         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2349 }
2350
2351 enum _ecore_status_t
2352 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2353                                    struct ecore_ptt *p_ptt,
2354                                    enum ecore_ov_client client)
2355 {
2356         enum _ecore_status_t rc;
2357         u32 resp = 0, param = 0;
2358         u32 drv_mb_param;
2359
2360         switch (client) {
2361         case ECORE_OV_CLIENT_DRV:
2362                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2363                 break;
2364         case ECORE_OV_CLIENT_USER:
2365                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2366                 break;
2367         case ECORE_OV_CLIENT_VENDOR_SPEC:
2368                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2369                 break;
2370         default:
2371                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2372                 return ECORE_INVAL;
2373         }
2374
2375         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2376                            drv_mb_param, &resp, &param);
2377         if (rc != ECORE_SUCCESS)
2378                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2379
2380         return rc;
2381 }
2382
2383 enum _ecore_status_t
2384 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2385                                  struct ecore_ptt *p_ptt,
2386                                  enum ecore_ov_driver_state drv_state)
2387 {
2388         enum _ecore_status_t rc;
2389         u32 resp = 0, param = 0;
2390         u32 drv_mb_param;
2391
2392         switch (drv_state) {
2393         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2394                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2395                 break;
2396         case ECORE_OV_DRIVER_STATE_DISABLED:
2397                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2398                 break;
2399         case ECORE_OV_DRIVER_STATE_ACTIVE:
2400                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2401                 break;
2402         default:
2403                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2404                 return ECORE_INVAL;
2405         }
2406
2407         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2408                            drv_mb_param, &resp, &param);
2409         if (rc != ECORE_SUCCESS)
2410                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2411
2412         return rc;
2413 }
2414
2415 enum _ecore_status_t
2416 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2417                          struct ecore_fc_npiv_tbl *p_table)
2418 {
2419         return 0;
2420 }
2421
2422 enum _ecore_status_t
2423 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2424                         struct ecore_ptt *p_ptt, u16 mtu)
2425 {
2426         return 0;
2427 }
2428
2429 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2430                                        struct ecore_ptt *p_ptt,
2431                                        enum ecore_led_mode mode)
2432 {
2433         u32 resp = 0, param = 0, drv_mb_param;
2434         enum _ecore_status_t rc;
2435
2436         switch (mode) {
2437         case ECORE_LED_MODE_ON:
2438                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2439                 break;
2440         case ECORE_LED_MODE_OFF:
2441                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2442                 break;
2443         case ECORE_LED_MODE_RESTORE:
2444                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2445                 break;
2446         default:
2447                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2448                 return ECORE_INVAL;
2449         }
2450
2451         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2452                            drv_mb_param, &resp, &param);
2453         if (rc != ECORE_SUCCESS)
2454                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2455
2456         return rc;
2457 }
2458
2459 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2460                                              struct ecore_ptt *p_ptt,
2461                                              u32 mask_parities)
2462 {
2463         u32 resp = 0, param = 0;
2464         enum _ecore_status_t rc;
2465
2466         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2467                            mask_parities, &resp, &param);
2468
2469         if (rc != ECORE_SUCCESS) {
2470                 DP_ERR(p_hwfn,
2471                        "MCP response failure for mask parities, aborting\n");
2472         } else if (resp != FW_MSG_CODE_OK) {
2473                 DP_ERR(p_hwfn,
2474                        "MCP did not ack mask parity request. Old MFW?\n");
2475                 rc = ECORE_INVAL;
2476         }
2477
2478         return rc;
2479 }
2480
2481 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2482                                         u8 *p_buf, u32 len)
2483 {
2484         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2485         u32 bytes_left, offset, bytes_to_copy, buf_size;
2486         u32 nvm_offset, resp, param;
2487         struct ecore_ptt *p_ptt;
2488         enum _ecore_status_t rc = ECORE_SUCCESS;
2489
2490         p_ptt = ecore_ptt_acquire(p_hwfn);
2491         if (!p_ptt)
2492                 return ECORE_BUSY;
2493
2494         bytes_left = len;
2495         offset = 0;
2496         while (bytes_left > 0) {
2497                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2498                                            MCP_DRV_NVM_BUF_LEN);
2499                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2500                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
2501                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2502                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2503                                           nvm_offset, &resp, &param, &buf_size,
2504                                           (u32 *)(p_buf + offset));
2505                 if (rc != ECORE_SUCCESS) {
2506                         DP_NOTICE(p_dev, false,
2507                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2508                                   rc);
2509                         resp = FW_MSG_CODE_ERROR;
2510                         break;
2511                 }
2512
2513                 if (resp != FW_MSG_CODE_NVM_OK) {
2514                         DP_NOTICE(p_dev, false,
2515                                   "nvm read failed, resp = 0x%08x\n", resp);
2516                         rc = ECORE_UNKNOWN_ERROR;
2517                         break;
2518                 }
2519
2520                 /* This can be a lengthy process, and it's possible scheduler
2521                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2522                  */
2523                 if (bytes_left % 0x1000 <
2524                     (bytes_left - buf_size) % 0x1000)
2525                         OSAL_MSLEEP(1);
2526
2527                 offset += buf_size;
2528                 bytes_left -= buf_size;
2529         }
2530
2531         p_dev->mcp_nvm_resp = resp;
2532         ecore_ptt_release(p_hwfn, p_ptt);
2533
2534         return rc;
2535 }
2536
2537 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2538                                         u32 addr, u8 *p_buf, u32 len)
2539 {
2540         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2541         struct ecore_ptt *p_ptt;
2542         u32 resp, param;
2543         enum _ecore_status_t rc;
2544
2545         p_ptt = ecore_ptt_acquire(p_hwfn);
2546         if (!p_ptt)
2547                 return ECORE_BUSY;
2548
2549         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2550                                   (cmd == ECORE_PHY_CORE_READ) ?
2551                                   DRV_MSG_CODE_PHY_CORE_READ :
2552                                   DRV_MSG_CODE_PHY_RAW_READ,
2553                                   addr, &resp, &param, &len, (u32 *)p_buf);
2554         if (rc != ECORE_SUCCESS)
2555                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2556
2557         p_dev->mcp_nvm_resp = resp;
2558         ecore_ptt_release(p_hwfn, p_ptt);
2559
2560         return rc;
2561 }
2562
2563 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2564 {
2565         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2566         struct ecore_ptt *p_ptt;
2567
2568         p_ptt = ecore_ptt_acquire(p_hwfn);
2569         if (!p_ptt)
2570                 return ECORE_BUSY;
2571
2572         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2573         ecore_ptt_release(p_hwfn, p_ptt);
2574
2575         return ECORE_SUCCESS;
2576 }
2577
2578 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2579 {
2580         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2581         struct ecore_ptt *p_ptt;
2582         u32 resp, param;
2583         enum _ecore_status_t rc;
2584
2585         p_ptt = ecore_ptt_acquire(p_hwfn);
2586         if (!p_ptt)
2587                 return ECORE_BUSY;
2588         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2589                            &resp, &param);
2590         p_dev->mcp_nvm_resp = resp;
2591         ecore_ptt_release(p_hwfn, p_ptt);
2592
2593         return rc;
2594 }
2595
2596 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2597                                                   u32 addr)
2598 {
2599         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2600         struct ecore_ptt *p_ptt;
2601         u32 resp, param;
2602         enum _ecore_status_t rc;
2603
2604         p_ptt = ecore_ptt_acquire(p_hwfn);
2605         if (!p_ptt)
2606                 return ECORE_BUSY;
2607         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2608                            &resp, &param);
2609         p_dev->mcp_nvm_resp = resp;
2610         ecore_ptt_release(p_hwfn, p_ptt);
2611
2612         return rc;
2613 }
2614
2615 /* rc receives ECORE_INVAL as default parameter because
2616  * it might not enter the while loop if the len is 0
2617  */
2618 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2619                                          u32 addr, u8 *p_buf, u32 len)
2620 {
2621         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2622         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2623         enum _ecore_status_t rc = ECORE_INVAL;
2624         struct ecore_ptt *p_ptt;
2625
2626         p_ptt = ecore_ptt_acquire(p_hwfn);
2627         if (!p_ptt)
2628                 return ECORE_BUSY;
2629
2630         switch (cmd) {
2631         case ECORE_PUT_FILE_DATA:
2632                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2633                 break;
2634         case ECORE_NVM_WRITE_NVRAM:
2635                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2636                 break;
2637         case ECORE_EXT_PHY_FW_UPGRADE:
2638                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2639                 break;
2640         default:
2641                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2642                           cmd);
2643                 rc = ECORE_INVAL;
2644                 goto out;
2645         }
2646
2647         buf_idx = 0;
2648         while (buf_idx < len) {
2649                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2650                                       MCP_DRV_NVM_BUF_LEN);
2651                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2652                               addr) +
2653                              buf_idx;
2654                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2655                                           &resp, &param, buf_size,
2656                                           (u32 *)&p_buf[buf_idx]);
2657                 if (rc != ECORE_SUCCESS) {
2658                         DP_NOTICE(p_dev, false,
2659                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2660                                   rc);
2661                         resp = FW_MSG_CODE_ERROR;
2662                         break;
2663                 }
2664
2665                 if (resp != FW_MSG_CODE_OK &&
2666                     resp != FW_MSG_CODE_NVM_OK &&
2667                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2668                         DP_NOTICE(p_dev, false,
2669                                   "nvm write failed, resp = 0x%08x\n", resp);
2670                         rc = ECORE_UNKNOWN_ERROR;
2671                         break;
2672                 }
2673
2674                 /* This can be a lengthy process, and it's possible scheduler
2675                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2676                  */
2677                 if (buf_idx % 0x1000 >
2678                     (buf_idx + buf_size) % 0x1000)
2679                         OSAL_MSLEEP(1);
2680
2681                 buf_idx += buf_size;
2682         }
2683
2684         p_dev->mcp_nvm_resp = resp;
2685 out:
2686         ecore_ptt_release(p_hwfn, p_ptt);
2687
2688         return rc;
2689 }
2690
2691 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2692                                          u32 addr, u8 *p_buf, u32 len)
2693 {
2694         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2695         struct ecore_ptt *p_ptt;
2696         u32 resp, param, nvm_cmd;
2697         enum _ecore_status_t rc;
2698
2699         p_ptt = ecore_ptt_acquire(p_hwfn);
2700         if (!p_ptt)
2701                 return ECORE_BUSY;
2702
2703         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2704                         DRV_MSG_CODE_PHY_RAW_WRITE;
2705         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2706                                   &resp, &param, len, (u32 *)p_buf);
2707         if (rc != ECORE_SUCCESS)
2708                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2709         p_dev->mcp_nvm_resp = resp;
2710         ecore_ptt_release(p_hwfn, p_ptt);
2711
2712         return rc;
2713 }
2714
2715 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2716                                                    u32 addr)
2717 {
2718         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2719         struct ecore_ptt *p_ptt;
2720         u32 resp, param;
2721         enum _ecore_status_t rc;
2722
2723         p_ptt = ecore_ptt_acquire(p_hwfn);
2724         if (!p_ptt)
2725                 return ECORE_BUSY;
2726
2727         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2728                            &resp, &param);
2729         p_dev->mcp_nvm_resp = resp;
2730         ecore_ptt_release(p_hwfn, p_ptt);
2731
2732         return rc;
2733 }
2734
2735 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2736                                             struct ecore_ptt *p_ptt,
2737                                             u32 port, u32 addr, u32 offset,
2738                                             u32 len, u8 *p_buf)
2739 {
2740         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2741         u32 resp, param;
2742         enum _ecore_status_t rc;
2743
2744         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2745                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2746         addr = offset;
2747         offset = 0;
2748         bytes_left = len;
2749         while (bytes_left > 0) {
2750                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2751                                            MAX_I2C_TRANSACTION_SIZE);
2752                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2753                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2754                 nvm_offset |= ((addr + offset) <<
2755                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2756                 nvm_offset |= (bytes_to_copy <<
2757                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2758                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2759                                           DRV_MSG_CODE_TRANSCEIVER_READ,
2760                                           nvm_offset, &resp, &param, &buf_size,
2761                                           (u32 *)(p_buf + offset));
2762                 if ((resp & FW_MSG_CODE_MASK) ==
2763                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2764                         return ECORE_NODEV;
2765                 } else if ((resp & FW_MSG_CODE_MASK) !=
2766                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2767                         return ECORE_UNKNOWN_ERROR;
2768
2769                 offset += buf_size;
2770                 bytes_left -= buf_size;
2771         }
2772
2773         return ECORE_SUCCESS;
2774 }
2775
2776 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2777                                              struct ecore_ptt *p_ptt,
2778                                              u32 port, u32 addr, u32 offset,
2779                                              u32 len, u8 *p_buf)
2780 {
2781         u32 buf_idx, buf_size, nvm_offset, resp, param;
2782         enum _ecore_status_t rc;
2783
2784         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2785                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2786         buf_idx = 0;
2787         while (buf_idx < len) {
2788                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2789                                       MAX_I2C_TRANSACTION_SIZE);
2790                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2791                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2792                 nvm_offset |= ((offset + buf_idx) <<
2793                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2794                 nvm_offset |= (buf_size <<
2795                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2796                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2797                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
2798                                           nvm_offset, &resp, &param, buf_size,
2799                                           (u32 *)&p_buf[buf_idx]);
2800                 if ((resp & FW_MSG_CODE_MASK) ==
2801                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2802                         return ECORE_NODEV;
2803                 } else if ((resp & FW_MSG_CODE_MASK) !=
2804                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2805                         return ECORE_UNKNOWN_ERROR;
2806
2807                 buf_idx += buf_size;
2808         }
2809
2810         return ECORE_SUCCESS;
2811 }
2812
2813 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2814                                          struct ecore_ptt *p_ptt,
2815                                          u16 gpio, u32 *gpio_val)
2816 {
2817         enum _ecore_status_t rc = ECORE_SUCCESS;
2818         u32 drv_mb_param = 0, rsp;
2819
2820         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2821
2822         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2823                            drv_mb_param, &rsp, gpio_val);
2824
2825         if (rc != ECORE_SUCCESS)
2826                 return rc;
2827
2828         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2829                 return ECORE_UNKNOWN_ERROR;
2830
2831         return ECORE_SUCCESS;
2832 }
2833
2834 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2835                                           struct ecore_ptt *p_ptt,
2836                                           u16 gpio, u16 gpio_val)
2837 {
2838         enum _ecore_status_t rc = ECORE_SUCCESS;
2839         u32 drv_mb_param = 0, param, rsp;
2840
2841         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
2842                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
2843
2844         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2845                            drv_mb_param, &rsp, &param);
2846
2847         if (rc != ECORE_SUCCESS)
2848                 return rc;
2849
2850         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2851                 return ECORE_UNKNOWN_ERROR;
2852
2853         return ECORE_SUCCESS;
2854 }
2855
2856 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2857                                          struct ecore_ptt *p_ptt,
2858                                          u16 gpio, u32 *gpio_direction,
2859                                          u32 *gpio_ctrl)
2860 {
2861         u32 drv_mb_param = 0, rsp, val = 0;
2862         enum _ecore_status_t rc = ECORE_SUCCESS;
2863
2864         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
2865
2866         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2867                            drv_mb_param, &rsp, &val);
2868         if (rc != ECORE_SUCCESS)
2869                 return rc;
2870
2871         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2872                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
2873         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2874                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
2875
2876         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2877                 return ECORE_UNKNOWN_ERROR;
2878
2879         return ECORE_SUCCESS;
2880 }
2881
2882 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2883                                                   struct ecore_ptt *p_ptt)
2884 {
2885         u32 drv_mb_param = 0, rsp, param;
2886         enum _ecore_status_t rc = ECORE_SUCCESS;
2887
2888         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2889                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2890
2891         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2892                            drv_mb_param, &rsp, &param);
2893
2894         if (rc != ECORE_SUCCESS)
2895                 return rc;
2896
2897         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2898             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2899                 rc = ECORE_UNKNOWN_ERROR;
2900
2901         return rc;
2902 }
2903
2904 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2905                                                struct ecore_ptt *p_ptt)
2906 {
2907         u32 drv_mb_param, rsp, param;
2908         enum _ecore_status_t rc = ECORE_SUCCESS;
2909
2910         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2911                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2912
2913         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2914                            drv_mb_param, &rsp, &param);
2915
2916         if (rc != ECORE_SUCCESS)
2917                 return rc;
2918
2919         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2920             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2921                 rc = ECORE_UNKNOWN_ERROR;
2922
2923         return rc;
2924 }
2925
2926 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2927         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2928 {
2929         u32 drv_mb_param = 0, rsp;
2930         enum _ecore_status_t rc = ECORE_SUCCESS;
2931
2932         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2933                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2934
2935         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2936                            drv_mb_param, &rsp, num_images);
2937
2938         if (rc != ECORE_SUCCESS)
2939                 return rc;
2940
2941         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2942                 rc = ECORE_UNKNOWN_ERROR;
2943
2944         return rc;
2945 }
2946
2947 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2948         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2949         struct bist_nvm_image_att *p_image_att, u32 image_index)
2950 {
2951         u32 buf_size, nvm_offset, resp, param;
2952         enum _ecore_status_t rc;
2953
2954         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2955                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2956         nvm_offset |= (image_index <<
2957                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
2958         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2959                                   nvm_offset, &resp, &param, &buf_size,
2960                                   (u32 *)p_image_att);
2961         if (rc != ECORE_SUCCESS)
2962                 return rc;
2963
2964         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2965             (p_image_att->return_code != 1))
2966                 rc = ECORE_UNKNOWN_ERROR;
2967
2968         return rc;
2969 }
2970
2971 enum _ecore_status_t
2972 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2973                                struct ecore_ptt *p_ptt,
2974                                struct ecore_temperature_info *p_temp_info)
2975 {
2976         struct ecore_temperature_sensor *p_temp_sensor;
2977         struct temperature_status_stc mfw_temp_info;
2978         struct ecore_mcp_mb_params mb_params;
2979         u32 val;
2980         enum _ecore_status_t rc;
2981         u8 i;
2982
2983         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2984         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2985         mb_params.p_data_dst = &mfw_temp_info;
2986         mb_params.data_dst_size = sizeof(mfw_temp_info);
2987         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2988         if (rc != ECORE_SUCCESS)
2989                 return rc;
2990
2991         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2992         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2993                                               ECORE_MAX_NUM_OF_SENSORS);
2994         for (i = 0; i < p_temp_info->num_sensors; i++) {
2995                 val = mfw_temp_info.sensor[i];
2996                 p_temp_sensor = &p_temp_info->sensors[i];
2997                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2998                                                  SENSOR_LOCATION_OFFSET;
2999                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3000                                                 THRESHOLD_HIGH_OFFSET;
3001                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3002                                           CRITICAL_TEMPERATURE_OFFSET;
3003                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3004                                               CURRENT_TEMP_OFFSET;
3005         }
3006
3007         return ECORE_SUCCESS;
3008 }
3009
3010 enum _ecore_status_t ecore_mcp_get_mba_versions(
3011         struct ecore_hwfn *p_hwfn,
3012         struct ecore_ptt *p_ptt,
3013         struct ecore_mba_vers *p_mba_vers)
3014 {
3015         u32 buf_size, resp, param;
3016         enum _ecore_status_t rc;
3017
3018         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3019                                   0, &resp, &param, &buf_size,
3020                                   &p_mba_vers->mba_vers[0]);
3021
3022         if (rc != ECORE_SUCCESS)
3023                 return rc;
3024
3025         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3026                 rc = ECORE_UNKNOWN_ERROR;
3027
3028         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3029                 rc = ECORE_UNKNOWN_ERROR;
3030
3031         return rc;
3032 }
3033
3034 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3035                                               struct ecore_ptt *p_ptt,
3036                                               u64 *num_events)
3037 {
3038         u32 rsp;
3039
3040         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3041                              0, &rsp, (u32 *)num_events);
3042 }
3043
3044 static enum resource_id_enum
3045 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3046 {
3047         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3048
3049         switch (res_id) {
3050         case ECORE_SB:
3051                 mfw_res_id = RESOURCE_NUM_SB_E;
3052                 break;
3053         case ECORE_L2_QUEUE:
3054                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3055                 break;
3056         case ECORE_VPORT:
3057                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3058                 break;
3059         case ECORE_RSS_ENG:
3060                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3061                 break;
3062         case ECORE_PQ:
3063                 mfw_res_id = RESOURCE_NUM_PQ_E;
3064                 break;
3065         case ECORE_RL:
3066                 mfw_res_id = RESOURCE_NUM_RL_E;
3067                 break;
3068         case ECORE_MAC:
3069         case ECORE_VLAN:
3070                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3071                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3072                 break;
3073         case ECORE_ILT:
3074                 mfw_res_id = RESOURCE_ILT_E;
3075                 break;
3076         case ECORE_LL2_QUEUE:
3077                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3078                 break;
3079         case ECORE_RDMA_CNQ_RAM:
3080         case ECORE_CMDQS_CQS:
3081                 /* CNQ/CMDQS are the same resource */
3082                 mfw_res_id = RESOURCE_CQS_E;
3083                 break;
3084         case ECORE_RDMA_STATS_QUEUE:
3085                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3086                 break;
3087         case ECORE_BDQ:
3088                 mfw_res_id = RESOURCE_BDQ_E;
3089                 break;
3090         default:
3091                 break;
3092         }
3093
3094         return mfw_res_id;
3095 }
3096
3097 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3098 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3099 #define ECORE_RESC_ALLOC_VERSION                                \
3100         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3101           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3102          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3103           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3104
3105 struct ecore_resc_alloc_in_params {
3106         u32 cmd;
3107         enum ecore_resources res_id;
3108         u32 resc_max_val;
3109 };
3110
3111 struct ecore_resc_alloc_out_params {
3112         u32 mcp_resp;
3113         u32 mcp_param;
3114         u32 resc_num;
3115         u32 resc_start;
3116         u32 vf_resc_num;
3117         u32 vf_resc_start;
3118         u32 flags;
3119 };
3120
3121 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3122
3123 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3124 {
3125         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3126         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3127         enum _ecore_status_t rc;
3128
3129         /* Allow ongoing PCIe transactions to complete */
3130         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3131
3132         /* Clear the PF's internal FID_enable in the PXP */
3133         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3134         if (rc != ECORE_SUCCESS)
3135                 DP_NOTICE(p_hwfn, false,
3136                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3137                           rc);
3138
3139         return rc;
3140 }
3141
3142 static enum _ecore_status_t
3143 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3144                               struct ecore_ptt *p_ptt,
3145                               struct ecore_resc_alloc_in_params *p_in_params,
3146                               struct ecore_resc_alloc_out_params *p_out_params)
3147 {
3148         struct ecore_mcp_mb_params mb_params;
3149         struct resource_info mfw_resc_info;
3150         enum _ecore_status_t rc;
3151
3152         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3153
3154         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3155         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3156                 DP_ERR(p_hwfn,
3157                        "Failed to match resource %d [%s] with the MFW resources\n",
3158                        p_in_params->res_id,
3159                        ecore_hw_get_resc_name(p_in_params->res_id));
3160                 return ECORE_INVAL;
3161         }
3162
3163         switch (p_in_params->cmd) {
3164         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3165                 mfw_resc_info.size = p_in_params->resc_max_val;
3166                 /* Fallthrough */
3167         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3168                 break;
3169         default:
3170                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3171                        p_in_params->cmd);
3172                 return ECORE_INVAL;
3173         }
3174
3175         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3176         mb_params.cmd = p_in_params->cmd;
3177         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3178         mb_params.p_data_src = &mfw_resc_info;
3179         mb_params.data_src_size = sizeof(mfw_resc_info);
3180         mb_params.p_data_dst = mb_params.p_data_src;
3181         mb_params.data_dst_size = mb_params.data_src_size;
3182
3183         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3184                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3185                    p_in_params->cmd, p_in_params->res_id,
3186                    ecore_hw_get_resc_name(p_in_params->res_id),
3187                    GET_MFW_FIELD(mb_params.param,
3188                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3189                    GET_MFW_FIELD(mb_params.param,
3190                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3191                    p_in_params->resc_max_val);
3192
3193         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3194         if (rc != ECORE_SUCCESS)
3195                 return rc;
3196
3197         p_out_params->mcp_resp = mb_params.mcp_resp;
3198         p_out_params->mcp_param = mb_params.mcp_param;
3199         p_out_params->resc_num = mfw_resc_info.size;
3200         p_out_params->resc_start = mfw_resc_info.offset;
3201         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3202         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3203         p_out_params->flags = mfw_resc_info.flags;
3204
3205         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3206                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3207                    GET_MFW_FIELD(p_out_params->mcp_param,
3208                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3209                    GET_MFW_FIELD(p_out_params->mcp_param,
3210                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3211                    p_out_params->resc_num, p_out_params->resc_start,
3212                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3213                    p_out_params->flags);
3214
3215         return ECORE_SUCCESS;
3216 }
3217
3218 enum _ecore_status_t
3219 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3220                            enum ecore_resources res_id, u32 resc_max_val,
3221                            u32 *p_mcp_resp)
3222 {
3223         struct ecore_resc_alloc_out_params out_params;
3224         struct ecore_resc_alloc_in_params in_params;
3225         enum _ecore_status_t rc;
3226
3227         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3228         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3229         in_params.res_id = res_id;
3230         in_params.resc_max_val = resc_max_val;
3231         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3232         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3233                                            &out_params);
3234         if (rc != ECORE_SUCCESS)
3235                 return rc;
3236
3237         *p_mcp_resp = out_params.mcp_resp;
3238
3239         return ECORE_SUCCESS;
3240 }
3241
3242 enum _ecore_status_t
3243 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3244                         enum ecore_resources res_id, u32 *p_mcp_resp,
3245                         u32 *p_resc_num, u32 *p_resc_start)
3246 {
3247         struct ecore_resc_alloc_out_params out_params;
3248         struct ecore_resc_alloc_in_params in_params;
3249         enum _ecore_status_t rc;
3250
3251         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3252         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3253         in_params.res_id = res_id;
3254         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3255         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3256                                            &out_params);
3257         if (rc != ECORE_SUCCESS)
3258                 return rc;
3259
3260         *p_mcp_resp = out_params.mcp_resp;
3261
3262         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3263                 *p_resc_num = out_params.resc_num;
3264                 *p_resc_start = out_params.resc_start;
3265         }
3266
3267         return ECORE_SUCCESS;
3268 }
3269
3270 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3271                                                struct ecore_ptt *p_ptt)
3272 {
3273         u32 mcp_resp, mcp_param;
3274
3275         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3276                              &mcp_resp, &mcp_param);
3277 }
3278
3279 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3280                                                    struct ecore_ptt *p_ptt,
3281                                                    u32 param, u32 *p_mcp_resp,
3282                                                    u32 *p_mcp_param)
3283 {
3284         enum _ecore_status_t rc;
3285
3286         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3287                            p_mcp_resp, p_mcp_param);
3288         if (rc != ECORE_SUCCESS)
3289                 return rc;
3290
3291         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3292                 DP_INFO(p_hwfn,
3293                         "The resource command is unsupported by the MFW\n");
3294                 return ECORE_NOTIMPL;
3295         }
3296
3297         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3298                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3299
3300                 DP_NOTICE(p_hwfn, false,
3301                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3302                           param, opcode);
3303                 return ECORE_INVAL;
3304         }
3305
3306         return rc;
3307 }
3308
3309 enum _ecore_status_t
3310 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3311                       struct ecore_resc_lock_params *p_params)
3312 {
3313         u32 param = 0, mcp_resp, mcp_param;
3314         u8 opcode;
3315         enum _ecore_status_t rc;
3316
3317         switch (p_params->timeout) {
3318         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3319                 opcode = RESOURCE_OPCODE_REQ;
3320                 p_params->timeout = 0;
3321                 break;
3322         case ECORE_MCP_RESC_LOCK_TO_NONE:
3323                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3324                 p_params->timeout = 0;
3325                 break;
3326         default:
3327                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3328                 break;
3329         }
3330
3331         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3332         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3333         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3334
3335         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3336                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3337                    param, p_params->timeout, opcode, p_params->resource);
3338
3339         /* Attempt to acquire the resource */
3340         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3341                                     &mcp_param);
3342         if (rc != ECORE_SUCCESS)
3343                 return rc;
3344
3345         /* Analyze the response */
3346         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3347         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3348
3349         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3350                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3351                    mcp_param, opcode, p_params->owner);
3352
3353         switch (opcode) {
3354         case RESOURCE_OPCODE_GNT:
3355                 p_params->b_granted = true;
3356                 break;
3357         case RESOURCE_OPCODE_BUSY:
3358                 p_params->b_granted = false;
3359                 break;
3360         default:
3361                 DP_NOTICE(p_hwfn, false,
3362                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3363                           mcp_param, opcode);
3364                 return ECORE_INVAL;
3365         }
3366
3367         return ECORE_SUCCESS;
3368 }
3369
3370 enum _ecore_status_t
3371 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3372                     struct ecore_resc_lock_params *p_params)
3373 {
3374         u32 retry_cnt = 0;
3375         enum _ecore_status_t rc;
3376
3377         do {
3378                 /* No need for an interval before the first iteration */
3379                 if (retry_cnt) {
3380                         if (p_params->sleep_b4_retry) {
3381                                 u16 retry_interval_in_ms =
3382                                         DIV_ROUND_UP(p_params->retry_interval,
3383                                                      1000);
3384
3385                                 OSAL_MSLEEP(retry_interval_in_ms);
3386                         } else {
3387                                 OSAL_UDELAY(p_params->retry_interval);
3388                         }
3389                 }
3390
3391                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3392                 if (rc != ECORE_SUCCESS)
3393                         return rc;
3394
3395                 if (p_params->b_granted)
3396                         break;
3397         } while (retry_cnt++ < p_params->retry_num);
3398
3399         return ECORE_SUCCESS;
3400 }
3401
3402 void
3403 ecore_mcp_resc_lock_default_init(struct ecore_hwfn *p_hwfn,
3404                                  struct ecore_resc_lock_params *p_lock,
3405                                  struct ecore_resc_unlock_params *p_unlock,
3406                                  enum ecore_resc_lock resource,
3407                                  bool b_is_permanent)
3408 {
3409         if (p_lock != OSAL_NULL) {
3410                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3411
3412                 /* Permanent resources don't require aging, and there's no
3413                  * point in trying to acquire them more than once since it's
3414                  * unexpected another entity would release them.
3415                  */
3416                 if (b_is_permanent) {
3417                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3418                 } else {
3419                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3420                         p_lock->retry_interval =
3421                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3422                         p_lock->sleep_b4_retry = true;
3423                 }
3424
3425                 p_lock->resource = resource;
3426         }
3427
3428         if (p_unlock != OSAL_NULL) {
3429                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3430                 p_unlock->resource = resource;
3431         }
3432 }
3433
3434 enum _ecore_status_t
3435 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3436                       struct ecore_resc_unlock_params *p_params)
3437 {
3438         u32 param = 0, mcp_resp, mcp_param;
3439         u8 opcode;
3440         enum _ecore_status_t rc;
3441
3442         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3443                                    : RESOURCE_OPCODE_RELEASE;
3444         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3445         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3446
3447         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3448                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3449                    param, opcode, p_params->resource);
3450
3451         /* Attempt to release the resource */
3452         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3453                                     &mcp_param);
3454         if (rc != ECORE_SUCCESS)
3455                 return rc;
3456
3457         /* Analyze the response */
3458         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3459
3460         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3461                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3462                    mcp_param, opcode);
3463
3464         switch (opcode) {
3465         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3466                 DP_INFO(p_hwfn,
3467                         "Resource unlock request for an already released resource [%d]\n",
3468                         p_params->resource);
3469                 /* Fallthrough */
3470         case RESOURCE_OPCODE_RELEASED:
3471                 p_params->b_released = true;
3472                 break;
3473         case RESOURCE_OPCODE_WRONG_OWNER:
3474                 p_params->b_released = false;
3475                 break;
3476         default:
3477                 DP_NOTICE(p_hwfn, false,
3478                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3479                           mcp_param, opcode);
3480                 return ECORE_INVAL;
3481         }
3482
3483         return ECORE_SUCCESS;
3484 }
3485
3486 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3487 {
3488         return !!(p_hwfn->mcp_info->capabilities &
3489                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3490 }
3491
3492 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3493                                                 struct ecore_ptt *p_ptt)
3494 {
3495         u32 mcp_resp;
3496         enum _ecore_status_t rc;
3497
3498         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3499                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3500         if (rc == ECORE_SUCCESS)
3501                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3502                            "MFW supported features: %08x\n",
3503                            p_hwfn->mcp_info->capabilities);
3504
3505         return rc;
3506 }
3507
3508 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3509                                                 struct ecore_ptt *p_ptt)
3510 {
3511         u32 mcp_resp, mcp_param, features;
3512
3513         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3514                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3515
3516         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3517                              features, &mcp_resp, &mcp_param);
3518 }