2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
24 #define CHIP_MCP_RESP_ITER_US 10
25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 OFFSETOF(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 OFFSETOF(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_SHIFT)
48 #define MCP_BYTES_PER_MBIT_SHIFT 17
52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
57 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
64 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
66 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
68 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
70 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
71 "port_addr = 0x%x, port_id 0x%02x\n",
72 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
77 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
82 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
86 if (!p_hwfn->mcp_info->public_base)
89 for (i = 0; i < length; i++) {
90 tmp = ecore_rd(p_hwfn, p_ptt,
91 p_hwfn->mcp_info->mfw_mb_addr +
92 (i << 2) + sizeof(u32));
94 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
95 OSAL_BE32_TO_CPU(tmp);
99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
101 if (p_hwfn->mcp_info) {
102 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
103 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
104 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
106 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
108 return ECORE_SUCCESS;
111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt)
114 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
115 u32 drv_mb_offsize, mfw_mb_offsize;
116 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
119 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
120 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
121 p_info->public_base = 0;
126 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
127 if (!p_info->public_base)
130 p_info->public_base |= GRCBASE_MCP;
132 /* Calculate the driver and MFW mailbox address */
133 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
134 SECTION_OFFSIZE_ADDR(p_info->public_base,
136 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
138 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
139 " mcp_pf_id = 0x%x\n",
140 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
142 /* Set the MFW MB address */
143 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
144 SECTION_OFFSIZE_ADDR(p_info->public_base,
146 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
147 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
148 p_info->mfw_mb_addr);
150 /* Get the current driver mailbox sequence before sending
153 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
154 DRV_MSG_SEQ_NUMBER_MASK;
156 /* Get current FW pulse sequence */
157 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
160 p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
161 MISCS_REG_GENERIC_POR_0);
163 return ECORE_SUCCESS;
166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
167 struct ecore_ptt *p_ptt)
169 struct ecore_mcp_info *p_info;
172 /* Allocate mcp_info structure */
173 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
174 sizeof(*p_hwfn->mcp_info));
175 if (!p_hwfn->mcp_info)
177 p_info = p_hwfn->mcp_info;
179 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
180 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
181 /* Do not free mcp_info here, since public_base indicate that
182 * the MCP is not initialized
184 return ECORE_SUCCESS;
187 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
188 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
189 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
190 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
193 /* Initialize the MFW spinlock */
194 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
195 OSAL_SPIN_LOCK_INIT(&p_info->lock);
197 return ECORE_SUCCESS;
200 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
201 ecore_mcp_free(p_hwfn);
205 /* Locks the MFW mailbox of a PF to ensure a single access.
206 * The lock is achieved in most cases by holding a spinlock, causing other
207 * threads to wait till a previous access is done.
208 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
209 * access is achieved by setting a blocking flag, which will fail other
210 * competing contexts to send their mailboxes.
212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
215 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
217 /* The spinlock shouldn't be acquired when the mailbox command is
218 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
219 * pending [UN]LOAD_REQ command of another PF together with a spinlock
220 * (i.e. interrupts are disabled) - can lead to a deadlock.
221 * It is assumed that for a single PF, no other mailbox commands can be
222 * sent from another context while sending LOAD_REQ, and that any
223 * parallel commands to UNLOAD_REQ can be cancelled.
225 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
226 p_hwfn->mcp_info->block_mb_sending = false;
228 /* There's at least a single command that is sent by ecore during the
229 * load sequence [expectation of MFW].
231 if ((p_hwfn->mcp_info->block_mb_sending) &&
232 (cmd != DRV_MSG_CODE_FEATURE_SUPPORT)) {
233 DP_NOTICE(p_hwfn, false,
234 "Trying to send a MFW mailbox command [0x%x]"
235 " in parallel to [UN]LOAD_REQ. Aborting.\n",
237 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
241 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
242 p_hwfn->mcp_info->block_mb_sending = true;
243 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
246 return ECORE_SUCCESS;
249 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
251 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
252 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
255 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
256 struct ecore_ptt *p_ptt)
258 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
259 u32 delay = CHIP_MCP_RESP_ITER_US;
260 u32 org_mcp_reset_seq, cnt = 0;
261 enum _ecore_status_t rc = ECORE_SUCCESS;
264 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
265 delay = EMUL_MCP_RESP_ITER_US;
268 /* Ensure that only a single thread is accessing the mailbox at a
271 rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
272 if (rc != ECORE_SUCCESS)
275 /* Set drv command along with the updated sequence */
276 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
277 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
280 /* Wait for MFW response */
282 /* Give the FW up to 500 second (50*1000*10usec) */
283 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
284 MISCS_REG_GENERIC_POR_0)) &&
285 (cnt++ < ECORE_MCP_RESET_RETRIES));
287 if (org_mcp_reset_seq !=
288 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
289 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
290 "MCP was reset after %d usec\n", cnt * delay);
292 DP_ERR(p_hwfn, "Failed to reset MCP\n");
296 ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
301 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
302 struct ecore_ptt *p_ptt,
307 u32 delay = CHIP_MCP_RESP_ITER_US;
308 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
309 u32 seq, cnt = 1, actual_mb_seq;
310 enum _ecore_status_t rc = ECORE_SUCCESS;
313 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
314 delay = EMUL_MCP_RESP_ITER_US;
315 /* There is a built-in delay of 100usec in each MFW response read */
316 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
320 /* Get actual driver mailbox sequence */
321 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
322 DRV_MSG_SEQ_NUMBER_MASK;
324 /* Use MCP history register to check if MCP reset occurred between
327 if (p_hwfn->mcp_info->mcp_hist !=
328 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
329 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
330 ecore_load_mcp_offsets(p_hwfn, p_ptt);
331 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
333 seq = ++p_hwfn->mcp_info->drv_mb_seq;
336 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
338 /* Set drv command along with the updated sequence */
339 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
342 /* Wait for MFW response */
344 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
346 /* Give the FW up to 5 second (500*10ms) */
347 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
348 (cnt++ < max_retries));
350 /* Is this a reply to our command? */
351 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
352 *o_mcp_resp &= FW_MSG_CODE_MASK;
353 /* Get the MCP param */
354 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
357 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
361 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
366 static enum _ecore_status_t
367 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
368 struct ecore_ptt *p_ptt,
369 struct ecore_mcp_mb_params *p_mb_params)
371 union drv_union_data union_data;
373 enum _ecore_status_t rc;
375 /* MCP not initialized */
376 if (!ecore_mcp_is_init(p_hwfn)) {
377 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
381 if (p_mb_params->data_src_size > sizeof(union_data) ||
382 p_mb_params->data_dst_size > sizeof(union_data)) {
384 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
385 p_mb_params->data_src_size, p_mb_params->data_dst_size,
390 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
391 OFFSETOF(struct public_drv_mb, union_data);
393 /* Ensure that only a single thread is accessing the mailbox at a
396 rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
397 if (rc != ECORE_SUCCESS)
400 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
401 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
402 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
403 p_mb_params->data_src_size);
404 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
407 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
408 p_mb_params->param, &p_mb_params->mcp_resp,
409 &p_mb_params->mcp_param);
411 if (p_mb_params->p_data_dst != OSAL_NULL &&
412 p_mb_params->data_dst_size)
413 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
414 union_data_addr, p_mb_params->data_dst_size);
416 ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
421 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
422 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
423 u32 *o_mcp_resp, u32 *o_mcp_param)
425 struct ecore_mcp_mb_params mb_params;
426 enum _ecore_status_t rc;
429 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
430 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
432 loaded_port[p_hwfn->port_id]--;
433 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
436 return ECORE_SUCCESS;
440 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
442 mb_params.param = param;
443 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
444 if (rc != ECORE_SUCCESS)
447 *o_mcp_resp = mb_params.mcp_resp;
448 *o_mcp_param = mb_params.mcp_param;
450 return ECORE_SUCCESS;
453 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
454 struct ecore_ptt *p_ptt,
459 u32 i_txn_size, u32 *i_buf)
461 struct ecore_mcp_mb_params mb_params;
462 enum _ecore_status_t rc;
464 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
466 mb_params.param = param;
467 mb_params.p_data_src = i_buf;
468 mb_params.data_src_size = (u8)i_txn_size;
469 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
470 if (rc != ECORE_SUCCESS)
473 *o_mcp_resp = mb_params.mcp_resp;
474 *o_mcp_param = mb_params.mcp_param;
476 return ECORE_SUCCESS;
479 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
480 struct ecore_ptt *p_ptt,
485 u32 *o_txn_size, u32 *o_buf)
487 struct ecore_mcp_mb_params mb_params;
488 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
489 enum _ecore_status_t rc;
491 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
493 mb_params.param = param;
494 mb_params.p_data_dst = raw_data;
496 /* Use the maximal value since the actual one is part of the response */
497 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
499 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
500 if (rc != ECORE_SUCCESS)
503 *o_mcp_resp = mb_params.mcp_resp;
504 *o_mcp_param = mb_params.mcp_param;
506 *o_txn_size = *o_mcp_param;
508 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
510 return ECORE_SUCCESS;
514 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
517 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
520 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
521 else if (!loaded_port[p_hwfn->port_id])
522 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
524 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
526 /* On CMT, always tell that it's engine */
527 if (p_hwfn->p_dev->num_hwfns > 1)
528 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
530 *p_load_code = load_phase;
532 loaded_port[p_hwfn->port_id]++;
534 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
535 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
536 *p_load_code, loaded, p_hwfn->port_id,
537 loaded_port[p_hwfn->port_id]);
541 static bool ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role)
543 return (drv_role == DRV_ROLE_OS &&
544 exist_drv_role == DRV_ROLE_PREBOOT) ||
545 (drv_role == DRV_ROLE_KDUMP && exist_drv_role == DRV_ROLE_OS);
548 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
549 struct ecore_ptt *p_ptt)
551 u32 resp = 0, param = 0;
552 enum _ecore_status_t rc;
554 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
556 if (rc != ECORE_SUCCESS)
557 DP_NOTICE(p_hwfn, false,
558 "Failed to send cancel load request, rc = %d\n", rc);
563 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
564 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
565 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
566 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
567 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
568 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
569 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
571 static u32 ecore_get_config_bitmap(void)
573 u32 config_bitmap = 0x0;
575 #ifdef CONFIG_ECORE_L2
576 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
578 #ifdef CONFIG_ECORE_SRIOV
579 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
581 #ifdef CONFIG_ECORE_ROCE
582 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
584 #ifdef CONFIG_ECORE_IWARP
585 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
587 #ifdef CONFIG_ECORE_FCOE
588 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
590 #ifdef CONFIG_ECORE_ISCSI
591 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
593 #ifdef CONFIG_ECORE_LL2
594 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
597 return config_bitmap;
600 struct ecore_load_req_in_params {
602 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
603 #define ECORE_LOAD_REQ_HSI_VER_1 1
610 bool avoid_eng_reset;
613 struct ecore_load_req_out_params {
623 static enum _ecore_status_t
624 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
625 struct ecore_load_req_in_params *p_in_params,
626 struct ecore_load_req_out_params *p_out_params)
628 struct ecore_mcp_mb_params mb_params;
629 struct load_req_stc load_req;
630 struct load_rsp_stc load_rsp;
632 enum _ecore_status_t rc;
634 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
635 load_req.drv_ver_0 = p_in_params->drv_ver_0;
636 load_req.drv_ver_1 = p_in_params->drv_ver_1;
637 load_req.fw_ver = p_in_params->fw_ver;
638 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
639 p_in_params->drv_role);
640 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
641 p_in_params->timeout_val);
642 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
643 p_in_params->force_cmd);
644 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
645 p_in_params->avoid_eng_reset);
647 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
648 DRV_ID_MCP_HSI_VER_CURRENT :
649 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
651 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
652 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
653 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
654 mb_params.p_data_src = &load_req;
655 mb_params.data_src_size = sizeof(load_req);
656 mb_params.p_data_dst = &load_rsp;
657 mb_params.data_dst_size = sizeof(load_rsp);
659 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
660 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
662 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
663 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
664 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
665 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
667 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
668 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
669 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
670 load_req.drv_ver_0, load_req.drv_ver_1,
671 load_req.fw_ver, load_req.misc0,
672 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
673 ECORE_MFW_GET_FIELD(load_req.misc0,
675 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
676 ECORE_MFW_GET_FIELD(load_req.misc0,
679 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
680 if (rc != ECORE_SUCCESS) {
681 DP_NOTICE(p_hwfn, false,
682 "Failed to send load request, rc = %d\n", rc);
686 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
687 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
688 p_out_params->load_code = mb_params.mcp_resp;
690 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
691 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
692 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
693 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
694 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
695 load_rsp.fw_ver, load_rsp.misc0,
696 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
697 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
698 ECORE_MFW_GET_FIELD(load_rsp.misc0,
701 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
702 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
703 p_out_params->exist_fw_ver = load_rsp.fw_ver;
704 p_out_params->exist_drv_role =
705 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
706 p_out_params->mfw_hsi_ver =
707 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
708 p_out_params->drv_exists =
709 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
710 LOAD_RSP_FLAGS0_DRV_EXISTS;
713 return ECORE_SUCCESS;
716 static enum _ecore_status_t eocre_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
717 enum ecore_drv_role drv_role,
721 case ECORE_DRV_ROLE_OS:
722 *p_mfw_drv_role = DRV_ROLE_OS;
724 case ECORE_DRV_ROLE_KDUMP:
725 *p_mfw_drv_role = DRV_ROLE_KDUMP;
728 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
732 return ECORE_SUCCESS;
735 enum ecore_load_req_force {
736 ECORE_LOAD_REQ_FORCE_NONE,
737 ECORE_LOAD_REQ_FORCE_PF,
738 ECORE_LOAD_REQ_FORCE_ALL,
741 static enum _ecore_status_t
742 ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
743 enum ecore_load_req_force force_cmd,
747 case ECORE_LOAD_REQ_FORCE_NONE:
748 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
750 case ECORE_LOAD_REQ_FORCE_PF:
751 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
753 case ECORE_LOAD_REQ_FORCE_ALL:
754 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
757 DP_ERR(p_hwfn, "Unexpected force value %d\n", force_cmd);
761 return ECORE_SUCCESS;
764 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
765 struct ecore_ptt *p_ptt,
766 struct ecore_load_req_params *p_params)
768 struct ecore_load_req_out_params out_params;
769 struct ecore_load_req_in_params in_params;
770 u8 mfw_drv_role, mfw_force_cmd;
771 enum _ecore_status_t rc;
774 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
775 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
776 return ECORE_SUCCESS;
780 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
781 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
782 in_params.drv_ver_0 = ECORE_VERSION;
783 in_params.drv_ver_1 = ecore_get_config_bitmap();
784 in_params.fw_ver = STORM_FW_VERSION;
785 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
786 if (rc != ECORE_SUCCESS)
789 in_params.drv_role = mfw_drv_role;
790 in_params.timeout_val = p_params->timeout_val;
791 rc = ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
793 if (rc != ECORE_SUCCESS)
796 in_params.force_cmd = mfw_force_cmd;
797 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
799 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
800 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
801 if (rc != ECORE_SUCCESS)
804 /* First handle cases where another load request should/might be sent:
805 * - MFW expects the old interface [HSI version = 1]
806 * - MFW responds that a force load request is required
808 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
810 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
812 /* The previous load request set the mailbox blocking */
813 p_hwfn->mcp_info->block_mb_sending = false;
815 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
816 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
817 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
819 if (rc != ECORE_SUCCESS)
821 } else if (out_params.load_code ==
822 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
823 /* The previous load request set the mailbox blocking */
824 p_hwfn->mcp_info->block_mb_sending = false;
826 if (ecore_mcp_can_force_load(in_params.drv_role,
827 out_params.exist_drv_role)) {
829 "A force load is required [existing: role %d, fw_ver 0x%08x, drv_ver 0x%08x_0x%08x]. Sending a force load request.\n",
830 out_params.exist_drv_role,
831 out_params.exist_fw_ver,
832 out_params.exist_drv_ver_0,
833 out_params.exist_drv_ver_1);
835 rc = ecore_get_mfw_force_cmd(p_hwfn,
836 ECORE_LOAD_REQ_FORCE_ALL,
838 if (rc != ECORE_SUCCESS)
841 in_params.force_cmd = mfw_force_cmd;
842 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
843 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
845 if (rc != ECORE_SUCCESS)
848 DP_NOTICE(p_hwfn, false,
849 "A force load is required [existing: role %d, fw_ver 0x%08x, drv_ver 0x%08x_0x%08x]. Avoiding to prevent disruption of active PFs.\n",
850 out_params.exist_drv_role,
851 out_params.exist_fw_ver,
852 out_params.exist_drv_ver_0,
853 out_params.exist_drv_ver_1);
855 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
860 /* Now handle the other types of responses.
861 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
862 * expected here after the additional revised load requests were sent.
864 switch (out_params.load_code) {
865 case FW_MSG_CODE_DRV_LOAD_ENGINE:
866 case FW_MSG_CODE_DRV_LOAD_PORT:
867 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
868 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
869 out_params.drv_exists) {
870 /* The role and fw/driver version match, but the PF is
871 * already loaded and has not been unloaded gracefully.
872 * This is unexpected since a quasi-FLR request was
873 * previously sent as part of ecore_hw_prepare().
875 DP_NOTICE(p_hwfn, false,
876 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
880 case FW_MSG_CODE_DRV_LOAD_REFUSED_PDA:
881 case FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG:
882 case FW_MSG_CODE_DRV_LOAD_REFUSED_HSI:
883 case FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT:
884 DP_NOTICE(p_hwfn, false,
885 "MFW refused a load request [resp 0x%08x]. Aborting.\n",
886 out_params.load_code);
889 DP_NOTICE(p_hwfn, false,
890 "Unexpected response to load request [resp 0x%08x]. Aborting.\n",
891 out_params.load_code);
895 p_params->load_code = out_params.load_code;
897 return ECORE_SUCCESS;
900 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
901 struct ecore_ptt *p_ptt)
903 u32 resp = 0, param = 0;
904 enum _ecore_status_t rc;
906 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
908 if (rc != ECORE_SUCCESS) {
909 DP_NOTICE(p_hwfn, false,
910 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
914 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
916 /* Check if there is a DID mismatch between nvm-cfg/efuse */
917 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
918 DP_NOTICE(p_hwfn, false,
919 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
921 return ECORE_SUCCESS;
924 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
925 struct ecore_ptt *p_ptt)
927 u32 wol_param, mcp_resp, mcp_param;
930 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
932 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
933 &mcp_resp, &mcp_param);
936 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
937 struct ecore_ptt *p_ptt)
939 struct ecore_mcp_mb_params mb_params;
940 struct mcp_mac wol_mac;
942 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
943 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
945 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
948 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
949 struct ecore_ptt *p_ptt)
951 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
953 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
954 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
955 ECORE_PATH_ID(p_hwfn));
956 u32 disabled_vfs[VF_MAX_STATIC / 32];
959 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
960 "Reading Disabled VF information from [offset %08x],"
962 mfw_path_offsize, path_addr);
964 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
965 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
967 OFFSETOF(struct public_path,
970 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
971 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
972 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
975 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
976 OSAL_VF_FLR_UPDATE(p_hwfn);
979 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
980 struct ecore_ptt *p_ptt,
983 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
985 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
986 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
988 struct ecore_mcp_mb_params mb_params;
989 enum _ecore_status_t rc;
992 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
993 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
994 "Acking VFs [%08x,...,%08x] - %08x\n",
995 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
997 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
998 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
999 mb_params.p_data_src = vfs_to_ack;
1000 mb_params.data_src_size = VF_MAX_STATIC / 8;
1001 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1003 if (rc != ECORE_SUCCESS) {
1004 DP_NOTICE(p_hwfn, false,
1005 "Failed to pass ACK for VF flr to MFW\n");
1006 return ECORE_TIMEOUT;
1009 /* TMP - clear the ACK bits; should be done by MFW */
1010 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1011 ecore_wr(p_hwfn, p_ptt,
1013 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1014 i * sizeof(u32), 0);
1019 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1020 struct ecore_ptt *p_ptt)
1022 u32 transceiver_state;
1024 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1025 p_hwfn->mcp_info->port_addr +
1026 OFFSETOF(struct public_port,
1029 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1030 "Received transceiver state update [0x%08x] from mfw"
1032 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1033 OFFSETOF(struct public_port,
1034 transceiver_data)));
1036 transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
1038 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1039 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1041 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1044 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1045 struct ecore_ptt *p_ptt,
1048 struct ecore_mcp_link_state *p_link;
1052 p_link = &p_hwfn->mcp_info->link_output;
1053 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1055 status = ecore_rd(p_hwfn, p_ptt,
1056 p_hwfn->mcp_info->port_addr +
1057 OFFSETOF(struct public_port, link_status));
1058 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1059 "Received link update [0x%08x] from mfw"
1061 status, (u32)(p_hwfn->mcp_info->port_addr +
1062 OFFSETOF(struct public_port,
1065 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1066 "Resetting link indications\n");
1070 if (p_hwfn->b_drv_link_init)
1071 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1073 p_link->link_up = false;
1075 p_link->full_duplex = true;
1076 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1077 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1078 p_link->speed = 100000;
1080 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1081 p_link->speed = 50000;
1083 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1084 p_link->speed = 40000;
1086 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1087 p_link->speed = 25000;
1089 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1090 p_link->speed = 20000;
1092 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1093 p_link->speed = 10000;
1095 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1096 p_link->full_duplex = false;
1098 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1099 p_link->speed = 1000;
1105 /* We never store total line speed as p_link->speed is
1106 * again changes according to bandwidth allocation.
1108 if (p_link->link_up && p_link->speed)
1109 p_link->line_speed = p_link->speed;
1111 p_link->line_speed = 0;
1113 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1114 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1116 /* Max bandwidth configuration */
1117 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1120 /* Mintz bandwidth configuration */
1121 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1123 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1124 p_link->min_pf_rate);
1126 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1127 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1128 p_link->parallel_detection = !!(status &
1129 LINK_STATUS_PARALLEL_DETECTION_USED);
1130 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1132 p_link->partner_adv_speed |=
1133 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1134 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1135 p_link->partner_adv_speed |=
1136 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1137 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1138 p_link->partner_adv_speed |=
1139 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1140 ECORE_LINK_PARTNER_SPEED_10G : 0;
1141 p_link->partner_adv_speed |=
1142 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1143 ECORE_LINK_PARTNER_SPEED_20G : 0;
1144 p_link->partner_adv_speed |=
1145 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1146 ECORE_LINK_PARTNER_SPEED_25G : 0;
1147 p_link->partner_adv_speed |=
1148 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1149 ECORE_LINK_PARTNER_SPEED_40G : 0;
1150 p_link->partner_adv_speed |=
1151 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1152 ECORE_LINK_PARTNER_SPEED_50G : 0;
1153 p_link->partner_adv_speed |=
1154 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1155 ECORE_LINK_PARTNER_SPEED_100G : 0;
1157 p_link->partner_tx_flow_ctrl_en =
1158 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1159 p_link->partner_rx_flow_ctrl_en =
1160 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1162 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1163 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1164 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1166 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1167 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1169 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1170 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1173 p_link->partner_adv_pause = 0;
1176 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1178 OSAL_LINK_UPDATE(p_hwfn);
1181 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1182 struct ecore_ptt *p_ptt, bool b_up)
1184 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1185 struct ecore_mcp_mb_params mb_params;
1186 struct eth_phy_cfg phy_cfg;
1187 enum _ecore_status_t rc = ECORE_SUCCESS;
1191 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1192 return ECORE_SUCCESS;
1195 /* Set the shmem configuration according to params */
1196 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1197 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1198 if (!params->speed.autoneg)
1199 phy_cfg.speed = params->speed.forced_speed;
1200 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1201 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1202 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1203 phy_cfg.adv_speed = params->speed.advertised_speeds;
1204 phy_cfg.loopback_mode = params->loopback_mode;
1205 p_hwfn->b_drv_link_init = b_up;
1208 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1209 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1210 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1211 phy_cfg.loopback_mode);
1213 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1215 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1216 mb_params.cmd = cmd;
1217 mb_params.p_data_src = &phy_cfg;
1218 mb_params.data_src_size = sizeof(phy_cfg);
1219 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1221 /* if mcp fails to respond we must abort */
1222 if (rc != ECORE_SUCCESS) {
1223 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1227 /* Reset the link status if needed */
1229 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
1234 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1235 struct ecore_ptt *p_ptt)
1237 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1239 /* TODO - Add support for VFs */
1240 if (IS_VF(p_hwfn->p_dev))
1243 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1245 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1246 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1248 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1250 OFFSETOF(struct public_path, process_kill)) &
1251 PROCESS_KILL_COUNTER_MASK;
1253 return proc_kill_cnt;
1256 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1257 struct ecore_ptt *p_ptt)
1259 struct ecore_dev *p_dev = p_hwfn->p_dev;
1262 /* Prevent possible attentions/interrupts during the recovery handling
1263 * and till its load phase, during which they will be re-enabled.
1265 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1267 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1269 /* The following operations should be done once, and thus in CMT mode
1270 * are carried out by only the first HW function.
1272 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1275 if (p_dev->recov_in_prog) {
1276 DP_NOTICE(p_hwfn, false,
1277 "Ignoring the indication since a recovery"
1278 " process is already in progress\n");
1282 p_dev->recov_in_prog = true;
1284 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1285 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1287 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1290 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1291 struct ecore_ptt *p_ptt,
1292 enum MFW_DRV_MSG_TYPE type)
1294 enum ecore_mcp_protocol_type stats_type;
1295 union ecore_mcp_protocol_stats stats;
1296 struct ecore_mcp_mb_params mb_params;
1298 enum _ecore_status_t rc;
1301 case MFW_DRV_MSG_GET_LAN_STATS:
1302 stats_type = ECORE_MCP_LAN_STATS;
1303 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1306 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1310 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1312 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1313 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1314 mb_params.param = hsi_param;
1315 mb_params.p_data_src = &stats;
1316 mb_params.data_src_size = sizeof(stats);
1317 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1318 if (rc != ECORE_SUCCESS)
1319 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1322 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1323 struct public_func *p_shmem_info)
1325 struct ecore_mcp_function_info *p_info;
1327 p_info = &p_hwfn->mcp_info->func_info;
1329 /* TODO - bandwidth min/max should have valid values of 1-100,
1330 * as well as some indication that the feature is disabled.
1331 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1332 * limit and correct value to min `1' and max `100' if limit isn't in
1335 p_info->bandwidth_min = (p_shmem_info->config &
1336 FUNC_MF_CFG_MIN_BW_MASK) >>
1337 FUNC_MF_CFG_MIN_BW_SHIFT;
1338 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1340 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1341 p_info->bandwidth_min);
1342 p_info->bandwidth_min = 1;
1345 p_info->bandwidth_max = (p_shmem_info->config &
1346 FUNC_MF_CFG_MAX_BW_MASK) >>
1347 FUNC_MF_CFG_MAX_BW_SHIFT;
1348 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1350 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1351 p_info->bandwidth_max);
1352 p_info->bandwidth_max = 100;
1356 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1357 struct ecore_ptt *p_ptt,
1358 struct public_func *p_data,
1361 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1363 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1364 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1367 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1369 size = OSAL_MIN_T(u32, sizeof(*p_data),
1370 SECTION_SIZE(mfw_path_offsize));
1371 for (i = 0; i < size / sizeof(u32); i++)
1372 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1373 func_addr + (i << 2));
1379 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1381 struct ecore_mcp_function_info *p_info;
1382 struct public_func shmem_info;
1383 u32 resp = 0, param = 0;
1385 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1387 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1389 p_info = &p_hwfn->mcp_info->func_info;
1391 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1393 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1395 /* Acknowledge the MFW */
1396 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1400 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1401 struct ecore_ptt *p_ptt)
1403 /* A single notification should be sent to upper driver in CMT mode */
1404 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1407 DP_NOTICE(p_hwfn, false,
1408 "Fan failure was detected on the network interface card"
1409 " and it's going to be shut down.\n");
1411 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1414 struct ecore_mdump_cmd_params {
1423 static enum _ecore_status_t
1424 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1425 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1427 struct ecore_mcp_mb_params mb_params;
1428 enum _ecore_status_t rc;
1430 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1431 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1432 mb_params.param = p_mdump_cmd_params->cmd;
1433 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1434 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1435 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1436 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1437 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1438 if (rc != ECORE_SUCCESS)
1441 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1442 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1443 DP_NOTICE(p_hwfn, false,
1444 "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1445 p_mdump_cmd_params->cmd);
1452 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1453 struct ecore_ptt *p_ptt)
1455 struct ecore_mdump_cmd_params mdump_cmd_params;
1457 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1458 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1460 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1463 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1464 struct ecore_ptt *p_ptt,
1467 struct ecore_mdump_cmd_params mdump_cmd_params;
1469 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1470 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1471 mdump_cmd_params.p_data_src = &epoch;
1472 mdump_cmd_params.data_src_size = sizeof(epoch);
1474 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1477 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1478 struct ecore_ptt *p_ptt)
1480 struct ecore_mdump_cmd_params mdump_cmd_params;
1482 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1483 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1485 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1488 static enum _ecore_status_t
1489 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1490 struct mdump_config_stc *p_mdump_config)
1492 struct ecore_mdump_cmd_params mdump_cmd_params;
1493 enum _ecore_status_t rc;
1495 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1496 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1497 mdump_cmd_params.p_data_dst = p_mdump_config;
1498 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1500 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1501 if (rc != ECORE_SUCCESS)
1504 if (mdump_cmd_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1506 "The mdump command is not supported by the MFW\n");
1507 return ECORE_NOTIMPL;
1510 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1511 DP_NOTICE(p_hwfn, false,
1512 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1513 mdump_cmd_params.mcp_resp);
1514 rc = ECORE_UNKNOWN_ERROR;
1520 enum _ecore_status_t
1521 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1522 struct ecore_mdump_info *p_mdump_info)
1524 u32 addr, global_offsize, global_addr;
1525 struct mdump_config_stc mdump_config;
1526 enum _ecore_status_t rc;
1528 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1530 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1532 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1533 global_addr = SECTION_ADDR(global_offsize, 0);
1534 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1536 OFFSETOF(struct public_global,
1539 if (p_mdump_info->reason) {
1540 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1541 if (rc != ECORE_SUCCESS)
1544 p_mdump_info->version = mdump_config.version;
1545 p_mdump_info->config = mdump_config.config;
1546 p_mdump_info->epoch = mdump_config.epoc;
1547 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1548 p_mdump_info->valid_logs = mdump_config.valid_logs;
1550 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1551 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1552 p_mdump_info->reason, p_mdump_info->version,
1553 p_mdump_info->config, p_mdump_info->epoch,
1554 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1556 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1557 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1560 return ECORE_SUCCESS;
1563 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1564 struct ecore_ptt *p_ptt)
1566 struct ecore_mdump_cmd_params mdump_cmd_params;
1568 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1569 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1571 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1574 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1575 struct ecore_ptt *p_ptt)
1577 /* In CMT mode - no need for more than a single acknowledgment to the
1578 * MFW, and no more than a single notification to the upper driver.
1580 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1583 DP_NOTICE(p_hwfn, false,
1584 "Received a critical error notification from the MFW!\n");
1586 if (p_hwfn->p_dev->allow_mdump) {
1587 DP_NOTICE(p_hwfn, false,
1588 "Not acknowledging the notification to allow the MFW crash dump\n");
1592 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1593 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1596 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1597 struct ecore_ptt *p_ptt)
1599 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1600 enum _ecore_status_t rc = ECORE_SUCCESS;
1604 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1606 /* Read Messages from MFW */
1607 ecore_mcp_read_mb(p_hwfn, p_ptt);
1609 /* Compare current messages to old ones */
1610 for (i = 0; i < info->mfw_mb_length; i++) {
1611 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1616 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1617 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1618 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1621 case MFW_DRV_MSG_LINK_CHANGE:
1622 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1624 case MFW_DRV_MSG_VF_DISABLED:
1625 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1627 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1628 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1629 ECORE_DCBX_REMOTE_LLDP_MIB);
1631 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1632 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1633 ECORE_DCBX_REMOTE_MIB);
1635 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1636 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1637 ECORE_DCBX_OPERATIONAL_MIB);
1639 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1640 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1642 case MFW_DRV_MSG_ERROR_RECOVERY:
1643 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1645 case MFW_DRV_MSG_GET_LAN_STATS:
1646 case MFW_DRV_MSG_GET_FCOE_STATS:
1647 case MFW_DRV_MSG_GET_ISCSI_STATS:
1648 case MFW_DRV_MSG_GET_RDMA_STATS:
1649 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1651 case MFW_DRV_MSG_BW_UPDATE:
1652 ecore_mcp_update_bw(p_hwfn, p_ptt);
1654 case MFW_DRV_MSG_FAILURE_DETECTED:
1655 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1657 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1658 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1661 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1666 /* ACK everything */
1667 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1668 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1670 /* MFW expect answer in BE, so we force write in that format */
1671 ecore_wr(p_hwfn, p_ptt,
1672 info->mfw_mb_addr + sizeof(u32) +
1673 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1674 sizeof(u32) + i * sizeof(u32), val);
1678 DP_NOTICE(p_hwfn, false,
1679 "Received an MFW message indication but no"
1684 /* Copy the new mfw messages into the shadow */
1685 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1690 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1691 struct ecore_ptt *p_ptt,
1693 u32 *p_running_bundle_id)
1698 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1699 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1700 return ECORE_SUCCESS;
1704 if (IS_VF(p_hwfn->p_dev)) {
1705 if (p_hwfn->vf_iov_info) {
1706 struct pfvf_acquire_resp_tlv *p_resp;
1708 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1709 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1710 return ECORE_SUCCESS;
1712 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1713 "VF requested MFW version prior to ACQUIRE\n");
1718 global_offsize = ecore_rd(p_hwfn, p_ptt,
1719 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1723 ecore_rd(p_hwfn, p_ptt,
1724 SECTION_ADDR(global_offsize,
1725 0) + OFFSETOF(struct public_global, mfw_ver));
1727 if (p_running_bundle_id != OSAL_NULL) {
1728 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1729 SECTION_ADDR(global_offsize,
1731 OFFSETOF(struct public_global,
1732 running_bundle_id));
1735 return ECORE_SUCCESS;
1738 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1741 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1742 struct ecore_ptt *p_ptt;
1744 /* TODO - Add support for VFs */
1748 if (!ecore_mcp_is_init(p_hwfn)) {
1749 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1753 *p_media_type = MEDIA_UNSPECIFIED;
1755 p_ptt = ecore_ptt_acquire(p_hwfn);
1759 *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1760 OFFSETOF(struct public_port, media_type));
1762 ecore_ptt_release(p_hwfn, p_ptt);
1764 return ECORE_SUCCESS;
1768 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1770 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
1771 enum ecore_pci_personality *p_proto)
1773 *p_proto = ECORE_PCI_ETH;
1775 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1776 "According to Legacy capabilities, L2 personality is %08x\n",
1781 static enum _ecore_status_t
1782 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
1783 struct ecore_ptt *p_ptt,
1784 enum ecore_pci_personality *p_proto)
1786 u32 resp = 0, param = 0;
1787 enum _ecore_status_t rc;
1789 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1790 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1791 (u32)*p_proto, resp, param);
1792 return ECORE_SUCCESS;
1795 static enum _ecore_status_t
1796 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1797 struct public_func *p_info,
1798 struct ecore_ptt *p_ptt,
1799 enum ecore_pci_personality *p_proto)
1801 enum _ecore_status_t rc = ECORE_SUCCESS;
1803 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1804 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1805 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
1807 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1816 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1817 struct ecore_ptt *p_ptt)
1819 struct ecore_mcp_function_info *info;
1820 struct public_func shmem_info;
1822 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1823 info = &p_hwfn->mcp_info->func_info;
1825 info->pause_on_host = (shmem_info.config &
1826 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1828 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1830 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1831 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1835 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1837 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1838 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1839 info->mac[1] = (u8)(shmem_info.mac_upper);
1840 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1841 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1842 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1843 info->mac[5] = (u8)(shmem_info.mac_lower);
1845 /* TODO - are there protocols for which there's no MAC? */
1846 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1849 /* TODO - are these calculations true for BE machine? */
1850 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1851 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1852 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1853 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1855 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1857 info->mtu = (u16)shmem_info.mtu_size;
1862 info->mtu = (u16)shmem_info.mtu_size;
1864 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1865 "Read configuration from shmem: pause_on_host %02x"
1866 " protocol %02x BW [%02x - %02x]"
1867 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1868 " node %lx ovlan %04x\n",
1869 info->pause_on_host, info->protocol,
1870 info->bandwidth_min, info->bandwidth_max,
1871 info->mac[0], info->mac[1], info->mac[2],
1872 info->mac[3], info->mac[4], info->mac[5],
1873 (unsigned long)info->wwn_port,
1874 (unsigned long)info->wwn_node, info->ovlan);
1876 return ECORE_SUCCESS;
1879 struct ecore_mcp_link_params
1880 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1882 if (!p_hwfn || !p_hwfn->mcp_info)
1884 return &p_hwfn->mcp_info->link_input;
1887 struct ecore_mcp_link_state
1888 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1890 if (!p_hwfn || !p_hwfn->mcp_info)
1894 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1895 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1896 p_hwfn->mcp_info->link_output.link_up = true;
1900 return &p_hwfn->mcp_info->link_output;
1903 struct ecore_mcp_link_capabilities
1904 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1906 if (!p_hwfn || !p_hwfn->mcp_info)
1908 return &p_hwfn->mcp_info->link_capabilities;
1911 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1912 struct ecore_ptt *p_ptt)
1914 u32 resp = 0, param = 0;
1915 enum _ecore_status_t rc;
1917 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1918 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
1920 /* Wait for the drain to complete before returning */
1926 const struct ecore_mcp_function_info
1927 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1929 if (!p_hwfn || !p_hwfn->mcp_info)
1931 return &p_hwfn->mcp_info->func_info;
1934 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1935 struct ecore_ptt *p_ptt,
1936 struct ecore_mcp_nvm_params *params)
1938 enum _ecore_status_t rc;
1940 switch (params->type) {
1941 case ECORE_MCP_NVM_RD:
1942 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1943 params->nvm_common.offset,
1944 ¶ms->nvm_common.resp,
1945 ¶ms->nvm_common.param,
1946 params->nvm_rd.buf_size,
1947 params->nvm_rd.buf);
1950 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1951 params->nvm_common.offset,
1952 ¶ms->nvm_common.resp,
1953 ¶ms->nvm_common.param);
1955 case ECORE_MCP_NVM_WR:
1956 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1957 params->nvm_common.offset,
1958 ¶ms->nvm_common.resp,
1959 ¶ms->nvm_common.param,
1960 params->nvm_wr.buf_size,
1961 params->nvm_wr.buf);
1970 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1971 struct ecore_ptt *p_ptt, u32 personalities)
1973 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1974 struct public_func shmem_info;
1975 int i, count = 0, num_pfs;
1977 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1979 for (i = 0; i < num_pfs; i++) {
1980 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1981 MCP_PF_ID_BY_REL(p_hwfn, i));
1982 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1985 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1990 if ((1 << ((u32)protocol)) & personalities)
1997 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1998 struct ecore_ptt *p_ptt,
2004 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2005 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2010 if (IS_VF(p_hwfn->p_dev))
2013 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2014 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2015 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2016 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2018 *p_flash_size = flash_size;
2020 return ECORE_SUCCESS;
2023 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2024 struct ecore_ptt *p_ptt)
2026 struct ecore_dev *p_dev = p_hwfn->p_dev;
2028 if (p_dev->recov_in_prog) {
2029 DP_NOTICE(p_hwfn, false,
2030 "Avoid triggering a recovery since such a process"
2031 " is already in progress\n");
2035 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2036 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2038 return ECORE_SUCCESS;
2041 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2042 struct ecore_ptt *p_ptt,
2045 u32 resp = 0, param = 0, rc_param = 0;
2046 enum _ecore_status_t rc;
2048 /* Only Leader can configure MSIX, and need to take CMT into account */
2050 if (!IS_LEAD_HWFN(p_hwfn))
2051 return ECORE_SUCCESS;
2052 num *= p_hwfn->p_dev->num_hwfns;
2054 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2055 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2056 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2057 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2059 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2062 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2063 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2067 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2068 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2075 enum _ecore_status_t
2076 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2077 struct ecore_mcp_drv_version *p_ver)
2079 struct ecore_mcp_mb_params mb_params;
2080 struct drv_version_stc drv_version;
2084 enum _ecore_status_t rc;
2087 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2088 return ECORE_SUCCESS;
2091 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2092 drv_version.version = p_ver->version;
2093 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2094 for (i = 0; i < num_words; i++) {
2095 /* The driver name is expected to be in a big-endian format */
2096 p_name = &p_ver->name[i * sizeof(u32)];
2097 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2098 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2101 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2102 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2103 mb_params.p_data_src = &drv_version;
2104 mb_params.data_src_size = sizeof(drv_version);
2105 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2106 if (rc != ECORE_SUCCESS)
2107 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2112 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2113 struct ecore_ptt *p_ptt)
2115 enum _ecore_status_t rc;
2116 u32 resp = 0, param = 0;
2118 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2120 if (rc != ECORE_SUCCESS)
2121 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2126 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2127 struct ecore_ptt *p_ptt)
2129 u32 value, cpu_mode;
2131 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2133 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2134 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2135 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2136 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2138 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2141 enum _ecore_status_t
2142 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2143 struct ecore_ptt *p_ptt,
2144 enum ecore_ov_client client)
2146 enum _ecore_status_t rc;
2147 u32 resp = 0, param = 0;
2151 case ECORE_OV_CLIENT_DRV:
2152 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2154 case ECORE_OV_CLIENT_USER:
2155 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2157 case ECORE_OV_CLIENT_VENDOR_SPEC:
2158 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2161 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2165 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2166 drv_mb_param, &resp, ¶m);
2167 if (rc != ECORE_SUCCESS)
2168 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2173 enum _ecore_status_t
2174 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2175 struct ecore_ptt *p_ptt,
2176 enum ecore_ov_driver_state drv_state)
2178 enum _ecore_status_t rc;
2179 u32 resp = 0, param = 0;
2182 switch (drv_state) {
2183 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2184 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2186 case ECORE_OV_DRIVER_STATE_DISABLED:
2187 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2189 case ECORE_OV_DRIVER_STATE_ACTIVE:
2190 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2193 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2197 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2198 drv_mb_param, &resp, ¶m);
2199 if (rc != ECORE_SUCCESS)
2200 DP_ERR(p_hwfn, "Failed to send driver state\n");
2205 enum _ecore_status_t
2206 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2207 struct ecore_fc_npiv_tbl *p_table)
2212 enum _ecore_status_t
2213 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2214 struct ecore_ptt *p_ptt, u16 mtu)
2219 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2220 struct ecore_ptt *p_ptt,
2221 enum ecore_led_mode mode)
2223 u32 resp = 0, param = 0, drv_mb_param;
2224 enum _ecore_status_t rc;
2227 case ECORE_LED_MODE_ON:
2228 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2230 case ECORE_LED_MODE_OFF:
2231 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2233 case ECORE_LED_MODE_RESTORE:
2234 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2237 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2241 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2242 drv_mb_param, &resp, ¶m);
2243 if (rc != ECORE_SUCCESS)
2244 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2249 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2250 struct ecore_ptt *p_ptt,
2253 enum _ecore_status_t rc;
2254 u32 resp = 0, param = 0;
2256 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2257 mask_parities, &resp, ¶m);
2259 if (rc != ECORE_SUCCESS) {
2261 "MCP response failure for mask parities, aborting\n");
2262 } else if (resp != FW_MSG_CODE_OK) {
2264 "MCP did not ack mask parity request. Old MFW?\n");
2271 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2274 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2275 u32 bytes_left, offset, bytes_to_copy, buf_size;
2276 struct ecore_mcp_nvm_params params;
2277 struct ecore_ptt *p_ptt;
2278 enum _ecore_status_t rc = ECORE_SUCCESS;
2280 p_ptt = ecore_ptt_acquire(p_hwfn);
2284 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2287 params.type = ECORE_MCP_NVM_RD;
2288 params.nvm_rd.buf_size = &buf_size;
2289 params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
2290 while (bytes_left > 0) {
2291 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2292 MCP_DRV_NVM_BUF_LEN);
2293 params.nvm_common.offset = (addr + offset) |
2294 (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
2295 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2296 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2297 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
2298 FW_MSG_CODE_NVM_OK)) {
2299 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2303 /* This can be a lengthy process, and it's possible scheduler
2304 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2306 if (bytes_left % 0x1000 <
2307 (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
2310 offset += *params.nvm_rd.buf_size;
2311 bytes_left -= *params.nvm_rd.buf_size;
2314 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2315 ecore_ptt_release(p_hwfn, p_ptt);
2320 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2321 u32 addr, u8 *p_buf, u32 len)
2323 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2324 struct ecore_mcp_nvm_params params;
2325 struct ecore_ptt *p_ptt;
2326 enum _ecore_status_t rc;
2328 p_ptt = ecore_ptt_acquire(p_hwfn);
2332 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2333 params.type = ECORE_MCP_NVM_RD;
2334 params.nvm_rd.buf_size = &len;
2335 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
2336 DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
2337 params.nvm_common.offset = addr;
2338 params.nvm_rd.buf = (u32 *)p_buf;
2339 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2340 if (rc != ECORE_SUCCESS)
2341 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2343 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2344 ecore_ptt_release(p_hwfn, p_ptt);
2349 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2351 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2352 struct ecore_mcp_nvm_params params;
2353 struct ecore_ptt *p_ptt;
2355 p_ptt = ecore_ptt_acquire(p_hwfn);
2359 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2360 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2361 ecore_ptt_release(p_hwfn, p_ptt);
2363 return ECORE_SUCCESS;
2366 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2368 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2369 struct ecore_mcp_nvm_params params;
2370 struct ecore_ptt *p_ptt;
2371 enum _ecore_status_t rc;
2373 p_ptt = ecore_ptt_acquire(p_hwfn);
2376 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2377 params.type = ECORE_MCP_CMD;
2378 params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
2379 params.nvm_common.offset = addr;
2380 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2381 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2382 ecore_ptt_release(p_hwfn, p_ptt);
2387 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2390 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2391 struct ecore_mcp_nvm_params params;
2392 struct ecore_ptt *p_ptt;
2393 enum _ecore_status_t rc;
2395 p_ptt = ecore_ptt_acquire(p_hwfn);
2398 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2399 params.type = ECORE_MCP_CMD;
2400 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
2401 params.nvm_common.offset = addr;
2402 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2403 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2404 ecore_ptt_release(p_hwfn, p_ptt);
2409 /* rc receives ECORE_INVAL as default parameter because
2410 * it might not enter the while loop if the len is 0
2412 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2413 u32 addr, u8 *p_buf, u32 len)
2415 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2416 enum _ecore_status_t rc = ECORE_INVAL;
2417 struct ecore_mcp_nvm_params params;
2418 struct ecore_ptt *p_ptt;
2419 u32 buf_idx, buf_size;
2421 p_ptt = ecore_ptt_acquire(p_hwfn);
2425 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2426 params.type = ECORE_MCP_NVM_WR;
2427 if (cmd == ECORE_PUT_FILE_DATA)
2428 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2430 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2432 while (buf_idx < len) {
2433 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2434 MCP_DRV_NVM_BUF_LEN);
2435 params.nvm_common.offset = ((buf_size <<
2436 DRV_MB_PARAM_NVM_LEN_SHIFT)
2438 params.nvm_wr.buf_size = buf_size;
2439 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2440 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2441 if (rc != ECORE_SUCCESS ||
2442 ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2443 (params.nvm_common.resp !=
2444 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2445 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2447 /* This can be a lengthy process, and it's possible scheduler
2448 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2450 if (buf_idx % 0x1000 >
2451 (buf_idx + buf_size) % 0x1000)
2454 buf_idx += buf_size;
2457 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2458 ecore_ptt_release(p_hwfn, p_ptt);
2463 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2464 u32 addr, u8 *p_buf, u32 len)
2466 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2467 struct ecore_mcp_nvm_params params;
2468 struct ecore_ptt *p_ptt;
2469 enum _ecore_status_t rc;
2471 p_ptt = ecore_ptt_acquire(p_hwfn);
2475 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2476 params.type = ECORE_MCP_NVM_WR;
2477 params.nvm_wr.buf_size = len;
2478 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2479 DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2480 params.nvm_common.offset = addr;
2481 params.nvm_wr.buf = (u32 *)p_buf;
2482 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2483 if (rc != ECORE_SUCCESS)
2484 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2485 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2486 ecore_ptt_release(p_hwfn, p_ptt);
2491 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2494 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2495 struct ecore_mcp_nvm_params params;
2496 struct ecore_ptt *p_ptt;
2497 enum _ecore_status_t rc;
2499 p_ptt = ecore_ptt_acquire(p_hwfn);
2503 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2504 params.type = ECORE_MCP_CMD;
2505 params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2506 params.nvm_common.offset = addr;
2507 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2508 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2509 ecore_ptt_release(p_hwfn, p_ptt);
2514 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2515 struct ecore_ptt *p_ptt,
2516 u32 port, u32 addr, u32 offset,
2519 struct ecore_mcp_nvm_params params;
2520 enum _ecore_status_t rc;
2521 u32 bytes_left, bytes_to_copy, buf_size;
2523 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2524 params.nvm_common.offset =
2525 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2526 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2530 params.type = ECORE_MCP_NVM_RD;
2531 params.nvm_rd.buf_size = &buf_size;
2532 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2533 while (bytes_left > 0) {
2534 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2535 MAX_I2C_TRANSACTION_SIZE);
2536 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2537 params.nvm_common.offset &=
2538 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2539 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2540 params.nvm_common.offset |=
2542 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2543 params.nvm_common.offset |=
2544 (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2545 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2546 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2547 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2549 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2550 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2551 return ECORE_UNKNOWN_ERROR;
2553 offset += *params.nvm_rd.buf_size;
2554 bytes_left -= *params.nvm_rd.buf_size;
2557 return ECORE_SUCCESS;
2560 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2561 struct ecore_ptt *p_ptt,
2562 u32 port, u32 addr, u32 offset,
2565 struct ecore_mcp_nvm_params params;
2566 enum _ecore_status_t rc;
2567 u32 buf_idx, buf_size;
2569 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2570 params.nvm_common.offset =
2571 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2572 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2573 params.type = ECORE_MCP_NVM_WR;
2574 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2576 while (buf_idx < len) {
2577 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2578 MAX_I2C_TRANSACTION_SIZE);
2579 params.nvm_common.offset &=
2580 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2581 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2582 params.nvm_common.offset |=
2583 ((offset + buf_idx) <<
2584 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2585 params.nvm_common.offset |=
2586 (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2587 params.nvm_wr.buf_size = buf_size;
2588 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2589 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2590 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2591 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2593 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2594 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2595 return ECORE_UNKNOWN_ERROR;
2597 buf_idx += buf_size;
2600 return ECORE_SUCCESS;
2603 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2604 struct ecore_ptt *p_ptt,
2605 u16 gpio, u32 *gpio_val)
2607 enum _ecore_status_t rc = ECORE_SUCCESS;
2608 u32 drv_mb_param = 0, rsp;
2610 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2612 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2613 drv_mb_param, &rsp, gpio_val);
2615 if (rc != ECORE_SUCCESS)
2618 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2619 return ECORE_UNKNOWN_ERROR;
2621 return ECORE_SUCCESS;
2624 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2625 struct ecore_ptt *p_ptt,
2626 u16 gpio, u16 gpio_val)
2628 enum _ecore_status_t rc = ECORE_SUCCESS;
2629 u32 drv_mb_param = 0, param, rsp;
2631 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2632 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2634 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2635 drv_mb_param, &rsp, ¶m);
2637 if (rc != ECORE_SUCCESS)
2640 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2641 return ECORE_UNKNOWN_ERROR;
2643 return ECORE_SUCCESS;
2646 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2647 struct ecore_ptt *p_ptt,
2648 u16 gpio, u32 *gpio_direction,
2651 u32 drv_mb_param = 0, rsp, val = 0;
2652 enum _ecore_status_t rc = ECORE_SUCCESS;
2654 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2656 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2657 drv_mb_param, &rsp, &val);
2658 if (rc != ECORE_SUCCESS)
2661 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2662 DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2663 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2664 DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2666 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2667 return ECORE_UNKNOWN_ERROR;
2669 return ECORE_SUCCESS;
2672 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2673 struct ecore_ptt *p_ptt)
2675 u32 drv_mb_param = 0, rsp, param;
2676 enum _ecore_status_t rc = ECORE_SUCCESS;
2678 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2679 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2681 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2682 drv_mb_param, &rsp, ¶m);
2684 if (rc != ECORE_SUCCESS)
2687 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2688 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2689 rc = ECORE_UNKNOWN_ERROR;
2694 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2695 struct ecore_ptt *p_ptt)
2697 u32 drv_mb_param, rsp, param;
2698 enum _ecore_status_t rc = ECORE_SUCCESS;
2700 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2701 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2703 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2704 drv_mb_param, &rsp, ¶m);
2706 if (rc != ECORE_SUCCESS)
2709 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2710 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2711 rc = ECORE_UNKNOWN_ERROR;
2716 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2717 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2719 u32 drv_mb_param = 0, rsp;
2720 enum _ecore_status_t rc = ECORE_SUCCESS;
2722 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2723 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2725 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2726 drv_mb_param, &rsp, num_images);
2728 if (rc != ECORE_SUCCESS)
2731 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2732 rc = ECORE_UNKNOWN_ERROR;
2737 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2738 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2739 struct bist_nvm_image_att *p_image_att, u32 image_index)
2741 struct ecore_mcp_nvm_params params;
2742 enum _ecore_status_t rc;
2745 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2746 params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2747 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2748 params.nvm_common.offset |= (image_index <<
2749 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2751 params.type = ECORE_MCP_NVM_RD;
2752 params.nvm_rd.buf_size = &buf_size;
2753 params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2754 params.nvm_rd.buf = (u32 *)p_image_att;
2756 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2757 if (rc != ECORE_SUCCESS)
2760 if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2761 (p_image_att->return_code != 1))
2762 rc = ECORE_UNKNOWN_ERROR;
2767 enum _ecore_status_t
2768 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2769 struct ecore_ptt *p_ptt,
2770 struct ecore_temperature_info *p_temp_info)
2772 struct ecore_temperature_sensor *p_temp_sensor;
2773 struct temperature_status_stc mfw_temp_info;
2774 struct ecore_mcp_mb_params mb_params;
2776 enum _ecore_status_t rc;
2779 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2780 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2781 mb_params.p_data_dst = &mfw_temp_info;
2782 mb_params.data_dst_size = sizeof(mfw_temp_info);
2783 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2784 if (rc != ECORE_SUCCESS)
2787 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2788 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2789 ECORE_MAX_NUM_OF_SENSORS);
2790 for (i = 0; i < p_temp_info->num_sensors; i++) {
2791 val = mfw_temp_info.sensor[i];
2792 p_temp_sensor = &p_temp_info->sensors[i];
2793 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2794 SENSOR_LOCATION_SHIFT;
2795 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2796 THRESHOLD_HIGH_SHIFT;
2797 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2798 CRITICAL_TEMPERATURE_SHIFT;
2799 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2803 return ECORE_SUCCESS;
2806 enum _ecore_status_t ecore_mcp_get_mba_versions(
2807 struct ecore_hwfn *p_hwfn,
2808 struct ecore_ptt *p_ptt,
2809 struct ecore_mba_vers *p_mba_vers)
2811 struct ecore_mcp_nvm_params params;
2812 enum _ecore_status_t rc;
2815 OSAL_MEM_ZERO(¶ms, sizeof(params));
2816 params.type = ECORE_MCP_NVM_RD;
2817 params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2818 params.nvm_common.offset = 0;
2819 params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2820 params.nvm_rd.buf_size = &buf_size;
2821 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2823 if (rc != ECORE_SUCCESS)
2826 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2828 rc = ECORE_UNKNOWN_ERROR;
2830 if (buf_size != MCP_DRV_NVM_BUF_LEN)
2831 rc = ECORE_UNKNOWN_ERROR;
2836 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2837 struct ecore_ptt *p_ptt,
2842 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2843 0, &rsp, (u32 *)num_events);
2846 static enum resource_id_enum
2847 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
2849 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2853 mfw_res_id = RESOURCE_NUM_SB_E;
2855 case ECORE_L2_QUEUE:
2856 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2859 mfw_res_id = RESOURCE_NUM_VPORT_E;
2862 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2865 mfw_res_id = RESOURCE_NUM_PQ_E;
2868 mfw_res_id = RESOURCE_NUM_RL_E;
2872 /* Each VFC resource can accommodate both a MAC and a VLAN */
2873 mfw_res_id = RESOURCE_VFC_FILTER_E;
2876 mfw_res_id = RESOURCE_ILT_E;
2878 case ECORE_LL2_QUEUE:
2879 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2881 case ECORE_RDMA_CNQ_RAM:
2882 case ECORE_CMDQS_CQS:
2883 /* CNQ/CMDQS are the same resource */
2884 mfw_res_id = RESOURCE_CQS_E;
2886 case ECORE_RDMA_STATS_QUEUE:
2887 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2890 mfw_res_id = RESOURCE_BDQ_E;
2899 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
2900 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
2901 #define ECORE_RESC_ALLOC_VERSION \
2902 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
2903 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2904 (ECORE_RESC_ALLOC_VERSION_MINOR << \
2905 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2907 struct ecore_resc_alloc_in_params {
2909 enum ecore_resources res_id;
2913 struct ecore_resc_alloc_out_params {
2923 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
2925 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
2927 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2928 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2929 enum _ecore_status_t rc;
2931 /* Allow ongoing PCIe transactions to complete */
2932 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
2934 /* Clear the PF's internal FID_enable in the PXP */
2935 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2936 if (rc != ECORE_SUCCESS)
2937 DP_NOTICE(p_hwfn, false,
2938 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2944 static enum _ecore_status_t
2945 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
2946 struct ecore_ptt *p_ptt,
2947 struct ecore_resc_alloc_in_params *p_in_params,
2948 struct ecore_resc_alloc_out_params *p_out_params)
2950 struct ecore_mcp_mb_params mb_params;
2951 struct resource_info mfw_resc_info;
2952 enum _ecore_status_t rc;
2954 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
2956 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
2957 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2959 "Failed to match resource %d [%s] with the MFW resources\n",
2960 p_in_params->res_id,
2961 ecore_hw_get_resc_name(p_in_params->res_id));
2965 switch (p_in_params->cmd) {
2966 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2967 mfw_resc_info.size = p_in_params->resc_max_val;
2969 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2972 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2977 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2978 mb_params.cmd = p_in_params->cmd;
2979 mb_params.param = ECORE_RESC_ALLOC_VERSION;
2980 mb_params.p_data_src = &mfw_resc_info;
2981 mb_params.data_src_size = sizeof(mfw_resc_info);
2982 mb_params.p_data_dst = mb_params.p_data_src;
2983 mb_params.data_dst_size = mb_params.data_src_size;
2985 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2986 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2987 p_in_params->cmd, p_in_params->res_id,
2988 ecore_hw_get_resc_name(p_in_params->res_id),
2989 ECORE_MFW_GET_FIELD(mb_params.param,
2990 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2991 ECORE_MFW_GET_FIELD(mb_params.param,
2992 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2993 p_in_params->resc_max_val);
2995 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2996 if (rc != ECORE_SUCCESS)
2999 p_out_params->mcp_resp = mb_params.mcp_resp;
3000 p_out_params->mcp_param = mb_params.mcp_param;
3001 p_out_params->resc_num = mfw_resc_info.size;
3002 p_out_params->resc_start = mfw_resc_info.offset;
3003 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3004 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3005 p_out_params->flags = mfw_resc_info.flags;
3007 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3008 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3009 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3010 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3011 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3012 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3013 p_out_params->resc_num, p_out_params->resc_start,
3014 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3015 p_out_params->flags);
3017 return ECORE_SUCCESS;
3020 enum _ecore_status_t
3021 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3022 enum ecore_resources res_id, u32 resc_max_val,
3025 struct ecore_resc_alloc_out_params out_params;
3026 struct ecore_resc_alloc_in_params in_params;
3027 enum _ecore_status_t rc;
3029 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3030 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3031 in_params.res_id = res_id;
3032 in_params.resc_max_val = resc_max_val;
3033 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3034 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3036 if (rc != ECORE_SUCCESS)
3039 *p_mcp_resp = out_params.mcp_resp;
3041 return ECORE_SUCCESS;
3044 enum _ecore_status_t
3045 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3046 enum ecore_resources res_id, u32 *p_mcp_resp,
3047 u32 *p_resc_num, u32 *p_resc_start)
3049 struct ecore_resc_alloc_out_params out_params;
3050 struct ecore_resc_alloc_in_params in_params;
3051 enum _ecore_status_t rc;
3053 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3054 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3055 in_params.res_id = res_id;
3056 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3057 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3059 if (rc != ECORE_SUCCESS)
3062 *p_mcp_resp = out_params.mcp_resp;
3064 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3065 *p_resc_num = out_params.resc_num;
3066 *p_resc_start = out_params.resc_start;
3069 return ECORE_SUCCESS;
3072 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3073 struct ecore_ptt *p_ptt)
3075 u32 mcp_resp, mcp_param;
3077 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3078 &mcp_resp, &mcp_param);
3081 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3082 struct ecore_ptt *p_ptt,
3083 u32 param, u32 *p_mcp_resp,
3086 enum _ecore_status_t rc;
3088 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3089 p_mcp_resp, p_mcp_param);
3090 if (rc != ECORE_SUCCESS)
3093 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3095 "The resource command is unsupported by the MFW\n");
3096 return ECORE_NOTIMPL;
3099 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3100 u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3102 DP_NOTICE(p_hwfn, false,
3103 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3111 enum _ecore_status_t
3112 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3113 struct ecore_resc_lock_params *p_params)
3115 u32 param = 0, mcp_resp, mcp_param;
3117 enum _ecore_status_t rc;
3119 switch (p_params->timeout) {
3120 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3121 opcode = RESOURCE_OPCODE_REQ;
3122 p_params->timeout = 0;
3124 case ECORE_MCP_RESC_LOCK_TO_NONE:
3125 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3126 p_params->timeout = 0;
3129 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3133 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3134 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3135 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3138 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3139 param, p_params->timeout, opcode, p_params->resource);
3141 /* Attempt to acquire the resource */
3142 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3144 if (rc != ECORE_SUCCESS)
3147 /* Analyze the response */
3148 p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
3149 RESOURCE_CMD_RSP_OWNER);
3150 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3152 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3153 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3154 mcp_param, opcode, p_params->owner);
3157 case RESOURCE_OPCODE_GNT:
3158 p_params->b_granted = true;
3160 case RESOURCE_OPCODE_BUSY:
3161 p_params->b_granted = false;
3164 DP_NOTICE(p_hwfn, false,
3165 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3170 return ECORE_SUCCESS;
3173 enum _ecore_status_t
3174 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3175 struct ecore_resc_lock_params *p_params)
3178 enum _ecore_status_t rc;
3181 /* No need for an interval before the first iteration */
3183 if (p_params->sleep_b4_retry) {
3184 u16 retry_interval_in_ms =
3185 DIV_ROUND_UP(p_params->retry_interval,
3188 OSAL_MSLEEP(retry_interval_in_ms);
3190 OSAL_UDELAY(p_params->retry_interval);
3194 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3195 if (rc != ECORE_SUCCESS)
3198 if (p_params->b_granted)
3200 } while (retry_cnt++ < p_params->retry_num);
3202 return ECORE_SUCCESS;
3205 enum _ecore_status_t
3206 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3207 struct ecore_resc_unlock_params *p_params)
3209 u32 param = 0, mcp_resp, mcp_param;
3211 enum _ecore_status_t rc;
3213 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3214 : RESOURCE_OPCODE_RELEASE;
3215 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3216 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3218 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3219 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3220 param, opcode, p_params->resource);
3222 /* Attempt to release the resource */
3223 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3225 if (rc != ECORE_SUCCESS)
3228 /* Analyze the response */
3229 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3231 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3232 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3236 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3238 "Resource unlock request for an already released resource [%d]\n",
3239 p_params->resource);
3241 case RESOURCE_OPCODE_RELEASED:
3242 p_params->b_released = true;
3244 case RESOURCE_OPCODE_WRONG_OWNER:
3245 p_params->b_released = false;
3248 DP_NOTICE(p_hwfn, false,
3249 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3254 return ECORE_SUCCESS;
3257 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3259 return !!(p_hwfn->mcp_info->capabilities &
3260 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3263 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3264 struct ecore_ptt *p_ptt)
3267 enum _ecore_status_t rc;
3269 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3270 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3271 if (rc == ECORE_SUCCESS)
3272 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3273 "MFW supported features: %08x\n",
3274 p_hwfn->mcp_info->capabilities);
3279 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3280 struct ecore_ptt *p_ptt)
3282 u32 mcp_resp, mcp_param, features;
3284 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ;
3286 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3287 features, &mcp_resp, &mcp_param);