drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 100 {
 101         if (p_hwfn->mcp_info) {
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 103                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 104                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 105         }
 106         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 107         p_hwfn->mcp_info = OSAL_NULL;
 108
 109         return ECORE_SUCCESS;
 110 }
 111
 112 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 113                                                    struct ecore_ptt *p_ptt)
 114 {
 115         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 116         u32 drv_mb_offsize, mfw_mb_offsize;
 117         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 118
 119 #ifndef ASIC_ONLY
 120         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 121                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 122                 p_info->public_base = 0;
 123                 return ECORE_INVAL;
 124         }
 125 #endif
 126
 127         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 128         if (!p_info->public_base)
 129                 return ECORE_INVAL;
 130
 131         p_info->public_base |= GRCBASE_MCP;
 132
 133         /* Calculate the driver and MFW mailbox address */
 134         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 135                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 136                                                        PUBLIC_DRV_MB));
 137         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 138         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 139                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 140                    " mcp_pf_id = 0x%x\n",
 141                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 142
 143         /* Set the MFW MB address */
 144         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 145                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 146                                                        PUBLIC_MFW_MB));
 147         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 148         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 149                                                p_info->mfw_mb_addr);
 150
 151         /* Get the current driver mailbox sequence before sending
 152          * the first command
 153          */
 154         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 155             DRV_MSG_SEQ_NUMBER_MASK;
 156
 157         /* Get current FW pulse sequence */
 158         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 159             DRV_PULSE_SEQ_MASK;
 160
 161         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 162                                           MISCS_REG_GENERIC_POR_0);
 163
 164         return ECORE_SUCCESS;
 165 }
 166
 167 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 168                                         struct ecore_ptt *p_ptt)
 169 {
 170         struct ecore_mcp_info *p_info;
 171         u32 size;
 172
 173         /* Allocate mcp_info structure */
 174         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 175                                        sizeof(*p_hwfn->mcp_info));
 176         if (!p_hwfn->mcp_info)
 177                 goto err;
 178         p_info = p_hwfn->mcp_info;
 179
 180         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 181                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 182                 /* Do not free mcp_info here, since public_base indicate that
 183                  * the MCP is not initialized
 184                  */
 185                 return ECORE_SUCCESS;
 186         }
 187
 188         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 189         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 191         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 192                 goto err;
 193
 194         /* Initialize the MFW spinlock */
 195         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 196         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 197
 198         return ECORE_SUCCESS;
 199
 200 err:
 201         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 202         ecore_mcp_free(p_hwfn);
 203         return ECORE_NOMEM;
 204 }
 205
 206 /* Locks the MFW mailbox of a PF to ensure a single access.
 207  * The lock is achieved in most cases by holding a spinlock, causing other
 208  * threads to wait till a previous access is done.
 209  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 210  * access is achieved by setting a blocking flag, which will fail other
 211  * competing contexts to send their mailboxes.
 212  */
 213 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 214                                               u32 cmd)
 215 {
 216         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 217
 218         /* The spinlock shouldn't be acquired when the mailbox command is
 219          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 220          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 221          * (i.e. interrupts are disabled) - can lead to a deadlock.
 222          * It is assumed that for a single PF, no other mailbox commands can be
 223          * sent from another context while sending LOAD_REQ, and that any
 224          * parallel commands to UNLOAD_REQ can be cancelled.
 225          */
 226         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 227                 p_hwfn->mcp_info->block_mb_sending = false;
 228
 229         if (p_hwfn->mcp_info->block_mb_sending) {
 230                 DP_NOTICE(p_hwfn, false,
 231                           "Trying to send a MFW mailbox command [0x%x]"
 232                           " in parallel to [UN]LOAD_REQ. Aborting.\n",
 233                           cmd);
 234                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 235                 return ECORE_BUSY;
 236         }
 237
 238         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 239                 p_hwfn->mcp_info->block_mb_sending = true;
 240                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 241         }
 242
 243         return ECORE_SUCCESS;
 244 }
 245
 246 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 247 {
 248         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 249                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 250 }
 251
 252 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 253                                      struct ecore_ptt *p_ptt)
 254 {
 255         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 256         u32 delay = CHIP_MCP_RESP_ITER_US;
 257         u32 org_mcp_reset_seq, cnt = 0;
 258         enum _ecore_status_t rc = ECORE_SUCCESS;
 259
 260 #ifndef ASIC_ONLY
 261         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 262                 delay = EMUL_MCP_RESP_ITER_US;
 263 #endif
 264
 265         /* Ensure that only a single thread is accessing the mailbox at a
 266          * certain time.
 267          */
 268         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 269         if (rc != ECORE_SUCCESS)
 270                 return rc;
 271
 272         /* Set drv command along with the updated sequence */
 273         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 274         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 275
 276         do {
 277                 /* Wait for MFW response */
 278                 OSAL_UDELAY(delay);
 279                 /* Give the FW up to 500 second (50*1000*10usec) */
 280         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 281                                                 MISCS_REG_GENERIC_POR_0)) &&
 282                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 283
 284         if (org_mcp_reset_seq !=
 285             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 286                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 287                            "MCP was reset after %d usec\n", cnt * delay);
 288         } else {
 289                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 290                 rc = ECORE_AGAIN;
 291         }
 292
 293         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 294
 295         return rc;
 296 }
 297
 298 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 299                                              struct ecore_ptt *p_ptt,
 300                                              u32 cmd, u32 param,
 301                                              u32 *o_mcp_resp,
 302                                              u32 *o_mcp_param)
 303 {
 304         u32 delay = CHIP_MCP_RESP_ITER_US;
 305         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 306         u32 seq, cnt = 1, actual_mb_seq;
 307         enum _ecore_status_t rc = ECORE_SUCCESS;
 308
 309 #ifndef ASIC_ONLY
 310         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 311                 delay = EMUL_MCP_RESP_ITER_US;
 312         /* There is a built-in delay of 100usec in each MFW response read */
 313         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 314                 max_retries /= 10;
 315 #endif
 316
 317         /* Get actual driver mailbox sequence */
 318         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 319             DRV_MSG_SEQ_NUMBER_MASK;
 320
 321         /* Use MCP history register to check if MCP reset occurred between
 322          * init time and now.
 323          */
 324         if (p_hwfn->mcp_info->mcp_hist !=
 325             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 326                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 327                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 328                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 329         }
 330         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 331
 332         /* Set drv param */
 333         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 334
 335         /* Set drv command along with the updated sequence */
 336         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 337
 338         do {
 339                 /* Wait for MFW response */
 340                 OSAL_UDELAY(delay);
 341                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 342
 343                 /* Give the FW up to 5 second (500*10ms) */
 344         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 345                  (cnt++ < max_retries));
 346
 347         /* Is this a reply to our command? */
 348         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 349                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 350                 /* Get the MCP param */
 351                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 352         } else {
 353                 /* FW BUG! */
 354                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 355                        cmd, param);
 356                 *o_mcp_resp = 0;
 357                 rc = ECORE_AGAIN;
 358                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 359         }
 360         return rc;
 361 }
 362
 363 static enum _ecore_status_t
 364 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 365                         struct ecore_ptt *p_ptt,
 366                         struct ecore_mcp_mb_params *p_mb_params)
 367 {
 368         u32 union_data_addr;
 369         enum _ecore_status_t rc;
 370
 371         /* MCP not initialized */
 372         if (!ecore_mcp_is_init(p_hwfn)) {
 373                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 374                 return ECORE_BUSY;
 375         }
 376
 377         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 378                           OFFSETOF(struct public_drv_mb, union_data);
 379
 380         /* Ensure that only a single thread is accessing the mailbox at a
 381          * certain time.
 382          */
 383         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 384         if (rc != ECORE_SUCCESS)
 385                 return rc;
 386
 387         if (p_mb_params->p_data_src != OSAL_NULL)
 388                 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 389                                 p_mb_params->p_data_src,
 390                                 sizeof(*p_mb_params->p_data_src));
 391
 392         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 393                               p_mb_params->param, &p_mb_params->mcp_resp,
 394                               &p_mb_params->mcp_param);
 395
 396         if (p_mb_params->p_data_dst != OSAL_NULL)
 397                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 398                                   union_data_addr,
 399                                   sizeof(*p_mb_params->p_data_dst));
 400
 401         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 402
 403         return rc;
 404 }
 405
 406 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 407                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 408                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 409 {
 410         struct ecore_mcp_mb_params mb_params;
 411         enum _ecore_status_t rc;
 412
 413 #ifndef ASIC_ONLY
 414         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 415                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 416                         loaded--;
 417                         loaded_port[p_hwfn->port_id]--;
 418                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 419                                    loaded);
 420                 }
 421                 return ECORE_SUCCESS;
 422         }
 423 #endif
 424
 425         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 426         mb_params.cmd = cmd;
 427         mb_params.param = param;
 428         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 429         if (rc != ECORE_SUCCESS)
 430                 return rc;
 431
 432         *o_mcp_resp = mb_params.mcp_resp;
 433         *o_mcp_param = mb_params.mcp_param;
 434
 435         return ECORE_SUCCESS;
 436 }
 437
 438 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 439                                           struct ecore_ptt *p_ptt,
 440                                           u32 cmd,
 441                                           u32 param,
 442                                           u32 *o_mcp_resp,
 443                                           u32 *o_mcp_param,
 444                                           u32 i_txn_size, u32 *i_buf)
 445 {
 446         struct ecore_mcp_mb_params mb_params;
 447         union drv_union_data union_data;
 448         enum _ecore_status_t rc;
 449
 450         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 451         mb_params.cmd = cmd;
 452         mb_params.param = param;
 453         OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
 454         mb_params.p_data_src = &union_data;
 455         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 456         if (rc != ECORE_SUCCESS)
 457                 return rc;
 458
 459         *o_mcp_resp = mb_params.mcp_resp;
 460         *o_mcp_param = mb_params.mcp_param;
 461
 462         return ECORE_SUCCESS;
 463 }
 464
 465 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 466                                           struct ecore_ptt *p_ptt,
 467                                           u32 cmd,
 468                                           u32 param,
 469                                           u32 *o_mcp_resp,
 470                                           u32 *o_mcp_param,
 471                                           u32 *o_txn_size, u32 *o_buf)
 472 {
 473         struct ecore_mcp_mb_params mb_params;
 474         union drv_union_data union_data;
 475         enum _ecore_status_t rc;
 476
 477         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 478         mb_params.cmd = cmd;
 479         mb_params.param = param;
 480         mb_params.p_data_dst = &union_data;
 481         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 482         if (rc != ECORE_SUCCESS)
 483                 return rc;
 484
 485         *o_mcp_resp = mb_params.mcp_resp;
 486         *o_mcp_param = mb_params.mcp_param;
 487
 488         *o_txn_size = *o_mcp_param;
 489         OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
 490
 491         return ECORE_SUCCESS;
 492 }
 493
 494 #ifndef ASIC_ONLY
 495 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 496                                     u32 *p_load_code)
 497 {
 498         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 499
 500         if (!loaded)
 501                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 502         else if (!loaded_port[p_hwfn->port_id])
 503                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 504         else
 505                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 506
 507         /* On CMT, always tell that it's engine */
 508         if (p_hwfn->p_dev->num_hwfns > 1)
 509                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 510
 511         *p_load_code = load_phase;
 512         loaded++;
 513         loaded_port[p_hwfn->port_id]++;
 514
 515         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 516                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 517                    *p_load_code, loaded, p_hwfn->port_id,
 518                    loaded_port[p_hwfn->port_id]);
 519 }
 520 #endif
 521
 522 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 523                                         struct ecore_ptt *p_ptt,
 524                                         u32 *p_load_code)
 525 {
 526         struct ecore_dev *p_dev = p_hwfn->p_dev;
 527         struct ecore_mcp_mb_params mb_params;
 528         union drv_union_data union_data;
 529         enum _ecore_status_t rc;
 530
 531 #ifndef ASIC_ONLY
 532         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 533                 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
 534                 return ECORE_SUCCESS;
 535         }
 536 #endif
 537
 538         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 539         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 540         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 541                           p_dev->drv_type;
 542         OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
 543         mb_params.p_data_src = &union_data;
 544         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 545
 546         /* if mcp fails to respond we must abort */
 547         if (rc != ECORE_SUCCESS) {
 548                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 549                 return rc;
 550         }
 551
 552         *p_load_code = mb_params.mcp_resp;
 553
 554         /* If MFW refused (e.g. other port is in diagnostic mode) we
 555          * must abort. This can happen in the following cases:
 556          * - Other port is in diagnostic mode
 557          * - Previously loaded function on the engine is not compliant with
 558          *   the requester.
 559          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 560          *      -
 561          */
 562         if (!(*p_load_code) ||
 563             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 564             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 565             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 566                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 567                 return ECORE_BUSY;
 568         }
 569
 570         return ECORE_SUCCESS;
 571 }
 572
 573 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 574                                     struct ecore_ptt *p_ptt)
 575 {
 576         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 577                                         PUBLIC_PATH);
 578         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 579         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 580                                      ECORE_PATH_ID(p_hwfn));
 581         u32 disabled_vfs[VF_MAX_STATIC / 32];
 582         int i;
 583
 584         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 585                    "Reading Disabled VF information from [offset %08x],"
 586                    " path_addr %08x\n",
 587                    mfw_path_offsize, path_addr);
 588
 589         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 590                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 591                                            path_addr +
 592                                            OFFSETOF(struct public_path,
 593                                                     mcp_vf_disabled) +
 594                                            sizeof(u32) * i);
 595                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 596                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 597                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 598         }
 599
 600         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 601                 OSAL_VF_FLR_UPDATE(p_hwfn);
 602 }
 603
 604 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 605                                           struct ecore_ptt *p_ptt,
 606                                           u32 *vfs_to_ack)
 607 {
 608         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 609                                         PUBLIC_FUNC);
 610         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 611         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 612                                      MCP_PF_ID(p_hwfn));
 613         struct ecore_mcp_mb_params mb_params;
 614         union drv_union_data union_data;
 615         enum _ecore_status_t rc;
 616         int i;
 617
 618         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 619                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 620                            "Acking VFs [%08x,...,%08x] - %08x\n",
 621                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 622
 623         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 624         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 625         OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 626         mb_params.p_data_src = &union_data;
 627         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
 628                                      &mb_params);
 629         if (rc != ECORE_SUCCESS) {
 630                 DP_NOTICE(p_hwfn, false,
 631                           "Failed to pass ACK for VF flr to MFW\n");
 632                 return ECORE_TIMEOUT;
 633         }
 634
 635         /* TMP - clear the ACK bits; should be done by MFW */
 636         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 637                 ecore_wr(p_hwfn, p_ptt,
 638                          func_addr +
 639                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
 640                          i * sizeof(u32), 0);
 641
 642         return rc;
 643 }
 644
 645 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
 646                                                 struct ecore_ptt *p_ptt)
 647 {
 648         u32 transceiver_state;
 649
 650         transceiver_state = ecore_rd(p_hwfn, p_ptt,
 651                                      p_hwfn->mcp_info->port_addr +
 652                                      OFFSETOF(struct public_port,
 653                                               transceiver_data));
 654
 655         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
 656                    "Received transceiver state update [0x%08x] from mfw"
 657                    " [Addr 0x%x]\n",
 658                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
 659                                             OFFSETOF(struct public_port,
 660                                                      transceiver_data)));
 661
 662         transceiver_state = GET_FIELD(transceiver_state, PMM_TRANSCEIVER_STATE);
 663
 664         if (transceiver_state == PMM_TRANSCEIVER_STATE_PRESENT)
 665                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
 666         else
 667                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
 668 }
 669
 670 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
 671                                          struct ecore_ptt *p_ptt,
 672                                          bool b_reset)
 673 {
 674         struct ecore_mcp_link_state *p_link;
 675         u8 max_bw, min_bw;
 676         u32 status = 0;
 677
 678         p_link = &p_hwfn->mcp_info->link_output;
 679         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
 680         if (!b_reset) {
 681                 status = ecore_rd(p_hwfn, p_ptt,
 682                                   p_hwfn->mcp_info->port_addr +
 683                                   OFFSETOF(struct public_port, link_status));
 684                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
 685                            "Received link update [0x%08x] from mfw"
 686                            " [Addr 0x%x]\n",
 687                            status, (u32)(p_hwfn->mcp_info->port_addr +
 688                                           OFFSETOF(struct public_port,
 689                                                    link_status)));
 690         } else {
 691                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 692                            "Resetting link indications\n");
 693                 return;
 694         }
 695
 696         if (p_hwfn->b_drv_link_init)
 697                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 698         else
 699                 p_link->link_up = false;
 700
 701         p_link->full_duplex = true;
 702         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 703         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 704                 p_link->speed = 100000;
 705                 break;
 706         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 707                 p_link->speed = 50000;
 708                 break;
 709         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 710                 p_link->speed = 40000;
 711                 break;
 712         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 713                 p_link->speed = 25000;
 714                 break;
 715         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 716                 p_link->speed = 20000;
 717                 break;
 718         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 719                 p_link->speed = 10000;
 720                 break;
 721         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 722                 p_link->full_duplex = false;
 723                 /* Fall-through */
 724         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 725                 p_link->speed = 1000;
 726                 break;
 727         default:
 728                 p_link->speed = 0;
 729         }
 730
 731         /* We never store total line speed as p_link->speed is
 732          * again changes according to bandwidth allocation.
 733          */
 734         if (p_link->link_up && p_link->speed)
 735                 p_link->line_speed = p_link->speed;
 736         else
 737                 p_link->line_speed = 0;
 738
 739         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 740         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 741
 742         /* Max bandwidth configuration */
 743         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
 744                                            p_link, max_bw);
 745
 746         /* Mintz bandwidth configuration */
 747         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
 748                                            p_link, min_bw);
 749         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
 750                                               p_link->min_pf_rate);
 751
 752         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 753         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 754         p_link->parallel_detection = !!(status &
 755                                          LINK_STATUS_PARALLEL_DETECTION_USED);
 756         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 757
 758         p_link->partner_adv_speed |=
 759             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 760             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
 761         p_link->partner_adv_speed |=
 762             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 763             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
 764         p_link->partner_adv_speed |=
 765             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 766             ECORE_LINK_PARTNER_SPEED_10G : 0;
 767         p_link->partner_adv_speed |=
 768             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 769             ECORE_LINK_PARTNER_SPEED_20G : 0;
 770         p_link->partner_adv_speed |=
 771             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 772             ECORE_LINK_PARTNER_SPEED_25G : 0;
 773         p_link->partner_adv_speed |=
 774             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 775             ECORE_LINK_PARTNER_SPEED_40G : 0;
 776         p_link->partner_adv_speed |=
 777             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 778             ECORE_LINK_PARTNER_SPEED_50G : 0;
 779         p_link->partner_adv_speed |=
 780             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 781             ECORE_LINK_PARTNER_SPEED_100G : 0;
 782
 783         p_link->partner_tx_flow_ctrl_en =
 784             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 785         p_link->partner_rx_flow_ctrl_en =
 786             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 787
 788         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 789         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 790                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
 791                 break;
 792         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 793                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
 794                 break;
 795         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 796                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
 797                 break;
 798         default:
 799                 p_link->partner_adv_pause = 0;
 800         }
 801
 802         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 803
 804         if (p_link->link_up)
 805                 ecore_dcbx_eagle_workaround(p_hwfn, p_ptt, p_link->pfc_enabled);
 806
 807         OSAL_LINK_UPDATE(p_hwfn);
 808 }
 809
 810 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 811                                         struct ecore_ptt *p_ptt, bool b_up)
 812 {
 813         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 814         struct ecore_mcp_mb_params mb_params;
 815         union drv_union_data union_data;
 816         struct pmm_phy_cfg *p_phy_cfg;
 817         enum _ecore_status_t rc = ECORE_SUCCESS;
 818         u32 cmd;
 819
 820 #ifndef ASIC_ONLY
 821         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 822                 return ECORE_SUCCESS;
 823 #endif
 824
 825         /* Set the shmem configuration according to params */
 826         p_phy_cfg = &union_data.drv_phy_cfg;
 827         OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
 828         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 829         if (!params->speed.autoneg)
 830                 p_phy_cfg->speed = params->speed.forced_speed;
 831         p_phy_cfg->pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0;
 832         p_phy_cfg->pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0;
 833         p_phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0;
 834         p_phy_cfg->adv_speed = params->speed.advertised_speeds;
 835         p_phy_cfg->loopback_mode = params->loopback_mode;
 836         p_hwfn->b_drv_link_init = b_up;
 837
 838         if (b_up)
 839                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 840                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
 841                            " adv_speed 0x%08x, loopback 0x%08x,"
 842                            " features 0x%08x\n",
 843                            p_phy_cfg->speed, p_phy_cfg->pause,
 844                            p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode,
 845                            p_phy_cfg->feature_config_flags);
 846         else
 847                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
 848
 849         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 850         mb_params.cmd = cmd;
 851         mb_params.p_data_src = &union_data;
 852         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 853
 854         /* if mcp fails to respond we must abort */
 855         if (rc != ECORE_SUCCESS) {
 856                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 857                 return rc;
 858         }
 859
 860         /* Reset the link status if needed */
 861         if (!b_up)
 862                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
 863
 864         return rc;
 865 }
 866
 867 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
 868                                    struct ecore_ptt *p_ptt)
 869 {
 870         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
 871
 872         /* TODO - Add support for VFs */
 873         if (IS_VF(p_hwfn->p_dev))
 874                 return ECORE_INVAL;
 875
 876         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 877                                                  PUBLIC_PATH);
 878         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
 879         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
 880
 881         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
 882                                  path_addr +
 883                                  OFFSETOF(struct public_path, process_kill)) &
 884             PROCESS_KILL_COUNTER_MASK;
 885
 886         return proc_kill_cnt;
 887 }
 888
 889 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
 890                                           struct ecore_ptt *p_ptt)
 891 {
 892         struct ecore_dev *p_dev = p_hwfn->p_dev;
 893         u32 proc_kill_cnt;
 894
 895         /* Prevent possible attentions/interrupts during the recovery handling
 896          * and till its load phase, during which they will be re-enabled.
 897          */
 898         ecore_int_igu_disable_int(p_hwfn, p_ptt);
 899
 900         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
 901
 902         /* The following operations should be done once, and thus in CMT mode
 903          * are carried out by only the first HW function.
 904          */
 905         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
 906                 return;
 907
 908         if (p_dev->recov_in_prog) {
 909                 DP_NOTICE(p_hwfn, false,
 910                           "Ignoring the indication since a recovery"
 911                           " process is already in progress\n");
 912                 return;
 913         }
 914
 915         p_dev->recov_in_prog = true;
 916
 917         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
 918         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
 919
 920         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
 921 }
 922
 923 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
 924                                           struct ecore_ptt *p_ptt,
 925                                           enum MFW_DRV_MSG_TYPE type)
 926 {
 927         enum ecore_mcp_protocol_type stats_type;
 928         union ecore_mcp_protocol_stats stats;
 929         struct ecore_mcp_mb_params mb_params;
 930         union drv_union_data union_data;
 931         u32 hsi_param;
 932
 933         switch (type) {
 934         case MFW_DRV_MSG_GET_LAN_STATS:
 935                 stats_type = ECORE_MCP_LAN_STATS;
 936                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 937                 break;
 938         default:
 939                 DP_NOTICE(p_hwfn, false, "Invalid protocol type %d\n", type);
 940                 return;
 941         }
 942
 943         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
 944
 945         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 946         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 947         mb_params.param = hsi_param;
 948         OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
 949         mb_params.p_data_src = &union_data;
 950         ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 951 }
 952
 953 static void
 954 ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 955                         struct public_func *p_shmem_info)
 956 {
 957         struct ecore_mcp_function_info *p_info;
 958
 959         p_info = &p_hwfn->mcp_info->func_info;
 960
 961         /* TODO - bandwidth min/max should have valid values of 1-100,
 962          * as well as some indication that the feature is disabled.
 963          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
 964          * limit and correct value to min `1' and max `100' if limit isn't in
 965          * range.
 966          */
 967         p_info->bandwidth_min = (p_shmem_info->config &
 968                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 969             FUNC_MF_CFG_MIN_BW_SHIFT;
 970         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 971                 DP_INFO(p_hwfn,
 972                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 973                         p_info->bandwidth_min);
 974                 p_info->bandwidth_min = 1;
 975         }
 976
 977         p_info->bandwidth_max = (p_shmem_info->config &
 978                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 979             FUNC_MF_CFG_MAX_BW_SHIFT;
 980         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 981                 DP_INFO(p_hwfn,
 982                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 983                         p_info->bandwidth_max);
 984                 p_info->bandwidth_max = 100;
 985         }
 986 }
 987
 988 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
 989                                     struct ecore_ptt *p_ptt,
 990                                     struct public_func *p_data,
 991                                     int pfid)
 992 {
 993         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 994                                         PUBLIC_FUNC);
 995         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 996         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 997         u32 i, size;
 998
 999         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1000
1001         size = OSAL_MIN_T(u32, sizeof(*p_data),
1002                           SECTION_SIZE(mfw_path_offsize));
1003         for (i = 0; i < size / sizeof(u32); i++)
1004                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1005                                               func_addr + (i << 2));
1006
1007         return size;
1008 }
1009
1010 static void
1011 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1012 {
1013         struct ecore_mcp_function_info *p_info;
1014         struct public_func shmem_info;
1015         u32 resp = 0, param = 0;
1016
1017         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1018
1019         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1020
1021         p_info = &p_hwfn->mcp_info->func_info;
1022
1023         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1024
1025         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1026
1027         /* Acknowledge the MFW */
1028         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1029                       &param);
1030 }
1031
1032 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1033                                          struct ecore_ptt *p_ptt)
1034 {
1035         /* A single notification should be sent to upper driver in CMT mode */
1036         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1037                 return;
1038
1039         DP_NOTICE(p_hwfn, false,
1040                   "Fan failure was detected on the network interface card"
1041                   " and it's going to be shut down.\n");
1042
1043         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1044 }
1045
1046 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1047                                              struct ecore_ptt *p_ptt)
1048 {
1049         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1050         enum _ecore_status_t rc = ECORE_SUCCESS;
1051         bool found = false;
1052         u16 i;
1053
1054         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1055
1056         /* Read Messages from MFW */
1057         ecore_mcp_read_mb(p_hwfn, p_ptt);
1058
1059         /* Compare current messages to old ones */
1060         for (i = 0; i < info->mfw_mb_length; i++) {
1061                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1062                         continue;
1063
1064                 found = true;
1065
1066                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1067                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1068                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1069
1070                 switch (i) {
1071                 case MFW_DRV_MSG_LINK_CHANGE:
1072                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1073                         break;
1074                 case MFW_DRV_MSG_VF_DISABLED:
1075                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1076                         break;
1077                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1078                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1079                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1080                         break;
1081                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1082                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1083                                                     ECORE_DCBX_REMOTE_MIB);
1084                         break;
1085                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1086                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1087                                                     ECORE_DCBX_OPERATIONAL_MIB);
1088                         break;
1089                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1090                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1091                         break;
1092                 case MFW_DRV_MSG_ERROR_RECOVERY:
1093                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1094                         break;
1095                 case MFW_DRV_MSG_GET_LAN_STATS:
1096                 case MFW_DRV_MSG_GET_FCOE_STATS:
1097                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1098                 case MFW_DRV_MSG_GET_RDMA_STATS:
1099                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1100                         break;
1101                 case MFW_DRV_MSG_BW_UPDATE:
1102                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1103                         break;
1104                 case MFW_DRV_MSG_FAILURE_DETECTED:
1105                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1106                         break;
1107                 default:
1108                         /* @DPDK */
1109                         DP_NOTICE(p_hwfn, false,
1110                                   "Unimplemented MFW message %d\n", i);
1111                         rc = ECORE_INVAL;
1112                 }
1113         }
1114
1115         /* ACK everything */
1116         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1117                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1118
1119                 /* MFW expect answer in BE, so we force write in that format */
1120                 ecore_wr(p_hwfn, p_ptt,
1121                          info->mfw_mb_addr + sizeof(u32) +
1122                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1123                          sizeof(u32) + i * sizeof(u32), val);
1124         }
1125
1126         if (!found) {
1127                 DP_NOTICE(p_hwfn, false,
1128                           "Received an MFW message indication but no"
1129                           " new message!\n");
1130                 rc = ECORE_INVAL;
1131         }
1132
1133         /* Copy the new mfw messages into the shadow */
1134         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1135
1136         return rc;
1137 }
1138
1139 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1140                                            struct ecore_ptt *p_ptt,
1141                                            u32 *p_mfw_ver,
1142                                            u32 *p_running_bundle_id)
1143 {
1144         u32 global_offsize;
1145
1146 #ifndef ASIC_ONLY
1147         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1148                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1149                 return ECORE_SUCCESS;
1150         }
1151 #endif
1152
1153         if (IS_VF(p_hwfn->p_dev)) {
1154                 if (p_hwfn->vf_iov_info) {
1155                         struct pfvf_acquire_resp_tlv *p_resp;
1156
1157                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1158                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1159                         return ECORE_SUCCESS;
1160                 } else {
1161                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1162                                    "VF requested MFW version prior to ACQUIRE\n");
1163                         return ECORE_INVAL;
1164                 }
1165         }
1166
1167         global_offsize = ecore_rd(p_hwfn, p_ptt,
1168                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1169                                                        public_base,
1170                                                        PUBLIC_GLOBAL));
1171         *p_mfw_ver =
1172             ecore_rd(p_hwfn, p_ptt,
1173                      SECTION_ADDR(global_offsize,
1174                                   0) + OFFSETOF(struct public_global, mfw_ver));
1175
1176         if (p_running_bundle_id != OSAL_NULL) {
1177                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1178                                                 SECTION_ADDR(global_offsize,
1179                                                              0) +
1180                                                 OFFSETOF(struct public_global,
1181                                                          running_bundle_id));
1182         }
1183
1184         return ECORE_SUCCESS;
1185 }
1186
1187 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1188                                               u32 *p_media_type)
1189 {
1190         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1191         struct ecore_ptt *p_ptt;
1192
1193         /* TODO - Add support for VFs */
1194         if (IS_VF(p_dev))
1195                 return ECORE_INVAL;
1196
1197         if (!ecore_mcp_is_init(p_hwfn)) {
1198                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1199                 return ECORE_BUSY;
1200         }
1201
1202         *p_media_type = MEDIA_UNSPECIFIED;
1203
1204         p_ptt = ecore_ptt_acquire(p_hwfn);
1205         if (!p_ptt)
1206                 return ECORE_BUSY;
1207
1208         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1209                                  OFFSETOF(struct public_port, media_type));
1210
1211         ecore_ptt_release(p_hwfn, p_ptt);
1212
1213         return ECORE_SUCCESS;
1214 }
1215
1216 static enum _ecore_status_t
1217 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1218                           struct public_func *p_info,
1219                           enum ecore_pci_personality *p_proto)
1220 {
1221         enum _ecore_status_t rc = ECORE_SUCCESS;
1222
1223         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1224         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1225                 *p_proto = ECORE_PCI_ETH;
1226                 break;
1227         default:
1228                 rc = ECORE_INVAL;
1229         }
1230
1231         return rc;
1232 }
1233
1234 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1235                                                     struct ecore_ptt *p_ptt)
1236 {
1237         struct ecore_mcp_function_info *info;
1238         struct public_func shmem_info;
1239
1240         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1241         info = &p_hwfn->mcp_info->func_info;
1242
1243         info->pause_on_host = (shmem_info.config &
1244                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1245
1246         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1247                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1248                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1249                 return ECORE_INVAL;
1250         }
1251
1252         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1253
1254         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1255                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1256                 info->mac[1] = (u8)(shmem_info.mac_upper);
1257                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1258                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1259                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1260                 info->mac[5] = (u8)(shmem_info.mac_lower);
1261         } else {
1262                 /* TODO - are there protocols for which there's no MAC? */
1263                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1264         }
1265
1266         /* TODO - are these calculations true for BE machine? */
1267         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1268                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1269         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1270                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1271
1272         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1273
1274         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1275                    "Read configuration from shmem: pause_on_host %02x"
1276                     " protocol %02x BW [%02x - %02x]"
1277                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1278                     " node %lx ovlan %04x\n",
1279                    info->pause_on_host, info->protocol,
1280                    info->bandwidth_min, info->bandwidth_max,
1281                    info->mac[0], info->mac[1], info->mac[2],
1282                    info->mac[3], info->mac[4], info->mac[5],
1283                    (unsigned long)info->wwn_port,
1284                    (unsigned long)info->wwn_node, info->ovlan);
1285
1286         return ECORE_SUCCESS;
1287 }
1288
1289 struct ecore_mcp_link_params
1290 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1291 {
1292         if (!p_hwfn || !p_hwfn->mcp_info)
1293                 return OSAL_NULL;
1294         return &p_hwfn->mcp_info->link_input;
1295 }
1296
1297 struct ecore_mcp_link_state
1298 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1299 {
1300         if (!p_hwfn || !p_hwfn->mcp_info)
1301                 return OSAL_NULL;
1302
1303 #ifndef ASIC_ONLY
1304         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1305                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1306                 p_hwfn->mcp_info->link_output.link_up = true;
1307         }
1308 #endif
1309
1310         return &p_hwfn->mcp_info->link_output;
1311 }
1312
1313 struct ecore_mcp_link_capabilities
1314 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1315 {
1316         if (!p_hwfn || !p_hwfn->mcp_info)
1317                 return OSAL_NULL;
1318         return &p_hwfn->mcp_info->link_capabilities;
1319 }
1320
1321 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1322                                      struct ecore_ptt *p_ptt)
1323 {
1324         u32 resp = 0, param = 0;
1325         enum _ecore_status_t rc;
1326
1327         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1328                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1329
1330         /* Wait for the drain to complete before returning */
1331         OSAL_MSLEEP(1020);
1332
1333         return rc;
1334 }
1335
1336 const struct ecore_mcp_function_info
1337 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1338 {
1339         if (!p_hwfn || !p_hwfn->mcp_info)
1340                 return OSAL_NULL;
1341         return &p_hwfn->mcp_info->func_info;
1342 }
1343
1344 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1345                                            struct ecore_ptt *p_ptt,
1346                                            struct ecore_mcp_nvm_params *params)
1347 {
1348         enum _ecore_status_t rc;
1349
1350         switch (params->type) {
1351         case ECORE_MCP_NVM_RD:
1352                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1353                                           params->nvm_common.offset,
1354                                           &params->nvm_common.resp,
1355                                           &params->nvm_common.param,
1356                                           params->nvm_rd.buf_size,
1357                                           params->nvm_rd.buf);
1358                 break;
1359         case ECORE_MCP_CMD:
1360                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1361                                    params->nvm_common.offset,
1362                                    &params->nvm_common.resp,
1363                                    &params->nvm_common.param);
1364                 break;
1365         case ECORE_MCP_NVM_WR:
1366                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1367                                           params->nvm_common.offset,
1368                                           &params->nvm_common.resp,
1369                                           &params->nvm_common.param,
1370                                           params->nvm_wr.buf_size,
1371                                           params->nvm_wr.buf);
1372                 break;
1373         default:
1374                 rc = ECORE_NOTIMPL;
1375                 break;
1376         }
1377         return rc;
1378 }
1379
1380 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1381                                   struct ecore_ptt *p_ptt, u32 personalities)
1382 {
1383         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1384         struct public_func shmem_info;
1385         int i, count = 0, num_pfs;
1386
1387         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1388
1389         for (i = 0; i < num_pfs; i++) {
1390                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1391                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1392                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1393                         continue;
1394
1395                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1396                                               &protocol) != ECORE_SUCCESS)
1397                         continue;
1398
1399                 if ((1 << ((u32)protocol)) & personalities)
1400                         count++;
1401         }
1402
1403         return count;
1404 }
1405
1406 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1407                                               struct ecore_ptt *p_ptt,
1408                                               u32 *p_flash_size)
1409 {
1410         u32 flash_size;
1411
1412 #ifndef ASIC_ONLY
1413         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1414                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1415                 return ECORE_INVAL;
1416         }
1417 #endif
1418
1419         if (IS_VF(p_hwfn->p_dev))
1420                 return ECORE_INVAL;
1421
1422         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1423         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1424             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1425         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1426
1427         *p_flash_size = flash_size;
1428
1429         return ECORE_SUCCESS;
1430 }
1431
1432 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1433                                                   struct ecore_ptt *p_ptt)
1434 {
1435         struct ecore_dev *p_dev = p_hwfn->p_dev;
1436
1437         if (p_dev->recov_in_prog) {
1438                 DP_NOTICE(p_hwfn, false,
1439                           "Avoid triggering a recovery since such a process"
1440                           " is already in progress\n");
1441                 return ECORE_AGAIN;
1442         }
1443
1444         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1445         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1446
1447         return ECORE_SUCCESS;
1448 }
1449
1450 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1451                                               struct ecore_ptt *p_ptt,
1452                                               u8 vf_id, u8 num)
1453 {
1454         u32 resp = 0, param = 0, rc_param = 0;
1455         enum _ecore_status_t rc;
1456
1457 /* Only Leader can configure MSIX, and need to take CMT into account */
1458
1459         if (!IS_LEAD_HWFN(p_hwfn))
1460                 return ECORE_SUCCESS;
1461         num *= p_hwfn->p_dev->num_hwfns;
1462
1463         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1464             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1465         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1466             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1467
1468         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1469                            &resp, &rc_param);
1470
1471         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1472                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1473                           vf_id);
1474                 rc = ECORE_INVAL;
1475         } else {
1476                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1477                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1478                             num, vf_id);
1479         }
1480
1481         return rc;
1482 }
1483
1484 enum _ecore_status_t
1485 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1486                            struct ecore_mcp_drv_version *p_ver)
1487 {
1488         struct drv_version_stc *p_drv_version;
1489         struct ecore_mcp_mb_params mb_params;
1490         union drv_union_data union_data;
1491         u32 num_words, i;
1492         void *p_name;
1493         OSAL_BE32 val;
1494         enum _ecore_status_t rc;
1495
1496 #ifndef ASIC_ONLY
1497         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1498                 return ECORE_SUCCESS;
1499 #endif
1500
1501         p_drv_version = &union_data.drv_version;
1502         p_drv_version->version = p_ver->version;
1503         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1504         for (i = 0; i < num_words; i++) {
1505                 p_name = &p_ver->name[i * sizeof(u32)];
1506                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1507                 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1508         }
1509
1510         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1511         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1512         mb_params.p_data_src = &union_data;
1513         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1514         if (rc != ECORE_SUCCESS)
1515                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1516
1517         return rc;
1518 }
1519
1520 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1521                                     struct ecore_ptt *p_ptt)
1522 {
1523         enum _ecore_status_t rc;
1524         u32 resp = 0, param = 0;
1525
1526         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1527                            &param);
1528         if (rc != ECORE_SUCCESS)
1529                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1530
1531         return rc;
1532 }
1533
1534 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1535                                       struct ecore_ptt *p_ptt)
1536 {
1537         u32 value, cpu_mode;
1538
1539         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1540
1541         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1542         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1543         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1544         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1545
1546         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1547 }
1548
1549 enum _ecore_status_t
1550 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1551                                    struct ecore_ptt *p_ptt,
1552                                    enum ecore_ov_config_method config,
1553                                    enum ecore_ov_client client)
1554 {
1555         enum _ecore_status_t rc;
1556         u32 resp = 0, param = 0;
1557         u32 drv_mb_param;
1558
1559         switch (config) {
1560         case ECORE_OV_CLIENT_DRV:
1561                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1562                 break;
1563         case ECORE_OV_CLIENT_USER:
1564                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1565                 break;
1566         default:
1567                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", config);
1568                 return ECORE_INVAL;
1569         }
1570
1571         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1572                            drv_mb_param, &resp, &param);
1573         if (rc != ECORE_SUCCESS)
1574                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1575
1576         return rc;
1577 }
1578
1579 enum _ecore_status_t
1580 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1581                                  struct ecore_ptt *p_ptt,
1582                                  enum ecore_ov_driver_state drv_state)
1583 {
1584         enum _ecore_status_t rc;
1585         u32 resp = 0, param = 0;
1586         u32 drv_mb_param;
1587
1588         switch (drv_state) {
1589         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1590                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1591                 break;
1592         case ECORE_OV_DRIVER_STATE_DISABLED:
1593                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1594                 break;
1595         case ECORE_OV_DRIVER_STATE_ACTIVE:
1596                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1597                 break;
1598         default:
1599                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1600                 return ECORE_INVAL;
1601         }
1602
1603         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1604                            drv_state, &resp, &param);
1605         if (rc != ECORE_SUCCESS)
1606                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1607
1608         return rc;
1609 }
1610
1611 enum _ecore_status_t
1612 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1613                          struct ecore_fc_npiv_tbl *p_table)
1614 {
1615         return 0;
1616 }
1617
1618 enum _ecore_status_t
1619 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1620                         struct ecore_ptt *p_ptt, u16 mtu)
1621 {
1622         return 0;
1623 }
1624
1625 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1626                                        struct ecore_ptt *p_ptt,
1627                                        enum ecore_led_mode mode)
1628 {
1629         u32 resp = 0, param = 0, drv_mb_param;
1630         enum _ecore_status_t rc;
1631
1632         switch (mode) {
1633         case ECORE_LED_MODE_ON:
1634                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1635                 break;
1636         case ECORE_LED_MODE_OFF:
1637                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1638                 break;
1639         case ECORE_LED_MODE_RESTORE:
1640                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1641                 break;
1642         default:
1643                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1644                 return ECORE_INVAL;
1645         }
1646
1647         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1648                            drv_mb_param, &resp, &param);
1649         if (rc != ECORE_SUCCESS)
1650                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1651
1652         return rc;
1653 }
1654
1655 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1656                                              struct ecore_ptt *p_ptt,
1657                                              u32 mask_parities)
1658 {
1659         enum _ecore_status_t rc;
1660         u32 resp = 0, param = 0;
1661
1662         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1663                            mask_parities, &resp, &param);
1664
1665         if (rc != ECORE_SUCCESS) {
1666                 DP_ERR(p_hwfn,
1667                        "MCP response failure for mask parities, aborting\n");
1668         } else if (resp != FW_MSG_CODE_OK) {
1669                 DP_ERR(p_hwfn,
1670                        "MCP did not ack mask parity request. Old MFW?\n");
1671                 rc = ECORE_INVAL;
1672         }
1673
1674         return rc;
1675 }
1676
1677 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1678                                         u8 *p_buf, u32 len)
1679 {
1680         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1681         u32 bytes_left, offset, bytes_to_copy, buf_size;
1682         struct ecore_mcp_nvm_params params;
1683         struct ecore_ptt *p_ptt;
1684         enum _ecore_status_t rc = ECORE_SUCCESS;
1685
1686         p_ptt = ecore_ptt_acquire(p_hwfn);
1687         if (!p_ptt)
1688                 return ECORE_BUSY;
1689
1690         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1691         bytes_left = len;
1692         offset = 0;
1693         params.type = ECORE_MCP_NVM_RD;
1694         params.nvm_rd.buf_size = &buf_size;
1695         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1696         while (bytes_left > 0) {
1697                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1698                                            MCP_DRV_NVM_BUF_LEN);
1699                 params.nvm_common.offset = (addr + offset) |
1700                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1701                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1702                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1703                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1704                                             FW_MSG_CODE_NVM_OK)) {
1705                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1706                         break;
1707                 }
1708
1709                 /* This can be a lengthy process, and it's possible scheduler
1710                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
1711                  */
1712                 if (bytes_left % 0x1000 <
1713                     (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
1714                         OSAL_MSLEEP(1);
1715
1716                 offset += *params.nvm_rd.buf_size;
1717                 bytes_left -= *params.nvm_rd.buf_size;
1718         }
1719
1720         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1721         ecore_ptt_release(p_hwfn, p_ptt);
1722
1723         return rc;
1724 }
1725
1726 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1727                                         u32 addr, u8 *p_buf, u32 len)
1728 {
1729         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1730         struct ecore_mcp_nvm_params params;
1731         struct ecore_ptt *p_ptt;
1732         enum _ecore_status_t rc;
1733
1734         p_ptt = ecore_ptt_acquire(p_hwfn);
1735         if (!p_ptt)
1736                 return ECORE_BUSY;
1737
1738         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1739         params.type = ECORE_MCP_NVM_RD;
1740         params.nvm_rd.buf_size = &len;
1741         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1742             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1743         params.nvm_common.offset = addr;
1744         params.nvm_rd.buf = (u32 *)p_buf;
1745         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1746         if (rc != ECORE_SUCCESS)
1747                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1748
1749         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1750         ecore_ptt_release(p_hwfn, p_ptt);
1751
1752         return rc;
1753 }
1754
1755 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1756 {
1757         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1758         struct ecore_mcp_nvm_params params;
1759         struct ecore_ptt *p_ptt;
1760
1761         p_ptt = ecore_ptt_acquire(p_hwfn);
1762         if (!p_ptt)
1763                 return ECORE_BUSY;
1764
1765         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1766         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1767         ecore_ptt_release(p_hwfn, p_ptt);
1768
1769         return ECORE_SUCCESS;
1770 }
1771
1772 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1773 {
1774         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1775         struct ecore_mcp_nvm_params params;
1776         struct ecore_ptt *p_ptt;
1777         enum _ecore_status_t rc;
1778
1779         p_ptt = ecore_ptt_acquire(p_hwfn);
1780         if (!p_ptt)
1781                 return ECORE_BUSY;
1782         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1783         params.type = ECORE_MCP_CMD;
1784         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1785         params.nvm_common.offset = addr;
1786         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1787         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1788         ecore_ptt_release(p_hwfn, p_ptt);
1789
1790         return rc;
1791 }
1792
1793 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1794                                                   u32 addr)
1795 {
1796         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1797         struct ecore_mcp_nvm_params params;
1798         struct ecore_ptt *p_ptt;
1799         enum _ecore_status_t rc;
1800
1801         p_ptt = ecore_ptt_acquire(p_hwfn);
1802         if (!p_ptt)
1803                 return ECORE_BUSY;
1804         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1805         params.type = ECORE_MCP_CMD;
1806         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1807         params.nvm_common.offset = addr;
1808         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1809         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1810         ecore_ptt_release(p_hwfn, p_ptt);
1811
1812         return rc;
1813 }
1814
1815 /* rc receives ECORE_INVAL as default parameter because
1816  * it might not enter the while loop if the len is 0
1817  */
1818 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1819                                          u32 addr, u8 *p_buf, u32 len)
1820 {
1821         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1822         enum _ecore_status_t rc = ECORE_INVAL;
1823         struct ecore_mcp_nvm_params params;
1824         struct ecore_ptt *p_ptt;
1825         u32 buf_idx, buf_size;
1826
1827         p_ptt = ecore_ptt_acquire(p_hwfn);
1828         if (!p_ptt)
1829                 return ECORE_BUSY;
1830
1831         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1832         params.type = ECORE_MCP_NVM_WR;
1833         if (cmd == ECORE_PUT_FILE_DATA)
1834                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
1835         else
1836                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
1837         buf_idx = 0;
1838         while (buf_idx < len) {
1839                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
1840                                       MCP_DRV_NVM_BUF_LEN);
1841                 params.nvm_common.offset = ((buf_size <<
1842                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
1843                                             | addr) + buf_idx;
1844                 params.nvm_wr.buf_size = buf_size;
1845                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
1846                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1847                 if (rc != ECORE_SUCCESS ||
1848                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
1849                      (params.nvm_common.resp !=
1850                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
1851                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1852
1853                 /* This can be a lengthy process, and it's possible scheduler
1854                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
1855                  */
1856                 if (buf_idx % 0x1000 >
1857                     (buf_idx + buf_size) % 0x1000)
1858                         OSAL_MSLEEP(1);
1859
1860                 buf_idx += buf_size;
1861         }
1862
1863         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1864         ecore_ptt_release(p_hwfn, p_ptt);
1865
1866         return rc;
1867 }
1868
1869 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
1870                                          u32 addr, u8 *p_buf, u32 len)
1871 {
1872         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1873         struct ecore_mcp_nvm_params params;
1874         struct ecore_ptt *p_ptt;
1875         enum _ecore_status_t rc;
1876
1877         p_ptt = ecore_ptt_acquire(p_hwfn);
1878         if (!p_ptt)
1879                 return ECORE_BUSY;
1880
1881         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1882         params.type = ECORE_MCP_NVM_WR;
1883         params.nvm_wr.buf_size = len;
1884         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
1885             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
1886         params.nvm_common.offset = addr;
1887         params.nvm_wr.buf = (u32 *)p_buf;
1888         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1889         if (rc != ECORE_SUCCESS)
1890                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1891         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1892         ecore_ptt_release(p_hwfn, p_ptt);
1893
1894         return rc;
1895 }
1896
1897 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
1898                                                    u32 addr)
1899 {
1900         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1901         struct ecore_mcp_nvm_params params;
1902         struct ecore_ptt *p_ptt;
1903         enum _ecore_status_t rc;
1904
1905         p_ptt = ecore_ptt_acquire(p_hwfn);
1906         if (!p_ptt)
1907                 return ECORE_BUSY;
1908
1909         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1910         params.type = ECORE_MCP_CMD;
1911         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
1912         params.nvm_common.offset = addr;
1913         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1914         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1915         ecore_ptt_release(p_hwfn, p_ptt);
1916
1917         return rc;
1918 }
1919
1920 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
1921                                             struct ecore_ptt *p_ptt,
1922                                             u32 port, u32 addr, u32 offset,
1923                                             u32 len, u8 *p_buf)
1924 {
1925         struct ecore_mcp_nvm_params params;
1926         enum _ecore_status_t rc;
1927         u32 bytes_left, bytes_to_copy, buf_size;
1928
1929         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1930         params.nvm_common.offset =
1931                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
1932                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
1933         addr = offset;
1934         offset = 0;
1935         bytes_left = len;
1936         params.type = ECORE_MCP_NVM_RD;
1937         params.nvm_rd.buf_size = &buf_size;
1938         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
1939         while (bytes_left > 0) {
1940                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1941                                            MAX_I2C_TRANSACTION_SIZE);
1942                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1943                 params.nvm_common.offset &=
1944                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
1945                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
1946                 params.nvm_common.offset |=
1947                         ((addr + offset) <<
1948                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
1949                 params.nvm_common.offset |=
1950                         (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
1951                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1952                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
1953                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
1954                         return ECORE_NODEV;
1955                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
1956                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
1957                         return ECORE_UNKNOWN_ERROR;
1958
1959                 offset += *params.nvm_rd.buf_size;
1960                 bytes_left -= *params.nvm_rd.buf_size;
1961         }
1962
1963         return ECORE_SUCCESS;
1964 }
1965
1966 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
1967                                              struct ecore_ptt *p_ptt,
1968                                              u32 port, u32 addr, u32 offset,
1969                                              u32 len, u8 *p_buf)
1970 {
1971         struct ecore_mcp_nvm_params params;
1972         enum _ecore_status_t rc;
1973         u32 buf_idx, buf_size;
1974
1975         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1976         params.nvm_common.offset =
1977                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
1978                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
1979         params.type = ECORE_MCP_NVM_WR;
1980         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
1981         buf_idx = 0;
1982         while (buf_idx < len) {
1983                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
1984                                       MAX_I2C_TRANSACTION_SIZE);
1985                 params.nvm_common.offset &=
1986                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
1987                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
1988                 params.nvm_common.offset |=
1989                         ((offset + buf_idx) <<
1990                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
1991                 params.nvm_common.offset |=
1992                         (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
1993                 params.nvm_wr.buf_size = buf_size;
1994                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
1995                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1996                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
1997                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
1998                         return ECORE_NODEV;
1999                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2000                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2001                         return ECORE_UNKNOWN_ERROR;
2002
2003                 buf_idx += buf_size;
2004         }
2005
2006         return ECORE_SUCCESS;
2007 }
2008
2009 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2010                                          struct ecore_ptt *p_ptt,
2011                                          u16 gpio, u32 *gpio_val)
2012 {
2013         enum _ecore_status_t rc = ECORE_SUCCESS;
2014         u32 drv_mb_param = 0, rsp;
2015
2016         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2017
2018         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2019                            drv_mb_param, &rsp, gpio_val);
2020
2021         if (rc != ECORE_SUCCESS)
2022                 return rc;
2023
2024         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2025                 return ECORE_UNKNOWN_ERROR;
2026
2027         return ECORE_SUCCESS;
2028 }
2029
2030 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2031                                           struct ecore_ptt *p_ptt,
2032                                           u16 gpio, u16 gpio_val)
2033 {
2034         enum _ecore_status_t rc = ECORE_SUCCESS;
2035         u32 drv_mb_param = 0, param, rsp;
2036
2037         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2038                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2039
2040         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2041                            drv_mb_param, &rsp, &param);
2042
2043         if (rc != ECORE_SUCCESS)
2044                 return rc;
2045
2046         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2047                 return ECORE_UNKNOWN_ERROR;
2048
2049         return ECORE_SUCCESS;
2050 }
2051
2052 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2053                                          struct ecore_ptt *p_ptt,
2054                                          u16 gpio, u32 *gpio_direction,
2055                                          u32 *gpio_ctrl)
2056 {
2057         u32 drv_mb_param = 0, rsp, val = 0;
2058         enum _ecore_status_t rc = ECORE_SUCCESS;
2059
2060         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2061
2062         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2063                            drv_mb_param, &rsp, &val);
2064         if (rc != ECORE_SUCCESS)
2065                 return rc;
2066
2067         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2068                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2069         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2070                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2071
2072         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2073                 return ECORE_UNKNOWN_ERROR;
2074
2075         return ECORE_SUCCESS;
2076 }
2077
2078 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2079                                                   struct ecore_ptt *p_ptt)
2080 {
2081         u32 drv_mb_param = 0, rsp, param;
2082         enum _ecore_status_t rc = ECORE_SUCCESS;
2083
2084         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2085                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2086
2087         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2088                            drv_mb_param, &rsp, &param);
2089
2090         if (rc != ECORE_SUCCESS)
2091                 return rc;
2092
2093         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2094             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2095                 rc = ECORE_UNKNOWN_ERROR;
2096
2097         return rc;
2098 }
2099
2100 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2101                                                struct ecore_ptt *p_ptt)
2102 {
2103         u32 drv_mb_param = 0, rsp, param;
2104         enum _ecore_status_t rc = ECORE_SUCCESS;
2105
2106         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2107                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2108
2109         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2110                            drv_mb_param, &rsp, &param);
2111
2112         if (rc != ECORE_SUCCESS)
2113                 return rc;
2114
2115         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2116             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2117                 rc = ECORE_UNKNOWN_ERROR;
2118
2119         return rc;
2120 }
2121
2122 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2123         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2124 {
2125         u32 drv_mb_param = 0, rsp;
2126         enum _ecore_status_t rc = ECORE_SUCCESS;
2127
2128         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2129                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2130
2131         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2132                            drv_mb_param, &rsp, num_images);
2133
2134         if (rc != ECORE_SUCCESS)
2135                 return rc;
2136
2137         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2138                 rc = ECORE_UNKNOWN_ERROR;
2139
2140         return rc;
2141 }
2142
2143 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2144         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2145         struct bist_nvm_image_att *p_image_att, u32 image_index)
2146 {
2147         struct ecore_mcp_nvm_params params;
2148         enum _ecore_status_t rc;
2149         u32 buf_size;
2150
2151         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2152         params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2153                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2154         params.nvm_common.offset |= (image_index <<
2155                                     DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2156
2157         params.type = ECORE_MCP_NVM_RD;
2158         params.nvm_rd.buf_size = &buf_size;
2159         params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2160         params.nvm_rd.buf = (u32 *)p_image_att;
2161
2162         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2163         if (rc != ECORE_SUCCESS)
2164                 return rc;
2165
2166         if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2167             (p_image_att->return_code != 1))
2168                 rc = ECORE_UNKNOWN_ERROR;
2169
2170         return rc;
2171 }
2172
2173 enum _ecore_status_t
2174 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2175                                struct ecore_ptt *p_ptt,
2176                                struct ecore_temperature_info *p_temp_info)
2177 {
2178         struct ecore_temperature_sensor *p_temp_sensor;
2179         struct temperature_status_stc *p_mfw_temp_info;
2180         struct ecore_mcp_mb_params mb_params;
2181         union drv_union_data union_data;
2182         u32 val;
2183         enum _ecore_status_t rc;
2184         u8 i;
2185
2186         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2187         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2188         mb_params.p_data_dst = &union_data;
2189         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2190         if (rc != ECORE_SUCCESS)
2191                 return rc;
2192
2193         p_mfw_temp_info = &union_data.temp_info;
2194
2195         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2196         p_temp_info->num_sensors = OSAL_MIN_T(u32,
2197                                               p_mfw_temp_info->num_of_sensors,
2198                                               ECORE_MAX_NUM_OF_SENSORS);
2199         for (i = 0; i < p_temp_info->num_sensors; i++) {
2200                 val = p_mfw_temp_info->sensor[i];
2201                 p_temp_sensor = &p_temp_info->sensors[i];
2202                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2203                                                  SENSOR_LOCATION_SHIFT;
2204                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2205                                                 THRESHOLD_HIGH_SHIFT;
2206                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2207                                           CRITICAL_TEMPERATURE_SHIFT;
2208                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2209                                               CURRENT_TEMP_SHIFT;
2210         }
2211
2212         return ECORE_SUCCESS;
2213 }
2214
2215 enum _ecore_status_t ecore_mcp_get_mba_versions(
2216         struct ecore_hwfn *p_hwfn,
2217         struct ecore_ptt *p_ptt,
2218         struct ecore_mba_vers *p_mba_vers)
2219 {
2220         struct ecore_mcp_nvm_params params;
2221         enum _ecore_status_t rc;
2222         u32 buf_size;
2223
2224         OSAL_MEM_ZERO(&params, sizeof(params));
2225         params.type = ECORE_MCP_NVM_RD;
2226         params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2227         params.nvm_common.offset = 0;
2228         params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2229         params.nvm_rd.buf_size = &buf_size;
2230         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2231
2232         if (rc != ECORE_SUCCESS)
2233                 return rc;
2234
2235         if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2236             FW_MSG_CODE_NVM_OK)
2237                 rc = ECORE_UNKNOWN_ERROR;
2238
2239         if (buf_size != MCP_DRV_NVM_BUF_LEN)
2240                 rc = ECORE_UNKNOWN_ERROR;
2241
2242         return rc;
2243 }
2244
2245 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2246                                               struct ecore_ptt *p_ptt,
2247                                               u64 *num_events)
2248 {
2249         u32 rsp;
2250
2251         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2252                              0, &rsp, (u32 *)num_events);
2253 }
2254
2255 #define ECORE_RESC_ALLOC_VERSION_MAJOR  1
2256 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
2257 #define ECORE_RESC_ALLOC_VERSION                                \
2258         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
2259           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
2260          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
2261           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2262
2263 enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
2264                                              struct ecore_ptt *p_ptt,
2265                                              struct resource_info *p_resc_info,
2266                                              u32 *p_mcp_resp, u32 *p_mcp_param)
2267 {
2268         struct ecore_mcp_mb_params mb_params;
2269         union drv_union_data *p_union_data;
2270         enum _ecore_status_t rc;
2271
2272         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2273         mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2274         mb_params.param = ECORE_RESC_ALLOC_VERSION;
2275         p_union_data = (union drv_union_data *)p_resc_info;
2276         mb_params.p_data_src = p_union_data;
2277         mb_params.p_data_dst = p_union_data;
2278         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2279         if (rc != ECORE_SUCCESS)
2280                 return rc;
2281
2282         *p_mcp_resp = mb_params.mcp_resp;
2283         *p_mcp_param = mb_params.mcp_param;
2284
2285         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2286                    "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
2287                    " offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
2288                    *p_mcp_param, p_resc_info->res_id, p_resc_info->size,
2289                    p_resc_info->offset, p_resc_info->vf_size,
2290                    p_resc_info->vf_offset, p_resc_info->flags);
2291
2292         return ECORE_SUCCESS;
2293 }