drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 struct ecore_mcp_cmd_elem {
 100         osal_list_entry_t list;
 101         struct ecore_mcp_mb_params *p_mb_params;
 102         u16 expected_seq_num;
 103         bool b_is_completed;
 104 };
 105
 106 /* Must be called while cmd_lock is acquired */
 107 static struct ecore_mcp_cmd_elem *
 108 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 109                        struct ecore_mcp_mb_params *p_mb_params,
 110                        u16 expected_seq_num)
 111 {
 112         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 113
 114         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 115                                  sizeof(*p_cmd_elem));
 116         if (!p_cmd_elem) {
 117                 DP_NOTICE(p_hwfn, false,
 118                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 119                 goto out;
 120         }
 121
 122         p_cmd_elem->p_mb_params = p_mb_params;
 123         p_cmd_elem->expected_seq_num = expected_seq_num;
 124         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 125 out:
 126         return p_cmd_elem;
 127 }
 128
 129 /* Must be called while cmd_lock is acquired */
 130 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 131                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 132 {
 133         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 134         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 135 }
 136
 137 /* Must be called while cmd_lock is acquired */
 138 static struct ecore_mcp_cmd_elem *
 139 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 140 {
 141         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 142
 143         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 144                                  struct ecore_mcp_cmd_elem) {
 145                 if (p_cmd_elem->expected_seq_num == seq_num)
 146                         return p_cmd_elem;
 147         }
 148
 149         return OSAL_NULL;
 150 }
 151
 152 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 153 {
 154         if (p_hwfn->mcp_info) {
 155                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 156
 157                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 158                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 159                                               &p_hwfn->mcp_info->cmd_list, list,
 160                                               struct ecore_mcp_cmd_elem) {
 161                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 162                 }
 163                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 164
 165                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 166                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 167 #ifdef CONFIG_ECORE_LOCK_ALLOC
 168                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 169                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 170 #endif
 171         }
 172
 173         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 174
 175         return ECORE_SUCCESS;
 176 }
 177
 178 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 179                                                    struct ecore_ptt *p_ptt)
 180 {
 181         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 182         u32 drv_mb_offsize, mfw_mb_offsize;
 183         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 184
 185 #ifndef ASIC_ONLY
 186         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 187                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 188                 p_info->public_base = 0;
 189                 return ECORE_INVAL;
 190         }
 191 #endif
 192
 193         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 194         if (!p_info->public_base)
 195                 return ECORE_INVAL;
 196
 197         p_info->public_base |= GRCBASE_MCP;
 198
 199         /* Calculate the driver and MFW mailbox address */
 200         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 201                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 202                                                        PUBLIC_DRV_MB));
 203         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 204         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 205                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 206                    " mcp_pf_id = 0x%x\n",
 207                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 208
 209         /* Set the MFW MB address */
 210         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 211                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 212                                                        PUBLIC_MFW_MB));
 213         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 214         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 215                                                p_info->mfw_mb_addr);
 216
 217         /* Get the current driver mailbox sequence before sending
 218          * the first command
 219          */
 220         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 221             DRV_MSG_SEQ_NUMBER_MASK;
 222
 223         /* Get current FW pulse sequence */
 224         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 225             DRV_PULSE_SEQ_MASK;
 226
 227         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 228
 229         return ECORE_SUCCESS;
 230 }
 231
 232 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 233                                         struct ecore_ptt *p_ptt)
 234 {
 235         struct ecore_mcp_info *p_info;
 236         u32 size;
 237
 238         /* Allocate mcp_info structure */
 239         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 240                                        sizeof(*p_hwfn->mcp_info));
 241         if (!p_hwfn->mcp_info)
 242                 goto err;
 243         p_info = p_hwfn->mcp_info;
 244
 245         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 246                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 247                 /* Do not free mcp_info here, since public_base indicate that
 248                  * the MCP is not initialized
 249                  */
 250                 return ECORE_SUCCESS;
 251         }
 252
 253         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 254         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 255         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 256         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 257                 goto err;
 258
 259         /* Initialize the MFW spinlocks */
 260 #ifdef CONFIG_ECORE_LOCK_ALLOC
 261         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 262         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 263 #endif
 264         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 265         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 266
 267         OSAL_LIST_INIT(&p_info->cmd_list);
 268
 269         return ECORE_SUCCESS;
 270
 271 err:
 272         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 273         ecore_mcp_free(p_hwfn);
 274         return ECORE_NOMEM;
 275 }
 276
 277 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 278                                      struct ecore_ptt *p_ptt)
 279 {
 280         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 281
 282         /* Use MCP history register to check if MCP reset occurred between init
 283          * time and now.
 284          */
 285         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 286                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 287                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 288                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 289
 290                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 291                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 292         }
 293 }
 294
 295 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 296                                      struct ecore_ptt *p_ptt)
 297 {
 298         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 299         enum _ecore_status_t rc = ECORE_SUCCESS;
 300
 301 #ifndef ASIC_ONLY
 302         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 303                 delay = EMUL_MCP_RESP_ITER_US;
 304 #endif
 305
 306         /* Ensure that only a single thread is accessing the mailbox */
 307         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 308
 309         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 310
 311         /* Set drv command along with the updated sequence */
 312         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 313         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 314         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 315
 316         do {
 317                 /* Wait for MFW response */
 318                 OSAL_UDELAY(delay);
 319                 /* Give the FW up to 500 second (50*1000*10usec) */
 320         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 321                                                 MISCS_REG_GENERIC_POR_0)) &&
 322                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 323
 324         if (org_mcp_reset_seq !=
 325             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 326                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 327                            "MCP was reset after %d usec\n", cnt * delay);
 328         } else {
 329                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 330                 rc = ECORE_AGAIN;
 331         }
 332
 333         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 334
 335         return rc;
 336 }
 337
 338 /* Must be called while cmd_lock is acquired */
 339 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 340 {
 341         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 342
 343         /* There is at most one pending command at a certain time, and if it
 344          * exists - it is placed at the HEAD of the list.
 345          */
 346         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 347                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 348                                                    struct ecore_mcp_cmd_elem,
 349                                                    list);
 350                 return !p_cmd_elem->b_is_completed;
 351         }
 352
 353         return false;
 354 }
 355
 356 /* Must be called while cmd_lock is acquired */
 357 static enum _ecore_status_t
 358 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 359 {
 360         struct ecore_mcp_mb_params *p_mb_params;
 361         struct ecore_mcp_cmd_elem *p_cmd_elem;
 362         u32 mcp_resp;
 363         u16 seq_num;
 364
 365         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 366         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 367
 368         /* Return if no new non-handled response has been received */
 369         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 370                 return ECORE_AGAIN;
 371
 372         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 373         if (!p_cmd_elem) {
 374                 DP_ERR(p_hwfn,
 375                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 376                        seq_num);
 377                 return ECORE_UNKNOWN_ERROR;
 378         }
 379
 380         p_mb_params = p_cmd_elem->p_mb_params;
 381
 382         /* Get the MFW response along with the sequence number */
 383         p_mb_params->mcp_resp = mcp_resp;
 384
 385         /* Get the MFW param */
 386         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 387
 388         /* Get the union data */
 389         if (p_mb_params->p_data_dst != OSAL_NULL &&
 390             p_mb_params->data_dst_size) {
 391                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 392                                       OFFSETOF(struct public_drv_mb,
 393                                                union_data);
 394                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 395                                   union_data_addr, p_mb_params->data_dst_size);
 396         }
 397
 398         p_cmd_elem->b_is_completed = true;
 399
 400         return ECORE_SUCCESS;
 401 }
 402
 403 /* Must be called while cmd_lock is acquired */
 404 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 405                                       struct ecore_ptt *p_ptt,
 406                                       struct ecore_mcp_mb_params *p_mb_params,
 407                                       u16 seq_num)
 408 {
 409         union drv_union_data union_data;
 410         u32 union_data_addr;
 411
 412         /* Set the union data */
 413         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 414                           OFFSETOF(struct public_drv_mb, union_data);
 415         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 416         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 417                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 418                             p_mb_params->data_src_size);
 419         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 420                         sizeof(union_data));
 421
 422         /* Set the drv param */
 423         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 424
 425         /* Set the drv command along with the sequence number */
 426         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 427
 428         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 429                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 430                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 431 }
 432
 433 static enum _ecore_status_t
 434 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 435                          struct ecore_mcp_mb_params *p_mb_params,
 436                          u32 max_retries, u32 delay)
 437 {
 438         struct ecore_mcp_cmd_elem *p_cmd_elem;
 439         u32 cnt = 0;
 440         u16 seq_num;
 441         enum _ecore_status_t rc = ECORE_SUCCESS;
 442
 443         /* Wait until the mailbox is non-occupied */
 444         do {
 445                 /* Exit the loop if there is no pending command, or if the
 446                  * pending command is completed during this iteration.
 447                  * The spinlock stays locked until the command is sent.
 448                  */
 449
 450                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 451
 452                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 453                         break;
 454
 455                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 456                 if (rc == ECORE_SUCCESS)
 457                         break;
 458                 else if (rc != ECORE_AGAIN)
 459                         goto err;
 460
 461                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 462                 OSAL_UDELAY(delay);
 463         } while (++cnt < max_retries);
 464
 465         if (cnt >= max_retries) {
 466                 DP_NOTICE(p_hwfn, false,
 467                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 468                           p_mb_params->cmd, p_mb_params->param);
 469                 return ECORE_AGAIN;
 470         }
 471
 472         /* Send the mailbox command */
 473         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 474         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 475         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 476         if (!p_cmd_elem) {
 477                 rc = ECORE_NOMEM;
 478                 goto err;
 479         }
 480
 481         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 482         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 483
 484         /* Wait for the MFW response */
 485         do {
 486                 /* Exit the loop if the command is already completed, or if the
 487                  * command is completed during this iteration.
 488                  * The spinlock stays locked until the list element is removed.
 489                  */
 490
 491                 OSAL_UDELAY(delay);
 492                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 493
 494                 if (p_cmd_elem->b_is_completed)
 495                         break;
 496
 497                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 498                 if (rc == ECORE_SUCCESS)
 499                         break;
 500                 else if (rc != ECORE_AGAIN)
 501                         goto err;
 502
 503                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 504         } while (++cnt < max_retries);
 505
 506         if (cnt >= max_retries) {
 507                 DP_NOTICE(p_hwfn, false,
 508                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 509                           p_mb_params->cmd, p_mb_params->param);
 510
 511                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 512                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 513                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 514
 515                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 516                 return ECORE_AGAIN;
 517         }
 518
 519         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 520         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 521
 522         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 523                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 524                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 525                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 526
 527         /* Clear the sequence number from the MFW response */
 528         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 529
 530         return ECORE_SUCCESS;
 531
 532 err:
 533         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 534         return rc;
 535 }
 536
 537 static enum _ecore_status_t
 538 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 539                         struct ecore_ptt *p_ptt,
 540                         struct ecore_mcp_mb_params *p_mb_params)
 541 {
 542         osal_size_t union_data_size = sizeof(union drv_union_data);
 543         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 544         u32 delay = CHIP_MCP_RESP_ITER_US;
 545
 546 #ifndef ASIC_ONLY
 547         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 548                 delay = EMUL_MCP_RESP_ITER_US;
 549         /* There is a built-in delay of 100usec in each MFW response read */
 550         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 551                 max_retries /= 10;
 552 #endif
 553
 554         /* MCP not initialized */
 555         if (!ecore_mcp_is_init(p_hwfn)) {
 556                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 557                 return ECORE_BUSY;
 558         }
 559
 560         if (p_mb_params->data_src_size > union_data_size ||
 561             p_mb_params->data_dst_size > union_data_size) {
 562                 DP_ERR(p_hwfn,
 563                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 564                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 565                        union_data_size);
 566                 return ECORE_INVAL;
 567         }
 568
 569         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 570                                         delay);
 571 }
 572
 573 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 574                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 575                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 576 {
 577         struct ecore_mcp_mb_params mb_params;
 578         enum _ecore_status_t rc;
 579
 580 #ifndef ASIC_ONLY
 581         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 582                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 583                         loaded--;
 584                         loaded_port[p_hwfn->port_id]--;
 585                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 586                                    loaded);
 587                 }
 588                 return ECORE_SUCCESS;
 589         }
 590 #endif
 591
 592         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 593         mb_params.cmd = cmd;
 594         mb_params.param = param;
 595         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 596         if (rc != ECORE_SUCCESS)
 597                 return rc;
 598
 599         *o_mcp_resp = mb_params.mcp_resp;
 600         *o_mcp_param = mb_params.mcp_param;
 601
 602         return ECORE_SUCCESS;
 603 }
 604
 605 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 606                                           struct ecore_ptt *p_ptt,
 607                                           u32 cmd,
 608                                           u32 param,
 609                                           u32 *o_mcp_resp,
 610                                           u32 *o_mcp_param,
 611                                           u32 i_txn_size, u32 *i_buf)
 612 {
 613         struct ecore_mcp_mb_params mb_params;
 614         enum _ecore_status_t rc;
 615
 616         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 617         mb_params.cmd = cmd;
 618         mb_params.param = param;
 619         mb_params.p_data_src = i_buf;
 620         mb_params.data_src_size = (u8)i_txn_size;
 621         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 622         if (rc != ECORE_SUCCESS)
 623                 return rc;
 624
 625         *o_mcp_resp = mb_params.mcp_resp;
 626         *o_mcp_param = mb_params.mcp_param;
 627
 628         return ECORE_SUCCESS;
 629 }
 630
 631 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 632                                           struct ecore_ptt *p_ptt,
 633                                           u32 cmd,
 634                                           u32 param,
 635                                           u32 *o_mcp_resp,
 636                                           u32 *o_mcp_param,
 637                                           u32 *o_txn_size, u32 *o_buf)
 638 {
 639         struct ecore_mcp_mb_params mb_params;
 640         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 641         enum _ecore_status_t rc;
 642
 643         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 644         mb_params.cmd = cmd;
 645         mb_params.param = param;
 646         mb_params.p_data_dst = raw_data;
 647
 648         /* Use the maximal value since the actual one is part of the response */
 649         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 650
 651         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 652         if (rc != ECORE_SUCCESS)
 653                 return rc;
 654
 655         *o_mcp_resp = mb_params.mcp_resp;
 656         *o_mcp_param = mb_params.mcp_param;
 657
 658         *o_txn_size = *o_mcp_param;
 659         /* @DPDK */
 660         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 661
 662         return ECORE_SUCCESS;
 663 }
 664
 665 #ifndef ASIC_ONLY
 666 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 667                                     u32 *p_load_code)
 668 {
 669         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 670
 671         if (!loaded)
 672                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 673         else if (!loaded_port[p_hwfn->port_id])
 674                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 675         else
 676                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 677
 678         /* On CMT, always tell that it's engine */
 679         if (p_hwfn->p_dev->num_hwfns > 1)
 680                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 681
 682         *p_load_code = load_phase;
 683         loaded++;
 684         loaded_port[p_hwfn->port_id]++;
 685
 686         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 687                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 688                    *p_load_code, loaded, p_hwfn->port_id,
 689                    loaded_port[p_hwfn->port_id]);
 690 }
 691 #endif
 692
 693 static bool
 694 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 695                          enum ecore_override_force_load override_force_load)
 696 {
 697         bool can_force_load = false;
 698
 699         switch (override_force_load) {
 700         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 701                 can_force_load = true;
 702                 break;
 703         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 704                 can_force_load = false;
 705                 break;
 706         default:
 707                 can_force_load = (drv_role == DRV_ROLE_OS &&
 708                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 709                                  (drv_role == DRV_ROLE_KDUMP &&
 710                                   exist_drv_role == DRV_ROLE_OS);
 711                 break;
 712         }
 713
 714         return can_force_load;
 715 }
 716
 717 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 718                                                       struct ecore_ptt *p_ptt)
 719 {
 720         u32 resp = 0, param = 0;
 721         enum _ecore_status_t rc;
 722
 723         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 724                            &resp, &param);
 725         if (rc != ECORE_SUCCESS)
 726                 DP_NOTICE(p_hwfn, false,
 727                           "Failed to send cancel load request, rc = %d\n", rc);
 728
 729         return rc;
 730 }
 731
 732 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 733 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 734 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 735 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 736 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 737 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 738 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 739
 740 static u32 ecore_get_config_bitmap(void)
 741 {
 742         u32 config_bitmap = 0x0;
 743
 744 #ifdef CONFIG_ECORE_L2
 745         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 746 #endif
 747 #ifdef CONFIG_ECORE_SRIOV
 748         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 749 #endif
 750 #ifdef CONFIG_ECORE_ROCE
 751         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 752 #endif
 753 #ifdef CONFIG_ECORE_IWARP
 754         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 755 #endif
 756 #ifdef CONFIG_ECORE_FCOE
 757         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 758 #endif
 759 #ifdef CONFIG_ECORE_ISCSI
 760         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 761 #endif
 762 #ifdef CONFIG_ECORE_LL2
 763         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 764 #endif
 765
 766         return config_bitmap;
 767 }
 768
 769 struct ecore_load_req_in_params {
 770         u8 hsi_ver;
 771 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 772 #define ECORE_LOAD_REQ_HSI_VER_1        1
 773         u32 drv_ver_0;
 774         u32 drv_ver_1;
 775         u32 fw_ver;
 776         u8 drv_role;
 777         u8 timeout_val;
 778         u8 force_cmd;
 779         bool avoid_eng_reset;
 780 };
 781
 782 struct ecore_load_req_out_params {
 783         u32 load_code;
 784         u32 exist_drv_ver_0;
 785         u32 exist_drv_ver_1;
 786         u32 exist_fw_ver;
 787         u8 exist_drv_role;
 788         u8 mfw_hsi_ver;
 789         bool drv_exists;
 790 };
 791
 792 static enum _ecore_status_t
 793 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 794                      struct ecore_load_req_in_params *p_in_params,
 795                      struct ecore_load_req_out_params *p_out_params)
 796 {
 797         struct ecore_mcp_mb_params mb_params;
 798         struct load_req_stc load_req;
 799         struct load_rsp_stc load_rsp;
 800         u32 hsi_ver;
 801         enum _ecore_status_t rc;
 802
 803         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 804         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 805         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 806         load_req.fw_ver = p_in_params->fw_ver;
 807         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
 808                             p_in_params->drv_role);
 809         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 810                             p_in_params->timeout_val);
 811         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 812                             p_in_params->force_cmd);
 813         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 814                             p_in_params->avoid_eng_reset);
 815
 816         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 817                   DRV_ID_MCP_HSI_VER_CURRENT :
 818                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 819
 820         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 821         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 822         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 823         mb_params.p_data_src = &load_req;
 824         mb_params.data_src_size = sizeof(load_req);
 825         mb_params.p_data_dst = &load_rsp;
 826         mb_params.data_dst_size = sizeof(load_rsp);
 827
 828         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 829                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 830                    mb_params.param,
 831                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 832                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 833                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 834                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 835
 836         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 837                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 838                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 839                            load_req.drv_ver_0, load_req.drv_ver_1,
 840                            load_req.fw_ver, load_req.misc0,
 841                            ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 842                            ECORE_MFW_GET_FIELD(load_req.misc0,
 843                                                LOAD_REQ_LOCK_TO),
 844                            ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 845                            ECORE_MFW_GET_FIELD(load_req.misc0,
 846                                                LOAD_REQ_FLAGS0));
 847
 848         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 849         if (rc != ECORE_SUCCESS) {
 850                 DP_NOTICE(p_hwfn, false,
 851                           "Failed to send load request, rc = %d\n", rc);
 852                 return rc;
 853         }
 854
 855         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 856                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 857         p_out_params->load_code = mb_params.mcp_resp;
 858
 859         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 860             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 861                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 862                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 863                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 864                            load_rsp.fw_ver, load_rsp.misc0,
 865                            ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 866                            ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 867                            ECORE_MFW_GET_FIELD(load_rsp.misc0,
 868                                                LOAD_RSP_FLAGS0));
 869
 870                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 871                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 872                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 873                 p_out_params->exist_drv_role =
 874                         ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 875                 p_out_params->mfw_hsi_ver =
 876                         ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 877                 p_out_params->drv_exists =
 878                         ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 879                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 880         }
 881
 882         return ECORE_SUCCESS;
 883 }
 884
 885 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
 886                                    enum ecore_drv_role drv_role,
 887                                    u8 *p_mfw_drv_role)
 888 {
 889         switch (drv_role) {
 890         case ECORE_DRV_ROLE_OS:
 891                 *p_mfw_drv_role = DRV_ROLE_OS;
 892                 break;
 893         case ECORE_DRV_ROLE_KDUMP:
 894                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 895                 break;
 896         }
 897 }
 898
 899 enum ecore_load_req_force {
 900         ECORE_LOAD_REQ_FORCE_NONE,
 901         ECORE_LOAD_REQ_FORCE_PF,
 902         ECORE_LOAD_REQ_FORCE_ALL,
 903 };
 904
 905 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
 906                                     enum ecore_load_req_force force_cmd,
 907                                     u8 *p_mfw_force_cmd)
 908 {
 909         switch (force_cmd) {
 910         case ECORE_LOAD_REQ_FORCE_NONE:
 911                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 912                 break;
 913         case ECORE_LOAD_REQ_FORCE_PF:
 914                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 915                 break;
 916         case ECORE_LOAD_REQ_FORCE_ALL:
 917                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 918                 break;
 919         }
 920 }
 921
 922 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 923                                         struct ecore_ptt *p_ptt,
 924                                         struct ecore_load_req_params *p_params)
 925 {
 926         struct ecore_load_req_out_params out_params;
 927         struct ecore_load_req_in_params in_params;
 928         u8 mfw_drv_role = 0, mfw_force_cmd;
 929         enum _ecore_status_t rc;
 930
 931 #ifndef ASIC_ONLY
 932         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 933                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 934                 return ECORE_SUCCESS;
 935         }
 936 #endif
 937
 938         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 939         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 940         in_params.drv_ver_0 = ECORE_VERSION;
 941         in_params.drv_ver_1 = ecore_get_config_bitmap();
 942         in_params.fw_ver = STORM_FW_VERSION;
 943         ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 944         in_params.drv_role = mfw_drv_role;
 945         in_params.timeout_val = p_params->timeout_val;
 946         ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
 947                                 &mfw_force_cmd);
 948         in_params.force_cmd = mfw_force_cmd;
 949         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 950
 951         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 952         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 953         if (rc != ECORE_SUCCESS)
 954                 return rc;
 955
 956         /* First handle cases where another load request should/might be sent:
 957          * - MFW expects the old interface [HSI version = 1]
 958          * - MFW responds that a force load request is required
 959          */
 960         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 961                 DP_INFO(p_hwfn,
 962                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 963
 964                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 965                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 966                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 967                                           &out_params);
 968                 if (rc != ECORE_SUCCESS)
 969                         return rc;
 970         } else if (out_params.load_code ==
 971                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 972                 if (ecore_mcp_can_force_load(in_params.drv_role,
 973                                              out_params.exist_drv_role,
 974                                              p_params->override_force_load)) {
 975                         DP_INFO(p_hwfn,
 976                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
 977                                 in_params.drv_role, in_params.fw_ver,
 978                                 in_params.drv_ver_0, in_params.drv_ver_1,
 979                                 out_params.exist_drv_role,
 980                                 out_params.exist_fw_ver,
 981                                 out_params.exist_drv_ver_0,
 982                                 out_params.exist_drv_ver_1);
 983
 984                         ecore_get_mfw_force_cmd(p_hwfn,
 985                                                 ECORE_LOAD_REQ_FORCE_ALL,
 986                                                 &mfw_force_cmd);
 987
 988                         in_params.force_cmd = mfw_force_cmd;
 989                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 990                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 991                                                   &out_params);
 992                         if (rc != ECORE_SUCCESS)
 993                                 return rc;
 994                 } else {
 995                         DP_NOTICE(p_hwfn, false,
 996                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
 997                                   in_params.drv_role, in_params.fw_ver,
 998                                   in_params.drv_ver_0, in_params.drv_ver_1,
 999                                   out_params.exist_drv_role,
1000                                   out_params.exist_fw_ver,
1001                                   out_params.exist_drv_ver_0,
1002                                   out_params.exist_drv_ver_1);
1003
1004                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1005                         return ECORE_BUSY;
1006                 }
1007         }
1008
1009         /* Now handle the other types of responses.
1010          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1011          * expected here after the additional revised load requests were sent.
1012          */
1013         switch (out_params.load_code) {
1014         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1015         case FW_MSG_CODE_DRV_LOAD_PORT:
1016         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1017                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1018                     out_params.drv_exists) {
1019                         /* The role and fw/driver version match, but the PF is
1020                          * already loaded and has not been unloaded gracefully.
1021                          * This is unexpected since a quasi-FLR request was
1022                          * previously sent as part of ecore_hw_prepare().
1023                          */
1024                         DP_NOTICE(p_hwfn, false,
1025                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1026                         return ECORE_INVAL;
1027                 }
1028                 break;
1029         default:
1030                 DP_NOTICE(p_hwfn, false,
1031                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1032                           out_params.load_code);
1033                 return ECORE_BUSY;
1034         }
1035
1036         p_params->load_code = out_params.load_code;
1037
1038         return ECORE_SUCCESS;
1039 }
1040
1041 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1042                                          struct ecore_ptt *p_ptt)
1043 {
1044         u32 resp = 0, param = 0;
1045         enum _ecore_status_t rc;
1046
1047         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1048                            &param);
1049         if (rc != ECORE_SUCCESS) {
1050                 DP_NOTICE(p_hwfn, false,
1051                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1052                 return rc;
1053         }
1054
1055 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR     (1 << 0)
1056
1057         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1058         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1059                 DP_NOTICE(p_hwfn, false,
1060                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1061
1062         return ECORE_SUCCESS;
1063 }
1064
1065 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1066                                           struct ecore_ptt *p_ptt)
1067 {
1068         u32 wol_param, mcp_resp, mcp_param;
1069
1070         /* @DPDK */
1071         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1072
1073         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1074                              &mcp_resp, &mcp_param);
1075 }
1076
1077 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1078                                            struct ecore_ptt *p_ptt)
1079 {
1080         struct ecore_mcp_mb_params mb_params;
1081         struct mcp_mac wol_mac;
1082
1083         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1084         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1085
1086         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1087 }
1088
1089 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1090                                     struct ecore_ptt *p_ptt)
1091 {
1092         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1093                                         PUBLIC_PATH);
1094         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1095         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1096                                      ECORE_PATH_ID(p_hwfn));
1097         u32 disabled_vfs[VF_MAX_STATIC / 32];
1098         int i;
1099
1100         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1101                    "Reading Disabled VF information from [offset %08x],"
1102                    " path_addr %08x\n",
1103                    mfw_path_offsize, path_addr);
1104
1105         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1106                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1107                                            path_addr +
1108                                            OFFSETOF(struct public_path,
1109                                                     mcp_vf_disabled) +
1110                                            sizeof(u32) * i);
1111                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1112                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1113                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1114         }
1115
1116         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1117                 OSAL_VF_FLR_UPDATE(p_hwfn);
1118 }
1119
1120 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1121                                           struct ecore_ptt *p_ptt,
1122                                           u32 *vfs_to_ack)
1123 {
1124         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1125                                         PUBLIC_FUNC);
1126         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1127         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1128                                      MCP_PF_ID(p_hwfn));
1129         struct ecore_mcp_mb_params mb_params;
1130         enum _ecore_status_t rc;
1131         int i;
1132
1133         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1134                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1135                            "Acking VFs [%08x,...,%08x] - %08x\n",
1136                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1137
1138         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1139         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1140         mb_params.p_data_src = vfs_to_ack;
1141         mb_params.data_src_size = VF_MAX_STATIC / 8;
1142         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1143                                      &mb_params);
1144         if (rc != ECORE_SUCCESS) {
1145                 DP_NOTICE(p_hwfn, false,
1146                           "Failed to pass ACK for VF flr to MFW\n");
1147                 return ECORE_TIMEOUT;
1148         }
1149
1150         /* TMP - clear the ACK bits; should be done by MFW */
1151         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1152                 ecore_wr(p_hwfn, p_ptt,
1153                          func_addr +
1154                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1155                          i * sizeof(u32), 0);
1156
1157         return rc;
1158 }
1159
1160 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1161                                                 struct ecore_ptt *p_ptt)
1162 {
1163         u32 transceiver_state;
1164
1165         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1166                                      p_hwfn->mcp_info->port_addr +
1167                                      OFFSETOF(struct public_port,
1168                                               transceiver_data));
1169
1170         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1171                    "Received transceiver state update [0x%08x] from mfw"
1172                    " [Addr 0x%x]\n",
1173                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1174                                             OFFSETOF(struct public_port,
1175                                                      transceiver_data)));
1176
1177         transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
1178
1179         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1180                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1181         else
1182                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1183 }
1184
1185 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1186                                       struct ecore_ptt *p_ptt,
1187                                       struct ecore_mcp_link_state *p_link)
1188 {
1189         u32 eee_status, val;
1190
1191         p_link->eee_adv_caps = 0;
1192         p_link->eee_lp_adv_caps = 0;
1193         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1194                                      OFFSETOF(struct public_port, eee_status));
1195         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1196         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_SHIFT;
1197         if (val & EEE_1G_ADV)
1198                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1199         if (val & EEE_10G_ADV)
1200                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1201         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_SHIFT;
1202         if (val & EEE_1G_ADV)
1203                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1204         if (val & EEE_10G_ADV)
1205                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1206 }
1207
1208 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1209                                          struct ecore_ptt *p_ptt,
1210                                          bool b_reset)
1211 {
1212         struct ecore_mcp_link_state *p_link;
1213         u8 max_bw, min_bw;
1214         u32 status = 0;
1215
1216         /* Prevent SW/attentions from doing this at the same time */
1217         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1218
1219         p_link = &p_hwfn->mcp_info->link_output;
1220         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1221         if (!b_reset) {
1222                 status = ecore_rd(p_hwfn, p_ptt,
1223                                   p_hwfn->mcp_info->port_addr +
1224                                   OFFSETOF(struct public_port, link_status));
1225                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1226                            "Received link update [0x%08x] from mfw"
1227                            " [Addr 0x%x]\n",
1228                            status, (u32)(p_hwfn->mcp_info->port_addr +
1229                                           OFFSETOF(struct public_port,
1230                                                    link_status)));
1231         } else {
1232                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1233                            "Resetting link indications\n");
1234                 goto out;
1235         }
1236
1237         if (p_hwfn->b_drv_link_init)
1238                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1239         else
1240                 p_link->link_up = false;
1241
1242         p_link->full_duplex = true;
1243         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1244         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1245                 p_link->speed = 100000;
1246                 break;
1247         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1248                 p_link->speed = 50000;
1249                 break;
1250         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1251                 p_link->speed = 40000;
1252                 break;
1253         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1254                 p_link->speed = 25000;
1255                 break;
1256         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1257                 p_link->speed = 20000;
1258                 break;
1259         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1260                 p_link->speed = 10000;
1261                 break;
1262         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1263                 p_link->full_duplex = false;
1264                 /* Fall-through */
1265         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1266                 p_link->speed = 1000;
1267                 break;
1268         default:
1269                 p_link->speed = 0;
1270         }
1271
1272         /* We never store total line speed as p_link->speed is
1273          * again changes according to bandwidth allocation.
1274          */
1275         if (p_link->link_up && p_link->speed)
1276                 p_link->line_speed = p_link->speed;
1277         else
1278                 p_link->line_speed = 0;
1279
1280         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1281         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1282
1283         /* Max bandwidth configuration */
1284         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1285                                            p_link, max_bw);
1286
1287         /* Mintz bandwidth configuration */
1288         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1289                                            p_link, min_bw);
1290         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1291                                               p_link->min_pf_rate);
1292
1293         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1294         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1295         p_link->parallel_detection = !!(status &
1296                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1297         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1298
1299         p_link->partner_adv_speed |=
1300             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1301             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1302         p_link->partner_adv_speed |=
1303             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1304             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1305         p_link->partner_adv_speed |=
1306             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1307             ECORE_LINK_PARTNER_SPEED_10G : 0;
1308         p_link->partner_adv_speed |=
1309             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1310             ECORE_LINK_PARTNER_SPEED_20G : 0;
1311         p_link->partner_adv_speed |=
1312             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1313             ECORE_LINK_PARTNER_SPEED_25G : 0;
1314         p_link->partner_adv_speed |=
1315             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1316             ECORE_LINK_PARTNER_SPEED_40G : 0;
1317         p_link->partner_adv_speed |=
1318             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1319             ECORE_LINK_PARTNER_SPEED_50G : 0;
1320         p_link->partner_adv_speed |=
1321             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1322             ECORE_LINK_PARTNER_SPEED_100G : 0;
1323
1324         p_link->partner_tx_flow_ctrl_en =
1325             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1326         p_link->partner_rx_flow_ctrl_en =
1327             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1328
1329         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1330         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1331                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1332                 break;
1333         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1334                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1335                 break;
1336         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1337                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1338                 break;
1339         default:
1340                 p_link->partner_adv_pause = 0;
1341         }
1342
1343         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1344
1345         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1346                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1347
1348         OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1349 out:
1350         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1351 }
1352
1353 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1354                                         struct ecore_ptt *p_ptt, bool b_up)
1355 {
1356         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1357         struct ecore_mcp_mb_params mb_params;
1358         struct eth_phy_cfg phy_cfg;
1359         enum _ecore_status_t rc = ECORE_SUCCESS;
1360         u32 cmd;
1361
1362 #ifndef ASIC_ONLY
1363         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1364                 return ECORE_SUCCESS;
1365 #endif
1366
1367         /* Set the shmem configuration according to params */
1368         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1369         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1370         if (!params->speed.autoneg)
1371                 phy_cfg.speed = params->speed.forced_speed;
1372         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1373         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1374         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1375         phy_cfg.adv_speed = params->speed.advertised_speeds;
1376         phy_cfg.loopback_mode = params->loopback_mode;
1377
1378         /* There are MFWs that share this capability regardless of whether
1379          * this is feasible or not. And given that at the very least adv_caps
1380          * would be set internally by ecore, we want to make sure LFA would
1381          * still work.
1382          */
1383         if ((p_hwfn->mcp_info->capabilities &
1384              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1385             params->eee.enable) {
1386                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1387                 if (params->eee.tx_lpi_enable)
1388                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1389                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1390                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1391                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1392                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1393                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1394                                     EEE_TX_TIMER_USEC_SHIFT) &
1395                                         EEE_TX_TIMER_USEC_MASK;
1396         }
1397
1398         p_hwfn->b_drv_link_init = b_up;
1399
1400         if (b_up)
1401                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1402                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1403                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1404                            phy_cfg.loopback_mode);
1405         else
1406                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1407
1408         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1409         mb_params.cmd = cmd;
1410         mb_params.p_data_src = &phy_cfg;
1411         mb_params.data_src_size = sizeof(phy_cfg);
1412         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1413
1414         /* if mcp fails to respond we must abort */
1415         if (rc != ECORE_SUCCESS) {
1416                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1417                 return rc;
1418         }
1419
1420         /* Mimic link-change attention, done for several reasons:
1421          *  - On reset, there's no guarantee MFW would trigger
1422          *    an attention.
1423          *  - On initialization, older MFWs might not indicate link change
1424          *    during LFA, so we'll never get an UP indication.
1425          */
1426         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1427
1428         return rc;
1429 }
1430
1431 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1432                                    struct ecore_ptt *p_ptt)
1433 {
1434         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1435
1436         /* TODO - Add support for VFs */
1437         if (IS_VF(p_hwfn->p_dev))
1438                 return ECORE_INVAL;
1439
1440         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1441                                                  PUBLIC_PATH);
1442         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1443         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1444
1445         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1446                                  path_addr +
1447                                  OFFSETOF(struct public_path, process_kill)) &
1448             PROCESS_KILL_COUNTER_MASK;
1449
1450         return proc_kill_cnt;
1451 }
1452
1453 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1454                                           struct ecore_ptt *p_ptt)
1455 {
1456         struct ecore_dev *p_dev = p_hwfn->p_dev;
1457         u32 proc_kill_cnt;
1458
1459         /* Prevent possible attentions/interrupts during the recovery handling
1460          * and till its load phase, during which they will be re-enabled.
1461          */
1462         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1463
1464         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1465
1466         /* The following operations should be done once, and thus in CMT mode
1467          * are carried out by only the first HW function.
1468          */
1469         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1470                 return;
1471
1472         if (p_dev->recov_in_prog) {
1473                 DP_NOTICE(p_hwfn, false,
1474                           "Ignoring the indication since a recovery"
1475                           " process is already in progress\n");
1476                 return;
1477         }
1478
1479         p_dev->recov_in_prog = true;
1480
1481         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1482         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1483
1484         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1485 }
1486
1487 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1488                                           struct ecore_ptt *p_ptt,
1489                                           enum MFW_DRV_MSG_TYPE type)
1490 {
1491         enum ecore_mcp_protocol_type stats_type;
1492         union ecore_mcp_protocol_stats stats;
1493         struct ecore_mcp_mb_params mb_params;
1494         u32 hsi_param;
1495         enum _ecore_status_t rc;
1496
1497         switch (type) {
1498         case MFW_DRV_MSG_GET_LAN_STATS:
1499                 stats_type = ECORE_MCP_LAN_STATS;
1500                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1501                 break;
1502         default:
1503                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1504                 return;
1505         }
1506
1507         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1508
1509         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1510         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1511         mb_params.param = hsi_param;
1512         mb_params.p_data_src = &stats;
1513         mb_params.data_src_size = sizeof(stats);
1514         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1515         if (rc != ECORE_SUCCESS)
1516                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1517 }
1518
1519 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1520                                     struct public_func *p_shmem_info)
1521 {
1522         struct ecore_mcp_function_info *p_info;
1523
1524         p_info = &p_hwfn->mcp_info->func_info;
1525
1526         /* TODO - bandwidth min/max should have valid values of 1-100,
1527          * as well as some indication that the feature is disabled.
1528          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1529          * limit and correct value to min `1' and max `100' if limit isn't in
1530          * range.
1531          */
1532         p_info->bandwidth_min = (p_shmem_info->config &
1533                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1534             FUNC_MF_CFG_MIN_BW_SHIFT;
1535         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1536                 DP_INFO(p_hwfn,
1537                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1538                         p_info->bandwidth_min);
1539                 p_info->bandwidth_min = 1;
1540         }
1541
1542         p_info->bandwidth_max = (p_shmem_info->config &
1543                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1544             FUNC_MF_CFG_MAX_BW_SHIFT;
1545         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1546                 DP_INFO(p_hwfn,
1547                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1548                         p_info->bandwidth_max);
1549                 p_info->bandwidth_max = 100;
1550         }
1551 }
1552
1553 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1554                                     struct ecore_ptt *p_ptt,
1555                                     struct public_func *p_data,
1556                                     int pfid)
1557 {
1558         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1559                                         PUBLIC_FUNC);
1560         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1561         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1562         u32 i, size;
1563
1564         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1565
1566         size = OSAL_MIN_T(u32, sizeof(*p_data),
1567                           SECTION_SIZE(mfw_path_offsize));
1568         for (i = 0; i < size / sizeof(u32); i++)
1569                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1570                                               func_addr + (i << 2));
1571
1572         return size;
1573 }
1574
1575 static void
1576 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1577 {
1578         struct ecore_mcp_function_info *p_info;
1579         struct public_func shmem_info;
1580         u32 resp = 0, param = 0;
1581
1582         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1583
1584         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1585
1586         p_info = &p_hwfn->mcp_info->func_info;
1587
1588         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1589
1590         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1591
1592         /* Acknowledge the MFW */
1593         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1594                       &param);
1595 }
1596
1597 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1598                                          struct ecore_ptt *p_ptt)
1599 {
1600         /* A single notification should be sent to upper driver in CMT mode */
1601         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1602                 return;
1603
1604         DP_NOTICE(p_hwfn, false,
1605                   "Fan failure was detected on the network interface card"
1606                   " and it's going to be shut down.\n");
1607
1608         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1609 }
1610
1611 struct ecore_mdump_cmd_params {
1612         u32 cmd;
1613         void *p_data_src;
1614         u8 data_src_size;
1615         void *p_data_dst;
1616         u8 data_dst_size;
1617         u32 mcp_resp;
1618 };
1619
1620 static enum _ecore_status_t
1621 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1622                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1623 {
1624         struct ecore_mcp_mb_params mb_params;
1625         enum _ecore_status_t rc;
1626
1627         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1628         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1629         mb_params.param = p_mdump_cmd_params->cmd;
1630         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1631         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1632         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1633         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1634         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1635         if (rc != ECORE_SUCCESS)
1636                 return rc;
1637
1638         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1639
1640         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1641                 DP_INFO(p_hwfn,
1642                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1643                         p_mdump_cmd_params->cmd);
1644                 rc = ECORE_NOTIMPL;
1645         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1646                 DP_INFO(p_hwfn,
1647                         "The mdump command is not supported by the MFW\n");
1648                 rc = ECORE_NOTIMPL;
1649         }
1650
1651         return rc;
1652 }
1653
1654 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1655                                                 struct ecore_ptt *p_ptt)
1656 {
1657         struct ecore_mdump_cmd_params mdump_cmd_params;
1658
1659         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1660         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1661
1662         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1663 }
1664
1665 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1666                                                 struct ecore_ptt *p_ptt,
1667                                                 u32 epoch)
1668 {
1669         struct ecore_mdump_cmd_params mdump_cmd_params;
1670
1671         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1672         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1673         mdump_cmd_params.p_data_src = &epoch;
1674         mdump_cmd_params.data_src_size = sizeof(epoch);
1675
1676         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1677 }
1678
1679 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1680                                              struct ecore_ptt *p_ptt)
1681 {
1682         struct ecore_mdump_cmd_params mdump_cmd_params;
1683
1684         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1685         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1686
1687         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1688 }
1689
1690 static enum _ecore_status_t
1691 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1692                            struct mdump_config_stc *p_mdump_config)
1693 {
1694         struct ecore_mdump_cmd_params mdump_cmd_params;
1695         enum _ecore_status_t rc;
1696
1697         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1698         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1699         mdump_cmd_params.p_data_dst = p_mdump_config;
1700         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1701
1702         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1703         if (rc != ECORE_SUCCESS)
1704                 return rc;
1705
1706         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1707                 DP_INFO(p_hwfn,
1708                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1709                         mdump_cmd_params.mcp_resp);
1710                 rc = ECORE_UNKNOWN_ERROR;
1711         }
1712
1713         return rc;
1714 }
1715
1716 enum _ecore_status_t
1717 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1718                          struct ecore_mdump_info *p_mdump_info)
1719 {
1720         u32 addr, global_offsize, global_addr;
1721         struct mdump_config_stc mdump_config;
1722         enum _ecore_status_t rc;
1723
1724         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1725
1726         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1727                                     PUBLIC_GLOBAL);
1728         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1729         global_addr = SECTION_ADDR(global_offsize, 0);
1730         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1731                                         global_addr +
1732                                         OFFSETOF(struct public_global,
1733                                                  mdump_reason));
1734
1735         if (p_mdump_info->reason) {
1736                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1737                 if (rc != ECORE_SUCCESS)
1738                         return rc;
1739
1740                 p_mdump_info->version = mdump_config.version;
1741                 p_mdump_info->config = mdump_config.config;
1742                 p_mdump_info->epoch = mdump_config.epoc;
1743                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1744                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1745
1746                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1747                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1748                            p_mdump_info->reason, p_mdump_info->version,
1749                            p_mdump_info->config, p_mdump_info->epoch,
1750                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1751         } else {
1752                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1753                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1754         }
1755
1756         return ECORE_SUCCESS;
1757 }
1758
1759 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1760                                                 struct ecore_ptt *p_ptt)
1761 {
1762         struct ecore_mdump_cmd_params mdump_cmd_params;
1763
1764         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1765         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1766
1767         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1768 }
1769
1770 enum _ecore_status_t
1771 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1772                            struct ecore_mdump_retain_data *p_mdump_retain)
1773 {
1774         struct ecore_mdump_cmd_params mdump_cmd_params;
1775         struct mdump_retain_data_stc mfw_mdump_retain;
1776         enum _ecore_status_t rc;
1777
1778         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1779         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1780         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1781         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1782
1783         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1784         if (rc != ECORE_SUCCESS)
1785                 return rc;
1786
1787         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1788                 DP_INFO(p_hwfn,
1789                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1790                         mdump_cmd_params.mcp_resp);
1791                 return ECORE_UNKNOWN_ERROR;
1792         }
1793
1794         p_mdump_retain->valid = mfw_mdump_retain.valid;
1795         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1796         p_mdump_retain->pf = mfw_mdump_retain.pf;
1797         p_mdump_retain->status = mfw_mdump_retain.status;
1798
1799         return ECORE_SUCCESS;
1800 }
1801
1802 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1803                                                 struct ecore_ptt *p_ptt)
1804 {
1805         struct ecore_mdump_cmd_params mdump_cmd_params;
1806
1807         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1808         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1809
1810         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1811 }
1812
1813 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1814                                             struct ecore_ptt *p_ptt)
1815 {
1816         struct ecore_mdump_retain_data mdump_retain;
1817         enum _ecore_status_t rc;
1818
1819         /* In CMT mode - no need for more than a single acknowledgment to the
1820          * MFW, and no more than a single notification to the upper driver.
1821          */
1822         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1823                 return;
1824
1825         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1826         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1827                 DP_NOTICE(p_hwfn, false,
1828                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1829                           mdump_retain.epoch, mdump_retain.pf,
1830                           mdump_retain.status);
1831         } else {
1832                 DP_NOTICE(p_hwfn, false,
1833                           "The MFW notified that a critical error occurred in the device\n");
1834         }
1835
1836         if (p_hwfn->p_dev->allow_mdump) {
1837                 DP_NOTICE(p_hwfn, false,
1838                           "Not acknowledging the notification to allow the MFW crash dump\n");
1839                 return;
1840         }
1841
1842         DP_NOTICE(p_hwfn, false,
1843                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1844         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1845         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1846 }
1847
1848 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1849                                              struct ecore_ptt *p_ptt)
1850 {
1851         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1852         enum _ecore_status_t rc = ECORE_SUCCESS;
1853         bool found = false;
1854         u16 i;
1855
1856         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1857
1858         /* Read Messages from MFW */
1859         ecore_mcp_read_mb(p_hwfn, p_ptt);
1860
1861         /* Compare current messages to old ones */
1862         for (i = 0; i < info->mfw_mb_length; i++) {
1863                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1864                         continue;
1865
1866                 found = true;
1867
1868                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1869                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1870                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1871
1872                 switch (i) {
1873                 case MFW_DRV_MSG_LINK_CHANGE:
1874                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1875                         break;
1876                 case MFW_DRV_MSG_VF_DISABLED:
1877                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1878                         break;
1879                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1880                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1881                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1882                         break;
1883                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1884                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1885                                                     ECORE_DCBX_REMOTE_MIB);
1886                         break;
1887                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1888                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1889                                                     ECORE_DCBX_OPERATIONAL_MIB);
1890                         break;
1891                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1892                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1893                         break;
1894                 case MFW_DRV_MSG_ERROR_RECOVERY:
1895                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1896                         break;
1897                 case MFW_DRV_MSG_GET_LAN_STATS:
1898                 case MFW_DRV_MSG_GET_FCOE_STATS:
1899                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1900                 case MFW_DRV_MSG_GET_RDMA_STATS:
1901                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1902                         break;
1903                 case MFW_DRV_MSG_BW_UPDATE:
1904                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1905                         break;
1906                 case MFW_DRV_MSG_FAILURE_DETECTED:
1907                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1908                         break;
1909                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1910                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1911                         break;
1912                 default:
1913                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1914                         rc = ECORE_INVAL;
1915                 }
1916         }
1917
1918         /* ACK everything */
1919         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1920                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1921
1922                 /* MFW expect answer in BE, so we force write in that format */
1923                 ecore_wr(p_hwfn, p_ptt,
1924                          info->mfw_mb_addr + sizeof(u32) +
1925                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1926                          sizeof(u32) + i * sizeof(u32), val);
1927         }
1928
1929         if (!found) {
1930                 DP_NOTICE(p_hwfn, false,
1931                           "Received an MFW message indication but no"
1932                           " new message!\n");
1933                 rc = ECORE_INVAL;
1934         }
1935
1936         /* Copy the new mfw messages into the shadow */
1937         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1938
1939         return rc;
1940 }
1941
1942 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1943                                            struct ecore_ptt *p_ptt,
1944                                            u32 *p_mfw_ver,
1945                                            u32 *p_running_bundle_id)
1946 {
1947         u32 global_offsize;
1948
1949 #ifndef ASIC_ONLY
1950         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1951                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1952                 return ECORE_SUCCESS;
1953         }
1954 #endif
1955
1956         if (IS_VF(p_hwfn->p_dev)) {
1957                 if (p_hwfn->vf_iov_info) {
1958                         struct pfvf_acquire_resp_tlv *p_resp;
1959
1960                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1961                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1962                         return ECORE_SUCCESS;
1963                 } else {
1964                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1965                                    "VF requested MFW version prior to ACQUIRE\n");
1966                         return ECORE_INVAL;
1967                 }
1968         }
1969
1970         global_offsize = ecore_rd(p_hwfn, p_ptt,
1971                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1972                                                        public_base,
1973                                                        PUBLIC_GLOBAL));
1974         *p_mfw_ver =
1975             ecore_rd(p_hwfn, p_ptt,
1976                      SECTION_ADDR(global_offsize,
1977                                   0) + OFFSETOF(struct public_global, mfw_ver));
1978
1979         if (p_running_bundle_id != OSAL_NULL) {
1980                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1981                                                 SECTION_ADDR(global_offsize,
1982                                                              0) +
1983                                                 OFFSETOF(struct public_global,
1984                                                          running_bundle_id));
1985         }
1986
1987         return ECORE_SUCCESS;
1988 }
1989
1990 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
1991                                               struct ecore_ptt *p_ptt,
1992                                               u32 *p_media_type)
1993 {
1994
1995         /* TODO - Add support for VFs */
1996         if (IS_VF(p_hwfn->p_dev))
1997                 return ECORE_INVAL;
1998
1999         if (!ecore_mcp_is_init(p_hwfn)) {
2000                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2001                 return ECORE_BUSY;
2002         }
2003
2004         if (!p_ptt) {
2005                 *p_media_type = MEDIA_UNSPECIFIED;
2006                 return ECORE_INVAL;
2007         } else {
2008                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2009                                          p_hwfn->mcp_info->port_addr +
2010                                          OFFSETOF(struct public_port,
2011                                                   media_type));
2012         }
2013
2014         return ECORE_SUCCESS;
2015 }
2016
2017 /* @DPDK */
2018 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2019 static void
2020 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2021                                  enum ecore_pci_personality *p_proto)
2022 {
2023         *p_proto = ECORE_PCI_ETH;
2024
2025         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2026                    "According to Legacy capabilities, L2 personality is %08x\n",
2027                    (u32)*p_proto);
2028 }
2029
2030 /* @DPDK */
2031 static enum _ecore_status_t
2032 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2033                               struct ecore_ptt *p_ptt,
2034                               enum ecore_pci_personality *p_proto)
2035 {
2036         u32 resp = 0, param = 0;
2037         enum _ecore_status_t rc;
2038
2039         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2040                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2041                    (u32)*p_proto, resp, param);
2042         return ECORE_SUCCESS;
2043 }
2044
2045 static enum _ecore_status_t
2046 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2047                           struct public_func *p_info,
2048                           struct ecore_ptt *p_ptt,
2049                           enum ecore_pci_personality *p_proto)
2050 {
2051         enum _ecore_status_t rc = ECORE_SUCCESS;
2052
2053         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2054         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2055                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2056                     ECORE_SUCCESS)
2057                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2058                 break;
2059         default:
2060                 rc = ECORE_INVAL;
2061         }
2062
2063         return rc;
2064 }
2065
2066 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2067                                                     struct ecore_ptt *p_ptt)
2068 {
2069         struct ecore_mcp_function_info *info;
2070         struct public_func shmem_info;
2071
2072         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2073         info = &p_hwfn->mcp_info->func_info;
2074
2075         info->pause_on_host = (shmem_info.config &
2076                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2077
2078         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2079                                       &info->protocol)) {
2080                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2081                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2082                 return ECORE_INVAL;
2083         }
2084
2085         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2086
2087         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2088                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2089                 info->mac[1] = (u8)(shmem_info.mac_upper);
2090                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2091                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2092                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2093                 info->mac[5] = (u8)(shmem_info.mac_lower);
2094         } else {
2095                 /* TODO - are there protocols for which there's no MAC? */
2096                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2097         }
2098
2099         /* TODO - are these calculations true for BE machine? */
2100         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2101                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2102         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2103                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2104
2105         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2106
2107         info->mtu = (u16)shmem_info.mtu_size;
2108
2109         if (info->mtu == 0)
2110                 info->mtu = 1500;
2111
2112         info->mtu = (u16)shmem_info.mtu_size;
2113
2114         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2115                    "Read configuration from shmem: pause_on_host %02x"
2116                     " protocol %02x BW [%02x - %02x]"
2117                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2118                     " node %lx ovlan %04x\n",
2119                    info->pause_on_host, info->protocol,
2120                    info->bandwidth_min, info->bandwidth_max,
2121                    info->mac[0], info->mac[1], info->mac[2],
2122                    info->mac[3], info->mac[4], info->mac[5],
2123                    (unsigned long)info->wwn_port,
2124                    (unsigned long)info->wwn_node, info->ovlan);
2125
2126         return ECORE_SUCCESS;
2127 }
2128
2129 struct ecore_mcp_link_params
2130 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2131 {
2132         if (!p_hwfn || !p_hwfn->mcp_info)
2133                 return OSAL_NULL;
2134         return &p_hwfn->mcp_info->link_input;
2135 }
2136
2137 struct ecore_mcp_link_state
2138 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2139 {
2140         if (!p_hwfn || !p_hwfn->mcp_info)
2141                 return OSAL_NULL;
2142
2143 #ifndef ASIC_ONLY
2144         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2145                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2146                 p_hwfn->mcp_info->link_output.link_up = true;
2147         }
2148 #endif
2149
2150         return &p_hwfn->mcp_info->link_output;
2151 }
2152
2153 struct ecore_mcp_link_capabilities
2154 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2155 {
2156         if (!p_hwfn || !p_hwfn->mcp_info)
2157                 return OSAL_NULL;
2158         return &p_hwfn->mcp_info->link_capabilities;
2159 }
2160
2161 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2162                                      struct ecore_ptt *p_ptt)
2163 {
2164         u32 resp = 0, param = 0;
2165         enum _ecore_status_t rc;
2166
2167         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2168                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2169
2170         /* Wait for the drain to complete before returning */
2171         OSAL_MSLEEP(1020);
2172
2173         return rc;
2174 }
2175
2176 const struct ecore_mcp_function_info
2177 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2178 {
2179         if (!p_hwfn || !p_hwfn->mcp_info)
2180                 return OSAL_NULL;
2181         return &p_hwfn->mcp_info->func_info;
2182 }
2183
2184 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2185                                   struct ecore_ptt *p_ptt, u32 personalities)
2186 {
2187         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2188         struct public_func shmem_info;
2189         int i, count = 0, num_pfs;
2190
2191         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2192
2193         for (i = 0; i < num_pfs; i++) {
2194                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2195                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2196                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2197                         continue;
2198
2199                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2200                                               &protocol) !=
2201                     ECORE_SUCCESS)
2202                         continue;
2203
2204                 if ((1 << ((u32)protocol)) & personalities)
2205                         count++;
2206         }
2207
2208         return count;
2209 }
2210
2211 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2212                                               struct ecore_ptt *p_ptt,
2213                                               u32 *p_flash_size)
2214 {
2215         u32 flash_size;
2216
2217 #ifndef ASIC_ONLY
2218         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2219                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2220                 return ECORE_INVAL;
2221         }
2222 #endif
2223
2224         if (IS_VF(p_hwfn->p_dev))
2225                 return ECORE_INVAL;
2226
2227         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2228         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2229             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2230         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2231
2232         *p_flash_size = flash_size;
2233
2234         return ECORE_SUCCESS;
2235 }
2236
2237 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2238                                                   struct ecore_ptt *p_ptt)
2239 {
2240         struct ecore_dev *p_dev = p_hwfn->p_dev;
2241
2242         if (p_dev->recov_in_prog) {
2243                 DP_NOTICE(p_hwfn, false,
2244                           "Avoid triggering a recovery since such a process"
2245                           " is already in progress\n");
2246                 return ECORE_AGAIN;
2247         }
2248
2249         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2250         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2251
2252         return ECORE_SUCCESS;
2253 }
2254
2255 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2256                                               struct ecore_ptt *p_ptt,
2257                                               u8 vf_id, u8 num)
2258 {
2259         u32 resp = 0, param = 0, rc_param = 0;
2260         enum _ecore_status_t rc;
2261
2262 /* Only Leader can configure MSIX, and need to take CMT into account */
2263
2264         if (!IS_LEAD_HWFN(p_hwfn))
2265                 return ECORE_SUCCESS;
2266         num *= p_hwfn->p_dev->num_hwfns;
2267
2268         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2269             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2270         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2271             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2272
2273         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2274                            &resp, &rc_param);
2275
2276         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2277                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2278                           vf_id);
2279                 rc = ECORE_INVAL;
2280         } else {
2281                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2282                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2283                             num, vf_id);
2284         }
2285
2286         return rc;
2287 }
2288
2289 enum _ecore_status_t
2290 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2291                            struct ecore_mcp_drv_version *p_ver)
2292 {
2293         struct ecore_mcp_mb_params mb_params;
2294         struct drv_version_stc drv_version;
2295         u32 num_words, i;
2296         void *p_name;
2297         OSAL_BE32 val;
2298         enum _ecore_status_t rc;
2299
2300 #ifndef ASIC_ONLY
2301         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2302                 return ECORE_SUCCESS;
2303 #endif
2304
2305         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2306         drv_version.version = p_ver->version;
2307         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2308         for (i = 0; i < num_words; i++) {
2309                 /* The driver name is expected to be in a big-endian format */
2310                 p_name = &p_ver->name[i * sizeof(u32)];
2311                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2312                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2313         }
2314
2315         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2316         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2317         mb_params.p_data_src = &drv_version;
2318         mb_params.data_src_size = sizeof(drv_version);
2319         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2320         if (rc != ECORE_SUCCESS)
2321                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2322
2323         return rc;
2324 }
2325
2326 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2327                                     struct ecore_ptt *p_ptt)
2328 {
2329         enum _ecore_status_t rc;
2330         u32 resp = 0, param = 0;
2331
2332         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2333                            &param);
2334         if (rc != ECORE_SUCCESS)
2335                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2336
2337         return rc;
2338 }
2339
2340 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2341                                       struct ecore_ptt *p_ptt)
2342 {
2343         u32 value, cpu_mode;
2344
2345         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2346
2347         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2348         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2349         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2350         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2351
2352         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2353 }
2354
2355 enum _ecore_status_t
2356 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2357                                    struct ecore_ptt *p_ptt,
2358                                    enum ecore_ov_client client)
2359 {
2360         enum _ecore_status_t rc;
2361         u32 resp = 0, param = 0;
2362         u32 drv_mb_param;
2363
2364         switch (client) {
2365         case ECORE_OV_CLIENT_DRV:
2366                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2367                 break;
2368         case ECORE_OV_CLIENT_USER:
2369                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2370                 break;
2371         case ECORE_OV_CLIENT_VENDOR_SPEC:
2372                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2373                 break;
2374         default:
2375                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2376                 return ECORE_INVAL;
2377         }
2378
2379         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2380                            drv_mb_param, &resp, &param);
2381         if (rc != ECORE_SUCCESS)
2382                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2383
2384         return rc;
2385 }
2386
2387 enum _ecore_status_t
2388 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2389                                  struct ecore_ptt *p_ptt,
2390                                  enum ecore_ov_driver_state drv_state)
2391 {
2392         enum _ecore_status_t rc;
2393         u32 resp = 0, param = 0;
2394         u32 drv_mb_param;
2395
2396         switch (drv_state) {
2397         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2398                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2399                 break;
2400         case ECORE_OV_DRIVER_STATE_DISABLED:
2401                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2402                 break;
2403         case ECORE_OV_DRIVER_STATE_ACTIVE:
2404                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2405                 break;
2406         default:
2407                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2408                 return ECORE_INVAL;
2409         }
2410
2411         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2412                            drv_mb_param, &resp, &param);
2413         if (rc != ECORE_SUCCESS)
2414                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2415
2416         return rc;
2417 }
2418
2419 enum _ecore_status_t
2420 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2421                          struct ecore_fc_npiv_tbl *p_table)
2422 {
2423         return 0;
2424 }
2425
2426 enum _ecore_status_t
2427 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2428                         struct ecore_ptt *p_ptt, u16 mtu)
2429 {
2430         return 0;
2431 }
2432
2433 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2434                                        struct ecore_ptt *p_ptt,
2435                                        enum ecore_led_mode mode)
2436 {
2437         u32 resp = 0, param = 0, drv_mb_param;
2438         enum _ecore_status_t rc;
2439
2440         switch (mode) {
2441         case ECORE_LED_MODE_ON:
2442                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2443                 break;
2444         case ECORE_LED_MODE_OFF:
2445                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2446                 break;
2447         case ECORE_LED_MODE_RESTORE:
2448                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2449                 break;
2450         default:
2451                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2452                 return ECORE_INVAL;
2453         }
2454
2455         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2456                            drv_mb_param, &resp, &param);
2457         if (rc != ECORE_SUCCESS)
2458                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2459
2460         return rc;
2461 }
2462
2463 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2464                                              struct ecore_ptt *p_ptt,
2465                                              u32 mask_parities)
2466 {
2467         u32 resp = 0, param = 0;
2468         enum _ecore_status_t rc;
2469
2470         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2471                            mask_parities, &resp, &param);
2472
2473         if (rc != ECORE_SUCCESS) {
2474                 DP_ERR(p_hwfn,
2475                        "MCP response failure for mask parities, aborting\n");
2476         } else if (resp != FW_MSG_CODE_OK) {
2477                 DP_ERR(p_hwfn,
2478                        "MCP did not ack mask parity request. Old MFW?\n");
2479                 rc = ECORE_INVAL;
2480         }
2481
2482         return rc;
2483 }
2484
2485 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2486                                         u8 *p_buf, u32 len)
2487 {
2488         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2489         u32 bytes_left, offset, bytes_to_copy, buf_size;
2490         u32 nvm_offset, resp, param;
2491         struct ecore_ptt *p_ptt;
2492         enum _ecore_status_t rc = ECORE_SUCCESS;
2493
2494         p_ptt = ecore_ptt_acquire(p_hwfn);
2495         if (!p_ptt)
2496                 return ECORE_BUSY;
2497
2498         bytes_left = len;
2499         offset = 0;
2500         while (bytes_left > 0) {
2501                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2502                                            MCP_DRV_NVM_BUF_LEN);
2503                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2504                                                 DRV_MB_PARAM_NVM_LEN_SHIFT);
2505                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2506                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2507                                           nvm_offset, &resp, &param, &buf_size,
2508                                           (u32 *)(p_buf + offset));
2509                 if (rc != ECORE_SUCCESS) {
2510                         DP_NOTICE(p_dev, false,
2511                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2512                                   rc);
2513                         resp = FW_MSG_CODE_ERROR;
2514                         break;
2515                 }
2516
2517                 if (resp != FW_MSG_CODE_NVM_OK) {
2518                         DP_NOTICE(p_dev, false,
2519                                   "nvm read failed, resp = 0x%08x\n", resp);
2520                         rc = ECORE_UNKNOWN_ERROR;
2521                         break;
2522                 }
2523
2524                 /* This can be a lengthy process, and it's possible scheduler
2525                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2526                  */
2527                 if (bytes_left % 0x1000 <
2528                     (bytes_left - buf_size) % 0x1000)
2529                         OSAL_MSLEEP(1);
2530
2531                 offset += buf_size;
2532                 bytes_left -= buf_size;
2533         }
2534
2535         p_dev->mcp_nvm_resp = resp;
2536         ecore_ptt_release(p_hwfn, p_ptt);
2537
2538         return rc;
2539 }
2540
2541 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2542                                         u32 addr, u8 *p_buf, u32 len)
2543 {
2544         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2545         struct ecore_ptt *p_ptt;
2546         u32 resp, param;
2547         enum _ecore_status_t rc;
2548
2549         p_ptt = ecore_ptt_acquire(p_hwfn);
2550         if (!p_ptt)
2551                 return ECORE_BUSY;
2552
2553         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2554                                   (cmd == ECORE_PHY_CORE_READ) ?
2555                                   DRV_MSG_CODE_PHY_CORE_READ :
2556                                   DRV_MSG_CODE_PHY_RAW_READ,
2557                                   addr, &resp, &param, &len, (u32 *)p_buf);
2558         if (rc != ECORE_SUCCESS)
2559                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2560
2561         p_dev->mcp_nvm_resp = resp;
2562         ecore_ptt_release(p_hwfn, p_ptt);
2563
2564         return rc;
2565 }
2566
2567 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2568 {
2569         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2570         struct ecore_ptt *p_ptt;
2571
2572         p_ptt = ecore_ptt_acquire(p_hwfn);
2573         if (!p_ptt)
2574                 return ECORE_BUSY;
2575
2576         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2577         ecore_ptt_release(p_hwfn, p_ptt);
2578
2579         return ECORE_SUCCESS;
2580 }
2581
2582 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2583 {
2584         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2585         struct ecore_ptt *p_ptt;
2586         u32 resp, param;
2587         enum _ecore_status_t rc;
2588
2589         p_ptt = ecore_ptt_acquire(p_hwfn);
2590         if (!p_ptt)
2591                 return ECORE_BUSY;
2592         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2593                            &resp, &param);
2594         p_dev->mcp_nvm_resp = resp;
2595         ecore_ptt_release(p_hwfn, p_ptt);
2596
2597         return rc;
2598 }
2599
2600 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2601                                                   u32 addr)
2602 {
2603         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2604         struct ecore_ptt *p_ptt;
2605         u32 resp, param;
2606         enum _ecore_status_t rc;
2607
2608         p_ptt = ecore_ptt_acquire(p_hwfn);
2609         if (!p_ptt)
2610                 return ECORE_BUSY;
2611         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2612                            &resp, &param);
2613         p_dev->mcp_nvm_resp = resp;
2614         ecore_ptt_release(p_hwfn, p_ptt);
2615
2616         return rc;
2617 }
2618
2619 /* rc receives ECORE_INVAL as default parameter because
2620  * it might not enter the while loop if the len is 0
2621  */
2622 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2623                                          u32 addr, u8 *p_buf, u32 len)
2624 {
2625         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2626         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2627         enum _ecore_status_t rc = ECORE_INVAL;
2628         struct ecore_ptt *p_ptt;
2629
2630         p_ptt = ecore_ptt_acquire(p_hwfn);
2631         if (!p_ptt)
2632                 return ECORE_BUSY;
2633
2634         switch (cmd) {
2635         case ECORE_PUT_FILE_DATA:
2636                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2637                 break;
2638         case ECORE_NVM_WRITE_NVRAM:
2639                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2640                 break;
2641         case ECORE_EXT_PHY_FW_UPGRADE:
2642                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2643                 break;
2644         default:
2645                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2646                           cmd);
2647                 rc = ECORE_INVAL;
2648                 goto out;
2649         }
2650
2651         buf_idx = 0;
2652         while (buf_idx < len) {
2653                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2654                                       MCP_DRV_NVM_BUF_LEN);
2655                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_SHIFT) | addr) +
2656                                 buf_idx;
2657                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2658                                           &resp, &param, buf_size,
2659                                           (u32 *)&p_buf[buf_idx]);
2660                 if (rc != ECORE_SUCCESS) {
2661                         DP_NOTICE(p_dev, false,
2662                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2663                                   rc);
2664                         resp = FW_MSG_CODE_ERROR;
2665                         break;
2666                 }
2667
2668                 if (resp != FW_MSG_CODE_OK &&
2669                     resp != FW_MSG_CODE_NVM_OK &&
2670                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2671                         DP_NOTICE(p_dev, false,
2672                                   "nvm write failed, resp = 0x%08x\n", resp);
2673                         rc = ECORE_UNKNOWN_ERROR;
2674                         break;
2675                 }
2676
2677                 /* This can be a lengthy process, and it's possible scheduler
2678                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2679                  */
2680                 if (buf_idx % 0x1000 >
2681                     (buf_idx + buf_size) % 0x1000)
2682                         OSAL_MSLEEP(1);
2683
2684                 buf_idx += buf_size;
2685         }
2686
2687         p_dev->mcp_nvm_resp = resp;
2688 out:
2689         ecore_ptt_release(p_hwfn, p_ptt);
2690
2691         return rc;
2692 }
2693
2694 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2695                                          u32 addr, u8 *p_buf, u32 len)
2696 {
2697         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2698         struct ecore_ptt *p_ptt;
2699         u32 resp, param, nvm_cmd;
2700         enum _ecore_status_t rc;
2701
2702         p_ptt = ecore_ptt_acquire(p_hwfn);
2703         if (!p_ptt)
2704                 return ECORE_BUSY;
2705
2706         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2707                         DRV_MSG_CODE_PHY_RAW_WRITE;
2708         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2709                                   &resp, &param, len, (u32 *)p_buf);
2710         if (rc != ECORE_SUCCESS)
2711                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2712         p_dev->mcp_nvm_resp = resp;
2713         ecore_ptt_release(p_hwfn, p_ptt);
2714
2715         return rc;
2716 }
2717
2718 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2719                                                    u32 addr)
2720 {
2721         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2722         struct ecore_ptt *p_ptt;
2723         u32 resp, param;
2724         enum _ecore_status_t rc;
2725
2726         p_ptt = ecore_ptt_acquire(p_hwfn);
2727         if (!p_ptt)
2728                 return ECORE_BUSY;
2729
2730         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2731                            &resp, &param);
2732         p_dev->mcp_nvm_resp = resp;
2733         ecore_ptt_release(p_hwfn, p_ptt);
2734
2735         return rc;
2736 }
2737
2738 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2739                                             struct ecore_ptt *p_ptt,
2740                                             u32 port, u32 addr, u32 offset,
2741                                             u32 len, u8 *p_buf)
2742 {
2743         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2744         u32 resp, param;
2745         enum _ecore_status_t rc;
2746
2747         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2748                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2749         addr = offset;
2750         offset = 0;
2751         bytes_left = len;
2752         while (bytes_left > 0) {
2753                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2754                                            MAX_I2C_TRANSACTION_SIZE);
2755                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2756                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2757                 nvm_offset |= ((addr + offset) <<
2758                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2759                 nvm_offset |= (bytes_to_copy <<
2760                                DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2761                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2762                                           DRV_MSG_CODE_TRANSCEIVER_READ,
2763                                           nvm_offset, &resp, &param, &buf_size,
2764                                           (u32 *)(p_buf + offset));
2765                 if ((resp & FW_MSG_CODE_MASK) ==
2766                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2767                         return ECORE_NODEV;
2768                 } else if ((resp & FW_MSG_CODE_MASK) !=
2769                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2770                         return ECORE_UNKNOWN_ERROR;
2771
2772                 offset += buf_size;
2773                 bytes_left -= buf_size;
2774         }
2775
2776         return ECORE_SUCCESS;
2777 }
2778
2779 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2780                                              struct ecore_ptt *p_ptt,
2781                                              u32 port, u32 addr, u32 offset,
2782                                              u32 len, u8 *p_buf)
2783 {
2784         u32 buf_idx, buf_size, nvm_offset, resp, param;
2785         enum _ecore_status_t rc;
2786
2787         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2788                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2789         buf_idx = 0;
2790         while (buf_idx < len) {
2791                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2792                                       MAX_I2C_TRANSACTION_SIZE);
2793                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2794                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2795                 nvm_offset |= ((offset + buf_idx) <<
2796                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2797                 nvm_offset |= (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2798                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2799                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
2800                                           nvm_offset, &resp, &param, buf_size,
2801                                           (u32 *)&p_buf[buf_idx]);
2802                 if ((resp & FW_MSG_CODE_MASK) ==
2803                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2804                         return ECORE_NODEV;
2805                 } else if ((resp & FW_MSG_CODE_MASK) !=
2806                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2807                         return ECORE_UNKNOWN_ERROR;
2808
2809                 buf_idx += buf_size;
2810         }
2811
2812         return ECORE_SUCCESS;
2813 }
2814
2815 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2816                                          struct ecore_ptt *p_ptt,
2817                                          u16 gpio, u32 *gpio_val)
2818 {
2819         enum _ecore_status_t rc = ECORE_SUCCESS;
2820         u32 drv_mb_param = 0, rsp;
2821
2822         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2823
2824         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2825                            drv_mb_param, &rsp, gpio_val);
2826
2827         if (rc != ECORE_SUCCESS)
2828                 return rc;
2829
2830         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2831                 return ECORE_UNKNOWN_ERROR;
2832
2833         return ECORE_SUCCESS;
2834 }
2835
2836 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2837                                           struct ecore_ptt *p_ptt,
2838                                           u16 gpio, u16 gpio_val)
2839 {
2840         enum _ecore_status_t rc = ECORE_SUCCESS;
2841         u32 drv_mb_param = 0, param, rsp;
2842
2843         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2844                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2845
2846         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2847                            drv_mb_param, &rsp, &param);
2848
2849         if (rc != ECORE_SUCCESS)
2850                 return rc;
2851
2852         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2853                 return ECORE_UNKNOWN_ERROR;
2854
2855         return ECORE_SUCCESS;
2856 }
2857
2858 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2859                                          struct ecore_ptt *p_ptt,
2860                                          u16 gpio, u32 *gpio_direction,
2861                                          u32 *gpio_ctrl)
2862 {
2863         u32 drv_mb_param = 0, rsp, val = 0;
2864         enum _ecore_status_t rc = ECORE_SUCCESS;
2865
2866         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2867
2868         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2869                            drv_mb_param, &rsp, &val);
2870         if (rc != ECORE_SUCCESS)
2871                 return rc;
2872
2873         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2874                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2875         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2876                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2877
2878         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2879                 return ECORE_UNKNOWN_ERROR;
2880
2881         return ECORE_SUCCESS;
2882 }
2883
2884 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2885                                                   struct ecore_ptt *p_ptt)
2886 {
2887         u32 drv_mb_param = 0, rsp, param;
2888         enum _ecore_status_t rc = ECORE_SUCCESS;
2889
2890         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2891                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2892
2893         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2894                            drv_mb_param, &rsp, &param);
2895
2896         if (rc != ECORE_SUCCESS)
2897                 return rc;
2898
2899         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2900             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2901                 rc = ECORE_UNKNOWN_ERROR;
2902
2903         return rc;
2904 }
2905
2906 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2907                                                struct ecore_ptt *p_ptt)
2908 {
2909         u32 drv_mb_param, rsp, param;
2910         enum _ecore_status_t rc = ECORE_SUCCESS;
2911
2912         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2913                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2914
2915         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2916                            drv_mb_param, &rsp, &param);
2917
2918         if (rc != ECORE_SUCCESS)
2919                 return rc;
2920
2921         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2922             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2923                 rc = ECORE_UNKNOWN_ERROR;
2924
2925         return rc;
2926 }
2927
2928 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2929         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2930 {
2931         u32 drv_mb_param = 0, rsp;
2932         enum _ecore_status_t rc = ECORE_SUCCESS;
2933
2934         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2935                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2936
2937         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2938                            drv_mb_param, &rsp, num_images);
2939
2940         if (rc != ECORE_SUCCESS)
2941                 return rc;
2942
2943         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2944                 rc = ECORE_UNKNOWN_ERROR;
2945
2946         return rc;
2947 }
2948
2949 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2950         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2951         struct bist_nvm_image_att *p_image_att, u32 image_index)
2952 {
2953         u32 buf_size, nvm_offset, resp, param;
2954         enum _ecore_status_t rc;
2955
2956         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2957                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2958         nvm_offset |= (image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2959         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2960                                   nvm_offset, &resp, &param, &buf_size,
2961                                   (u32 *)p_image_att);
2962         if (rc != ECORE_SUCCESS)
2963                 return rc;
2964
2965         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2966             (p_image_att->return_code != 1))
2967                 rc = ECORE_UNKNOWN_ERROR;
2968
2969         return rc;
2970 }
2971
2972 enum _ecore_status_t
2973 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2974                                struct ecore_ptt *p_ptt,
2975                                struct ecore_temperature_info *p_temp_info)
2976 {
2977         struct ecore_temperature_sensor *p_temp_sensor;
2978         struct temperature_status_stc mfw_temp_info;
2979         struct ecore_mcp_mb_params mb_params;
2980         u32 val;
2981         enum _ecore_status_t rc;
2982         u8 i;
2983
2984         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2985         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2986         mb_params.p_data_dst = &mfw_temp_info;
2987         mb_params.data_dst_size = sizeof(mfw_temp_info);
2988         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2989         if (rc != ECORE_SUCCESS)
2990                 return rc;
2991
2992         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2993         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2994                                               ECORE_MAX_NUM_OF_SENSORS);
2995         for (i = 0; i < p_temp_info->num_sensors; i++) {
2996                 val = mfw_temp_info.sensor[i];
2997                 p_temp_sensor = &p_temp_info->sensors[i];
2998                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2999                                                  SENSOR_LOCATION_SHIFT;
3000                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3001                                                 THRESHOLD_HIGH_SHIFT;
3002                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3003                                           CRITICAL_TEMPERATURE_SHIFT;
3004                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3005                                               CURRENT_TEMP_SHIFT;
3006         }
3007
3008         return ECORE_SUCCESS;
3009 }
3010
3011 enum _ecore_status_t ecore_mcp_get_mba_versions(
3012         struct ecore_hwfn *p_hwfn,
3013         struct ecore_ptt *p_ptt,
3014         struct ecore_mba_vers *p_mba_vers)
3015 {
3016         u32 buf_size, resp, param;
3017         enum _ecore_status_t rc;
3018
3019         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3020                                   0, &resp, &param, &buf_size,
3021                                   &p_mba_vers->mba_vers[0]);
3022
3023         if (rc != ECORE_SUCCESS)
3024                 return rc;
3025
3026         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3027                 rc = ECORE_UNKNOWN_ERROR;
3028
3029         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3030                 rc = ECORE_UNKNOWN_ERROR;
3031
3032         return rc;
3033 }
3034
3035 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3036                                               struct ecore_ptt *p_ptt,
3037                                               u64 *num_events)
3038 {
3039         u32 rsp;
3040
3041         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3042                              0, &rsp, (u32 *)num_events);
3043 }
3044
3045 static enum resource_id_enum
3046 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3047 {
3048         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3049
3050         switch (res_id) {
3051         case ECORE_SB:
3052                 mfw_res_id = RESOURCE_NUM_SB_E;
3053                 break;
3054         case ECORE_L2_QUEUE:
3055                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3056                 break;
3057         case ECORE_VPORT:
3058                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3059                 break;
3060         case ECORE_RSS_ENG:
3061                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3062                 break;
3063         case ECORE_PQ:
3064                 mfw_res_id = RESOURCE_NUM_PQ_E;
3065                 break;
3066         case ECORE_RL:
3067                 mfw_res_id = RESOURCE_NUM_RL_E;
3068                 break;
3069         case ECORE_MAC:
3070         case ECORE_VLAN:
3071                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3072                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3073                 break;
3074         case ECORE_ILT:
3075                 mfw_res_id = RESOURCE_ILT_E;
3076                 break;
3077         case ECORE_LL2_QUEUE:
3078                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3079                 break;
3080         case ECORE_RDMA_CNQ_RAM:
3081         case ECORE_CMDQS_CQS:
3082                 /* CNQ/CMDQS are the same resource */
3083                 mfw_res_id = RESOURCE_CQS_E;
3084                 break;
3085         case ECORE_RDMA_STATS_QUEUE:
3086                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3087                 break;
3088         case ECORE_BDQ:
3089                 mfw_res_id = RESOURCE_BDQ_E;
3090                 break;
3091         default:
3092                 break;
3093         }
3094
3095         return mfw_res_id;
3096 }
3097
3098 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3099 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3100 #define ECORE_RESC_ALLOC_VERSION                                \
3101         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3102           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
3103          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3104           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
3105
3106 struct ecore_resc_alloc_in_params {
3107         u32 cmd;
3108         enum ecore_resources res_id;
3109         u32 resc_max_val;
3110 };
3111
3112 struct ecore_resc_alloc_out_params {
3113         u32 mcp_resp;
3114         u32 mcp_param;
3115         u32 resc_num;
3116         u32 resc_start;
3117         u32 vf_resc_num;
3118         u32 vf_resc_start;
3119         u32 flags;
3120 };
3121
3122 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3123
3124 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3125 {
3126         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3127         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3128         enum _ecore_status_t rc;
3129
3130         /* Allow ongoing PCIe transactions to complete */
3131         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3132
3133         /* Clear the PF's internal FID_enable in the PXP */
3134         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3135         if (rc != ECORE_SUCCESS)
3136                 DP_NOTICE(p_hwfn, false,
3137                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3138                           rc);
3139
3140         return rc;
3141 }
3142
3143 static enum _ecore_status_t
3144 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3145                               struct ecore_ptt *p_ptt,
3146                               struct ecore_resc_alloc_in_params *p_in_params,
3147                               struct ecore_resc_alloc_out_params *p_out_params)
3148 {
3149         struct ecore_mcp_mb_params mb_params;
3150         struct resource_info mfw_resc_info;
3151         enum _ecore_status_t rc;
3152
3153         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3154
3155         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3156         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3157                 DP_ERR(p_hwfn,
3158                        "Failed to match resource %d [%s] with the MFW resources\n",
3159                        p_in_params->res_id,
3160                        ecore_hw_get_resc_name(p_in_params->res_id));
3161                 return ECORE_INVAL;
3162         }
3163
3164         switch (p_in_params->cmd) {
3165         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3166                 mfw_resc_info.size = p_in_params->resc_max_val;
3167                 /* Fallthrough */
3168         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3169                 break;
3170         default:
3171                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3172                        p_in_params->cmd);
3173                 return ECORE_INVAL;
3174         }
3175
3176         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3177         mb_params.cmd = p_in_params->cmd;
3178         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3179         mb_params.p_data_src = &mfw_resc_info;
3180         mb_params.data_src_size = sizeof(mfw_resc_info);
3181         mb_params.p_data_dst = mb_params.p_data_src;
3182         mb_params.data_dst_size = mb_params.data_src_size;
3183
3184         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3185                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3186                    p_in_params->cmd, p_in_params->res_id,
3187                    ecore_hw_get_resc_name(p_in_params->res_id),
3188                    ECORE_MFW_GET_FIELD(mb_params.param,
3189                            DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3190                    ECORE_MFW_GET_FIELD(mb_params.param,
3191                            DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3192                    p_in_params->resc_max_val);
3193
3194         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3195         if (rc != ECORE_SUCCESS)
3196                 return rc;
3197
3198         p_out_params->mcp_resp = mb_params.mcp_resp;
3199         p_out_params->mcp_param = mb_params.mcp_param;
3200         p_out_params->resc_num = mfw_resc_info.size;
3201         p_out_params->resc_start = mfw_resc_info.offset;
3202         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3203         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3204         p_out_params->flags = mfw_resc_info.flags;
3205
3206         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3207                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3208                    ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3209                            FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3210                    ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3211                            FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3212                    p_out_params->resc_num, p_out_params->resc_start,
3213                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3214                    p_out_params->flags);
3215
3216         return ECORE_SUCCESS;
3217 }
3218
3219 enum _ecore_status_t
3220 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3221                            enum ecore_resources res_id, u32 resc_max_val,
3222                            u32 *p_mcp_resp)
3223 {
3224         struct ecore_resc_alloc_out_params out_params;
3225         struct ecore_resc_alloc_in_params in_params;
3226         enum _ecore_status_t rc;
3227
3228         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3229         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3230         in_params.res_id = res_id;
3231         in_params.resc_max_val = resc_max_val;
3232         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3233         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3234                                            &out_params);
3235         if (rc != ECORE_SUCCESS)
3236                 return rc;
3237
3238         *p_mcp_resp = out_params.mcp_resp;
3239
3240         return ECORE_SUCCESS;
3241 }
3242
3243 enum _ecore_status_t
3244 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3245                         enum ecore_resources res_id, u32 *p_mcp_resp,
3246                         u32 *p_resc_num, u32 *p_resc_start)
3247 {
3248         struct ecore_resc_alloc_out_params out_params;
3249         struct ecore_resc_alloc_in_params in_params;
3250         enum _ecore_status_t rc;
3251
3252         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3253         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3254         in_params.res_id = res_id;
3255         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3256         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3257                                            &out_params);
3258         if (rc != ECORE_SUCCESS)
3259                 return rc;
3260
3261         *p_mcp_resp = out_params.mcp_resp;
3262
3263         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3264                 *p_resc_num = out_params.resc_num;
3265                 *p_resc_start = out_params.resc_start;
3266         }
3267
3268         return ECORE_SUCCESS;
3269 }
3270
3271 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3272                                                struct ecore_ptt *p_ptt)
3273 {
3274         u32 mcp_resp, mcp_param;
3275
3276         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3277                              &mcp_resp, &mcp_param);
3278 }
3279
3280 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3281                                                    struct ecore_ptt *p_ptt,
3282                                                    u32 param, u32 *p_mcp_resp,
3283                                                    u32 *p_mcp_param)
3284 {
3285         enum _ecore_status_t rc;
3286
3287         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3288                            p_mcp_resp, p_mcp_param);
3289         if (rc != ECORE_SUCCESS)
3290                 return rc;
3291
3292         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3293                 DP_INFO(p_hwfn,
3294                         "The resource command is unsupported by the MFW\n");
3295                 return ECORE_NOTIMPL;
3296         }
3297
3298         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3299                 u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3300
3301                 DP_NOTICE(p_hwfn, false,
3302                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3303                           param, opcode);
3304                 return ECORE_INVAL;
3305         }
3306
3307         return rc;
3308 }
3309
3310 enum _ecore_status_t
3311 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3312                       struct ecore_resc_lock_params *p_params)
3313 {
3314         u32 param = 0, mcp_resp, mcp_param;
3315         u8 opcode;
3316         enum _ecore_status_t rc;
3317
3318         switch (p_params->timeout) {
3319         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3320                 opcode = RESOURCE_OPCODE_REQ;
3321                 p_params->timeout = 0;
3322                 break;
3323         case ECORE_MCP_RESC_LOCK_TO_NONE:
3324                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3325                 p_params->timeout = 0;
3326                 break;
3327         default:
3328                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3329                 break;
3330         }
3331
3332         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3333         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3334         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3335
3336         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3337                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3338                    param, p_params->timeout, opcode, p_params->resource);
3339
3340         /* Attempt to acquire the resource */
3341         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3342                                     &mcp_param);
3343         if (rc != ECORE_SUCCESS)
3344                 return rc;
3345
3346         /* Analyze the response */
3347         p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
3348                                              RESOURCE_CMD_RSP_OWNER);
3349         opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3350
3351         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3352                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3353                    mcp_param, opcode, p_params->owner);
3354
3355         switch (opcode) {
3356         case RESOURCE_OPCODE_GNT:
3357                 p_params->b_granted = true;
3358                 break;
3359         case RESOURCE_OPCODE_BUSY:
3360                 p_params->b_granted = false;
3361                 break;
3362         default:
3363                 DP_NOTICE(p_hwfn, false,
3364                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3365                           mcp_param, opcode);
3366                 return ECORE_INVAL;
3367         }
3368
3369         return ECORE_SUCCESS;
3370 }
3371
3372 enum _ecore_status_t
3373 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3374                     struct ecore_resc_lock_params *p_params)
3375 {
3376         u32 retry_cnt = 0;
3377         enum _ecore_status_t rc;
3378
3379         do {
3380                 /* No need for an interval before the first iteration */
3381                 if (retry_cnt) {
3382                         if (p_params->sleep_b4_retry) {
3383                                 u16 retry_interval_in_ms =
3384                                         DIV_ROUND_UP(p_params->retry_interval,
3385                                                      1000);
3386
3387                                 OSAL_MSLEEP(retry_interval_in_ms);
3388                         } else {
3389                                 OSAL_UDELAY(p_params->retry_interval);
3390                         }
3391                 }
3392
3393                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3394                 if (rc != ECORE_SUCCESS)
3395                         return rc;
3396
3397                 if (p_params->b_granted)
3398                         break;
3399         } while (retry_cnt++ < p_params->retry_num);
3400
3401         return ECORE_SUCCESS;
3402 }
3403
3404 void
3405 ecore_mcp_resc_lock_default_init(struct ecore_hwfn *p_hwfn,
3406                                  struct ecore_resc_lock_params *p_lock,
3407                                  struct ecore_resc_unlock_params *p_unlock,
3408                                  enum ecore_resc_lock resource,
3409                                  bool b_is_permanent)
3410 {
3411         if (p_lock != OSAL_NULL) {
3412                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3413
3414                 /* Permanent resources don't require aging, and there's no
3415                  * point in trying to acquire them more than once since it's
3416                  * unexpected another entity would release them.
3417                  */
3418                 if (b_is_permanent) {
3419                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3420                 } else {
3421                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3422                         p_lock->retry_interval =
3423                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3424                         p_lock->sleep_b4_retry = true;
3425                 }
3426
3427                 p_lock->resource = resource;
3428         }
3429
3430         if (p_unlock != OSAL_NULL) {
3431                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3432                 p_unlock->resource = resource;
3433         }
3434 }
3435
3436 enum _ecore_status_t
3437 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3438                       struct ecore_resc_unlock_params *p_params)
3439 {
3440         u32 param = 0, mcp_resp, mcp_param;
3441         u8 opcode;
3442         enum _ecore_status_t rc;
3443
3444         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3445                                    : RESOURCE_OPCODE_RELEASE;
3446         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3447         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3448
3449         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3450                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3451                    param, opcode, p_params->resource);
3452
3453         /* Attempt to release the resource */
3454         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3455                                     &mcp_param);
3456         if (rc != ECORE_SUCCESS)
3457                 return rc;
3458
3459         /* Analyze the response */
3460         opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3461
3462         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3463                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3464                    mcp_param, opcode);
3465
3466         switch (opcode) {
3467         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3468                 DP_INFO(p_hwfn,
3469                         "Resource unlock request for an already released resource [%d]\n",
3470                         p_params->resource);
3471                 /* Fallthrough */
3472         case RESOURCE_OPCODE_RELEASED:
3473                 p_params->b_released = true;
3474                 break;
3475         case RESOURCE_OPCODE_WRONG_OWNER:
3476                 p_params->b_released = false;
3477                 break;
3478         default:
3479                 DP_NOTICE(p_hwfn, false,
3480                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3481                           mcp_param, opcode);
3482                 return ECORE_INVAL;
3483         }
3484
3485         return ECORE_SUCCESS;
3486 }
3487
3488 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3489 {
3490         return !!(p_hwfn->mcp_info->capabilities &
3491                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3492 }
3493
3494 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3495                                                 struct ecore_ptt *p_ptt)
3496 {
3497         u32 mcp_resp;
3498         enum _ecore_status_t rc;
3499
3500         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3501                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3502         if (rc == ECORE_SUCCESS)
3503                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3504                            "MFW supported features: %08x\n",
3505                            p_hwfn->mcp_info->capabilities);
3506
3507         return rc;
3508 }
3509
3510 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3511                                                 struct ecore_ptt *p_ptt)
3512 {
3513         u32 mcp_resp, mcp_param, features;
3514
3515         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3516                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3517
3518         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3519                              features, &mcp_resp, &mcp_param);
3520 }